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authorTopi Pohjolainen <[email protected]>2017-01-17 11:04:22 +0200
committerTopi Pohjolainen <[email protected]>2017-01-18 22:42:47 +0200
commit4840a53e902b0f2b9841d9dbb90e479a3688153d (patch)
tree74742e5387bde22765facb2f2b2a2947bba266e7 /src/mesa/drivers
parentea8b2624c8da1061e93124a760cae2ffb5f027ad (diff)
i965/blorp: Use the render cache mechanism instead of explicit flushing
by replacing brw_emit_mi_flush() with brw_render_cache_set_check_flush(). The latter splits the flush in two: brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE); instead of int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; if (brw->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL; } brw_emit_pipe_control_flush(brw, flags); v2 (Jason): Check that destination exists before trying to add to render cache. Depth clears and resolves don't have it. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/genX_blorp_exec.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index bb1dfa98063..b72ecb6f66c 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -25,6 +25,7 @@
#include "intel_batchbuffer.h"
#include "intel_mipmap_tree.h"
+#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
@@ -179,7 +180,9 @@ genX(blorp_exec)(struct blorp_batch *batch,
* data with different formats, which blorp does for stencil and depth
* data.
*/
- brw_emit_mi_flush(brw);
+ if (params->src.enabled)
+ brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
+ brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
@@ -256,6 +259,9 @@ retry:
brw->no_depth_or_stencil = false;
brw->ib.type = -1;
+ if (params->dst.enabled)
+ brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
+
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/