intel/blorp: Handle gen6 stencil/HiZ offsets in the back-end

Reviewed-by: Topi Pohjolainen <[email protected]>

4 files changed, 11 insertions, 72 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 61c6bda56b5..28be6204293 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -118,36 +118,6 @@ brw_blorp_init(struct brw_context *brw)
 }
 
 static void
-apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
-                              struct intel_mipmap_tree *mt,
-                              uint32_t lod,
-                              uint32_t *offset)
-{
-   assert(mt->array_layout == GEN6_HIZ_STENCIL);
-
-   if (mt->format == MESA_FORMAT_S_UINT8) {
-      /* Note: we can't compute the stencil offset using
-       * intel_miptree_get_aligned_offset(), because the miptree
-       * claims that the region is untiled even though it's W tiled.
-       */
-      *offset = mt->level[lod].level_y * mt->pitch +
-                mt->level[lod].level_x * 64;
-   } else {
-      *offset = intel_miptree_get_aligned_offset(mt,
-                                                 mt->level[lod].level_x,
-                                                 mt->level[lod].level_y);
-   }
-
-   surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
-   surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
-   surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
-   surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
-   surf->levels = 1;
-   surf->array_pitch_el_rows =
-      ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
-}
-
-static void
 blorp_surf_for_miptree(struct brw_context *brw,
                        struct blorp_surf *surf,
                        struct intel_mipmap_tree *mt,
@@ -181,24 +151,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
       .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
    };
 
-   if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
-       mt->array_layout == GEN6_HIZ_STENCIL) {
-      /* Sandy bridge stencil and HiZ use this GEN6_HIZ_STENCIL hack in
-       * order to allow for layered rendering.  The hack makes each LOD of the
-       * stencil or HiZ buffer a single tightly packed array surface at some
-       * offset into the surface.  Since ISL doesn't know how to deal with the
-       * crazy GEN6_HIZ_STENCIL layout and since we have to do a manual
-       * offset of it anyway, we might as well do the offset here and keep the
-       * hacks inside the i965 driver.
-       *
-       * See also gen6_depth_stencil_state.c
-       */
-      uint32_t offset;
-      apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
-      surf->addr.offset += offset;
-      *level = 0;
-   }
-
    struct isl_surf *aux_surf = &tmp_surfs[1];
    intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
 
@@ -258,19 +210,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
          surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
          surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
-
-         struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
-         if (hiz_mt) {
-            assert(brw->gen == 6 && hiz_mt->array_layout == GEN6_HIZ_STENCIL);
-
-            /* gen6 requires the HiZ buffer to be manually offset to the
-             * right location.  We could fixup the surf but it doesn't
-             * matter since most of those fields don't matter.
-             */
-            apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
-                                          &surf->aux_addr.offset);
-            assert(hiz_mt->pitch == aux_surf->row_pitch);
-         }
       }
    } else {
       surf->aux_addr = (struct blorp_address) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 1a92424b5dd..e9a1c9bd709 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -89,7 +89,8 @@ brw_emit_surface_state(struct brw_context *brw,
    surf.dim = get_isl_surf_dim(target);
 
    const enum isl_dim_layout dim_layout =
-      get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target);
+      get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target,
+                         mt->array_layout);
 
    if (surf.dim_layout != dim_layout) {
       /* The layout of the specified texture target is not compatible with the
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f7a69a0e235..b77b7fdadd2 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1814,13 +1814,7 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
    buf->aux_base.bo = buf->mt->bo;
    buf->aux_base.size = buf->mt->total_height * buf->mt->pitch;
    buf->aux_base.pitch = buf->mt->pitch;
-
-   /* On gen6 hiz is unconditionally laid out packing all slices
-    * at each level-of-detail (LOD). This means there is no valid qpitch
-    * setting. In fact, this is ignored when hardware is setup - there is no
-    * hardware qpitch setting of hiz on gen6.
-    */
-   buf->aux_base.qpitch = 0;
+   buf->aux_base.qpitch = buf->mt->qpitch * 2;
 
    return buf;
 }
@@ -3134,8 +3128,11 @@ get_isl_surf_dim(GLenum target)
 
 enum isl_dim_layout
 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
-                   GLenum target)
+                   GLenum target, enum miptree_array_layout array_layout)
 {
+   if (array_layout == GEN6_HIZ_STENCIL)
+      return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ;
+
    switch (target) {
    case GL_TEXTURE_1D:
    case GL_TEXTURE_1D_ARRAY:
@@ -3189,7 +3186,8 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
 {
    surf->dim = get_isl_surf_dim(mt->target);
    surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo,
-                                         mt->tiling, mt->target);
+                                         mt->tiling, mt->target,
+                                         mt->array_layout);
 
    if (mt->num_samples > 1) {
       switch (mt->msaa_layout) {
@@ -3268,6 +3266,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
    switch (surf->dim_layout) {
    case ISL_DIM_LAYOUT_GEN4_2D:
    case ISL_DIM_LAYOUT_GEN4_3D:
+   case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
       if (brw->gen >= 9) {
          surf->array_pitch_el_rows = mt->qpitch;
       } else {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index be460f33eb8..6096cabbdff 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -804,7 +804,7 @@ get_isl_surf_dim(GLenum target);
 
 enum isl_dim_layout
 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
-                   GLenum target);
+                   GLenum target, enum miptree_array_layout array_layout);
 
 enum isl_tiling
 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);