diff options
author | Chad Versace <[email protected]> | 2011-12-21 16:58:38 -0800 |
---|---|---|
committer | Chad Versace <[email protected]> | 2012-01-10 15:52:27 -0800 |
commit | bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9 (patch) | |
tree | 951bbf31bbbdb5236fd1970afc7aad9f742290f0 /src/mesa/drivers | |
parent | b755f5894ce211dcb8ec881ba9cd9856383c3c79 (diff) |
i965: Replace references to stencil region size with buffer size
It is unwise to use a stencil region's size to determine its
renderbuffer's size, because at region creation we fudge the width and
height to accomodate interleaved rows. (See the comment for MESA_FORMAT_S8
in intel_miptree_create()). Most users of stencil_region->{width,height}
should be converted to use stencil_rb->{Width,Height}.
We have already done the replacement in several locations. This patch
continues the replacement in {brw,gen7}_emit_depthbuffer(). To make those
functions look consistent, I've also done the equivalent replacement for
the depth buffer.
Acked-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 8 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen7_misc_state.c | 6 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 1c0c52bf52b..726d8d80af4 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -343,8 +343,8 @@ static void emit_depthbuffer(struct brw_context *brw) (1 << 27) | /* tiled surface */ (BRW_SURFACE_2D << 29)); OUT_BATCH(0); - OUT_BATCH(((region->width - 1) << 6) | - (2 * region->height - 1) << 19); + OUT_BATCH(((stencil_irb->Base.Width - 1) << 6) | + (stencil_irb->Base.Height - 1) << 19); OUT_BATCH(0); OUT_BATCH(0); @@ -378,8 +378,8 @@ static void emit_depthbuffer(struct brw_context *brw) I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | - ((region->width - 1) << 6) | - ((region->height - 1) << 19)); + ((depth_irb->Base.Width - 1) << 6) | + ((depth_irb->Base.Height - 1) << 19)); OUT_BATCH(0); if (intel->is_g4x || intel->gen >= 5) diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 89a4e719ae0..9c93046fdfb 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -71,7 +71,8 @@ static void emit_depthbuffer(struct brw_context *brw) /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */ dw1 |= (BRW_SURFACE_2D << 29); - dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18); + dw3 = ((srb->Base.Width - 1) << 4) | + ((srb->Base.Height - 1) << 18); } BEGIN_BATCH(7); @@ -103,7 +104,8 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_RELOC(region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); - OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18)); + OUT_BATCH(((drb->Base.Width - 1) << 4) | + ((drb->Base.Height - 1) << 18)); OUT_BATCH(0); OUT_BATCH(tile_x | (tile_y << 16)); OUT_BATCH(0); |