diff options
author | Chris Wilson <[email protected]> | 2017-03-17 00:58:13 -0700 |
---|---|---|
committer | Matt Turner <[email protected]> | 2017-06-06 11:47:56 -0700 |
commit | 7063696b71b995388f247e108a6b2b53a521d385 (patch) | |
tree | b039cbde2476f2b6cd8ebc9e8b00129dc235e491 /src/mesa/drivers | |
parent | bc17155fd0e6cb3ec0a19ffbe39f0c981ef48d4f (diff) |
i965: Explicitly disallow tiled memcpy path on Gen4 with swizzling.
The manual detiling paths are not prepared to handle Gen4-G45 with
swizzling enabled, so explicitly disable them. (They're already
disabled because these platforms don't have LLC but a future patch could
enable this path).
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
Acked-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_pixel_read.c | 11 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_image.c | 11 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_subimage.c | 11 |
3 files changed, 33 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index 4614279c643..7074d7db9a2 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -133,6 +133,17 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, return false; } + /* tiled_to_linear() assumes that if the object is swizzled, it is using + * I915_BIT6_SWIZZLE_9_10 for X and I915_BIT6_SWIZZLE_9 for Y. This is only + * true on gen5 and above. + * + * The killer on top is that some gen4 have an L-shaped swizzle mode, where + * parts of the memory aren't swizzled at all. Userspace just can't handle + * that. + */ + if (brw->gen < 5 && brw->has_swizzling) + return false; + /* Since we are going to read raw data to the miptree, we need to resolve * any pending fast color clears before we start. */ diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 828f20b7b67..77e09e83a58 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -522,6 +522,17 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, return false; } + /* tiled_to_linear() assumes that if the object is swizzled, it is using + * I915_BIT6_SWIZZLE_9_10 for X and I915_BIT6_SWIZZLE_9 for Y. This is only + * true on gen5 and above. + * + * The killer on top is that some gen4 have an L-shaped swizzle mode, where + * parts of the memory aren't swizzled at all. Userspace just can't handle + * that. + */ + if (brw->gen < 5 && brw->has_swizzling) + return false; + /* Since we are going to write raw data to the miptree, we need to resolve * any pending fast color clears before we start. */ diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 40569e17a33..e9c7b802b11 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -134,6 +134,17 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, return false; } + /* linear_to_tiled() assumes that if the object is swizzled, it is using + * I915_BIT6_SWIZZLE_9_10 for X and I915_BIT6_SWIZZLE_9 for Y. This is only + * true on gen5 and above. + * + * The killer on top is that some gen4 have an L-shaped swizzle mode, where + * parts of the memory aren't swizzled at all. Userspace just can't handle + * that. + */ + if (brw->gen < 5 && brw->has_swizzling) + return false; + /* Since we are going to write raw data to the miptree, we need to resolve * any pending fast color clears before we start. */ |