diff options
| author | Kenneth Graunke <[email protected]> | 2014-02-06 16:49:31 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-02-19 01:46:17 -0800 |
| commit | 67f073b91c1be3a6ca15b36a579473c7562e6632 (patch) | |
| tree | 2e3e50d9b82d3d00953d61575a67d2b2849285b3 /src/mesa/drivers | |
| parent | 577fdf1f4896041263b6de5980343c6721f6ec00 (diff) | |
i965: Add #defines for the 3DSTATE_WM_HZ_OP packet's contents.
We're going to need these to implement HiZ.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 75d09fc72b2..dea09404825 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1753,6 +1753,31 @@ enum brw_message_target { #define GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE (1 << 0) #define _3DSTATE_WM_HZ_OP 0x7852 /* GEN8+ */ +/* DW1 */ +# define GEN8_WM_HZ_STENCIL_CLEAR (1 << 31) +# define GEN8_WM_HZ_DEPTH_CLEAR (1 << 30) +# define GEN8_WM_HZ_DEPTH_RESOLVE (1 << 28) +# define GEN8_WM_HZ_HIZ_RESOLVE (1 << 27) +# define GEN8_WM_HZ_PIXEL_OFFSET_ENABLE (1 << 26) +# define GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR (1 << 25) +# define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_MASK INTEL_MASK(23, 16) +# define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_SHIFT 16 +# define GEN8_WM_HZ_NUM_SAMPLES_MASK INTEL_MASK(15, 13) +# define GEN8_WM_HZ_NUM_SAMPLES_SHIFT 13 +/* DW2 */ +# define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_MASK INTEL_MASK(31, 16) +# define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_SHIFT 16 +# define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_MASK INTEL_MASK(15, 0) +# define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_SHIFT 0 +/* DW3 */ +# define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_MASK INTEL_MASK(31, 16) +# define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_SHIFT 16 +# define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_MASK INTEL_MASK(15, 0) +# define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_SHIFT 0 +/* DW4 */ +# define GEN8_WM_HZ_SAMPLE_MASK_MASK INTEL_MASK(15, 0) +# define GEN8_WM_HZ_SAMPLE_MASK_SHIFT 0 + #define _3DSTATE_PS_BLEND 0x784D /* GEN8+ */ /* DW1 */ |