diff options
| author | Francisco Jerez <[email protected]> | 2015-07-06 18:23:57 +0300 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2015-07-07 20:20:22 +0300 |
| commit | 40e2102e528498dd4c03c4567d3522241f4d1f22 (patch) | |
| tree | 92112f656bc741e77c063f49f3c979359f17543d /src/mesa/drivers | |
| parent | 248b26429f52d0f19949a083aa3e0aeebcbe2138 (diff) | |
i965/gen4-5: Set ENDIF dst and src0 fields to the null register.
The hardware docs don't mention explicitly what these fields should
be, but I've verified experimentally on ILK that using a GRF as
destination causes the register to be corrupted when the execution
size of an ENDIF instruction is higher than 8 -- and because the
destination we were using was g0, eventually a hang.
Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with
if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3.
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 0f536046f6f..4d397622fc1 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1584,8 +1584,8 @@ brw_ENDIF(struct brw_codegen *p) } if (devinfo->gen < 6) { - brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); - brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); + brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); brw_set_src1(p, insn, brw_imm_d(0x0)); } else if (devinfo->gen == 6) { brw_set_dest(p, insn, brw_imm_w(0)); |