i965/blorp: Set up HiZ surfaces up-front

Reviewed-by: Topi Pohjolainen <[email protected]>

4 files changed, 65 insertions, 32 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 6bc60ef9a4b..ea49adc2f34 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -105,6 +105,28 @@ blorp_get_image_offset_sa(struct isl_device *dev, const struct isl_surf *surf,
    }
 }
 
+static void
+apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
+                              struct intel_mipmap_tree *mt,
+                              uint32_t lod,
+                              uint32_t *offset)
+{
+   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+
+   *offset = intel_miptree_get_aligned_offset(mt,
+                                              mt->level[lod].level_x,
+                                              mt->level[lod].level_y,
+                                              false);
+
+   surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
+   surf->logical_level0_px.height = minify(surf->logical_level0_px.height, lod);
+   surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
+   surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
+   surf->levels = 1;
+   surf->array_pitch_el_rows =
+      ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
+}
+
 void
 brw_blorp_surface_info_init(struct brw_context *brw,
                             struct brw_blorp_surface_info *info,
@@ -125,7 +147,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 
    intel_miptree_check_level_layer(mt, level, layer);
 
-   info->mt = mt;
    if (is_render_target)
       intel_miptree_used_for_rendering(mt);
 
@@ -133,24 +154,51 @@ brw_blorp_surface_info_init(struct brw_context *brw,
    info->bo = mt->bo;
    info->offset = mt->offset;
 
-   if (mt->mcs_mt &&
-       (is_render_target ||
-        mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)) {
-      intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
-                                     &info->aux_usage);
-      info->aux_bo = mt->mcs_mt->bo;
-      info->aux_offset = mt->mcs_mt->offset;
+   intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
+                                  &info->aux_usage);
+
+   /* For textures that are in the RESOLVED state, we ignore the MCS */
+   if (mt->mcs_mt && !is_render_target &&
+       mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED)
+      info->aux_usage = ISL_AUX_USAGE_NONE;
 
+   if (info->aux_usage != ISL_AUX_USAGE_NONE) {
       /* We only really need a clear color if we also have an auxiliary
        * surface.  Without one, it does nothing.
        */
       info->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
+
+      if (mt->mcs_mt) {
+         info->aux_bo = mt->mcs_mt->bo;
+         info->aux_offset = mt->mcs_mt->offset;
+      } else {
+         assert(info->aux_usage == ISL_AUX_USAGE_HIZ);
+         struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
+         if (hiz_mt) {
+            info->aux_bo = hiz_mt->bo;
+            if (brw->gen == 6 &&
+                hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+               /* gen6 requires the HiZ buffer to be manually offset to the
+                * right location.  We could fixup the surf but it doesn't
+                * matter since most of those fields don't matter.
+                */
+               apply_gen6_stencil_hiz_offset(&info->aux_surf, hiz_mt, level,
+                                             &info->aux_offset);
+            } else {
+               info->aux_offset = 0;
+            }
+            assert(hiz_mt->pitch == info->aux_surf.row_pitch);
+         } else {
+            info->aux_bo = mt->hiz_buf->bo;
+            info->aux_offset = 0;
+         }
+      }
    } else {
-      info->aux_usage = ISL_AUX_USAGE_NONE;
       info->aux_bo = NULL;
       info->aux_offset = 0;
       memset(&info->clear_color, 0, sizeof(info->clear_color));
    }
+   assert((info->aux_usage == ISL_AUX_USAGE_NONE) == (info->aux_bo == NULL));
 
    info->view = (struct isl_view) {
       .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index d74788021ef..95a6257549c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -69,8 +69,6 @@ enum {
 
 struct brw_blorp_surface_info
 {
-   struct intel_mipmap_tree *mt;
-
    struct isl_surf surf;
    drm_intel_bo *bo;
    uint32_t offset;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 6f3073b71dd..8aeaf61443e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -759,23 +759,12 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
-      uint32_t offset = 0;
-
-      if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-         const unsigned lod = params->depth.view.base_level;
-         offset = intel_miptree_get_aligned_offset(hiz_mt,
-                                                   hiz_mt->level[lod].level_x,
-                                                   hiz_mt->level[lod].level_y,
-                                                   false);
-      }
-
       BEGIN_BATCH(3);
       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-      OUT_BATCH(hiz_mt->pitch - 1);
-      OUT_RELOC(hiz_mt->bo,
+      OUT_BATCH(params->depth.aux_surf.row_pitch - 1);
+      OUT_RELOC(params->depth.aux_bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                offset);
+                params->depth.aux_offset);
       ADVANCE_BATCH();
    }
 
@@ -835,7 +824,7 @@ gen6_blorp_emit_clear_params(struct brw_context *brw,
    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
 	     GEN5_DEPTH_CLEAR_VALID |
 	     (2 - 2));
-   OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
+   OUT_BATCH(params->depth.clear_color.u32[0]);
    ADVANCE_BATCH();
 }
 
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 0ca1a7b7b0c..43dea3e77a4 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -529,15 +529,13 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
-
       BEGIN_BATCH(3);
       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_buf->pitch - 1));
-      OUT_RELOC(hiz_buf->bo,
+                (params->depth.aux_surf.row_pitch - 1));
+      OUT_RELOC(params->depth.aux_bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                0);
+                params->depth.aux_offset);
       ADVANCE_BATCH();
    }
 
@@ -595,7 +593,7 @@ gen7_blorp_emit_clear_params(struct brw_context *brw,
 {
    BEGIN_BATCH(3);
    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
-   OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
+   OUT_BATCH(params->depth.clear_color.u32[0]);
    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
    ADVANCE_BATCH();
 }