diff options
| author | Kenneth Graunke <[email protected]> | 2014-04-21 16:37:04 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-11-03 15:32:43 -0800 |
| commit | 822e791321c387cadcec562820a0521aae90cc77 (patch) | |
| tree | 284173651bc01e679ab70c1cff205f807890ceb6 /src/mesa/drivers | |
| parent | e813728b2b7cba0c5aa4cad7a3eee909dc7afcc0 (diff) | |
i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.
Skylake has some extra bits in PIPELINE_SELECT, none of which are
interesting for a 3D driver. In order to selectively change them, it
also introduces new "mask bits" in 15:8. We care about the "Pipeline
Selection" bits (1:0), so set the mask to 0x3.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e3980fc3408..99fcddc6a21 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -902,7 +902,7 @@ brw_upload_invariant_state(struct brw_context *brw) const uint32_t _3DSTATE_PIPELINE_SELECT = is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; BEGIN_BATCH(1); - OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0); + OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0)); ADVANCE_BATCH(); if (brw->gen < 6) { |