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authorAnuj Phogat <[email protected]>2015-04-14 22:06:48 -0700
committerAnuj Phogat <[email protected]>2015-06-16 14:52:48 -0700
commit54591bb67f189820ef0d61b040179abbd5ecf78a (patch)
treebacc1d27d58abd7061c13df16811469b7fbc3c4c /src/mesa/drivers
parent6c380d42b161da977d164ccf75ccc25a2e056bb1 (diff)
i965/gen9: Set vertical and horizontal surface alignments
Patch sets the alignments for texture and renderbuffer surfaces. V3: Make changes inside horizontal_alignment() and vertical_alignment() (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/gen8_surface_state.c32
1 files changed, 26 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 96310742bf1..2514d960e2e 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -83,8 +83,18 @@ surface_tiling_mode(uint32_t tiling)
}
static unsigned
-vertical_alignment(const struct intel_mipmap_tree *mt)
+vertical_alignment(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ uint32_t surf_type)
{
+ /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
+ * tr_mode is not TRMODE_NONE.
+ */
+ if (brw->gen > 8 &&
+ (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
+ surf_type == BRW_SURFACE_1D))
+ return 0;
+
switch (mt->align_h) {
case 4:
return GEN8_SURFACE_VALIGN_4;
@@ -98,8 +108,18 @@ vertical_alignment(const struct intel_mipmap_tree *mt)
}
static unsigned
-horizontal_alignment(const struct intel_mipmap_tree *mt)
+horizontal_alignment(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ uint32_t surf_type)
{
+ /* On Gen9+ horizontal alignment is ignored when tr_mode is not
+ * TRMODE_NONE.
+ */
+ if (brw->gen > 8 &&
+ (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
+ gen9_use_linear_1d_layout(brw, mt)))
+ return 0;
+
switch (mt->align_w) {
case 4:
return GEN8_SURFACE_HALIGN_4;
@@ -210,8 +230,8 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
format << BRW_SURFACE_FORMAT_SHIFT |
- vertical_alignment(mt) |
- horizontal_alignment(mt) |
+ vertical_alignment(brw, mt, surf_type) |
+ horizontal_alignment(brw, mt, surf_type) |
tiling_mode;
if (surf_type == BRW_SURFACE_CUBE) {
@@ -438,8 +458,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
(is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
(format << BRW_SURFACE_FORMAT_SHIFT) |
- vertical_alignment(mt) |
- horizontal_alignment(mt) |
+ vertical_alignment(brw, mt, surf_type) |
+ horizontal_alignment(brw, mt, surf_type) |
surface_tiling_mode(tiling);
surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;