i965: Track the brw_state_batch() data while under INTEL_DEBUG=batch.

Reviewed-by: Kenneth Graunke <[email protected]>

3 files changed, 36 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 012617b1d2f..1a918f47b26 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -768,6 +768,14 @@ struct brw_context
 
    int num_prepare_atoms, num_emit_atoms;
    struct brw_tracked_state prepare_atoms[64], emit_atoms[64];
+
+   /* If (INTEL_DEBUG & DEBUG_BATCH) */
+   struct {
+      uint32_t offset;
+      uint32_t size;
+      enum state_struct_type type;
+   } *state_batch_list;
+   int state_batch_count;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 32f315ef107..5a983c3d847 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -32,6 +32,29 @@
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
 #include "main/imports.h"
+#include "../glsl/ralloc.h"
+
+static void
+brw_track_state_batch(struct brw_context *brw,
+		      enum state_struct_type type,
+		      uint32_t offset,
+		      int size)
+{
+   struct intel_batchbuffer *batch = &brw->intel.batch;
+
+   if (!brw->state_batch_list) {
+      /* Our structs are always aligned to at least 32 bytes, so
+       * our array doesn't need to be any larger
+       */
+      brw->state_batch_list = ralloc_size(brw, sizeof(*brw->state_batch_list) *
+					  batch->bo->size / 32);
+   }
+
+   brw->state_batch_list[brw->state_batch_count].offset = offset;
+   brw->state_batch_list[brw->state_batch_count].size = size;
+   brw->state_batch_list[brw->state_batch_count].type = type;
+   brw->state_batch_count++;
+}
 
 /**
  * Allocates a block of space in the batchbuffer for indirect state.
@@ -72,6 +95,9 @@ brw_state_batch(struct brw_context *brw,
 
    batch->state_batch_offset = offset;
 
+   if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
+      brw_track_state_batch(brw, type, offset, size);
+
    *out_offset = offset;
    return batch->map + (offset>>2);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 8612e743265..6aeeda6e0fa 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -123,6 +123,8 @@ static void brw_new_batch( struct intel_context *intel )
     */
    intel->batch.need_workaround_flush = true;
 
+   brw->state_batch_count = 0;
+
    brw->vb.nr_current_buffers = 0;
 
    /* Mark that the current program cache BO has been used by the GPU.