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authorSamuel Iglesias Gonsálvez <siglesias@igalia.com>2016-06-13 08:29:53 +0200
committerSamuel Iglesias Gonsálvez <siglesias@igalia.com>2016-06-17 11:33:18 +0200
commitbdab572a86f27b92ba10124f85d278e9c8861fff (patch)
tree93a3938893bd9ab6d148b1ffda97f8fdb82dbb51 /src/mesa/drivers
parent0177dbb6c2fe876a9761a4a97eec44accfa4c007 (diff)
i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT
From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region Restrictions, page 844: "When source or destination datatype is 64b or operation is integer DWord multiply, indirect addressing must not be used." v2: - Fix it for Broxton too. v3: - Simplify code by using subscript() and not creating a new num_components variable (Kenneth). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Cc: "12.0" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_nir.cpp28
1 files changed, 25 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index d72b37b5854..ad9b421fff4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3611,10 +3611,32 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
unsigned read_size = instr->const_index[1] -
(instr->num_components - 1) * type_sz(dest.type);
+ fs_reg indirect_chv_high_32bit;
+ bool is_chv_bxt_64bit =
+ (devinfo->is_cherryview || devinfo->is_broxton) &&
+ type_sz(dest.type) == 8;
+ if (is_chv_bxt_64bit) {
+ indirect_chv_high_32bit = vgrf(glsl_type::uint_type);
+ /* Calculate indirect address to read high 32 bits */
+ bld.ADD(indirect_chv_high_32bit, indirect, brw_imm_ud(4));
+ }
+
for (unsigned j = 0; j < instr->num_components; j++) {
- bld.emit(SHADER_OPCODE_MOV_INDIRECT,
- offset(dest, bld, j), offset(src, bld, j),
- indirect, brw_imm_ud(read_size));
+ if (!is_chv_bxt_64bit) {
+ bld.emit(SHADER_OPCODE_MOV_INDIRECT,
+ offset(dest, bld, j), offset(src, bld, j),
+ indirect, brw_imm_ud(read_size));
+ } else {
+ bld.emit(SHADER_OPCODE_MOV_INDIRECT,
+ subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 0),
+ offset(src, bld, j),
+ indirect, brw_imm_ud(read_size));
+
+ bld.emit(SHADER_OPCODE_MOV_INDIRECT,
+ subscript(offset(dest, bld, j), BRW_REGISTER_TYPE_UD, 1),
+ offset(src, bld, j),
+ indirect_chv_high_32bit, brw_imm_ud(read_size));
+ }
}
}
break;