i965/vec4: Add and use vec4_instruction::writes_flag().

To be consistent with the fs backend. Also the instruction scheduler
incorrectly considered SEL with a conditional modifier to read the flag
register.

Reviewed-by: Eric Anholt <[email protected]>

2 files changed, 7 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 5449c1bd7bc..e86c258cc5e 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1060,7 +1060,7 @@ vec4_instruction_scheduler::calculate_deps()
          }
       }
 
-      if (inst->conditional_mod) {
+      if (inst->writes_flag()) {
          add_dep(last_conditional_mod, n, 0);
          last_conditional_mod = n;
       }
@@ -1129,7 +1129,7 @@ vec4_instruction_scheduler::calculate_deps()
          }
       }
 
-      if (inst->conditional_mod) {
+      if (inst->writes_flag()) {
          last_conditional_mod = n;
       }
    }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 52cc0582acb..6ea3ca4de94 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -271,6 +271,11 @@ public:
    {
       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
    }
+
+   bool writes_flag()
+   {
+      return conditional_mod && opcode != BRW_OPCODE_SEL;
+   }
 };
 
 /**