diff options
| author | Matt Turner <[email protected]> | 2015-10-19 19:02:16 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2015-10-21 10:17:38 -0700 |
| commit | 2ce659b5e422f7e7639d6e451160c197717df823 (patch) | |
| tree | 2937b4445e06b9b732db0ac7d1d9fcedd21608eb /src/mesa/drivers | |
| parent | 05cc56cca3abac0dc8e34469a260fe3c635a12d8 (diff) | |
i965: Mark compacted 3-src instructions as Gen8+.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_inst.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h b/src/mesa/drivers/dri/i965/brw_inst.h index 524a4fb1d37..db05a8a5f30 100644 --- a/src/mesa/drivers/dri/i965/brw_inst.h +++ b/src/mesa/drivers/dri/i965/brw_inst.h @@ -804,24 +804,24 @@ F(opcode, 6, 0) /* Same location as brw_inst */ * (Gen8+) Compacted three-source instructions: * @{ */ -F(3src_src2_reg_nr, 63, 57) -F(3src_src1_reg_nr, 56, 50) -F(3src_src0_reg_nr, 49, 43) -F(3src_src2_subreg_nr, 42, 40) -F(3src_src1_subreg_nr, 39, 37) -F(3src_src0_subreg_nr, 36, 34) -F(3src_src2_rep_ctrl, 33, 33) -F(3src_src1_rep_ctrl, 32, 32) -F(3src_saturate, 31, 31) -F(3src_debug_control, 30, 30) -F(3src_cmpt_control, 29, 29) -F(3src_src0_rep_ctrl, 28, 28) +FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8) +FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8) +FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8) +FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8) +FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8) +FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8) +FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8) +FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8) +FC(3src_saturate, 31, 31, devinfo->gen >= 8) +FC(3src_debug_control, 30, 30, devinfo->gen >= 8) +FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8) +FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8) /* Reserved */ -F(3src_dst_reg_nr, 18, 12) -F(3src_source_index, 11, 10) -F(3src_control_index, 9, 8) +FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8) +FC(3src_source_index, 11, 10, devinfo->gen >= 8) +FC(3src_control_index, 9, 8, devinfo->gen >= 8) /* Bit 7 is Reserved (for future Opcode expansion) */ -F(3src_opcode, 6, 0) +FC(3src_opcode, 6, 0, devinfo->gen >= 8) /** @} */ #undef F |