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authorIago Toral Quiroga <[email protected]>2016-08-25 11:49:53 +0200
committerSamuel Iglesias Gonsálvez <[email protected]>2017-01-03 11:26:50 +0100
commit9527a50da06f03885aad9e0f6d5693ced6c22bd4 (patch)
tree08ac5f0dc04fa2b1095a7d1cb3b866ad4461946b /src/mesa/drivers
parentb58026b31e7258a4bd2bb630a1d41a433fb01799 (diff)
i965: move exec_size from fs_instruction to backend_instruction
We are going to need this in the vec4 backend too. Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_ir_fs.h7
-rw-r--r--src/mesa/drivers/dri/i965/brw_shader.h7
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp1
3 files changed, 8 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 16ee3d2906c..c569bd473d7 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -368,13 +368,6 @@ public:
uint8_t sources; /**< Number of fs_reg sources. */
/**
- * Execution size of the instruction. This is used by the generator to
- * generate the correct binary for the given fs_inst. Current valid
- * values are 1, 8, 16.
- */
- uint8_t exec_size;
-
- /**
* Channel group from the hardware execution and predication mask that
* should be applied to the instruction. The subset of channel enable
* signals (calculated from the EU control flow and predication state)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index e8b34d59ab6..b5af6ab841f 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -133,6 +133,13 @@ struct backend_instruction {
const char *annotation;
/** @} */
+ /**
+ * Execution size of the instruction. This is used by the generator to
+ * generate the correct binary for the given instruction. Current valid
+ * values are 1, 4, 8, 16, 32.
+ */
+ uint8_t exec_size;
+
uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c615ac0bca0..e88bb7c7e4b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -55,6 +55,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
this->mlen = 0;
this->base_mrf = 0;
this->offset = 0;
+ this->exec_size = 8;
this->annotation = NULL;
}