diff options
author | Iago Toral Quiroga <[email protected]> | 2018-01-08 09:41:23 +0100 |
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committer | Iago Toral Quiroga <[email protected]> | 2018-01-10 08:21:02 +0100 |
commit | 4317c848b9c8f5a650815e20c792fc9f3564b68e (patch) | |
tree | 78e103068adfa7ddf0787c4d39a14a95a191e398 /src/mesa/drivers | |
parent | ea227f4322debd68380feaad1de44a2feaf3d2a9 (diff) |
i965/nir: add a helper to lower gl_PatchVerticesIn to a uniform
v2: do not try to handle it as a system value directly for the SPIR-V
path. In GL we rather handle it as a uniform like we do for the
GLSL path (Jason).
v3:
- Remove the uniform variable, it is alwats -1 now (Jason)
- Also do the lowering for the TessEval stage (Jason)
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp index 9e135cbb1a1..05f61674c3c 100644 --- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp +++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp @@ -243,3 +243,28 @@ brw_nir_setup_arb_uniforms(void *mem_ctx, nir_shader *shader, stage_prog_data->param[4 * p + i] = BRW_PARAM_BUILTIN_ZERO; } } + +void +brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir) +{ + nir_foreach_variable_safe(var, &nir->system_values) { + if (var->data.location != SYSTEM_VALUE_VERTICES_IN) + continue; + + gl_state_index tokens[STATE_LENGTH] = { + STATE_INTERNAL, + nir->info.stage == MESA_SHADER_TESS_CTRL ? + STATE_TCS_PATCH_VERTICES_IN : STATE_TES_PATCH_VERTICES_IN, + }; + var->num_state_slots = 1; + var->state_slots = + ralloc_array(var, nir_state_slot, var->num_state_slots); + memcpy(var->state_slots[0].tokens, tokens, sizeof(tokens)); + var->state_slots[0].swizzle = SWIZZLE_XXXX; + + var->data.mode = nir_var_uniform; + var->data.location = -1; + exec_node_remove(&var->node); + exec_list_push_tail(&nir->uniforms, &var->node); + } +} |