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authorJuha-Pekka Heikkila <[email protected]>2014-03-28 15:28:30 +0200
committerMatt Turner <[email protected]>2014-04-16 22:46:45 -0700
commit09747066714a341b85907c474f18a0d05bbc7071 (patch)
tree821fdd17be5bc82ab1b190cee2803be0dc8ba869 /src/mesa/drivers
parent306ed81b9363721058c568244f9860c5c8c819f4 (diff)
i965/vec4: Add support for the MAC instruction.
This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp1
3 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 5df6bb7d499..f10ad50e9c3 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -183,6 +183,7 @@ ALU1(FBL)
ALU1(CBIT)
ALU2(ADDC)
ALU2(SUBB)
+ALU2(MAC)
ROUND(RNDZ)
ROUND(RNDE)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 5f85d315c71..bcacde92dd1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1081,6 +1081,9 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
assert(brw->gen >= 7);
brw_SUBB(p, dst, src[0], src[1]);
break;
+ case BRW_OPCODE_MAC:
+ brw_MAC(p, dst, src[0], src[1]);
+ break;
case BRW_OPCODE_BFE:
assert(brw->gen >= 7);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 3a764424df8..059dc73adcc 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -175,6 +175,7 @@ ALU1(CBIT)
ALU3(MAD)
ALU2_ACC(ADDC)
ALU2_ACC(SUBB)
+ALU2(MAC)
/** Gen4 predicated IF. */
vec4_instruction *