diff options
| author | Ian Romanick <[email protected]> | 2008-07-25 18:31:44 -0700 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2008-07-25 18:31:44 -0700 |
| commit | 1e645b365900cf1c71ca5594bd6b549a1f203040 (patch) | |
| tree | d114e55df428550c9829acf929b9fb7bcb89c429 /src/mesa/drivers | |
| parent | e5022c3fdf9888857f22f9a1690035ff3f90d36b (diff) | |
| parent | 9bc9e0ecb0fb2069b2c123e665eb2118e358098f (diff) | |
Merge branch 'master' into drm-gem
Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
Diffstat (limited to 'src/mesa/drivers')
125 files changed, 3382 insertions, 26050 deletions
diff --git a/src/mesa/drivers/beos/Makefile b/src/mesa/drivers/beos/Makefile index 342d7ce0243..c79dd24c390 100644 --- a/src/mesa/drivers/beos/Makefile +++ b/src/mesa/drivers/beos/Makefile @@ -181,9 +181,10 @@ $(TOP)/$(LIB_DIR): mkdir $(TOP)/$(LIB_DIR) $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME): $(OBJECTS) $(MESA_MODULES) $(GLU_MODULES) - @$(TOP)/bin/mklib -o $(GL_LIB) -ldflags '$(LDFLAGS)' -install $(TOP)/$(LIB_DIR) \ + @$(MKLIB) -o $(GL_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ - $(MKLIB_OPTIONS) $(GL_LIB_DEPS) $(OBJECTS) $(MESA_MODULES) $(GLU_MODULES) + -install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) $(GL_LIB_DEPS) \ + $(OBJECTS) $(MESA_MODULES) $(GLU_MODULES) # $(GLU_OBJECTS): # cd $(GLU_DIR) && $(MAKE) $< ; diff --git a/src/mesa/drivers/directfb/Makefile b/src/mesa/drivers/directfb/Makefile index ece0457cffa..94c82a2c9c9 100644 --- a/src/mesa/drivers/directfb/Makefile +++ b/src/mesa/drivers/directfb/Makefile @@ -37,7 +37,7 @@ default: directfb-libgl directfbgl_mesa # XXX this used to be in src/mesa/Makefile and is probably broken now directfb-libgl: $(LIBS) - @ $(TOP)/bin/mklib -o $(GL_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ + @ $(MKLIB) -o $(GL_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ -install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) $(LIBS) \ $(GL_LIB_DEPS) diff --git a/src/mesa/drivers/dri/Makefile b/src/mesa/drivers/dri/Makefile index 41dfc67e0cf..3b3fcf11df1 100644 --- a/src/mesa/drivers/dri/Makefile +++ b/src/mesa/drivers/dri/Makefile @@ -20,16 +20,30 @@ subdirs: fi \ done +pcedit = sed \ + -e 's,@INSTALL_DIR@,$(INSTALL_DIR),' \ + -e 's,@INSTALL_LIB_DIR@,$(INSTALL_LIB_DIR),' \ + -e 's,@INSTALL_INC_DIR@,$(INSTALL_INC_DIR),' \ + -e 's,@VERSION@,$(MESA_MAJOR).$(MESA_MINOR).$(MESA_TINY),' \ + -e 's,@DRI_DRIVER_DIR@,$(DRI_DRIVER_SEARCH_DIR),' -install: +dri.pc: dri.pc.in + $(pcedit) $< > $@ + + +install: dri.pc @for dir in $(DRI_DIRS) ; do \ if [ -d $$dir ] ; then \ (cd $$dir && $(MAKE) install) || exit 1 ; \ fi \ done - $(INSTALL) -d $(DESTDIR)$(INSTALL_DIR)/include/GL/internal - $(INSTALL) -m 0644 $(TOP)/include/GL/internal/dri_interface.h $(DESTDIR)$(INSTALL_DIR)/include/GL/internal - $(INSTALL) -m 0644 $(TOP)/include/GL/internal/dri_sarea.h $(DESTDIR)$(INSTALL_DIR)/include/GL/internal + $(INSTALL) -d $(DESTDIR)$(INSTALL_INC_DIR)/GL/internal + $(INSTALL) -m 0644 $(TOP)/include/GL/internal/dri_interface.h \ + $(DESTDIR)$(INSTALL_INC_DIR)/GL/internal + $(INSTALL) -m 0644 $(TOP)/include/GL/internal/dri_sarea.h \ + $(DESTDIR)$(INSTALL_INC_DIR)/GL/internal + $(INSTALL) -d $(DESTDIR)$(INSTALL_LIB_DIR)/pkgconfig + $(INSTALL) -m 0644 dri.pc $(DESTDIR)$(INSTALL_LIB_DIR)/pkgconfig clean: @@ -39,3 +53,4 @@ clean: fi \ done -rm -f common/*.o + -rm -f *.pc diff --git a/src/mesa/drivers/dri/Makefile.template b/src/mesa/drivers/dri/Makefile.template index 7dcb077dca7..072d16ce8bf 100644 --- a/src/mesa/drivers/dri/Makefile.template +++ b/src/mesa/drivers/dri/Makefile.template @@ -63,7 +63,7 @@ default: symlinks depend $(LIBNAME) $(TOP)/$(LIB_DIR)/$(LIBNAME) $(LIBNAME): $(OBJECTS) $(MESA_MODULES) $(WINOBJ) Makefile $(TOP)/src/mesa/drivers/dri/Makefile.template - $(TOP)/bin/mklib -ldflags '$(LDFLAGS)' -noprefix -o $@ \ + $(MKLIB) -o $@ -noprefix -linker '$(CC)' -ldflags '$(LDFLAGS)' \ $(OBJECTS) $(MESA_MODULES) $(WINOBJ) $(DRI_LIB_DEPS) diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index 10d2e801dcc..9655741bbba 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -283,7 +283,7 @@ __driUtilUpdateDrawableInfo(__DRIdrawablePrivate *pdp) int __driParseEvents(__DRIcontextPrivate *pcp, __DRIdrawablePrivate *pdp) { - __DRIscreenPrivate *psp = pcp->driScreenPriv; + __DRIscreenPrivate *psp = pdp->driScreenPriv; __DRIDrawableConfigEvent *dc, *last_dc; __DRIBufferAttachEvent *ba, *last_ba; unsigned int tail, mask, *p, end, total, size, changed; @@ -291,7 +291,7 @@ __driParseEvents(__DRIcontextPrivate *pcp, __DRIdrawablePrivate *pdp) size_t rect_size; /* Check for wraparound. */ - if (psp->dri2.buffer->prealloc - pdp->dri2.tail > psp->dri2.buffer->size) { + if (pcp && psp->dri2.buffer->prealloc - pdp->dri2.tail > psp->dri2.buffer->size) { /* If prealloc overlaps into what we just parsed, the * server overwrote it and we have to reset our tail * pointer. */ @@ -460,6 +460,9 @@ static void driSwapBuffers(__DRIdrawable *dPriv) if (!dPriv->numClipRects) return; + if (psp->dri2.enabled) + __driParseEvents(NULL, dPriv); + psp->DriverAPI.SwapBuffers(dPriv); driReportDamage(dPriv, dPriv->pClipRects, dPriv->numClipRects); diff --git a/src/mesa/drivers/dri/common/extension_helper.h b/src/mesa/drivers/dri/common/extension_helper.h index 65e96657b8a..ea5b9973dde 100644 --- a/src/mesa/drivers/dri/common/extension_helper.h +++ b/src/mesa/drivers/dri/common/extension_helper.h @@ -1077,13 +1077,6 @@ static const char AreTexturesResident_names[] = ""; #endif -#if defined(need_GL_EXT_framebuffer_object) -static const char IsRenderbufferEXT_names[] = - "i\0" /* Parameter signature */ - "glIsRenderbufferEXT\0" - ""; -#endif - #if defined(need_GL_VERSION_2_0) || defined(need_GL_ATI_separate_stencil) static const char StencilOpSeparate_names[] = "iiii\0" /* Parameter signature */ @@ -1763,13 +1756,6 @@ static const char DeleteFencesNV_names[] = ""; #endif -#if defined(need_GL_SGIX_polynomial_ffd) -static const char DeformationMap3dSGIX_names[] = - "iddiiddiiddiip\0" /* Parameter signature */ - "glDeformationMap3dSGIX\0" - ""; -#endif - #if defined(need_GL_VERSION_2_0) static const char IsShader_names[] = "i\0" /* Parameter signature */ @@ -2015,6 +2001,13 @@ static const char WeightfvARB_names[] = ""; #endif +#if defined(need_GL_EXT_framebuffer_object) +static const char IsRenderbufferEXT_names[] = + "i\0" /* Parameter signature */ + "glIsRenderbufferEXT\0" + ""; +#endif + #if defined(need_GL_MESA_window_pos) static const char WindowPos4fMESA_names[] = "ffff\0" /* Parameter signature */ @@ -4530,6 +4523,13 @@ static const char Minmax_names[] = ""; #endif +#if defined(need_GL_SGIX_polynomial_ffd) +static const char DeformationMap3dSGIX_names[] = + "iddiiddiiddiip\0" /* Parameter signature */ + "glDeformationMap3dSGIX\0" + ""; +#endif + #if defined(need_GL_VERSION_1_4) || defined(need_GL_EXT_fog_coord) static const char FogCoorddvEXT_names[] = "p\0" /* Parameter signature */ @@ -5319,13 +5319,13 @@ static const struct dri_extension_function GL_EXT_framebuffer_blit_functions[] = #if defined(need_GL_EXT_framebuffer_object) static const struct dri_extension_function GL_EXT_framebuffer_object_functions[] = { { GenerateMipmapEXT_names, GenerateMipmapEXT_remap_index, -1 }, - { IsRenderbufferEXT_names, IsRenderbufferEXT_remap_index, -1 }, { RenderbufferStorageEXT_names, RenderbufferStorageEXT_remap_index, -1 }, { CheckFramebufferStatusEXT_names, CheckFramebufferStatusEXT_remap_index, -1 }, { DeleteRenderbuffersEXT_names, DeleteRenderbuffersEXT_remap_index, -1 }, { FramebufferTexture3DEXT_names, FramebufferTexture3DEXT_remap_index, -1 }, { FramebufferRenderbufferEXT_names, FramebufferRenderbufferEXT_remap_index, -1 }, { FramebufferTexture1DEXT_names, FramebufferTexture1DEXT_remap_index, -1 }, + { IsRenderbufferEXT_names, IsRenderbufferEXT_remap_index, -1 }, { BindFramebufferEXT_names, BindFramebufferEXT_remap_index, -1 }, { GenRenderbuffersEXT_names, GenRenderbuffersEXT_remap_index, -1 }, { IsFramebufferEXT_names, IsFramebufferEXT_remap_index, -1 }, @@ -5965,9 +5965,9 @@ static const struct dri_extension_function GL_SGIX_pixel_texture_functions[] = { #if defined(need_GL_SGIX_polynomial_ffd) static const struct dri_extension_function GL_SGIX_polynomial_ffd_functions[] = { { LoadIdentityDeformationMapSGIX_names, LoadIdentityDeformationMapSGIX_remap_index, -1 }, - { DeformationMap3dSGIX_names, DeformationMap3dSGIX_remap_index, -1 }, { DeformSGIX_names, DeformSGIX_remap_index, -1 }, { DeformationMap3fSGIX_names, DeformationMap3fSGIX_remap_index, -1 }, + { DeformationMap3dSGIX_names, DeformationMap3dSGIX_remap_index, -1 }, { NULL, 0, 0 } }; #endif diff --git a/src/mesa/drivers/dri/common/texmem.c b/src/mesa/drivers/dri/common/texmem.c index b0e8c4c1c28..caabac3448f 100644 --- a/src/mesa/drivers/dri/common/texmem.c +++ b/src/mesa/drivers/dri/common/texmem.c @@ -1278,6 +1278,7 @@ driCalculateTextureFirstLastLevel( driTextureObject * t ) else { firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5); firstLevel = MAX2(firstLevel, tObj->BaseLevel); + firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); lastLevel = MAX2(lastLevel, t->tObj->BaseLevel); lastLevel = MIN2(lastLevel, t->tObj->BaseLevel + baseImage->MaxLog2); diff --git a/src/mesa/drivers/dri/dri.pc.in b/src/mesa/drivers/dri/dri.pc.in new file mode 100644 index 00000000000..c47ee9c7e7d --- /dev/null +++ b/src/mesa/drivers/dri/dri.pc.in @@ -0,0 +1,10 @@ +prefix=@INSTALL_DIR@ +exec_prefix=${prefix} +libdir=@INSTALL_LIB_DIR@ +includedir=@INSTALL_INC_DIR@ +dridriverdir=@DRI_DRIVER_DIR@ + +Name: dri +Description: Direct Rendering Infrastructure +Version: @VERSION@ +Cflags: -I${includedir} diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c index 4c7a742b982..116b52511f5 100644 --- a/src/mesa/drivers/dri/i915/i830_context.c +++ b/src/mesa/drivers/dri/i915/i830_context.c @@ -42,12 +42,6 @@ * Mesa's Driver Functions ***************************************/ -static const struct dri_extension i830_extensions[] = { - {"GL_ARB_texture_env_crossbar", NULL}, - {NULL, NULL} -}; - - static void i830InitDriverFunctions(struct dd_function_table *functions) { @@ -108,8 +102,6 @@ i830CreateContext(const __GLcontextModes * mesaVis, intel->verts = TNL_CONTEXT(ctx)->clipspace.vertex_buf; - driInitExtensions(ctx, i830_extensions, GL_FALSE); - i830InitState(i830); i830InitMetaFuncs(i830); diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index 46326cf1dc1..940b02513da 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -54,7 +54,6 @@ static const struct dri_extension i915_extensions[] = { {"GL_ARB_depth_texture", NULL}, {"GL_ARB_fragment_program", NULL}, {"GL_ARB_shadow", NULL}, - {"GL_ARB_texture_env_crossbar", NULL}, {"GL_ARB_texture_non_power_of_two", NULL}, {"GL_EXT_shadow_funcs", NULL}, /* ARB extn won't work if not enabled */ diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index af7166e681d..69c1e0755ef 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -257,18 +257,15 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) */ if (tObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB && tObj->Target != GL_TEXTURE_3D) { + if (tObj->Target == GL_TEXTURE_1D) + return GL_FALSE; state[I915_TEXREG_SS2] |= (SS2_SHADOW_ENABLE | intel_translate_shadow_compare_func(tObj->CompareFunc)); - if (tObj->Target == GL_TEXTURE_1D) { - minFilt = FILTER_NEAREST; - magFilt = FILTER_NEAREST; - } else { - minFilt = FILTER_4X4_FLAT; - magFilt = FILTER_4X4_FLAT; - } + minFilt = FILTER_4X4_FLAT; + magFilt = FILTER_4X4_FLAT; } state[I915_TEXREG_SS2] |= ((minFilt << SS2_MIN_FILTER_SHIFT) | diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 7d51cddfc3d..0930e6a5739 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -148,7 +148,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - if (!BRW_IS_IGD(p->brw)) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 22bd38a9f3f..974cb77cb8c 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -102,7 +102,7 @@ clip_unit_create_from_key(struct brw_context *brw, clip.clip5.api_mode = BRW_CLIP_API_OGL; clip.clip5.clip_mode = key->clip_mode; - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) clip.clip5.negative_w_clip_test = 1; clip.clip6.clipper_viewport_state_ptr = 0; diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index f1fc6e1e9da..7c703179fea 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -536,7 +536,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ - if (!BRW_IS_IGD(p->brw)) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index efe850b4d39..b4e2619929a 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -125,7 +125,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, ctx->Const.MaxTextureUnits = BRW_MAX_TEX_UNIT; ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT; ctx->Const.MaxTextureCoordUnits = BRW_MAX_TEX_UNIT; - + ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */ /* Advertise the full hardware capabilities. The new memory * manager should cope much better with overload situations: diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2ed417824d2..0593e8d5f5f 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -740,7 +740,7 @@ #define CMD_STATE_BASE_ADDRESS 0x6101 #define CMD_STATE_INSN_POINTER 0x6102 #define CMD_PIPELINE_SELECT_965 0x6104 -#define CMD_PIPELINE_SELECT_IGD 0x6904 +#define CMD_PIPELINE_SELECT_GM45 0x6904 #define CMD_PIPELINED_STATE_POINTERS 0x7800 #define CMD_BINDING_TABLE_PTRS 0x7801 @@ -772,7 +772,7 @@ #define CMD_INDEX_BUFFER 0x780a #define CMD_VF_STATISTICS_965 0x780b -#define CMD_VF_STATISTICS_IGD 0x680b +#define CMD_VF_STATISTICS_GM45 0x680b #define CMD_DRAW_RECT 0x7900 #define CMD_BLEND_CONSTANT_COLOR 0x7901 @@ -798,9 +798,10 @@ #include "intel_chipset.h" -#define BRW_IS_IGD(brw) (IS_IGD((brw)->intel.intelScreen->deviceID)) -#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_IGD(brw)) ? CMD_PIPELINE_SELECT_IGD : CMD_PIPELINE_SELECT_965) -#define CMD_VF_STATISTICS(brw) ((BRW_IS_IGD(brw)) ? CMD_VF_STATISTICS_IGD : CMD_VF_STATISTICS_965) -#define URB_SIZES(brw) ((BRW_IS_IGD(brw)) ? 384 : 256) /* 512 bit unit */ +#define BRW_IS_GM45(brw) (IS_GM45_GM((brw)->intel.intelScreen->deviceID)) +#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID)) +#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965) +#define CMD_VF_STATISTICS(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965) +#define URB_SIZES(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? 384 : 256) /* 512 bit unit */ #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index fefd30bc7f5..6b97f8b170c 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -329,14 +329,14 @@ static void brw_set_sampler_message(struct brw_context *brw, { brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGD(brw)) { - insn->bits3.sampler_igd.binding_table_index = binding_table_index; - insn->bits3.sampler_igd.sampler = sampler; - insn->bits3.sampler_igd.msg_type = msg_type; - insn->bits3.sampler_igd.response_length = response_length; - insn->bits3.sampler_igd.msg_length = msg_length; - insn->bits3.sampler_igd.end_of_thread = eot; - insn->bits3.sampler_igd.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) { + insn->bits3.sampler_gm45_g4x.binding_table_index = binding_table_index; + insn->bits3.sampler_gm45_g4x.sampler = sampler; + insn->bits3.sampler_gm45_g4x.msg_type = msg_type; + insn->bits3.sampler_gm45_g4x.response_length = response_length; + insn->bits3.sampler_gm45_g4x.msg_length = msg_length; + insn->bits3.sampler_gm45_g4x.end_of_thread = eot; + insn->bits3.sampler_gm45_g4x.msg_target = BRW_MESSAGE_TARGET_SAMPLER; } else { insn->bits3.sampler.binding_table_index = binding_table_index; insn->bits3.sampler.sampler = sampler; diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index b5cf821a938..8a8fb50cb99 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -73,7 +73,10 @@ static GLboolean do_check_fallback(struct brw_context *brw) if (texUnit->_ReallyEnabled) { struct intel_texture_object *intelObj = intel_texture_object(texUnit->_Current); struct gl_texture_image *texImage = intelObj->base.Image[0][intelObj->firstLevel]; - if (texImage->Border) { + if (texImage->Border || + ((texImage->_BaseFormat == GL_DEPTH_COMPONENT) && + ((texImage->TexObject->WrapS == GL_CLAMP_TO_BORDER) || + (texImage->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) { DBG("FALLBACK: texture border\n"); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index bd282352819..653695cdf56 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -194,7 +194,7 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = BRW_IS_IGD(brw) ? sizeof(struct brw_depthbuffer_igd) / 4 : sizeof(struct brw_depthbuffer) / 4; + unsigned int len = (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? sizeof(struct brw_depthbuffer_gm45_g4x) / 4 : sizeof(struct brw_depthbuffer) / 4; if (region == NULL) { BEGIN_BATCH(len, IGNORE_CLIPRECTS); @@ -205,7 +205,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) OUT_BATCH(0); ADVANCE_BATCH(); @@ -242,7 +242,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) OUT_BATCH(0); ADVANCE_BATCH(); @@ -327,7 +327,7 @@ static void upload_aa_line_parameters(struct brw_context *brw) { struct brw_aa_line_parameters balp; - if (!BRW_IS_IGD(brw)) + if (!(BRW_IS_GM45(brw) || BRW_IS_G4X(brw))) return; /* use legacy aa line coverage computation */ diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 1326280e00a..ec865c925a7 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -175,7 +175,7 @@ struct brw_depthbuffer } dword4; }; -struct brw_depthbuffer_igd +struct brw_depthbuffer_gm45_g4x { union header_union header; @@ -1405,7 +1405,7 @@ struct brw_instruction GLuint msg_target:4; GLuint pad1:3; GLuint end_of_thread:1; - } sampler_igd; + } sampler_gm45_g4x; struct brw_urb_immediate urb; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 3cac97c71f4..7767d1369ce 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -867,7 +867,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * Later, clipping will detect ucp[6] and ensure the primitive is * clipped against all fixed planes. */ - if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw)) && !c->key.know_w_is_one) { brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_L, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index ba9168b6efc..9b919b9cfed 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -948,15 +948,16 @@ static void emit_fb_write( struct brw_wm_compile *c, GLuint off = c->key.dest_depth_reg % 2; if (off != 0) { - brw_push_insn_state(p); - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, brw_message_reg(nr), arg1[comp]); - /* 2nd half? */ - brw_MOV(p, brw_message_reg(nr+1), offset(arg1[comp],1)); - brw_pop_insn_state(p); + brw_push_insn_state(p); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + + brw_MOV(p, brw_message_reg(nr), offset(arg1[comp],1)); + /* 2nd half? */ + brw_MOV(p, brw_message_reg(nr+1), arg1[comp+1]); + brw_pop_insn_state(p); } else { - brw_MOV(p, brw_message_reg(nr), arg1[comp]); + brw_MOV(p, brw_message_reg(nr), arg1[comp]); } nr += 2; } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index 80b87b40f79..52d6ecc2238 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -120,8 +120,10 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch, if (batch->cliprect_mode == IGNORE_CLIPRECTS) { batch->cliprect_mode = cliprect_mode; } else { - if (batch->cliprect_mode != cliprect_mode) + if (batch->cliprect_mode != cliprect_mode) { intel_batchbuffer_flush(batch); + batch->cliprect_mode = cliprect_mode; + } } } } diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 2a05d29124e..e9076f9ac97 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -115,7 +115,8 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv, dst_pitch /= 4; } #endif - + /* do space/cliprects check before going any further */ + intel_batchbuffer_require_space(intel->batch, 8 * 4, REFERENCES_CLIPRECTS); again: ret = dri_bufmgr_check_aperture_space(dst->buffer); ret |= dri_bufmgr_check_aperture_space(src->buffer); @@ -275,6 +276,8 @@ intelEmitCopyBlit(struct intel_context *intel, int ret; BATCH_LOCALS; + /* do space/cliprects check before going any further */ + intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); again: ret = dri_bufmgr_check_aperture_space(dst_buffer); ret |= dri_bufmgr_check_aperture_space(src_buffer); diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index d5257ae27e2..77352e6a531 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -197,7 +197,6 @@ intelSetBackClipRects(struct intel_context *intel) } } -#ifdef I915 static void intelUpdatePageFlipping(struct intel_context *intel, GLint areaA, GLint areaB) @@ -267,7 +266,6 @@ intelUpdatePageFlipping(struct intel_context *intel, intel_flip_renderbuffers(intel_fb); intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer); } -#endif /* I915 */ /** * This will be called whenever the currently bound window is moved/resized. @@ -318,9 +316,7 @@ intelWindowMoved(struct intel_context *intel) GLint areaB = driIntersectArea( drw_rect, planeB_rect ); GLuint flags = dPriv->vblFlags; -#ifdef I915 intelUpdatePageFlipping(intel, areaA, areaB); -#endif /* Update vblank info */ @@ -645,7 +641,6 @@ intel_wait_flips(struct intel_context *intel) static GLboolean intelPageFlip(const __DRIdrawablePrivate * dPriv) { -#ifdef I915 struct intel_context *intel; int ret; struct intel_framebuffer *intel_fb = dPriv->driverPrivate; @@ -698,40 +693,8 @@ intelPageFlip(const __DRIdrawablePrivate * dPriv) intel_draw_buffer(&intel->ctx, &intel_fb->Base); return GL_TRUE; -#else - return GL_FALSE; -#endif } -#if 0 -void -intelSwapBuffers(__DRIdrawablePrivate * dPriv) -{ - if (dPriv->driverPrivate) { - const struct gl_framebuffer *fb - = (struct gl_framebuffer *) dPriv->driverPrivate; - if (fb->Visual.doubleBufferMode) { - GET_CURRENT_CONTEXT(ctx); - if (ctx && ctx->DrawBuffer == fb) { - _mesa_notifySwapBuffers(ctx); /* flush pending rendering */ - } - if (intel->doPageFlip) { - intelPageFlip(dPriv); - } - else { - intelCopyBuffer(dPriv); - } - } - } - else { - _mesa_problem(NULL, - "dPriv has no gl_framebuffer pointer in intelSwapBuffers"); - } -} -#else -/* Trunk version: - */ - static GLboolean intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) { @@ -755,9 +718,8 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) if (dPriv->vblFlags & VBLANK_FLAG_SYNC) { swap.seqtype |= DRM_VBLANK_NEXTONMISS; - } else if (interval == 0) { + } else if (interval == 0) return GL_FALSE; - } swap.drawable = dPriv->hHWDrawable; target = swap.sequence = dPriv->vblSeq + interval; @@ -834,6 +796,15 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv) if (!intelScheduleSwap(dPriv, &missed_target)) { driWaitForVBlank(dPriv, &missed_target); + /* + * Update each buffer's vbl_pending so we don't get too out of + * sync + */ + intel_get_renderbuffer(&intel_fb->Base, + BUFFER_BACK_LEFT)->vbl_pending = + intel_get_renderbuffer(&intel_fb->Base, + BUFFER_FRONT_LEFT)->vbl_pending = + dPriv->vblSeq; if (!intelPageFlip(dPriv)) { intelCopyBuffer(dPriv, NULL); } @@ -856,7 +827,6 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv) fprintf(stderr, "%s: drawable has no context!\n", __FUNCTION__); } } -#endif void intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 4a5166263ac..15b9ef43127 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -53,7 +53,7 @@ #define PCI_CHIP_I965_GM 0x2A02 #define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_IGD_GM 0x2A42 +#define PCI_CHIP_GM45_GM 0x2A42 #define PCI_CHIP_IGD_E_G 0x2E02 #define PCI_CHIP_Q45_G 0x2E12 @@ -65,13 +65,12 @@ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ - devid == PCI_CHIP_IGD_GM) + devid == PCI_CHIP_GM45_GM) -#define IS_IGD_GM(devid) (devid == PCI_CHIP_IGD_GM) +#define IS_GM45_GM(devid) (devid == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ devid == PCI_CHIP_G45_G) -#define IS_IGD(devid) (IS_IGD_GM(devid) || IS_G4X(devid)) #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_E7221_G || \ @@ -90,7 +89,8 @@ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_I946_GZ || \ - IS_IGD(devid)) + IS_GM45_GM(devid) || \ + IS_G4X(devid)) #define IS_9XX(devid) (IS_915(devid) || \ IS_945(devid) || \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index f573cf4d4f9..082dfe87e38 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -168,7 +168,9 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_I965_GME: chipset = "Intel(R) 965GME/GLE"; break; - case PCI_CHIP_IGD_GM: + case PCI_CHIP_GM45_GM: + chipset = "Mobile Intel® GM45 Express Chipset"; + break; case PCI_CHIP_IGD_E_G: chipset = "Intel(R) Integrated Graphics Device"; break; @@ -196,9 +198,8 @@ intelGetString(GLcontext * ctx, GLenum name) /** * Extension strings exported by the intel driver. * - * \note - * It appears that ARB_texture_env_crossbar has "disappeared" compared to the - * old i830-specific driver. + * Extensions supported by all chips supported by i830_dri, i915_dri, or + * i965_dri. */ static const struct dri_extension card_extensions[] = { {"GL_ARB_multisample", GL_ARB_multisample_functions}, @@ -210,6 +211,7 @@ static const struct dri_extension card_extensions[] = { {"GL_ARB_texture_cube_map", NULL}, {"GL_ARB_texture_env_add", NULL}, {"GL_ARB_texture_env_combine", NULL}, + {"GL_ARB_texture_env_crossbar", NULL}, {"GL_ARB_texture_env_dot3", NULL}, {"GL_ARB_texture_mirrored_repeat", NULL}, {"GL_ARB_texture_non_power_of_two", NULL }, @@ -266,7 +268,6 @@ static const struct dri_extension brw_extensions[] = { { "GL_EXT_shadow_funcs", NULL }, /* ARB extn won't work if not enabled */ { "GL_SGIX_depth_texture", NULL }, - { "GL_ARB_texture_env_crossbar", NULL }, { "GL_EXT_texture_sRGB", NULL}, { NULL, NULL } }; diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 9205627813c..1b645c72621 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -265,7 +265,10 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, { /* Images with borders are never pulled into mipmap trees. */ - if (image->Border) + if (image->Border || + ((image->_BaseFormat == GL_DEPTH_COMPONENT) && + ((image->TexObject->WrapS == GL_CLAMP_TO_BORDER) || + (image->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) return GL_FALSE; if (image->InternalFormat != mt->internal_format || diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index b8dcd1e0610..c11687a2cf6 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -75,7 +75,10 @@ guess_and_alloc_mipmap_tree(struct intel_context *intel, DBG("%s\n", __FUNCTION__); - if (intelImage->base.Border) + if (intelImage->base.Border || + ((intelImage->base._BaseFormat == GL_DEPTH_COMPONENT) && + ((intelObj->base.WrapS == GL_CLAMP_TO_BORDER) || + (intelObj->base.WrapT == GL_CLAMP_TO_BORDER)))) return; if (intelImage->level > intelObj->base.BaseLevel && diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index b5803fb8130..9fe4aac1492 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -43,6 +43,7 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj) #ifdef I915 firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5); firstLevel = MAX2(firstLevel, tObj->BaseLevel); + firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5); lastLevel = MAX2(lastLevel, tObj->BaseLevel); lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); @@ -140,7 +141,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* Fallback case: */ - if (firstImage->base.Border) { + if (firstImage->base.Border || + ((firstImage->base._BaseFormat == GL_DEPTH_COMPONENT) && + ((tObj->WrapS == GL_CLAMP_TO_BORDER) || + (tObj->WrapT == GL_CLAMP_TO_BORDER)))) { if (intelObj->mt) { intel_miptree_release(intel, &intelObj->mt); } diff --git a/src/mesa/drivers/dri/nouveau/Makefile b/src/mesa/drivers/dri/nouveau/Makefile deleted file mode 100644 index 6ea4594f1e6..00000000000 --- a/src/mesa/drivers/dri/nouveau/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -# src/mesa/drivers/dri/nouveau/Makefile - -TOP = ../../../../.. -include $(TOP)/configs/current - -LIBNAME = nouveau_dri.so - -MINIGLX_SOURCES = - -DRIVER_SOURCES = \ - nouveau_bufferobj.c \ - nouveau_card.c \ - nouveau_context.c \ - nouveau_driver.c \ - nouveau_fbo.c \ - nouveau_fifo.c \ - nouveau_lock.c \ - nouveau_mem.c \ - nouveau_object.c \ - nouveau_screen.c \ - nouveau_span.c \ - nouveau_state.c \ - nouveau_state_cache.c \ - nouveau_shader.c \ - nouveau_shader_0.c \ - nouveau_shader_1.c \ - nouveau_shader_2.c \ - nouveau_tex.c \ - nouveau_swtcl.c \ - nouveau_sync.c \ - nouveau_query.c \ - nv04_state.c \ - nv04_swtcl.c \ - nv10_state.c \ - nv10_swtcl.c \ - nv20_state.c \ - nv20_vertprog.c \ - nv30_state.c \ - nv30_fragprog.c \ - nv30_vertprog.c \ - nv40_fragprog.c \ - nv40_vertprog.c \ - nv50_state.c - -C_SOURCES = \ - $(COMMON_SOURCES) \ - $(DRIVER_SOURCES) - -ASM_SOURCES = - - -include ../Makefile.template - -symlinks: diff --git a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c b/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c deleted file mode 100644 index 25c7b8206a0..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c +++ /dev/null @@ -1,627 +0,0 @@ -#include "bufferobj.h" -#include "enums.h" - -#include "nouveau_bufferobj.h" -#include "nouveau_context.h" -#include "nouveau_drm.h" -#include "nouveau_mem.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" - -#define NOUVEAU_MEM_FREE(mem) do { \ - nouveau_mem_free(ctx, (mem)); \ - (mem) = NULL; \ -} while(0) - -#define DEBUG(fmt,args...) do { \ - if (NOUVEAU_DEBUG & DEBUG_BUFFEROBJ) { \ - fprintf(stderr, "%s: "fmt, __func__, ##args); \ - } \ -} while(0) - -static GLboolean -nouveau_bo_download_from_screen(GLcontext *ctx, GLuint offset, GLuint size, - struct gl_buffer_object *bo) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - nouveau_mem *in_mem; - - DEBUG("bo=%p, offset=%d, size=%d\n", bo, offset, size); - - /* If there's a permanent backing store, blit directly into it */ - if (nbo->cpu_mem) { - if (nbo->cpu_mem != nbo->gpu_mem) { - DEBUG("..cpu_mem\n"); - nouveau_memformat_flat_emit(ctx, nbo->cpu_mem, - nbo->gpu_mem, - offset, offset, size); - } - } else { - DEBUG("..sys_mem\n"); - in_mem = nouveau_mem_alloc(ctx, NOUVEAU_MEM_AGP, size, 0); - if (in_mem) { - DEBUG("....via GART\n"); - /* otherwise, try blitting to faster memory and - * copying from there - */ - nouveau_memformat_flat_emit(ctx, in_mem, nbo->gpu_mem, - 0, offset, size); - nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier, - NvSubMemFormat); - _mesa_memcpy(nbo->cpu_mem_sys + offset, - in_mem->map, size); - NOUVEAU_MEM_FREE(in_mem); - } else { - DEBUG("....direct VRAM copy\n"); - /* worst case, copy directly from vram */ - _mesa_memcpy(nbo->cpu_mem_sys + offset, - nbo->gpu_mem + offset, - size); - } - } - - return GL_TRUE; -} - -static GLboolean -nouveau_bo_upload_to_screen(GLcontext *ctx, GLuint offset, GLuint size, - struct gl_buffer_object *bo) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - nouveau_mem *out_mem; - - DEBUG("bo=%p, offset=%d, size=%d\n", bo, offset, size); - - if (nbo->cpu_mem) { - if (nbo->cpu_mem != nbo->gpu_mem) { - DEBUG("..cpu_mem\n"); - nouveau_memformat_flat_emit(ctx, nbo->gpu_mem, - nbo->cpu_mem, - offset, offset, size); - } - } else { - out_mem = nouveau_mem_alloc(ctx, NOUVEAU_MEM_AGP | - NOUVEAU_MEM_MAPPED, - size, 0); - if (out_mem) { - DEBUG("....via GART\n"); - _mesa_memcpy(out_mem->map, - nbo->cpu_mem_sys + offset, size); - nouveau_memformat_flat_emit(ctx, nbo->gpu_mem, out_mem, - offset, 0, size); - nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier, - NvSubMemFormat); - NOUVEAU_MEM_FREE(out_mem); - } else { - DEBUG("....direct VRAM copy\n"); - _mesa_memcpy(nbo->gpu_mem->map + offset, - nbo->cpu_mem_sys + offset, - size); - } - } - - return GL_TRUE; -} - -GLboolean -nouveau_bo_move_in(GLcontext *ctx, struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - - DEBUG("bo=%p\n", bo); - - if (bo->OnCard) - return GL_TRUE; - assert(nbo->gpu_mem_flags); - - nbo->gpu_mem = nouveau_mem_alloc(ctx, nbo->gpu_mem_flags | - NOUVEAU_MEM_MAPPED, - bo->Size, 0); - assert(nbo->gpu_mem); - - if (nbo->cpu_mem_flags) { - if ((nbo->cpu_mem_flags|NOUVEAU_MEM_MAPPED) != nbo->gpu_mem->type) { - DEBUG("..need cpu_mem buffer\n"); - - nbo->cpu_mem = nouveau_mem_alloc(ctx, - nbo->cpu_mem_flags | - NOUVEAU_MEM_MAPPED, - bo->Size, 0); - - if (nbo->cpu_mem) { - DEBUG("....alloc ok, kill sys_mem buffer\n"); - _mesa_memcpy(nbo->cpu_mem->map, - nbo->cpu_mem_sys, bo->Size); - FREE(nbo->cpu_mem_sys); - } - } else { - DEBUG("..cpu direct access to GPU buffer\n"); - nbo->cpu_mem = nbo->gpu_mem; - } - } - nouveau_bo_upload_to_screen(ctx, 0, bo->Size, bo); - - bo->OnCard = GL_TRUE; - return GL_TRUE; -} - -GLboolean -nouveau_bo_move_out(GLcontext *ctx, struct gl_buffer_object *bo) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - GLuint nr_dirty; - - DEBUG("bo=%p\n", bo); - if (!bo->OnCard) - return GL_TRUE; - - nr_dirty = nouveau_bo_download_dirty(ctx, bo); - if (nbo->cpu_mem) { - if (nr_dirty && nbo->cpu_mem != nbo->gpu_mem) - nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier, - NvSubMemFormat); - DEBUG("..destroy cpu_mem buffer\n"); - nbo->cpu_mem_sys = malloc(bo->Size); - assert(nbo->cpu_mem_sys); - _mesa_memcpy(nbo->cpu_mem_sys, nbo->cpu_mem->map, bo->Size); - if (nbo->cpu_mem == nbo->gpu_mem) - nbo->cpu_mem = NULL; - else - NOUVEAU_MEM_FREE(nbo->cpu_mem); - } - NOUVEAU_MEM_FREE(nbo->gpu_mem); - - bo->OnCard = GL_FALSE; - return GL_TRUE; -} - -static void -nouveau_bo_choose_storage_method(GLcontext *ctx, GLenum usage, - struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - GLuint gpu_type = 0; - GLuint cpu_type = 0; - - switch (usage) { - /* Client source, changes often, used by GL many times */ - case GL_DYNAMIC_DRAW_ARB: - gpu_type = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE; - cpu_type = NOUVEAU_MEM_AGP; - break; - /* GL source, changes often, client reads many times */ - case GL_DYNAMIC_READ_ARB: - /* Client source, specified once, used by GL many times */ - case GL_STATIC_DRAW_ARB: - /* GL source, specified once, client reads many times */ - case GL_STATIC_READ_ARB: - /* Client source, specified once, used by GL a few times */ - case GL_STREAM_DRAW_ARB: - /* GL source, specified once, client reads a few times */ - case GL_STREAM_READ_ARB: - /* GL source, changes often, used by GL many times*/ - case GL_DYNAMIC_COPY_ARB: - /* GL source, specified once, used by GL many times */ - case GL_STATIC_COPY_ARB: - /* GL source, specified once, used by GL a few times */ - case GL_STREAM_COPY_ARB: - gpu_type = NOUVEAU_MEM_FB; - break; - default: - assert(0); - } - - nbo->gpu_mem_flags = gpu_type; - nbo->cpu_mem_flags = cpu_type; - nbo->usage = usage; -} - -void -nouveau_bo_init_storage(GLcontext *ctx, GLuint valid_gpu_access, - GLsizeiptrARB size, - const GLvoid *data, - GLenum usage, - struct gl_buffer_object *bo, int flags) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - - DEBUG("bo=%p\n", bo); - - /* Free up previous buffers if we can't reuse them */ - if (nbo->usage != usage || - (nbo->gpu_mem && (nbo->gpu_mem->size != size))) { - if (nbo->cpu_mem_sys) - FREE(nbo->cpu_mem_sys); - if (nbo->cpu_mem) { - if (nbo->cpu_mem != nbo->gpu_mem) - NOUVEAU_MEM_FREE(nbo->cpu_mem); - else - nbo->cpu_mem = NULL; - } - if (nbo->gpu_mem) - NOUVEAU_MEM_FREE(nbo->gpu_mem); - - bo->OnCard = GL_FALSE; - nbo->cpu_mem_sys = calloc(1, size); - } - - nouveau_bo_choose_storage_method(ctx, usage, bo); - /* Force off flags that may not be ok for a given buffer */ - nbo->gpu_mem_flags &= valid_gpu_access; - - bo->Usage = usage; - bo->Size = size; - - if (data) { - GLvoid *map = nouveau_bo_map(ctx, GL_WRITE_ONLY_ARB, bo); -#ifdef MESA_BIG_ENDIAN - int i; - if (flags) { - for (i = 0; i < size; i+=4) { - uint32_t _data = *(unsigned int *)(data+i); - _data = ((_data >> 16) | ((_data & 0xffff) << 16)); - *(unsigned int *)(map+i) = _data; - } - } else -#endif - _mesa_memcpy(map, data, size); - (void)flags; /* get rid of warning */ - nouveau_bo_dirty_all(ctx, GL_FALSE, bo); - nouveau_bo_unmap(ctx, bo); - } -} - -void * -nouveau_bo_map(GLcontext *ctx, GLenum access, struct gl_buffer_object *bo) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - - DEBUG("bo=%p, access=%s\n", bo, _mesa_lookup_enum_by_nr(access)); - - if (bo->OnCard && - (access == GL_READ_ONLY_ARB || access == GL_READ_WRITE_ARB)) { - GLuint nr_dirty; - - DEBUG("..on card\n"); - nr_dirty = nouveau_bo_download_dirty(ctx, bo); - - /* nouveau_bo_download_dirty won't wait unless it needs to - * free a temp buffer, which isn't the case if cpu_mem is - * present. - */ - if (nr_dirty && nbo->cpu_mem && nbo->cpu_mem != nbo->gpu_mem) - nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier, - NvSubMemFormat); - } - - if (nbo->cpu_mem) { - DEBUG("..access via cpu_mem\n"); - return nbo->cpu_mem->map; - } else { - DEBUG("..access via cpu_mem_sys\n"); - return nbo->cpu_mem_sys; - } -} - -void -nouveau_bo_unmap(GLcontext *ctx, struct gl_buffer_object *bo) -{ - DEBUG("unmap bo=%p\n", bo); -} - -uint32_t -nouveau_bo_gpu_ref(GLcontext *ctx, struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - - assert(nbo->mapped == GL_FALSE); - - DEBUG("gpu_ref\n"); - - if (!bo->OnCard) { - nouveau_bo_move_in(ctx, bo); - bo->OnCard = GL_TRUE; - } - nouveau_bo_upload_dirty(ctx, bo); - - return nouveau_mem_gpu_offset_get(ctx, nbo->gpu_mem); -} - -void -nouveau_bo_dirty_linear(GLcontext *ctx, GLboolean on_card, - uint32_t offset, uint32_t size, - struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - nouveau_bufferobj_dirty *dirty; - uint32_t start = offset; - uint32_t end = offset + size; - int i; - - if (nbo->cpu_mem == nbo->gpu_mem) - return; - - dirty = on_card ? &nbo->gpu_dirty : &nbo->cpu_dirty; - - DEBUG("on_card=%d, offset=%d, size=%d, bo=%p\n", - on_card, offset, size, bo); - - for (i=0; i<dirty->nr_dirty; i++) { - nouveau_bufferobj_region *r = &dirty->dirty[i]; - - /* already dirty */ - if (start >= r->start && end <= r->end) { - DEBUG("..already dirty\n"); - return; - } - - /* add to the end of a region */ - if (start >= r->start && start <= r->end) { - if (end > r->end) { - DEBUG("..extend end of region\n"); - r->end = end; - return; - } - } - - /* add to the start of a region */ - if (start < r->start && end >= r->end) { - DEBUG("..extend start of region\n"); - r->start = start; - /* .. and to the end */ - if (end > r->end) { - DEBUG("....and end\n"); - r->end = end; - } - return; - } - } - - /* new region */ - DEBUG("..new dirty\n"); - dirty->nr_dirty++; - dirty->dirty = realloc(dirty->dirty, - sizeof(nouveau_bufferobj_region) * - dirty->nr_dirty); - dirty->dirty[dirty->nr_dirty - 1].start = start; - dirty->dirty[dirty->nr_dirty - 1].end = end; -} - -void -nouveau_bo_dirty_all(GLcontext *ctx, GLboolean on_card, - struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - nouveau_bufferobj_dirty *dirty; - - dirty = on_card ? &nbo->gpu_dirty : &nbo->cpu_dirty; - - DEBUG("dirty all\n"); - if (dirty->nr_dirty) { - FREE(dirty->dirty); - dirty->dirty = NULL; - dirty->nr_dirty = 0; - } - - nouveau_bo_dirty_linear(ctx, on_card, 0, bo->Size, bo); -} - -GLuint -nouveau_bo_upload_dirty(GLcontext *ctx, struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - nouveau_bufferobj_dirty *dirty = &nbo->cpu_dirty; - GLuint nr_dirty; - int i; - - nr_dirty = dirty->nr_dirty; - if (!nr_dirty) { - DEBUG("clean\n"); - return nr_dirty; - } - - for (i=0; i<nr_dirty; i++) { - nouveau_bufferobj_region *r = &dirty->dirty[i]; - - DEBUG("dirty %d: o=0x%08x, s=0x%08x\n", - i, r->start, r->end - r->start); - nouveau_bo_upload_to_screen(ctx, - r->start, r->end - r->start, bo); - } - - FREE(dirty->dirty); - dirty->dirty = NULL; - dirty->nr_dirty = 0; - - return nr_dirty; -} - -GLuint -nouveau_bo_download_dirty(GLcontext *ctx, struct gl_buffer_object *bo) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo; - nouveau_bufferobj_dirty *dirty = &nbo->gpu_dirty; - GLuint nr_dirty; - int i; - - nr_dirty = dirty->nr_dirty; - if (nr_dirty) { - DEBUG("clean\n"); - return nr_dirty; - } - - for (i=0; i<nr_dirty; i++) { - nouveau_bufferobj_region *r = &dirty->dirty[i]; - - DEBUG("dirty %d: o=0x%08x, s=0x%08x\n", - i, r->start, r->end - r->start); - nouveau_bo_download_from_screen(ctx, - r->start, - r->end - r->start, bo); - } - - FREE(dirty->dirty); - dirty->dirty = NULL; - dirty->nr_dirty = 0; - - return nr_dirty; -} - -static void -nouveauBindBuffer(GLcontext *ctx, GLenum target, struct gl_buffer_object *obj) -{ -} - -static struct gl_buffer_object * -nouveauNewBufferObject(GLcontext *ctx, GLuint buffer, GLenum target) -{ - nouveau_buffer_object *nbo; - - nbo = CALLOC_STRUCT(nouveau_buffer_object_t); - if (nbo) - _mesa_initialize_buffer_object(&nbo->mesa, buffer, target); - DEBUG("bo=%p\n", nbo); - - return nbo ? &nbo->mesa : NULL; -} - -static void -nouveauDeleteBuffer(GLcontext *ctx, struct gl_buffer_object *obj) -{ - nouveau_buffer_object *nbo = (nouveau_buffer_object *)obj; - - if (nbo->gpu_dirty.nr_dirty) - FREE(nbo->gpu_dirty.dirty); - if (nbo->cpu_dirty.nr_dirty) - FREE(nbo->cpu_dirty.dirty); - if (nbo->cpu_mem) nouveau_mem_free(ctx, nbo->cpu_mem); - if (nbo->gpu_mem) nouveau_mem_free(ctx, nbo->gpu_mem); - - _mesa_delete_buffer_object(ctx, obj); -} - -static void -nouveauBufferData(GLcontext *ctx, GLenum target, GLsizeiptrARB size, - const GLvoid *data, GLenum usage, - struct gl_buffer_object *obj) -{ - GLuint gpu_flags; - - DEBUG("target=%s, size=%d, data=%p, usage=%s, obj=%p\n", - _mesa_lookup_enum_by_nr(target), - (GLuint)size, data, - _mesa_lookup_enum_by_nr(usage), - obj); - - switch (target) { - case GL_ELEMENT_ARRAY_BUFFER_ARB: - gpu_flags = 0; - break; - default: - gpu_flags = NOUVEAU_BO_VRAM_OK | NOUVEAU_BO_GART_OK; - break; - } - nouveau_bo_init_storage(ctx, gpu_flags, size, data, usage, obj, 0); -} - -static void -nouveauBufferSubData(GLcontext *ctx, GLenum target, GLintptrARB offset, - GLsizeiptrARB size, const GLvoid *data, - struct gl_buffer_object *obj) -{ - GLvoid *out; - - DEBUG("target=%s, offset=0x%x, size=%d, data=%p, obj=%p\n", - _mesa_lookup_enum_by_nr(target), - (GLuint)offset, (GLuint)size, data, obj); - - out = nouveau_bo_map(ctx, GL_WRITE_ONLY_ARB, obj); - _mesa_memcpy(out + offset, data, size); - nouveau_bo_dirty_linear(ctx, GL_FALSE, offset, size, obj); - nouveau_bo_unmap(ctx, obj); -} - -static void -nouveauGetBufferSubData(GLcontext *ctx, GLenum target, GLintptrARB offset, - GLsizeiptrARB size, GLvoid *data, - struct gl_buffer_object *obj) -{ - const GLvoid *in; - - DEBUG("target=%s, offset=0x%x, size=%d, data=%p, obj=%p\n", - _mesa_lookup_enum_by_nr(target), - (GLuint)offset, (GLuint)size, data, obj); - - in = nouveau_bo_map(ctx, GL_READ_ONLY_ARB, obj); - _mesa_memcpy(data, in + offset, size); - nouveau_bo_unmap(ctx, obj); -} - -static void * -nouveauMapBuffer(GLcontext *ctx, GLenum target, GLenum access, - struct gl_buffer_object *obj) -{ - DEBUG("target=%s, access=%s, obj=%p\n", - _mesa_lookup_enum_by_nr(target), - _mesa_lookup_enum_by_nr(access), - obj - ); - - /* Already mapped.. */ - if (obj->Pointer) - return NULL; - - /* Have to pass READ_WRITE here, nouveau_bo_map will only ensure that - * the cpu_mem buffer is up-to-date if we ask for read access. - * - * However, even if the client only asks for write access, we're still - * forced to reupload the entire buffer. So, we need the cpu_mem buffer - * to have the correct data all the time. - */ - obj->Pointer = nouveau_bo_map(ctx, GL_READ_WRITE_ARB, obj); - - /* The GL spec says that a client attempting to write to a bufferobj - * mapped READ_ONLY object may have unpredictable results, possibly - * even program termination. - * - * We're going to use this, and only mark the buffer as dirtied if - * the client asks for write access. - */ - if (target != GL_READ_ONLY_ARB) { - /* We have no way of knowing what was modified by the client, - * so the entire buffer gets dirtied. */ - nouveau_bo_dirty_all(ctx, GL_FALSE, obj); - } - - return obj->Pointer; -} - -static GLboolean -nouveauUnmapBuffer(GLcontext *ctx, GLenum target, struct gl_buffer_object *obj) -{ - DEBUG("target=%s, obj=%p\n", _mesa_lookup_enum_by_nr(target), obj); - - assert(obj->Pointer); - - nouveau_bo_unmap(ctx, obj); - obj->Pointer = NULL; - return GL_TRUE; -} - -void -nouveauInitBufferObjects(GLcontext *ctx) -{ - ctx->Driver.BindBuffer = nouveauBindBuffer; - ctx->Driver.NewBufferObject = nouveauNewBufferObject; - ctx->Driver.DeleteBuffer = nouveauDeleteBuffer; - ctx->Driver.BufferData = nouveauBufferData; - ctx->Driver.BufferSubData = nouveauBufferSubData; - ctx->Driver.GetBufferSubData = nouveauGetBufferSubData; - ctx->Driver.MapBuffer = nouveauMapBuffer; - ctx->Driver.UnmapBuffer = nouveauUnmapBuffer; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h b/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h deleted file mode 100644 index fb3afc1c300..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef __NOUVEAU_BUFFEROBJ_H__ -#define __NOUVEAU_BUFFEROBJ_H__ - -#include "mtypes.h" -#include "nouveau_mem.h" - -#define NOUVEAU_BO_VRAM_OK (NOUVEAU_MEM_FB | NOUVEAU_MEM_FB_ACCEPTABLE) -#define NOUVEAU_BO_GART_OK (NOUVEAU_MEM_AGP | NOUVEAU_MEM_AGP_ACCEPTABLE) - -typedef struct nouveau_bufferobj_region_t { - uint32_t start; - uint32_t end; -} nouveau_bufferobj_region; - -typedef struct nouveau_bufferobj_dirty_t { - nouveau_bufferobj_region *dirty; - int nr_dirty; -} nouveau_bufferobj_dirty; - -typedef struct nouveau_buffer_object_t { - /* Base class, must be first */ - struct gl_buffer_object mesa; - - GLboolean mapped; - GLenum usage; - - /* Memory used for GPU access to the buffer*/ - GLuint gpu_mem_flags; - nouveau_mem * gpu_mem; - nouveau_bufferobj_dirty gpu_dirty; - - /* Memory used for CPU access to the buffer */ - GLuint cpu_mem_flags; - nouveau_mem * cpu_mem; - GLvoid * cpu_mem_sys; - nouveau_bufferobj_dirty cpu_dirty; -} nouveau_buffer_object; - -extern void -nouveau_bo_init_storage(GLcontext *ctx, GLuint valid_gpu_access, - GLsizeiptrARB size, const GLvoid *data, GLenum usage, - struct gl_buffer_object *bo, int flags); - -extern GLboolean -nouveau_bo_move_in(GLcontext *ctx, struct gl_buffer_object *bo); - -extern GLboolean -nouveau_bo_move_out(GLcontext *ctx, struct gl_buffer_object *bo); - -extern void * -nouveau_bo_map(GLcontext *ctx, GLenum usage, struct gl_buffer_object *bo); - -extern void -nouveau_bo_unmap(GLcontext *ctx, struct gl_buffer_object *bo); - -extern uint32_t -nouveau_bo_gpu_ref(GLcontext *ctx, struct gl_buffer_object *bo); - -extern void -nouveau_bo_dirty_linear(GLcontext *ctx, GLboolean on_card, - uint32_t offset, uint32_t size, - struct gl_buffer_object *bo); - -extern void -nouveau_bo_dirty_all(GLcontext *ctx, GLboolean on_card, - struct gl_buffer_object *bo); - -extern GLuint -nouveau_bo_upload_dirty(GLcontext *ctx, struct gl_buffer_object *bo); - -extern GLuint -nouveau_bo_download_dirty(GLcontext *ctx, struct gl_buffer_object *bo); - -extern void -nouveauInitBufferObjects(GLcontext *ctx); - -#endif diff --git a/src/mesa/drivers/dri/nouveau/nouveau_card.c b/src/mesa/drivers/dri/nouveau/nouveau_card.c deleted file mode 100644 index 91f12f0d704..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_card.c +++ /dev/null @@ -1,17 +0,0 @@ - -#include "nouveau_card.h" -#include "nouveau_reg.h" -#include "nouveau_drm.h" -#include "nouveau_card_list.h" - - -nouveau_card* nouveau_card_lookup(uint32_t device_id) -{ - int i; - for(i=0;i<sizeof(nouveau_card_list)/sizeof(nouveau_card)-1;i++) - if (nouveau_card_list[i].id==(device_id&0xffff)) - return &(nouveau_card_list[i]); - return NULL; -} - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_card.h b/src/mesa/drivers/dri/nouveau/nouveau_card.h deleted file mode 100644 index 8a4c5f2244e..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_card.h +++ /dev/null @@ -1,49 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#ifndef __NOUVEAU_CARD_H__ -#define __NOUVEAU_CARD_H__ - -#include "dri_util.h" -#include "drm.h" -#include "nouveau_drm.h" - -typedef struct nouveau_card_t { - uint16_t id; /* last 4 digits of pci id, last digit is always 0 */ - char* name; /* the user-friendly card name */ - uint32_t class_3d; /* the object class this card uses for 3D */ - uint32_t type; /* the major card family */ - uint32_t flags; -} -nouveau_card; - -#define NV_HAS_LMA 0x00000001 - -extern nouveau_card* nouveau_card_lookup(uint32_t device_id); - -#endif - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_card_list.h b/src/mesa/drivers/dri/nouveau/nouveau_card_list.h deleted file mode 100644 index 94f170e057d..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_card_list.h +++ /dev/null @@ -1,226 +0,0 @@ -static nouveau_card nouveau_card_list[]={ -{0x0020, "RIVA TNT", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x0028, "RIVA TNT2/TNT2 Pro", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x0029, "RIVA TNT2 Ultra", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002A, "Riva TnT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002B, "Riva TnT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002C, "Vanta/Vanta LT", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002D, "RIVA TNT2 Model 64/Model 64 Pro", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002E, "Vanta", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002F, "Vanta", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x0040, "GeForce 6800 Ultra", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0041, "GeForce 6800", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0042, "GeForce 6800 LE", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0043, "NV40.3", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0044, "GeForce 6800 XT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0045, "GeForce 6800 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0046, "GeForce 6800 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0047, "GeForce 6800 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0048, "GeForce 6800 XT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0049, "NV40GL", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x004D, "Quadro FX 4000", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x004E, "Quadro FX 4000", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0090, "GeForce 7800 GTX", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0091, "GeForce 7800 GTX", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0092, "GeForce 7800 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0093, "GeForce 7800 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0098, "GeForce Go 7800", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0099, "GE Force Go 7800 GTX", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x009D, "Quadro FX4500", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00A0, "Aladdin TNT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x00C0, "GeForce 6800 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00C1, "GeForce 6800", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00C2, "GeForce 6800 LE", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00C3, "Geforce 6800 XT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00C8, "GeForce Go 6800", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00C9, "GeForce Go 6800 Ultra", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00CC, "Quadro FX Go1400", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00CD, "Quadro FX 3450/4000 SDI", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00CE, "Quadro FX 1400", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F0, "GeForce 6800/GeForce 6800 Ultra", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F1, "GeForce 6600/GeForce 6600 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F2, "GeForce 6600/GeForce 6600 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F3, "GeForce 6200", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F4, "GeForce 6600 LE", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F5, "GeForce 7800 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F6, "GeForce 6600 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F8, "Quadro FX 3400/4400", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00F9, "GeForce 6800 Ultra/GeForce 6800 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x00FA, "GeForce PCX 5750", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x00FB, "GeForce PCX 5900", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x00FC, "Quadro FX 330/GeForce PCX 5300", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x00FD, "Quadro FX 330/Quadro NVS280", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x00FE, "Quadro FX 1300", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x00FF, "GeForce PCX 4300", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0100, "GeForce 256 SDR", NV10_TCL_PRIMITIVE_3D, NV_10, 0}, -{0x0101, "GeForce 256 DDR", NV10_TCL_PRIMITIVE_3D, NV_10, 0}, -{0x0103, "Quadro", NV10_TCL_PRIMITIVE_3D, NV_10, 0}, -{0x0110, "GeForce2 MX/MX 400", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0111, "GeForce2 MX 100 DDR/200 DDR", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0112, "GeForce2 Go", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0113, "Quadro2 MXR/EX/Go", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0140, "GeForce 6600 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0141, "GeForce 6600", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0142, "GeForce 6600 PCIe", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0144, "GeForce Go 6600", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0145, "GeForce 6610 XL", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0146, "Geforce Go 6600TE/6200TE", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0148, "GeForce Go 6600", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0149, "GeForce Go 6600 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x014A, "Quadro NVS 440", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x014C, "Quadro FX 550", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x014D, "Quadro FX 550", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x014E, "Quadro FX 540", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x014F, "GeForce 6200", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0150, "GeForce2 GTS/Pro", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0151, "GeForce2 Ti", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0152, "GeForce2 Ultra, Bladerunner", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0153, "Quadro2 Pro", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x0161, "GeForce 6200 TurboCache(TM)", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0162, "GeForce 6200 SE TurboCache (TM)", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0163, "GeForce 6200 LE", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0164, "GeForce Go 6200", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0165, "Quadro NVS 285", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0166, "GeForce Go 6400", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0167, "GeForce Go 6200 TurboCache", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0168, "GeForce Go 6200 TurboCache", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0170, "GeForce4 MX 460", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0171, "GeForce4 MX 440", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0172, "GeForce4 MX 420", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0173, "GeForce4 MX 440-SE", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0174, "GeForce4 440 Go", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0175, "GeForce4 420 Go", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0176, "GeForce4 420 Go 32M", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0177, "GeForce4 460 Go", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0178, "Quadro4 550 XGL", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0179, "GeForce4 420 Go 32M", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x017A, "Quadro4 200/400 NVS", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x017B, "Quadro4 550 XGL", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x017C, "Quadro4 500 GoGL", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x017D, "GeForce4 410 Go 16M", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0181, "GeForce4 MX 440 AGP 8x", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0182, "GeForce4 MX 440SE AGP 8x", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0183, "GeForce4 MX 420 AGP 8x", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0185, "GeForce4 MX 4000 AGP 8x", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0186, "GeForce4 448 Go", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0187, "GeForce4 488 Go", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0188, "Quadro4 580 XGL", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x018A, "Quadro4 NVS AGP 8x", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x018B, "Quadro4 380 XGL", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x018C, "Quadro NVS 50 PCI", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x018D, "GeForce4 448 Go", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0191, "GeForce 8800 GTX", NV30_TCL_PRIMITIVE_3D|0x5000, NV_50, 0}, -{0x0193, "GeForce 8800 GTS", NV30_TCL_PRIMITIVE_3D|0x5000, NV_50, 0}, -{0x01A0, "GeForce2 MX Integrated Graphics", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, -{0x01D1, "GeForce 7300 LE", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01D3, "GeForce 7300 SE", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01D6, "GeForce Go 7200", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01D7, "Quadro NVS 110M / GeForce Go 7300", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01D8, "GeForce Go 7400", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01DA, "Quadro NVS 110M", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01DF, "GeForce 7300 GS", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x01F0, "GeForce4 MX - nForce GPU", NV17_TCL_PRIMITIVE_3D, NV_17, 0}, -{0x0200, "GeForce3", NV20_TCL_PRIMITIVE_3D, NV_20, 0}, -{0x0201, "GeForce3 Ti 200", NV20_TCL_PRIMITIVE_3D, NV_20, 0}, -{0x0202, "GeForce3 Ti 500", NV20_TCL_PRIMITIVE_3D, NV_20, 0}, -{0x0203, "Quadro DCC", NV20_TCL_PRIMITIVE_3D, NV_20, 0}, -{0x0211, "GeForce 6800", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0212, "GeForce 6800 LE", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0215, "GeForce 6800 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0218, "GeForce 6800 XT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0221, "GeForce 6200", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0240, "GeForce 6150", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0242, "GeForce 6100", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0244, "Geforce 6150 Go", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0250, "GeForce4 Ti 4600", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0251, "GeForce4 Ti 4400", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0252, "GeForce4 Ti", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0253, "GeForce4 Ti 4200", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0258, "Quadro4 900 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0259, "Quadro4 750 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x025B, "Quadro4 700 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0280, "GeForce4 Ti 4800", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0281, "GeForce4 Ti 4200 AGP 8x", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0282, "GeForce4 Ti 4800 SE", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0286, "GeForce4 Ti 4200 Go AGP 8x", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0288, "Quadro4 980 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0289, "Quadro4 780 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x028C, "Quadro4 700 GoGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, -{0x0290, "GeForce 7900 GTX", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0291, "GeForce 7900 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0292, "GeForce 7900 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0298, "GeForce Go 7900 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0299, "GeForce Go 7900 GTX", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x029A, "Quadro FX 2500M", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x029B, "Quadro FX 1500M", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x029C, "Quadro FX 5500", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x029D, "Quadro FX 3500", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x029E, "Quadro FX 1500", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x029F, "Quadro FX 4500 X2", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x02A0, "XGPU", NV20_TCL_PRIMITIVE_3D, NV_20, 0}, -{0x02E1, "GeForce 7600 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0300, "GeForce FX", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0301, "GeForce FX 5800 Ultra", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0302, "GeForce FX 5800", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0308, "Quadro FX 2000", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0309, "Quadro FX 1000", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0311, "GeForce FX 5600 Ultra", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0312, "GeForce FX 5600", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0313, "NV31", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0314, "GeForce FX 5600XT", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0316, "NV31M", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0317, "NV31M Pro", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x031A, "GeForce FX Go5600", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x031B, "GeForce FX Go5650", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x031C, "NVIDIA Quadro FX Go700", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x031D, "NV31GLM", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x031E, "NV31GLM Pro", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x031F, "NV31GLM Pro", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0320, "GeForce FX 5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0321, "GeForce FX 5200 Ultra", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0322, "GeForce FX 5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0323, "GeForce FX 5200LE", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0324, "GeForce FX Go5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0325, "GeForce FX Go5250", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0326, "GeForce FX 5500", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0327, "GeForce FX 5100", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0328, "GeForce FX Go5200 32M/64M", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0329, "GeForce FX Go5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x032A, "Quadro NVS 280 PCI", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x032B, "Quadro FX 500/600 PCI", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x032C, "GeForce FX Go 5300", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x032D, "GeForce FX Go5100", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x032F, "NV34GL", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, -{0x0330, "GeForce FX 5900 Ultra", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0331, "GeForce FX 5900", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0332, "GeForce FX 5900XT", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0333, "GeForce FX 5950 Ultra", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0334, "GeForce FX 5900ZT", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0338, "Quadro FX 3000", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x033F, "Quadro FX 700", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0341, "GeForce FX 5700 Ultra", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0342, "GeForce FX 5700", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0343, "GeForce FX 5700LE", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0344, "GeForce FX 5700VE", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0345, "NV36.5", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0347, "GeForce FX Go5700", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0348, "GeForce FX Go5700", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0349, "NV36M Pro", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x034B, "NV36MAP", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x034C, "Quadro FX Go1000", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x034E, "Quadro FX 1100", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x034F, "NV36GL", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -{0x0391, "GeForce 7600 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0392, "GeForce 7600 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0393, "GeForce 7300 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0398, "GeForce Go 7600", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x03D0, "GeForce 6100 nForce 430", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x03D1, "GeForce 6100 nForce 405", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x03D2, "GeForce 6100 nForce 400", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x03D5, "GeForce 6100 nForce 420", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0020, "TNT", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x0028, "TNT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x0029, "UTNT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x002C, "VTNT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -{0x00A0, "ITNT2", NV04_DX5_TEXTURED_TRIANGLE, NV_04, 0}, -}; diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c deleted file mode 100644 index f18dd644905..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_context.c +++ /dev/null @@ -1,422 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "glheader.h" -#include "context.h" -#include "simple_list.h" -#include "imports.h" -#include "matrix.h" -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "framebuffer.h" - -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" -#include "tnl/t_vp_build.h" - -#include "drivers/common/driverfuncs.h" - -#include "nouveau_context.h" -#include "nouveau_driver.h" -//#include "nouveau_state.h" -#include "nouveau_span.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_tex.h" -#include "nouveau_msg.h" -#include "nouveau_reg.h" -#include "nouveau_lock.h" -#include "nouveau_query.h" -#include "nv04_swtcl.h" -#include "nv10_swtcl.h" - -#include "vblank.h" -#include "utils.h" -#include "texmem.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ - -#ifndef NOUVEAU_DEBUG -int NOUVEAU_DEBUG = 0; -#endif - -static const struct dri_debug_control debug_control[] = -{ - { "shaders" , DEBUG_SHADERS }, - { "mem" , DEBUG_MEM }, - { "bufferobj" , DEBUG_BUFFEROBJ }, - { NULL , 0 } -}; - -#define need_GL_ARB_vertex_program -#define need_GL_ARB_occlusion_query -#include "extension_helper.h" - -const struct dri_extension common_extensions[] = -{ - { NULL, 0 } -}; - -const struct dri_extension nv10_extensions[] = -{ - { NULL, 0 } -}; - -const struct dri_extension nv20_extensions[] = -{ - { NULL, 0 } -}; - -const struct dri_extension nv30_extensions[] = -{ - { "GL_ARB_fragment_program", NULL }, - { NULL, 0 } -}; - -const struct dri_extension nv40_extensions[] = -{ - /* ARB_vp can be moved to nv20/30 once the shader backend has been - * written for those cards. - */ - { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions }, - { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, - { NULL, 0 } -}; - -const struct dri_extension nv50_extensions[] = -{ - { NULL, 0 } -}; - -/* Create the device specific context. - */ -GLboolean nouveauCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, - void *sharedContextPrivate ) -{ - GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; - struct dd_function_table functions; - nouveauContextPtr nmesa; - nouveauScreenPtr screen; - - /* Allocate the context */ - nmesa = (nouveauContextPtr) CALLOC( sizeof(*nmesa) ); - if ( !nmesa ) - return GL_FALSE; - - nmesa->driContext = driContextPriv; - nmesa->driScreen = sPriv; - nmesa->driDrawable = NULL; - nmesa->hHWContext = driContextPriv->hHWContext; - nmesa->driHwLock = &sPriv->pSAREA->lock; - nmesa->driFd = sPriv->fd; - - nmesa->screen = (nouveauScreenPtr)(sPriv->private); - screen=nmesa->screen; - - /* Create the hardware context */ - if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_FB_PHYSICAL, - &nmesa->vram_phys)) - return GL_FALSE; - if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_FB_SIZE, - &nmesa->vram_size)) - return GL_FALSE; - if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_AGP_PHYSICAL, - &nmesa->gart_phys)) - return GL_FALSE; - if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_AGP_SIZE, - &nmesa->gart_size)) - return GL_FALSE; - if (!nouveauFifoInit(nmesa)) - return GL_FALSE; - nouveauObjectInit(nmesa); - - - /* Init default driver functions then plug in our nouveau-specific functions - * (the texture functions are especially important) - */ - _mesa_init_driver_functions( &functions ); - nouveauDriverInitFunctions( &functions ); - nouveauTexInitFunctions( &functions ); - - /* Allocate the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((nouveauContextPtr) sharedContextPrivate)->glCtx; - else - shareCtx = NULL; - nmesa->glCtx = _mesa_create_context(glVisual, shareCtx, - &functions, (void *) nmesa); - if (!nmesa->glCtx) { - FREE(nmesa); - return GL_FALSE; - } - driContextPriv->driverPrivate = nmesa; - ctx = nmesa->glCtx; - - /* Parse configuration files */ - driParseConfigFiles (&nmesa->optionCache, &screen->optionCache, - screen->driScreen->myNum, "nouveau"); - - nmesa->sarea = (struct drm_nouveau_sarea *)((char *)sPriv->pSAREA + - screen->sarea_priv_offset); - - /* Enable any supported extensions */ - driInitExtensions(ctx, common_extensions, GL_TRUE); - if (nmesa->screen->card->type >= NV_10) - driInitExtensions(ctx, nv10_extensions, GL_FALSE); - if (nmesa->screen->card->type >= NV_20) - driInitExtensions(ctx, nv20_extensions, GL_FALSE); - if (nmesa->screen->card->type >= NV_30) - driInitExtensions(ctx, nv30_extensions, GL_FALSE); - if (nmesa->screen->card->type >= NV_40) - driInitExtensions(ctx, nv40_extensions, GL_FALSE); - if (nmesa->screen->card->type >= NV_50) - driInitExtensions(ctx, nv50_extensions, GL_FALSE); - - nmesa->current_primitive = -1; - - nouveauShaderInitFuncs(ctx); - /* Install Mesa's fixed-function texenv shader support */ - if (nmesa->screen->card->type >= NV_40) - ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; - - /* Initialize the swrast */ - _swrast_CreateContext( ctx ); - _vbo_CreateContext( ctx ); - _tnl_CreateContext( ctx ); - _swsetup_CreateContext( ctx ); - - _math_matrix_ctr(&nmesa->viewport); - - nouveauDDInitStateFuncs( ctx ); - nouveauSpanInitFunctions( ctx ); - nouveauDDInitState( nmesa ); - switch(nmesa->screen->card->type) - { - case NV_04: - case NV_05: - nv04TriInitFunctions( ctx ); - break; - case NV_10: - case NV_11: - case NV_17: - case NV_20: - case NV_30: - case NV_40: - case NV_44: - case NV_50: - default: - nv10TriInitFunctions( ctx ); - break; - } - - nouveauInitBufferObjects(ctx); - if (!nouveauSyncInitFuncs(ctx)) - return GL_FALSE; - nouveauQueryInitFuncs(ctx); - nmesa->hw_func.InitCard(nmesa); - nouveauInitState(ctx); - - driContextPriv->driverPrivate = (void *)nmesa; - - NOUVEAU_DEBUG = driParseDebugString( getenv( "NOUVEAU_DEBUG" ), - debug_control ); - - if (driQueryOptionb(&nmesa->optionCache, "no_rast")) { - fprintf(stderr, "disabling 3D acceleration\n"); - FALLBACK(nmesa, NOUVEAU_FALLBACK_DISABLE, 1); - } - - return GL_TRUE; -} - -/* Destroy the device specific context. */ -void nouveauDestroyContext( __DRIcontextPrivate *driContextPriv ) -{ - nouveauContextPtr nmesa = (nouveauContextPtr) driContextPriv->driverPrivate; - - assert(nmesa); - if ( nmesa ) { - /* free the option cache */ - driDestroyOptionCache (&nmesa->optionCache); - - FREE( nmesa ); - } - -} - - -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean nouveauMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) -{ - if ( driContextPriv ) { - nouveauContextPtr nmesa = (nouveauContextPtr) driContextPriv->driverPrivate; - struct gl_framebuffer *draw_fb = - (struct gl_framebuffer*)driDrawPriv->driverPrivate; - struct gl_framebuffer *read_fb = - (struct gl_framebuffer*)driReadPriv->driverPrivate; - - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = - driGetDefaultVBlankFlags(&nmesa->optionCache); - - driDrawableInitVBlank(driDrawPriv); - } - - nmesa->driDrawable = driDrawPriv; - - _mesa_resize_framebuffer(nmesa->glCtx, draw_fb, - driDrawPriv->w, driDrawPriv->h); - if (draw_fb != read_fb) { - _mesa_resize_framebuffer(nmesa->glCtx, draw_fb, - driReadPriv->w, - driReadPriv->h); - } - _mesa_make_current(nmesa->glCtx, draw_fb, read_fb); - - nouveau_build_framebuffer(nmesa->glCtx, - driDrawPriv->driverPrivate); - } else { - _mesa_make_current( NULL, NULL, NULL ); - } - - return GL_TRUE; -} - - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean nouveauUnbindContext( __DRIcontextPrivate *driContextPriv ) -{ - return GL_TRUE; -} - -void -nouveauDoSwapBuffers(nouveauContextPtr nmesa, __DRIdrawablePrivate *dPriv) -{ - struct gl_framebuffer *fb; - nouveauScreenPtr screen = dPriv->driScreenPriv->private; - nouveau_renderbuffer_t *src; - drm_clip_rect_t *box; - int nbox, i; - - fb = (struct gl_framebuffer *)dPriv->driverPrivate; - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - src = (nouveau_renderbuffer_t *) - fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } else { - src = (nouveau_renderbuffer_t *) - fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } - - LOCK_HARDWARE(nmesa); - nbox = dPriv->numClipRects; - box = dPriv->pClipRects; - - if (nbox) { - BEGIN_RING_SIZE(NvSubCtxSurf2D, - NV10_CONTEXT_SURFACES_2D_FORMAT, 4); - if (src->mesa._ActualFormat == GL_RGBA8) - OUT_RING (6); /* X8R8G8B8 */ - else - OUT_RING (4); /* R5G6B5 */ - OUT_RING(((screen->frontPitch * screen->fbFormat) << 16) | - src->pitch); - OUT_RING(src->offset); - OUT_RING(screen->frontOffset); - } - - for (i=0; i<nbox; i++, box++) { - BEGIN_RING_SIZE(NvSubImageBlit, NV_IMAGE_BLIT_POINT_IN, 3); - OUT_RING (((box->y1 - dPriv->y) << 16) | - (box->x1 - dPriv->x)); - OUT_RING ((box->y1 << 16) | box->x1); - OUT_RING (((box->y2 - box->y1) << 16) | - (box->x2 - box->x1)); - } - FIRE_RING(); - - UNLOCK_HARDWARE(nmesa); -} - -void nouveauSwapBuffers(__DRIdrawablePrivate *dPriv) -{ - if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { - nouveauContextPtr nmesa = dPriv->driContextPriv->driverPrivate; - - if (nmesa->glCtx->Visual.doubleBufferMode) { - _mesa_notifySwapBuffers(nmesa->glCtx); - nouveauDoSwapBuffers(nmesa, dPriv); - } - - } -} - -void nouveauCopySubBuffer(__DRIdrawablePrivate *dPriv, - int x, int y, int w, int h) -{ -} - -void nouveauClearBuffer(GLcontext *ctx, nouveau_renderbuffer_t *buffer, - int fill, int mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - int dimensions; - - if (!buffer) { - return; - } - - /* FIXME: only support 32 bits atm */ - - /* Surface that we will work on */ - nouveauObjectOnSubchannel(nmesa, NvSubCtxSurf2D, NvCtxSurf2D); - - BEGIN_RING_SIZE(NvSubCtxSurf2D, NV10_CONTEXT_SURFACES_2D_FORMAT, 4); - OUT_RING(0x0b); /* Y32 color format */ - OUT_RING((buffer->pitch<<16)|buffer->pitch); - OUT_RING(buffer->offset); - OUT_RING(buffer->offset); - - /* Now clear a rectangle */ - dimensions = ((buffer->mesa.Height)<<16) | (buffer->mesa.Width); - - nouveauObjectOnSubchannel(nmesa, NvSubGdiRectText, NvGdiRectText); - - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1); - OUT_RING(3); /* SRCCOPY */ - - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL, 5); - OUT_RING(0); /* top left */ - OUT_RING(dimensions); /* bottom right */ - OUT_RING(fill); - OUT_RING(0); /* top left */ - OUT_RING(dimensions); /* bottom right */ -} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.h b/src/mesa/drivers/dri/nouveau/nouveau_context.h deleted file mode 100644 index a617dd62826..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_context.h +++ /dev/null @@ -1,241 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - -#ifndef __NOUVEAU_CONTEXT_H__ -#define __NOUVEAU_CONTEXT_H__ - -#include "dri_util.h" -#include "drm.h" -#include "nouveau_drm.h" - -#include "mtypes.h" -#include "tnl/t_vertex.h" - -#include "nouveau_fbo.h" -#include "nouveau_screen.h" -#include "nouveau_shader.h" -#include "nouveau_state_cache.h" -#include "nouveau_sync.h" - -#include "xmlconfig.h" - -typedef struct nouveau_fifo { - struct drm_nouveau_channel_alloc drm; - uint32_t *pushbuf; - uint32_t *mmio; - uint32_t *notifier_block; - uint32_t current; - uint32_t put; - uint32_t free; - uint32_t max; -} nouveau_fifo_t; - -#define TAG(x) nouveau##x -#include "tnl_dd/t_dd_vertex.h" -#undef TAG - -/* Subpixel offsets for window coordinates (triangles): */ -#define SUBPIXEL_X (0.0F) -#define SUBPIXEL_Y (0.125F) - -struct nouveau_context; - -typedef void (*nouveau_tri_func)( struct nouveau_context*, - nouveauVertex *, - nouveauVertex *, - nouveauVertex * ); - -typedef void (*nouveau_line_func)( struct nouveau_context*, - nouveauVertex *, - nouveauVertex * ); - -typedef void (*nouveau_point_func)( struct nouveau_context*, - nouveauVertex * ); - -typedef struct nouveau_hw_func_t { - /* Initialise any card-specific non-GL related state */ - GLboolean (*InitCard)(struct nouveau_context *); - /* Update buffer offset/pitch/format */ - GLboolean (*BindBuffers)(struct nouveau_context *, int num_color, - nouveau_renderbuffer_t **color, - nouveau_renderbuffer_t *depth); - /* Update anything that depends on the window position/size */ - void (*WindowMoved)(struct nouveau_context *); - - /* Update projection matrix */ - void (*UpdateProjectionMatrix)(GLcontext *); - - /* Update modelview matrix (used for lighting and vertex weight) */ - void (*UpdateModelviewMatrix)(GLcontext *); -} nouveau_hw_func; - -typedef struct nouveau_context { - /* Mesa context */ - GLcontext *glCtx; - - /* The per-context fifo */ - nouveau_fifo_t fifo; - - /* Physical addresses of AGP/VRAM apertures */ - uint64_t vram_phys; - uint64_t vram_size; - uint64_t gart_phys; - uint64_t gart_size; - - /* Channel synchronisation */ - struct drm_nouveau_notifierobj_alloc *syncNotifier; - - /* ARB_occlusion_query / EXT_timer_query */ - GLuint query_object_max; - GLboolean * query_alloc; - struct drm_nouveau_notifierobj_alloc *queryNotifier; - - /* Additional hw-specific functions */ - nouveau_hw_func hw_func; - - /* FIXME : do we want to put all state into a separate struct ? */ - /* State for tris */ - GLuint color_offset; - GLuint specular_offset; - - /* Vertex state */ - GLuint vertex_size; - GLubyte *verts; - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - GLuint vertex_attr_count; - - /* Color and depth renderbuffers */ - nouveau_renderbuffer_t *color_buffer; - nouveau_renderbuffer_t *depth_buffer; - - /* Depth/stencil clear value */ - uint32_t clear_value; - - /* Light state */ - GLboolean lighting_enabled; - uint32_t enabled_lights; - - /* Cached state */ - nouveau_state_cache state_cache; - - /* The drawing fallbacks */ - GLuint Fallback; - nouveau_tri_func draw_tri; - nouveau_line_func draw_line; - nouveau_point_func draw_point; - - /* Cliprects information */ - GLuint numClipRects; - drm_clip_rect_t *pClipRects; - drm_clip_rect_t osClipRect; - GLuint drawX, drawY, drawW, drawH; - - /* The rendering context information */ - GLenum current_primitive; /* the current primitive enum */ - DECLARE_RENDERINPUTS(render_inputs_bitset); /* the current render inputs */ - - /* Shader state */ - nvsFunc VPfunc; - nvsFunc FPfunc; - nouveauShader *current_fragprog; - nouveauShader *current_vertprog; - nouveauShader *passthrough_vp; - nouveauShader *passthrough_fp; - - nouveauScreenRec *screen; - struct drm_nouveau_sarea *sarea; - - __DRIcontextPrivate *driContext; /* DRI context */ - __DRIscreenPrivate *driScreen; /* DRI screen */ - __DRIdrawablePrivate *driDrawable; /* DRI drawable bound to this ctx */ - GLint lastStamp; - - drm_context_t hHWContext; - drm_hw_lock_t *driHwLock; - int driFd; - - /* Configuration cache */ - driOptionCache optionCache; - - GLuint new_state; - GLuint new_render_state; - GLuint render_index; - GLmatrix viewport; - GLfloat depth_scale; - -}nouveauContextRec, *nouveauContextPtr; - - -#define NOUVEAU_CONTEXT(ctx) ((nouveauContextPtr)(ctx->DriverCtx)) - -/* Flags for software fallback cases: */ -#define NOUVEAU_FALLBACK_TEXTURE 0x0001 -#define NOUVEAU_FALLBACK_DRAW_BUFFER 0x0002 -#define NOUVEAU_FALLBACK_READ_BUFFER 0x0004 -#define NOUVEAU_FALLBACK_STENCIL 0x0008 -#define NOUVEAU_FALLBACK_RENDER_MODE 0x0010 -#define NOUVEAU_FALLBACK_LOGICOP 0x0020 -#define NOUVEAU_FALLBACK_SEP_SPECULAR 0x0040 -#define NOUVEAU_FALLBACK_BLEND_EQ 0x0080 -#define NOUVEAU_FALLBACK_BLEND_FUNC 0x0100 -#define NOUVEAU_FALLBACK_PROJTEX 0x0200 -#define NOUVEAU_FALLBACK_DISABLE 0x0400 - - -extern GLboolean nouveauCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, - void *sharedContextPrivate ); - -extern void nouveauDestroyContext( __DRIcontextPrivate * ); - -extern GLboolean nouveauMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ); - -extern GLboolean nouveauUnbindContext( __DRIcontextPrivate *driContextPriv ); - -extern void nouveauDoSwapBuffers(nouveauContextPtr nmesa, - __DRIdrawablePrivate *dPriv); - -extern void nouveauSwapBuffers(__DRIdrawablePrivate *dPriv); - -extern void nouveauCopySubBuffer(__DRIdrawablePrivate *dPriv, - int x, int y, int w, int h); - -extern void nouveauClearBuffer(GLcontext *ctx, nouveau_renderbuffer_t *buffer, - int fill, int mask); - -/* Debugging utils: */ -extern int NOUVEAU_DEBUG; - -#define DEBUG_SHADERS 0x00000001 -#define DEBUG_MEM 0x00000002 -#define DEBUG_BUFFEROBJ 0x00000004 - -#endif /* __NOUVEAU_CONTEXT_H__ */ - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h b/src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h deleted file mode 100644 index c9b2d590077..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h +++ /dev/null @@ -1,44 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin, Sylvain Munaut -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - - -#define NV03_STATUS 0x004006b0 -#define NV04_STATUS 0x00400700 - -#define NV03_FIFO_REGS_SIZE 0x10000 -# define NV03_FIFO_REGS_DMAPUT 0x00000040 -# define NV03_FIFO_REGS_DMAGET 0x00000044 - -/* Fifo commands. These are not regs, neither masks */ -#define NV03_FIFO_CMD_JUMP 0x20000000 -#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc -#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) - - -#define NONINC_METHOD 0x40000000 - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_dri.h b/src/mesa/drivers/dri/nouveau/nouveau_dri.h deleted file mode 100644 index ce3c3fb9cc4..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_dri.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _NOUVEAU_DRI_ -#define _NOUVEAU_DRI_ - -#include "xf86drm.h" -#include "drm.h" -#include "nouveau_drm.h" - -typedef struct { - uint32_t device_id; /**< \brief PCI device ID */ - uint32_t width; /**< \brief width in pixels of display */ - uint32_t height; /**< \brief height in scanlines of display */ - uint32_t depth; /**< \brief depth of display (8, 15, 16, 24) */ - uint32_t bpp; /**< \brief bit depth of display (8, 16, 24, 32) */ - - uint32_t bus_type; /**< \brief ths bus type */ - uint32_t bus_mode; /**< \brief bus mode (used for AGP, maybe also for PCI-E ?) */ - - uint32_t front_offset; /**< \brief front buffer offset */ - uint32_t front_pitch; /**< \brief front buffer pitch */ - uint32_t back_offset; /**< \brief private back buffer offset */ - uint32_t back_pitch; /**< \brief private back buffer pitch */ - uint32_t depth_offset; /**< \brief private depth buffer offset */ - uint32_t depth_pitch; /**< \brief private depth buffer pitch */ - -} NOUVEAUDRIRec, *NOUVEAUDRIPtr; - -#endif - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.c b/src/mesa/drivers/dri/nouveau/nouveau_driver.c deleted file mode 100644 index 7bd42fdfe27..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_driver.c +++ /dev/null @@ -1,218 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -//#include "nouveau_state.h" -#include "nouveau_lock.h" -#include "nouveau_fifo.h" -#include "nouveau_driver.h" -#include "swrast/swrast.h" - -#include "context.h" -#include "framebuffer.h" - -#include "utils.h" -#include "colormac.h" - -/* Wrapper for DRM_NOUVEAU_GETPARAM ioctl */ -GLboolean nouveauDRMGetParam(nouveauContextPtr nmesa, - unsigned int param, - uint64_t* value) -{ - struct drm_nouveau_getparam getp; - - getp.param = param; - if (!value || drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_GETPARAM, - &getp, sizeof(getp))) - return GL_FALSE; - *value = getp.value; - return GL_TRUE; -} - -/* Wrapper for DRM_NOUVEAU_GETPARAM ioctl */ -GLboolean nouveauDRMSetParam(nouveauContextPtr nmesa, - unsigned int param, - uint64_t value) -{ - struct drm_nouveau_setparam setp; - - setp.param = param; - setp.value = value; - if (drmCommandWrite(nmesa->driFd, DRM_NOUVEAU_SETPARAM, &setp, - sizeof(setp))) - return GL_FALSE; - return GL_TRUE; -} - -/* Return the width and height of the current color buffer */ -static void nouveauGetBufferSize( GLframebuffer *buffer, - GLuint *width, GLuint *height ) -{ - GET_CURRENT_CONTEXT(ctx); - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - LOCK_HARDWARE( nmesa ); - *width = nmesa->driDrawable->w; - *height = nmesa->driDrawable->h; - UNLOCK_HARDWARE( nmesa ); -} - -/* glGetString */ -static const GLubyte *nouveauGetString( GLcontext *ctx, GLenum name ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - static char buffer[128]; - const char * card_name = "Unknown"; - GLuint agp_mode = 0; - - switch ( name ) { - case GL_VENDOR: - return (GLubyte *)DRIVER_AUTHOR; - - case GL_RENDERER: - card_name=nmesa->screen->card->name; - - switch(nmesa->screen->bus_type) - { - case NV_PCI: - case NV_PCIE: - default: - agp_mode=0; - break; - case NV_AGP: - agp_mode=nmesa->screen->agp_mode; - break; - } - driGetRendererString( buffer, card_name, DRIVER_DATE, - agp_mode ); - return (GLubyte *)buffer; - default: - return NULL; - } -} - -/* glFlush */ -static void nouveauFlush( GLcontext *ctx ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (ctx->DrawBuffer->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) - nouveauDoSwapBuffers(nmesa, nmesa->driDrawable); - FIRE_RING(); -} - -/* glFinish */ -static void nouveauFinish( GLcontext *ctx ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - nouveauFlush( ctx ); - nouveauWaitForIdle( nmesa ); -} - -/* glClear */ -static void nouveauClear( GLcontext *ctx, GLbitfield mask ) -{ - uint32_t clear_value; - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* FIXME: should we clear front buffer, even if asked to do it? */ - if (mask & (BUFFER_BIT_FRONT_LEFT|BUFFER_BIT_BACK_LEFT)) { - GLubyte c[4]; - int color_bits = 32; - int color_mask = 0xffffffff; - - UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,ctx->Color.ClearColor); - clear_value = PACK_COLOR_8888(c[3],c[0],c[1],c[2]); - - if (ctx->DrawBuffer) { - /* FIXME: find correct color buffer, instead of [0] */ - if (ctx->DrawBuffer->_ColorDrawBuffers[0]) { - color_bits = ctx->DrawBuffer->_ColorDrawBuffers[0]->RedBits; - color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0]->GreenBits; - color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0]->BlueBits; - color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0]->AlphaBits; - } - } - - if (color_bits<24) { - clear_value = PACK_COLOR_565(c[0],c[1],c[2]); - color_mask = 0xffff; - } - - nouveauClearBuffer(ctx, nmesa->color_buffer, - clear_value, color_mask); - } - - if (mask & (BUFFER_BIT_DEPTH)) { - int depth_bits = 24; - int depth_mask; - if (ctx->DrawBuffer) { - if (ctx->DrawBuffer->_DepthBuffer) { - depth_bits = ctx->DrawBuffer->_DepthBuffer->DepthBits; - } - } - - switch(depth_bits) { - case 16: - clear_value = (uint32_t) (ctx->Depth.Clear * 32767.0); - depth_mask = 0xffff; - break; - default: - clear_value = ((uint32_t) (ctx->Depth.Clear * 16777215.0)) << 8; - depth_mask = 0xffffff00; - break; - } - - nouveauClearBuffer(ctx, nmesa->depth_buffer, - clear_value, depth_mask); - } - - if (mask & (BUFFER_BIT_STENCIL)) { - int stencil_bits = 0; - if (ctx->DrawBuffer) { - if (ctx->DrawBuffer->_StencilBuffer) { - stencil_bits = ctx->DrawBuffer->_StencilBuffer->StencilBits; - } - } - - if (stencil_bits>0) { - nouveauClearBuffer(ctx, nmesa->depth_buffer, - ctx->Stencil.Clear, (1<<stencil_bits)-1); - } - } -} - -void nouveauDriverInitFunctions( struct dd_function_table *functions ) -{ - functions->GetBufferSize = nouveauGetBufferSize; - functions->ResizeBuffers = _mesa_resize_framebuffer; - functions->GetString = nouveauGetString; - functions->Flush = nouveauFlush; - functions->Finish = nouveauFinish; - functions->Clear = nouveauClear; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.h b/src/mesa/drivers/dri/nouveau/nouveau_driver.h deleted file mode 100644 index 6164012b5b7..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_driver.h +++ /dev/null @@ -1,42 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - -#ifndef __NOUVEAU_DRIVER_H__ -#define __NOUVEAU_DRIVER_H__ - -#define DRIVER_DATE "20060219" -#define DRIVER_AUTHOR "Stephane Marchesin" - -extern void nouveauDriverInitFunctions( struct dd_function_table *functions ); -extern GLboolean nouveauDRMGetParam(nouveauContextPtr nmesa, unsigned int param, - uint64_t *value); -extern GLboolean nouveauDRMSetParam(nouveauContextPtr nmesa, unsigned int param, - uint64_t value); - -#endif /* __NOUVEAU_DRIVER_H__ */ - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c b/src/mesa/drivers/dri/nouveau/nouveau_fbo.c deleted file mode 100644 index 23525509d14..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c +++ /dev/null @@ -1,289 +0,0 @@ -#include "utils.h" -#include "framebuffer.h" -#include "renderbuffer.h" -#include "fbobject.h" - -#include "nouveau_context.h" -#include "nouveau_fbo.h" -#include "nouveau_fifo.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" -#include "nouveau_reg.h" - -static GLboolean -nouveau_renderbuffer_pixelformat(nouveau_renderbuffer_t * nrb, - GLenum internalFormat) -{ - nrb->mesa.InternalFormat = internalFormat; - - /*TODO: We probably want to extend this a bit, and maybe make - * card-specific? - */ - switch (internalFormat) { - case GL_RGBA: - case GL_RGBA8: - nrb->mesa._BaseFormat = GL_RGBA; - nrb->mesa._ActualFormat = GL_RGBA8; - nrb->mesa.DataType = GL_UNSIGNED_BYTE; - nrb->mesa.RedBits = 8; - nrb->mesa.GreenBits = 8; - nrb->mesa.BlueBits = 8; - nrb->mesa.AlphaBits = 8; - nrb->cpp = 4; - break; - case GL_RGB: - case GL_RGB5: - nrb->mesa._BaseFormat = GL_RGB; - nrb->mesa._ActualFormat = GL_RGB5; - nrb->mesa.DataType = GL_UNSIGNED_BYTE; - nrb->mesa.RedBits = 5; - nrb->mesa.GreenBits = 6; - nrb->mesa.BlueBits = 5; - nrb->mesa.AlphaBits = 0; - nrb->cpp = 2; - break; - case GL_DEPTH_COMPONENT16: - nrb->mesa._BaseFormat = GL_DEPTH_COMPONENT; - nrb->mesa._ActualFormat = GL_DEPTH_COMPONENT16; - nrb->mesa.DataType = GL_UNSIGNED_SHORT; - nrb->mesa.DepthBits = 16; - nrb->cpp = 2; - break; - case GL_DEPTH_COMPONENT24: - nrb->mesa._BaseFormat = GL_DEPTH_COMPONENT; - nrb->mesa._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - nrb->mesa.DataType = GL_UNSIGNED_INT_24_8_EXT; - nrb->mesa.DepthBits = 24; - nrb->cpp = 4; - break; - case GL_STENCIL_INDEX8_EXT: - nrb->mesa._BaseFormat = GL_STENCIL_INDEX; - nrb->mesa._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - nrb->mesa.DataType = GL_UNSIGNED_INT_24_8_EXT; - nrb->mesa.StencilBits = 8; - nrb->cpp = 4; - break; - case GL_DEPTH24_STENCIL8_EXT: - nrb->mesa._BaseFormat = GL_DEPTH_STENCIL_EXT; - nrb->mesa._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - nrb->mesa.DataType = GL_UNSIGNED_INT_24_8_EXT; - nrb->mesa.DepthBits = 24; - nrb->mesa.StencilBits = 8; - nrb->cpp = 4; - break; - default: - return GL_FALSE; - break; - } - - return GL_TRUE; -} - -static GLboolean -nouveau_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, - GLenum internalFormat, - GLuint width, GLuint height) -{ - nouveau_renderbuffer_t *nrb = (nouveau_renderbuffer_t *) rb; - - if (!nouveau_renderbuffer_pixelformat(nrb, internalFormat)) { - fprintf(stderr, "%s: unknown internalFormat\n", __func__); - return GL_FALSE; - } - - /* If this buffer isn't statically alloc'd, we may need to ask the - * drm for more memory */ - if (rb->Width != width || rb->Height != height) { - GLuint pitch; - - /* align pitches to 64 bytes */ - pitch = ((width * nrb->cpp) + 63) & ~63; - - if (nrb->mem) - nouveau_mem_free(ctx, nrb->mem); - nrb->mem = nouveau_mem_alloc(ctx, - NOUVEAU_MEM_FB | - NOUVEAU_MEM_MAPPED, - pitch * height, 0); - if (!nrb->mem) - return GL_FALSE; - - /* update nouveau_renderbuffer info */ - nrb->offset = nouveau_mem_gpu_offset_get(ctx, nrb->mem); - nrb->pitch = pitch; - } - - rb->Width = width; - rb->Height = height; - rb->InternalFormat = internalFormat; - - nouveauSpanSetFunctions(nrb); - - return GL_TRUE; -} - -static void -nouveau_renderbuffer_delete(struct gl_renderbuffer *rb) -{ - GET_CURRENT_CONTEXT(ctx); - nouveau_renderbuffer_t *nrb = (nouveau_renderbuffer_t *) rb; - - if (nrb->mem) - nouveau_mem_free(ctx, nrb->mem); - FREE(nrb); -} - -nouveau_renderbuffer_t * -nouveau_renderbuffer_new(GLenum internalFormat) -{ - nouveau_renderbuffer_t *nrb; - - nrb = CALLOC_STRUCT(nouveau_renderbuffer); - if (!nrb) - return NULL; - - _mesa_init_renderbuffer(&nrb->mesa, 0); - - if (!nouveau_renderbuffer_pixelformat(nrb, internalFormat)) { - fprintf(stderr, "%s: unknown internalFormat\n", __func__); - return GL_FALSE; - } - - nrb->mesa.AllocStorage = nouveau_renderbuffer_storage; - nrb->mesa.Delete = nouveau_renderbuffer_delete; - - return nrb; -} - -static void -nouveau_cliprects_renderbuffer_set(nouveauContextPtr nmesa, - nouveau_renderbuffer_t * nrb) -{ - nmesa->numClipRects = 1; - nmesa->pClipRects = &nmesa->osClipRect; - nmesa->osClipRect.x1 = 0; - nmesa->osClipRect.y1 = 0; - nmesa->osClipRect.x2 = nrb->mesa.Width; - nmesa->osClipRect.y2 = nrb->mesa.Height; - nmesa->drawX = 0; - nmesa->drawY = 0; - nmesa->drawW = nrb->mesa.Width; - nmesa->drawH = nrb->mesa.Height; -} - -void -nouveau_window_moved(GLcontext * ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_renderbuffer_t *nrb; - - nrb = (nouveau_renderbuffer_t *) ctx->DrawBuffer->_ColorDrawBuffers[0]; - if (!nrb) - return; - - nouveau_cliprects_renderbuffer_set(nmesa, nrb); - - /* Viewport depends on window size/position, nouveauCalcViewport - * will take care of calling the hw-specific WindowMoved - */ - ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, - ctx->Viewport.Width, ctx->Viewport.Height); - /* Scissor depends on window position */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); -} - -GLboolean -nouveau_build_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_renderbuffer_t *color[MAX_DRAW_BUFFERS]; - nouveau_renderbuffer_t *depth; - - _mesa_update_framebuffer(ctx); - _mesa_update_draw_buffer_bounds(ctx); - - color[0] = (nouveau_renderbuffer_t *) fb->_ColorDrawBuffers[0]; - if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) - depth = (nouveau_renderbuffer_t *) fb->_DepthBuffer->Wrapped; - else - depth = (nouveau_renderbuffer_t *) fb->_DepthBuffer; - - if (!nmesa->hw_func.BindBuffers(nmesa, 1, color, depth)) - return GL_FALSE; - nouveau_window_moved(ctx); - - return GL_TRUE; -} - -static void -nouveauDrawBuffer(GLcontext *ctx, GLenum buffer) -{ - nouveau_build_framebuffer(ctx, ctx->DrawBuffer); -} - -static struct gl_framebuffer * -nouveauNewFramebuffer(GLcontext *ctx, GLuint name) -{ - return _mesa_new_framebuffer(ctx, name); -} - -static struct gl_renderbuffer * -nouveauNewRenderbuffer(GLcontext *ctx, GLuint name) -{ - nouveau_renderbuffer_t *nrb; - - nrb = CALLOC_STRUCT(nouveau_renderbuffer); - if (!nrb) - return NULL; - - _mesa_init_renderbuffer(&nrb->mesa, name); - - nrb->mesa.AllocStorage = nouveau_renderbuffer_storage; - nrb->mesa.Delete = nouveau_renderbuffer_delete; - return &nrb->mesa; -} - -static void -nouveauBindFramebuffer(GLcontext *ctx, GLenum target, - struct gl_framebuffer *fb, - struct gl_framebuffer *fbread) -{ - if (target == GL_FRAMEBUFFER_EXT || target == GL_DRAW_FRAMEBUFFER_EXT) { - nouveau_build_framebuffer(ctx, fb); - } -} - -static void -nouveauFramebufferRenderbuffer(GLcontext *ctx, struct gl_framebuffer *fb, - GLenum attachment, struct gl_renderbuffer *rb) -{ - _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb); - nouveau_build_framebuffer(ctx, fb); -} - -static void -nouveauRenderTexture(GLcontext * ctx, struct gl_framebuffer *fb, - struct gl_renderbuffer_attachment *att) -{ -} - -static void -nouveauFinishRenderTexture(GLcontext * ctx, - struct gl_renderbuffer_attachment *att) -{ -} - -void -nouveauInitBufferFuncs(struct dd_function_table *func) -{ - func->DrawBuffer = nouveauDrawBuffer; - - func->NewFramebuffer = nouveauNewFramebuffer; - func->NewRenderbuffer = nouveauNewRenderbuffer; - func->BindFramebuffer = nouveauBindFramebuffer; - func->FramebufferRenderbuffer = nouveauFramebufferRenderbuffer; - func->RenderTexture = nouveauRenderTexture; - func->FinishRenderTexture = nouveauFinishRenderTexture; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.h b/src/mesa/drivers/dri/nouveau/nouveau_fbo.h deleted file mode 100644 index 787af4e9e4b..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __NOUVEAU_BUFFERS_H__ -#define __NOUVEAU_BUFFERS_H__ - -#include <stdint.h> -#include "mtypes.h" -#include "utils.h" -#include "renderbuffer.h" - -#include "nouveau_mem.h" - -typedef struct nouveau_renderbuffer { - struct gl_renderbuffer mesa; /* must be first! */ - - nouveau_mem *mem; - void *map; - - int cpp; - uint32_t offset; - uint32_t pitch; -} nouveau_renderbuffer_t; - -extern nouveau_renderbuffer_t *nouveau_renderbuffer_new(GLenum internalFormat); -extern void nouveau_window_moved(GLcontext *); -extern GLboolean nouveau_build_framebuffer(GLcontext *, - struct gl_framebuffer *); -extern nouveau_renderbuffer_t *nouveau_current_draw_buffer(GLcontext *); - -extern void nouveauInitBufferFuncs(struct dd_function_table *); - -#endif diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fifo.c b/src/mesa/drivers/dri/nouveau/nouveau_fifo.c deleted file mode 100644 index 5dc94e0520a..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_fifo.c +++ /dev/null @@ -1,153 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#include "vblank.h" -#include <errno.h> -#include "mtypes.h" -#include "macros.h" -#include "dd.h" -#include "swrast/swrast.h" -#include "nouveau_context.h" -#include "nouveau_msg.h" -#include "nouveau_fifo.h" -#include "nouveau_lock.h" -#include "nouveau_object.h" -#include "nouveau_sync.h" - -#ifdef NOUVEAU_RING_DEBUG -int nouveau_fifo_remaining=0; -#endif - - -#define RING_SKIPS 8 - -void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size) -{ -#ifdef NOUVEAU_RING_DEBUG - return; -#endif - u_int32_t fifo_get; - while(nmesa->fifo.free < size+1) { - fifo_get = NV_FIFO_READ_GET(); - - if(nmesa->fifo.put >= fifo_get) { - nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current; - if(nmesa->fifo.free < size+1) { - OUT_RING(NV03_FIFO_CMD_JUMP | - nmesa->fifo.drm.put_base); - if(fifo_get <= RING_SKIPS) { - if(nmesa->fifo.put <= RING_SKIPS) /* corner case - will be idle */ - NV_FIFO_WRITE_PUT(RING_SKIPS + 1); - do { fifo_get = NV_FIFO_READ_GET(); } - while(fifo_get <= RING_SKIPS); - } - NV_FIFO_WRITE_PUT(RING_SKIPS); - nmesa->fifo.current = nmesa->fifo.put = RING_SKIPS; - nmesa->fifo.free = fifo_get - (RING_SKIPS + 1); - } - } else - nmesa->fifo.free = fifo_get - nmesa->fifo.current - 1; - } -} - -/* - * Wait for the channel to be idle - */ -void nouveauWaitForIdleLocked(nouveauContextPtr nmesa) -{ - /* Wait for FIFO idle */ - FIRE_RING(); - while(RING_AHEAD()>0); - - /* Wait on notifier to indicate all commands in the channel have - * been completed. - */ - nouveau_notifier_wait_nop(nmesa->glCtx, nmesa->syncNotifier, NvSub3D); -} - -void nouveauWaitForIdle(nouveauContextPtr nmesa) -{ - LOCK_HARDWARE(nmesa); - nouveauWaitForIdleLocked(nmesa); - UNLOCK_HARDWARE(nmesa); -} - -// here we call the fifo initialization ioctl and fill in stuff accordingly -GLboolean nouveauFifoInit(nouveauContextPtr nmesa) -{ - int i, ret; - -#ifdef NOUVEAU_RING_DEBUG - return GL_TRUE; -#endif - - nmesa->fifo.drm.fb_ctxdma_handle = NvDmaFB; - nmesa->fifo.drm.tt_ctxdma_handle = NvDmaTT; - ret = drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_CHANNEL_ALLOC, - &nmesa->fifo.drm, sizeof(nmesa->fifo.drm)); - if (ret) { - FATAL("Fifo initialization ioctl failed (returned %d)\n", ret); - return GL_FALSE; - } - - ret = drmMap(nmesa->driFd, nmesa->fifo.drm.cmdbuf, - nmesa->fifo.drm.cmdbuf_size, &nmesa->fifo.pushbuf); - if (ret) { - FATAL("Unable to map the fifo (returned %d)\n", ret); - return GL_FALSE; - } - - ret = drmMap(nmesa->driFd, nmesa->fifo.drm.ctrl, - nmesa->fifo.drm.ctrl_size, &nmesa->fifo.mmio); - if (ret) { - FATAL("Unable to map the control regs (returned %d)\n", ret); - return GL_FALSE; - } - - ret = drmMap(nmesa->driFd, nmesa->fifo.drm.notifier, - nmesa->fifo.drm.notifier_size, - &nmesa->fifo.notifier_block); - if (ret) { - FATAL("Unable to map the notifier block (returned %d)\n", ret); - return GL_FALSE; - } - - /* Setup our initial FIFO tracking params */ - nmesa->fifo.current = 0; - nmesa->fifo.put = 0; - nmesa->fifo.max = (nmesa->fifo.drm.cmdbuf_size >> 2) - 1; - nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current; - - for (i=0; i<RING_SKIPS; i++) - OUT_RING(0); - nmesa->fifo.free -= RING_SKIPS; - - MESSAGE("Fifo init ok. Using context %d\n", nmesa->fifo.drm.channel); - return GL_TRUE; -} - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fifo.h b/src/mesa/drivers/dri/nouveau/nouveau_fifo.h deleted file mode 100644 index 3ca1560e3ac..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_fifo.h +++ /dev/null @@ -1,222 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - -#ifndef __NOUVEAU_FIFO_H__ -#define __NOUVEAU_FIFO_H__ - -#include "nouveau_context.h" -#include "nouveau_ctrlreg.h" -#include "nouveau_state_cache.h" - -//#define NOUVEAU_RING_TRACE -//#define NOUVEAU_RING_DEBUG -//#define NOUVEAU_STATE_CACHE_DISABLE - -#ifndef NOUVEAU_RING_TRACE -#define NOUVEAU_RING_TRACE 0 -#else -#undef NOUVEAU_RING_TRACE -#define NOUVEAU_RING_TRACE 1 -#endif - -#define NV_READ(reg) *(volatile u_int32_t *)(nmesa->mmio + (reg)) - -#define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4)) -#define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4)) = value; -#define NV_FIFO_READ_GET() ((NV_FIFO_READ(NV03_FIFO_REGS_DMAGET) - nmesa->fifo.drm.put_base) >> 2) -#define NV_FIFO_WRITE_PUT(val) do { \ - if (NOUVEAU_RING_TRACE) {\ - printf("FIRE_RING : 0x%08x\n", nmesa->fifo.current << 2); \ - fflush(stdout); \ - sleep(1); \ - } \ - NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, ((val)<<2) + nmesa->fifo.drm.put_base); \ -} while(0) - -/* - * Ring/fifo interface - * - * - Begin a ring section with BEGIN_RING_SIZE (if you know the full size in advance) - * - Output stuff to the ring with either OUT_RINGp (outputs a raw mem chunk), OUT_RING (1 uint32_t) or OUT_RINGf (1 float) - * - RING_AVAILABLE returns the available fifo (in uint32_ts) - * - RING_AHEAD returns how much ahead of the last submission point we are - * - FIRE_RING fires whatever we have that wasn't fired before - * - WAIT_RING waits for size (in uint32_ts) to be available in the fifo - */ - -/* Enable for ring debugging. Prints out writes to the ring buffer - * but does not actually write to it. - */ -#ifdef NOUVEAU_RING_DEBUG - -extern int nouveau_fifo_remaining; - -#define OUT_RINGp(ptr,sz) do { \ -uint32_t* p=(uint32_t*)(ptr); \ -int i; printf("OUT_RINGp: (size 0x%x dwords)\n",sz); for(i=0;i<sz;i++) printf(" 0x%08x %f\n", *(p+i), *((float*)(p+i))); \ -nouveau_fifo_remaining-=sz; \ -}while(0) - -#define OUT_RING(n) do { \ - printf("OUT_RINGn: 0x%08x (%s)\n", n, __func__); \ - nouveau_fifo_remaining--; \ -}while(0) - -#define OUT_RINGf(n) do { \ - printf("OUT_RINGf: %.04f (%s)\n", n, __func__); \ - nouveau_fifo_remaining--; \ -}while(0) - -#define BEGIN_RING_SIZE(subchannel,tag,size) do { \ - if (nouveau_fifo_remaining!=0) \ - printf("RING ERROR : remaining %d\n",nouveau_fifo_remaining); \ - nouveau_state_cache_flush(nmesa); \ - if (nmesa->fifo.free <= (size)) \ - WAIT_RING(nmesa,(size)); \ - OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \ - nmesa->fifo.free -= ((size) + 1); \ - nouveau_fifo_remaining=size; \ -}while(0) - -#else - -#define OUT_RINGp(ptr,sz) do{ \ - if (NOUVEAU_RING_TRACE) { \ - uint32_t* p=(uint32_t*)(ptr); \ - int i; printf("OUT_RINGp: (size 0x%x dwords) (%s)\n",sz, __func__); for(i=0;i<sz;i++) printf(" [0x%08x] 0x%08x %f\n", (nmesa->fifo.current+i) << 2, *(p+i), *((float*)(p+i))); \ - } \ - memcpy(nmesa->fifo.pushbuf+nmesa->fifo.current,ptr,(sz)*4); \ - nmesa->fifo.current+=(sz); \ -}while(0) - -#define OUT_RING(n) do { \ -if (NOUVEAU_RING_TRACE) \ - printf("OUT_RINGn: [0x%08x] 0x%08x (%s)\n", nmesa->fifo.current << 2, n, __func__); \ -nmesa->fifo.pushbuf[nmesa->fifo.current++]=(n); \ -}while(0) - -#define OUT_RINGf(n) do { \ -if (NOUVEAU_RING_TRACE) \ - printf("OUT_RINGf: [0x%08x] %.04f (%s)\n", nmesa->fifo.current << 2, n, __func__); \ -*((float*)(nmesa->fifo.pushbuf+nmesa->fifo.current++))=(n); \ -}while(0) - -#define BEGIN_RING_SIZE(subchannel,tag,size) do { \ - nouveau_state_cache_flush(nmesa); \ - if (nmesa->fifo.free <= (size)) \ - WAIT_RING(nmesa,(size)); \ - OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \ - nmesa->fifo.free -= ((size) + 1); \ -}while(0) - -#endif - -extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size); -extern void nouveau_state_cache_flush(nouveauContextPtr nmesa); -extern void nouveau_state_cache_init(nouveauContextPtr nmesa); - -#ifdef NOUVEAU_STATE_CACHE_DISABLE -#define BEGIN_RING_CACHE(subc,tag,size) BEGIN_RING_SIZE((subc), (tag), (size)) -#define OUT_RING_CACHE(n) OUT_RING((n)) -#define OUT_RING_CACHEf(n) OUT_RINGf((n)) -#define OUT_RING_CACHEp(ptr, sz) OUT_RINGp((ptr), (sz)) -#define OUT_RING_CACHE_FORCE(n) OUT_RING((n)) -#define OUT_RING_CACHE_FORCEf(n) OUT_RINGf((n)) -#define OUT_RING_CACHE_FORCEp(ptr, sz) OUT_RINGp((ptr), (sz)) -#else -#define BEGIN_RING_CACHE(subchannel,tag,size) do { \ - nmesa->state_cache.dirty=1; \ - nmesa->state_cache.current_pos=((tag)/4); \ - assert(nmesa->state_cache.current_pos + size <= NOUVEAU_STATE_CACHE_ENTRIES); \ -}while(0) - -#define OUT_RING_CACHE(n) do { \ - if (nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value!=(n)) { \ - nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \ - nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \ - nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value=(n); \ - } \ - nmesa->state_cache.current_pos++; \ -}while(0) - -#define OUT_RING_CACHEf(n) do { \ - if ((*(GLfloat*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))!=(n)){ \ - nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \ - nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \ - (*(GLfloat*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))=(n);\ - } \ - nmesa->state_cache.current_pos++; \ -}while(0) - -#define OUT_RING_CACHEp(ptr,sz) do { \ - GLuint* p=(GLuint*)(ptr); \ - int i; \ - for(i=0;i<sz;i++) \ - OUT_RING_CACHE(*(p+i)); \ -}while(0) - -#define OUT_RING_CACHE_FORCE(n) do { \ - nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \ - nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \ - nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value=(n); \ - nmesa->state_cache.current_pos++; \ -}while(0) - -#define OUT_RING_CACHE_FORCEf(n) do { \ - nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \ - nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \ - (*(GLfloat*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))=(n);\ - nmesa->state_cache.current_pos++; \ -}while(0) - -#define OUT_RING_CACHE_FORCEp(ptr,sz) do { \ - GLuint* p=(GLuint*)(ptr); \ - int i; \ - for(i=0;i<sz;i++) \ - OUT_RING_CACHE_FORCE(*(p+i)); \ -}while(0) -#endif - -#define RING_AVAILABLE() (nmesa->fifo.free-1) - -#define RING_AHEAD() ((nmesa->fifo.put<=nmesa->fifo.current)?(nmesa->fifo.current-nmesa->fifo.put):nmesa->fifo.max-nmesa->fifo.put+nmesa->fifo.current) - -#define FIRE_RING() do { \ - if (nmesa->fifo.current!=nmesa->fifo.put) { \ - nmesa->fifo.put=nmesa->fifo.current; \ - NV_FIFO_WRITE_PUT(nmesa->fifo.put); \ - } \ -}while(0) - -extern void nouveauWaitForIdle(nouveauContextPtr nmesa); -extern void nouveauWaitForIdleLocked(nouveauContextPtr nmesa); -extern GLboolean nouveauFifoInit(nouveauContextPtr nmesa); - -#endif /* __NOUVEAU_FIFO_H__ */ - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_lock.c b/src/mesa/drivers/dri/nouveau/nouveau_lock.c deleted file mode 100644 index aa86c9e7838..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_lock.c +++ /dev/null @@ -1,81 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#include "nouveau_context.h" -#include "nouveau_lock.h" - -#include "drirenderbuffer.h" -#include "framebuffer.h" - - -/* Update the hardware state. This is called if another context has - * grabbed the hardware lock, which includes the X server. This - * function also updates the driver's window state after the X server - * moves, resizes or restacks a window -- the change will be reflected - * in the drawable position and clip rects. Since the X server grabs - * the hardware lock when it changes the window state, this routine will - * automatically be called after such a change. - */ -void nouveauGetLock( nouveauContextPtr nmesa, GLuint flags ) -{ - __DRIdrawablePrivate *dPriv = nmesa->driDrawable; - __DRIscreenPrivate *sPriv = nmesa->driScreen; - struct drm_nouveau_sarea *sarea = nmesa->sarea; - - drmGetLock( nmesa->driFd, nmesa->hHWContext, flags ); - - /* The window might have moved, so we might need to get new clip - * rects. - * - * NOTE: This releases and regrabs the hw lock to allow the X server - * to respond to the DRI protocol request for new drawable info. - * Since the hardware state depends on having the latest drawable - * clip rects, all state checking must be done _after_ this call. - */ - DRI_VALIDATE_DRAWABLE_INFO( sPriv, dPriv ); - - /* If timestamps don't match, the window has been changed */ - if (nmesa->lastStamp != dPriv->lastStamp) { - struct gl_framebuffer *fb = (struct gl_framebuffer *)dPriv->driverPrivate; - - /* _mesa_resize_framebuffer will take care of calling the renderbuffer's - * AllocStorage function if we need more memory to hold it */ - if (fb->Width != dPriv->w || fb->Height != dPriv->h) { - _mesa_resize_framebuffer(nmesa->glCtx, fb, dPriv->w, dPriv->h); - /* resize buffers, will call nouveau_window_moved */ - nouveau_build_framebuffer(nmesa->glCtx, fb); - } else { - nouveau_window_moved(nmesa->glCtx); - } - - nmesa->lastStamp = dPriv->lastStamp; - } - - nmesa->numClipRects = dPriv->numClipRects; - nmesa->pClipRects = dPriv->pClipRects; - -} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_lock.h b/src/mesa/drivers/dri/nouveau/nouveau_lock.h deleted file mode 100644 index 38bb0014258..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_lock.h +++ /dev/null @@ -1,69 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#ifndef __NOUVEAU_LOCK_H__ -#define __NOUVEAU_LOCK_H__ - -#include "nouveau_context.h" - -extern void nouveauGetLock( nouveauContextPtr nmesa, GLuint flags ); - -/* - * !!! We may want to separate locks from locks with validation. This - * could be used to improve performance for those things commands that - * do not do any drawing !!! - */ - -/* Lock the hardware and validate our state. - */ -#define LOCK_HARDWARE( nmesa ) \ - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ - DRM_CAS( nmesa->driHwLock, nmesa->hHWContext, \ - (DRM_LOCK_HELD | nmesa->hHWContext), __ret ); \ - if ( __ret ) \ - nouveauGetLock( nmesa, 0 ); \ - DEBUG_LOCK(); \ - } while (0) - -/* Unlock the hardware. - */ -#define UNLOCK_HARDWARE( nmesa ) \ - do { \ - DRM_UNLOCK( nmesa->driFd, \ - nmesa->driHwLock, \ - nmesa->hHWContext ); \ - DEBUG_RESET(); \ - } while (0) - -#define DEBUG_LOCK() -#define DEBUG_RESET() -#define DEBUG_CHECK_LOCK() - - -#endif /* __NOUVEAU_LOCK_H__ */ diff --git a/src/mesa/drivers/dri/nouveau/nouveau_mem.c b/src/mesa/drivers/dri/nouveau/nouveau_mem.c deleted file mode 100644 index 35c53268b06..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_mem.c +++ /dev/null @@ -1,144 +0,0 @@ -#include "mtypes.h" - -#include "nouveau_context.h" -#include "nouveau_fifo.h" -#include "nouveau_mem.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" -#include "nouveau_reg.h" - -#define MAX_MEMFMT_LENGTH 32768 - -/* Unstrided blit using NV_MEMORY_TO_MEMORY_FORMAT */ -GLboolean -nouveau_memformat_flat_emit(GLcontext * ctx, - nouveau_mem * dst, nouveau_mem * src, - GLuint dst_offset, GLuint src_offset, - GLuint size) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - uint32_t src_handle, dst_handle; - GLuint count; - - if (src_offset + size > src->size) { - MESSAGE("src out of nouveau_mem bounds\n"); - return GL_FALSE; - } - if (dst_offset + size > dst->size) { - MESSAGE("dst out of nouveau_mem bounds\n"); - return GL_FALSE; - } - - src_handle = (src->type & NOUVEAU_MEM_FB) ? NvDmaFB : NvDmaTT; - dst_handle = (dst->type & NOUVEAU_MEM_FB) ? NvDmaFB : NvDmaTT; - src_offset += nouveau_mem_gpu_offset_get(ctx, src); - dst_offset += nouveau_mem_gpu_offset_get(ctx, dst); - - BEGIN_RING_SIZE(NvSubMemFormat, - NV_MEMORY_TO_MEMORY_FORMAT_OBJECT_IN, 2); - OUT_RING(src_handle); - OUT_RING(dst_handle); - - count = (size / MAX_MEMFMT_LENGTH) + - ((size % MAX_MEMFMT_LENGTH) ? 1 : 0); - - while (count--) { - GLuint length = - (size > MAX_MEMFMT_LENGTH) ? MAX_MEMFMT_LENGTH : size; - - BEGIN_RING_SIZE(NvSubMemFormat, - NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); - OUT_RING(src_offset); - OUT_RING(dst_offset); - OUT_RING(0); /* pitch in */ - OUT_RING(0); /* pitch out */ - OUT_RING(length); /* line length */ - OUT_RING(1); /* number of lines */ - OUT_RING((1 << 8) /* dst_inc */ |(1 << 0) /* src_inc */ ); - OUT_RING(0); /* buffer notify? */ - FIRE_RING(); - - src_offset += length; - dst_offset += length; - size -= length; - } - - return GL_TRUE; -} - -void nouveau_mem_free(GLcontext * ctx, nouveau_mem * mem) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - struct drm_nouveau_mem_free memf; - - if (NOUVEAU_DEBUG & DEBUG_MEM) { - fprintf(stderr, "%s: type=0x%x, offset=0x%x, size=0x%x\n", - __func__, mem->type, (GLuint) mem->offset, - (GLuint) mem->size); - } - - if (mem->map) - drmUnmap(mem->map, mem->size); - memf.flags = mem->type; - memf.offset = mem->offset; - drmCommandWrite(nmesa->driFd, DRM_NOUVEAU_MEM_FREE, &memf, - sizeof(memf)); - FREE(mem); -} - -nouveau_mem *nouveau_mem_alloc(GLcontext *ctx, uint32_t flags, GLuint size, - GLuint align) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - struct drm_nouveau_mem_alloc mema; - nouveau_mem *mem; - int ret; - - if (NOUVEAU_DEBUG & DEBUG_MEM) { - fprintf(stderr, - "%s: requested: flags=0x%x, size=0x%x, align=0x%x\n", - __func__, flags, (GLuint) size, align); - } - - mem = CALLOC(sizeof(nouveau_mem)); - if (!mem) - return NULL; - - mema.flags = flags; - mema.size = mem->size = size; - mema.alignment = align; - mem->map = NULL; - ret = drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_MEM_ALLOC, - &mema, sizeof(mema)); - if (ret) { - FREE(mem); - return NULL; - } - mem->offset = mema.offset; - mem->type = mema.flags; - - if (NOUVEAU_DEBUG & DEBUG_MEM) { - fprintf(stderr, - "%s: actual: type=0x%x, offset=0x%x, size=0x%x\n", - __func__, mem->type, (GLuint) mem->offset, - (GLuint) mem->size); - } - - if (flags & NOUVEAU_MEM_MAPPED) - ret = drmMap(nmesa->driFd, mema.map_handle, mem->size, - &mem->map); - if (ret) { - mem->map = NULL; - nouveau_mem_free(ctx, mem); - mem = NULL; - } - - return mem; -} - -uint32_t nouveau_mem_gpu_offset_get(GLcontext * ctx, nouveau_mem * mem) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - return mem->offset; -} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_mem.h b/src/mesa/drivers/dri/nouveau/nouveau_mem.h deleted file mode 100644 index 6db73f4708e..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_mem.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __NOUVEAU_MEM_H__ -#define __NOUVEAU_MEM_H__ - -typedef struct nouveau_mem_t { - int type; - uint64_t offset; - uint64_t size; - void *map; -} nouveau_mem; - -extern nouveau_mem *nouveau_mem_alloc(GLcontext *, uint32_t flags, - GLuint size, GLuint align); -extern void nouveau_mem_free(GLcontext *, nouveau_mem *); -extern uint32_t nouveau_mem_gpu_offset_get(GLcontext *, nouveau_mem *); - -extern GLboolean nouveau_memformat_flat_emit(GLcontext *, - nouveau_mem *dst, - nouveau_mem *src, - GLuint dst_offset, - GLuint src_offset, - GLuint size); - -#endif diff --git a/src/mesa/drivers/dri/nouveau/nouveau_msg.h b/src/mesa/drivers/dri/nouveau/nouveau_msg.h deleted file mode 100644 index 5dea2189c72..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_msg.h +++ /dev/null @@ -1,67 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. -Copyright 2006 Stephane Marchesin. All Rights Reserved - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <[email protected]> - * Nicolai Haehnle <[email protected]> - */ - - -#ifndef __NOUVEAU_MSG_H__ -#define __NOUVEAU_MSG_H__ - -#define WARN_ONCE(a, ...) do {\ - static int warn##__LINE__=1;\ - if(warn##__LINE__){\ - fprintf(stderr, "*********************************WARN_ONCE*********************************\n");\ - fprintf(stderr, "File %s function %s line %d\n", __FILE__, __FUNCTION__, __LINE__);\ - fprintf(stderr, a, ## __VA_ARGS__);\ - fprintf(stderr, "***************************************************************************\n");\ - warn##__LINE__=0;\ - } \ - }while(0) - -#define MESSAGE(a, ...) do{\ - fprintf(stderr, "************************************INFO***********************************\n");\ - fprintf(stderr, "File %s function %s line %d\n", __FILE__, __FUNCTION__, __LINE__); \ - fprintf(stderr, a, ## __VA_ARGS__);\ - fprintf(stderr, "***************************************************************************\n");\ - }while(0) - -#define FATAL(a, ...) do{\ - fprintf(stderr, "***********************************FATAL***********************************\n");\ - fprintf(stderr, "File %s function %s line %d\n", __FILE__, __FUNCTION__, __LINE__); \ - fprintf(stderr, a, ## __VA_ARGS__);\ - fprintf(stderr, "***************************************************************************\n");\ - }while(0) - -#endif /* __NOUVEAU_MSG_H__ */ - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_object.c b/src/mesa/drivers/dri/nouveau/nouveau_object.c deleted file mode 100644 index 8f33093f1a5..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_object.c +++ /dev/null @@ -1,98 +0,0 @@ - -#include "nouveau_fifo.h" -#include "nouveau_object.h" -#include "nouveau_reg.h" - - -GLboolean nouveauCreateContextObject(nouveauContextPtr nmesa, - uint32_t handle, int class) -{ - struct drm_nouveau_grobj_alloc cto; - int ret; - - cto.channel = nmesa->fifo.drm.channel; - cto.handle = handle; - cto.class = class; - ret = drmCommandWrite(nmesa->driFd, DRM_NOUVEAU_GROBJ_ALLOC, - &cto, sizeof(cto)); - - return ret == 0; -} - -void nouveauObjectOnSubchannel(nouveauContextPtr nmesa, int subchannel, int handle) -{ - BEGIN_RING_SIZE(subchannel, 0, 1); - OUT_RING(handle); -} - -void nouveauObjectInit(nouveauContextPtr nmesa) -{ -#ifdef NOUVEAU_RING_DEBUG - return; -#endif - - nouveauCreateContextObject(nmesa, Nv3D, nmesa->screen->card->class_3d); - if (nmesa->screen->card->type>=NV_10) { - nouveauCreateContextObject(nmesa, NvCtxSurf2D, NV10_CONTEXT_SURFACES_2D); - } else { - nouveauCreateContextObject(nmesa, NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D); - nouveauCreateContextObject(nmesa, NvCtxSurf3D, NV04_CONTEXT_SURFACES_3D); - } - if (nmesa->screen->card->type>=NV_11) { - nouveauCreateContextObject(nmesa, NvImageBlit, NV11_IMAGE_BLIT); - } else { - nouveauCreateContextObject(nmesa, NvImageBlit, NV_IMAGE_BLIT); - } - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<NV_20)) { - nouveauCreateContextObject(nmesa, NvGdiRectText, NV04_GDI_RECTANGLE_TEXT); - nouveauCreateContextObject(nmesa, NvRasterOp, NV03_PRIMITIVE_RASTER_OP); - nouveauCreateContextObject(nmesa, NvPattern, NV04_IMAGE_PATTERN); - } - nouveauCreateContextObject(nmesa, NvMemFormat, NV_MEMORY_TO_MEMORY_FORMAT); - - nouveauObjectOnSubchannel(nmesa, NvSubCtxSurf2D, NvCtxSurf2D); - BEGIN_RING_SIZE(NvSubCtxSurf2D, NV10_CONTEXT_SURFACES_2D_SET_DMA_IN_MEMORY0, 2); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaFB); - - nouveauObjectOnSubchannel(nmesa, NvSubImageBlit, NvImageBlit); - BEGIN_RING_SIZE(NvSubImageBlit, NV_IMAGE_BLIT_SET_SURFACES_2D, 1); - OUT_RING(NvCtxSurf2D); - BEGIN_RING_SIZE(NvSubImageBlit, NV_IMAGE_BLIT_OPERATION, 1); - OUT_RING(3); /* SRCCOPY */ - - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<NV_20)) { - nouveauObjectOnSubchannel(nmesa, NvSubPattern, NvPattern); - - BEGIN_RING_SIZE(NvSubPattern, NV04_IMAGE_PATTERN_COLOR_FORMAT, 4); - OUT_RING(1); /* A16R5G6B5 */ - OUT_RING(1); /* little endian */ - OUT_RING(0); /* 8x8 */ - OUT_RING(1); /* monochrome */ - - nouveauObjectOnSubchannel(nmesa, NvSubRasterOp, NvRasterOp); - - BEGIN_RING_SIZE(NvSubRasterOp, NV03_PRIMITIVE_RASTER_OP_DMA_NOTIFY, 1); - OUT_RING(NvSyncNotify); - - nouveauObjectOnSubchannel(nmesa, NvSubGdiRectText, NvGdiRectText); - - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_SET_DMA_NOTIFY, 1); - OUT_RING(NvSyncNotify); - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_PATTERN, 2); - OUT_RING(NvPattern); - OUT_RING(NvRasterOp); - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1); - OUT_RING(NvCtxSurf2D); - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_FORMAT, 2); - OUT_RING(1); /* X1R5G5B5 */ - OUT_RING(1); /* little endian */ - } - - nouveauObjectOnSubchannel(nmesa, NvSubMemFormat, NvMemFormat); - - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); -} - - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_object.h b/src/mesa/drivers/dri/nouveau/nouveau_object.h deleted file mode 100644 index 10859de1190..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_object.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef __NOUVEAU_OBJECT_H__ -#define __NOUVEAU_OBJECT_H__ - -#include "nouveau_context.h" - -void nouveauObjectInit(nouveauContextPtr nmesa); - -enum DMAObjects { - Nv3D = 0x80000019, - NvCtxSurf2D = 0x80000020, - NvImageBlit = 0x80000021, - NvMemFormat = 0x80000022, - NvCtxSurf3D = 0x80000023, - NvGdiRectText = 0x80000024, - NvPattern = 0x80000025, - NvRasterOp = 0x80000026, - NvDmaFB = 0xD0FB0001, - NvDmaTT = 0xD0AA0001, - NvSyncNotify = 0xD0000001, - NvQueryNotify = 0xD0000002 -}; - -enum DMASubchannel { - NvSubCtxSurf2D = 0, - NvSubImageBlit = 1, - NvSubMemFormat = 2, - NvSubCtxSurf3D = 3, - NvSubGdiRectText= 4, - NvSubPattern = 5, - NvSubRasterOp = 6, - NvSub3D = 7, -}; - -extern void nouveauObjectOnSubchannel(nouveauContextPtr nmesa, int subchannel, int handle); - -extern GLboolean nouveauCreateContextObject(nouveauContextPtr nmesa, - uint32_t handle, int class); - -#endif diff --git a/src/mesa/drivers/dri/nouveau/nouveau_query.c b/src/mesa/drivers/dri/nouveau/nouveau_query.c deleted file mode 100644 index e5c1750a8ec..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_query.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* GL_ARB_occlusion_query support for NV20/30/40 */ - -#include "mtypes.h" - -#include "nouveau_fifo.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" -#include "nouveau_reg.h" -#include "nouveau_sync.h" -#include "nouveau_query.h" - -static struct gl_query_object * -nouveauNewQueryObject(GLcontext *ctx, GLuint id) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_query_object *nq; - int i; - - for (i=0; i<nmesa->query_object_max; i++) - if (nmesa->query_alloc[i] == GL_FALSE) - break; - if (i==nmesa->query_object_max) - return NULL; - - nq = CALLOC_STRUCT(nouveau_query_object_t); - if (nq) { - nq->notifier_id = i; - - nq->mesa.Id = id; - nq->mesa.Result = 0; - nq->mesa.Active = GL_FALSE; - nq->mesa.Ready = GL_TRUE; - } - - return (struct gl_query_object *)nq; -} - -static void -nouveauBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_query_object *nq = (nouveau_query_object *)q; - - nouveau_notifier_reset(ctx, nmesa->queryNotifier, nq->notifier_id); - - switch (nmesa->screen->card->type) { - case NV_20: - BEGIN_RING_CACHE(NvSub3D, 0x17c8, 1); - OUT_RING_CACHE (1); - BEGIN_RING_CACHE(NvSub3D, 0x17cc, 1); - OUT_RING_CACHE (1); - break; - case NV_30: - case NV_40: - case NV_44: - /* I don't think this is OCC_QUERY enable, but it *is* needed to make - * the SET_OBJECT7 notifier block work with STORE_RESULT. - * - * Also, this appears to reset the pixel pass counter */ - BEGIN_RING_SIZE(NvSub3D, - NV30_TCL_PRIMITIVE_3D_OCC_QUERY_OR_COLOR_BUFF_ENABLE, - 1); - OUT_RING (1); - /* Probably OCC_QUERY_ENABLE */ - BEGIN_RING_CACHE(NvSub3D, 0x17cc, 1); - OUT_RING_CACHE (1); - break; - default: - WARN_ONCE("no support for this card\n"); - break; - } -} - -static void -nouveauUpdateQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_query_object *nq = (nouveau_query_object *)q; - int status; - - status = nouveau_notifier_status(ctx, nmesa->queryNotifier, - nq->notifier_id); - - q->Ready = (status == NV_NOTIFY_STATE_STATUS_COMPLETED); - if (q->Ready) - q->Result = nouveau_notifier_return_val(ctx, - nmesa->queryNotifier, - nq->notifier_id); -} - -static void -nouveauWaitQueryResult(GLcontext *ctx, GLenum target, struct gl_query_object *q) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nouveau_query_object *nq = (nouveau_query_object *)q; - - nouveau_notifier_wait_status(ctx, nmesa->queryNotifier, nq->notifier_id, - NV_NOTIFY_STATE_STATUS_COMPLETED, 0); - nouveauUpdateQuery(ctx, target, q); -} - -static void -nouveauEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) -{ - nouveau_query_object *nq = (nouveau_query_object *)q; - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - switch (nmesa->screen->card->type) { - case NV_20: - BEGIN_RING_SIZE(NvSub3D, 0x17d0, 1); - OUT_RING (0x01000000 | nq->notifier_id*32); - break; - case NV_30: - case NV_40: - case NV_44: - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STORE_RESULT, 1); - OUT_RING (0x01000000 | nq->notifier_id*32); - break; - default: - WARN_ONCE("no support for this card\n"); - break; - } - FIRE_RING(); - - /*XXX: wait for query to complete, mesa doesn't give the driver - * an interface to query the status of a query object so - * this has to stall the channel. - */ - nouveauWaitQueryResult(ctx, target, q); - - BEGIN_RING_CACHE(NvSub3D, 0x17cc, 1); - OUT_RING_CACHE (0); -} - -void -nouveauQueryInitFuncs(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (nmesa->screen->card->type < NV_20) - return; - - /* Reserve half the notifier block for use as query objects */ - nmesa->query_object_max = (nmesa->fifo.drm.notifier_size / 2) / 32; - nmesa->queryNotifier = - nouveau_notifier_new(ctx, NvQueryNotify, - nmesa->query_object_max); - nmesa->query_alloc = calloc(nmesa->query_object_max, sizeof(GLboolean)); - - switch (nmesa->screen->card->type) { - case NV_20: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT8, 1); - OUT_RING_CACHE (NvQueryNotify); - break; - case NV_30: - case NV_40: - case NV_44: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT7, 1); - OUT_RING_CACHE (NvQueryNotify); - break; - default: - break; - }; - - ctx->Driver.NewQueryObject = nouveauNewQueryObject; - ctx->Driver.BeginQuery = nouveauBeginQuery; - ctx->Driver.EndQuery = nouveauEndQuery; -#if 0 - ctx->Driver.UpdateQuery = nouveauUpdateQuery; - ctx->Driver.WaitQueryResult = nouveauWaitQueryResult; -#endif -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_reg.h b/src/mesa/drivers/dri/nouveau/nouveau_reg.h deleted file mode 100644 index 6b90bab0766..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_reg.h +++ /dev/null @@ -1,4998 +0,0 @@ -/* - Autogenerated file, do not edit ! - -************************************************************************** - - Copyright (C) 2006 : - Dmitry Baryshkov, - Laurent Carlier, - Matthieu Castet, - Dawid Gajownik, - Jeremy Kolb, - Stephane Loeuillet, - Patrice Mandin, - Stephane Marchesin, - Serge Martin, - Sylvain Munaut, - Ben Skeggs, - Erik Waling, - koala_br, - sturmflut. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -************************************************************************** - - Created from objects.c rev. 1.440 -*/ - -#ifndef _NOUVEAU_REG_H -#define _NOUVEAU_REG_H - -/****************************************** -Object NV01_CONTEXT_CLIP_RECTANGLE used on: NV03 NV04 NV10 NV15 NV20 NV40 G70 -*/ -#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019 -# define NV01_CONTEXT_CLIP_RECTANGLE_NOP 0x00000100 -# define NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY 0x00000104 -# define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180 -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT 0x00000300 /* Parameters: x y */ -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT_X_MASK 0x0000ffff -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT_Y_MASK 0xffff0000 -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT_Y_SHIFT 16 -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE 0x00000304 /* Parameters: width height */ -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE_WIDTH_MASK 0x0000ffff -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE_HEIGHT_MASK 0xffff0000 -# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE_HEIGHT_SHIFT 16 - -/****************************************** -Object NV_MEMORY_TO_MEMORY_FORMAT used on: NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -# define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -# define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -# define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 -# define NV_MEMORY_TO_MEMORY_FORMAT_OBJECT_IN 0x00000184 -# define NV_MEMORY_TO_MEMORY_FORMAT_OBJECT_OUT 0x00000188 -# define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c -# define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310 -# define NV_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314 -# define NV_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318 -# define NV_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c -# define NV_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320 -# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324 /* Parameters: src_inc dst_inc */ -# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_SRC_INC_MASK 0x00000007 -# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_DST_INC_MASK 0x00000700 -# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_DST_INC_SHIFT 8 -# define NV_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328 - -/****************************************** -Object NV03_PRIMITIVE_RASTER_OP used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV03_PRIMITIVE_RASTER_OP 0x00000043 -# define NV03_PRIMITIVE_RASTER_OP_NOP 0x00000100 -# define NV03_PRIMITIVE_RASTER_OP_NOTIFY 0x00000104 -# define NV03_PRIMITIVE_RASTER_OP_DMA_NOTIFY 0x00000180 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP 0x00000300 /* Parameters: logic_op */ -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_MASK 0x000000f0 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_SHIFT 4 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_CLEAR 0x0000 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_NOR 0x0001 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_AND_INVERTED 0x0002 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_COPY_INVERTED 0x0003 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_AND_REVERSE 0x0004 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_INVERT 0x0005 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_XOR 0x0006 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_NAND 0x0007 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_AND 0x0008 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_EQUIV 0x0009 -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_NOOP 0x000a -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_OR_INVERTED 0x000b -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_COPY 0x000c -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_OR_REVERSE 0x000d -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_OR 0x000e -# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_SET 0x000f - -/****************************************** -Object NV04_GDI_RECTANGLE_TEXT used on: NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV04_GDI_RECTANGLE_TEXT 0x0000004a -# define NV04_GDI_RECTANGLE_TEXT_NOP 0x00000100 -# define NV04_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104 -# define NV04_GDI_RECTANGLE_TEXT_SET_DMA_NOTIFY 0x00000180 -# define NV04_GDI_RECTANGLE_TEXT_SET_DMA_FONTS 0x00000184 -# define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188 -# define NV04_GDI_RECTANGLE_TEXT_ROP5 0x0000018c -# define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198 -# define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc -# define NV04_GDI_RECTANGLE_TEXT_FORMAT 0x00000300 -# define NV04_GDI_RECTANGLE_TEXT_MONO_FORMAT 0x00000304 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL 0x000005f4 /* Parameters: left top */ -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL_LEFT_MASK 0x0000ffff -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL_TOP_MASK 0xffff0000 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL_TOP_SHIFT 16 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR 0x000005f8 /* Parameters: right bottom */ -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR_RIGHT_MASK 0x0000ffff -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR_BOTTOM_MASK 0xffff0000 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR_BOTTOM_SHIFT 16 -# define NV04_GDI_RECTANGLE_TEXT_FILL_VALUE 0x000005fc -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL 0x00000600 /* Parameters: left top */ -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL_LEFT_MASK 0x0000ffff -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL_TOP_MASK 0xffff0000 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL_TOP_SHIFT 16 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR 0x00000604 /* Parameters: right bottom */ -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR_RIGHT_MASK 0x0000ffff -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR_BOTTOM_MASK 0xffff0000 -# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR_BOTTOM_SHIFT 16 - -/****************************************** -Object NV04_SWIZZLED_SURFACE used on: NV04 NV10 NV15 -*/ -#define NV04_SWIZZLED_SURFACE 0x00000052 -# define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180 -# define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184 -# define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300 /* Parameters: log2_height log2_width color */ -# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_MASK 0xff000000 -# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_SHIFT 24 -# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_MASK 0x00ff0000 -# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_SHIFT 16 -# define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x0000ffff -# define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304 - -/****************************************** -Object NV04_CONTEXT_SURFACES_3D used on: NV04 -*/ -#define NV04_CONTEXT_SURFACES_3D 0x00000053 -# define NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180 -# define NV04_CONTEXT_SURFACES_3D_DMA_COLOR 0x00000184 -# define NV04_CONTEXT_SURFACES_3D_DMA_ZETA 0x00000188 -# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL 0x000002f8 /* Parameters: x width */ -# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK 0x0000ffff -# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_WIDTH_MASK 0xffff0000 -# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_WIDTH_SHIFT 16 -# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL 0x000002fc /* Parameters: y height */ -# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK 0x0000ffff -# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_HEIGHT_MASK 0xffff0000 -# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_HEIGHT_SHIFT 16 -# define NV04_CONTEXT_SURFACES_3D_FORMAT 0x00000300 /* Parameters: color type width height */ -# define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK 0x000000ff -# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK 0x0000ff00 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT 8 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_pitch 0x0001 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_swizzle 0x0002 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_WIDTH_MASK 0x00ff0000 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_WIDTH_SHIFT 16 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_HEIGHT_MASK 0xff000000 -# define NV04_CONTEXT_SURFACES_3D_FORMAT_HEIGHT_SHIFT 24 -# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE 0x00000304 /* Parameters: width height */ -# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_WIDTH_MASK 0x0000ffff -# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_HEIGHT_MASK 0xffff8000 -# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_HEIGHT_SHIFT 15 -# define NV04_CONTEXT_SURFACES_3D_PITCH 0x00000308 /* Parameters: color zeta */ -# define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK 0x0000ffff -# define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK 0xffff0000 -# define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT 16 -# define NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x0000030c -# define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000310 - -/****************************************** -Object NV04_DX5_TEXTURED_TRIANGLE used on: NV04 -*/ -#define NV04_DX5_TEXTURED_TRIANGLE 0x00000054 -# define NV04_DX5_TEXTURED_TRIANGLE_NOP 0x00000100 -# define NV04_DX5_TEXTURED_TRIANGLE_NOTIFY 0x00000104 -# define NV04_DX5_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180 -# define NV04_DX5_TEXTURED_TRIANGLE_DMA_1 0x00000184 -# define NV04_DX5_TEXTURED_TRIANGLE_DMA_2 0x00000188 -# define NV04_DX5_TEXTURED_TRIANGLE_SURFACE 0x0000018c -# define NV04_DX5_TEXTURED_TRIANGLE_COLOR_KEY 0x00000300 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308 /* Parameters: color mipmaps log_u log_v wrap_s wrap_t */ -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00000f00 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 8 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_Y8 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_A1R5G5B5 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_X1R5G5B5 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_A4R4G4B4 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_R5G6B5 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_A8R8G8B8 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_X8R8G8B8 0x0007 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_MIPMAPS_MASK 0x0000f000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_MIPMAPS_SHIFT 12 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_U_MASK 0x000f0000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_U_SHIFT 16 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_V_MASK 0x00f00000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_V_SHIFT 20 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_MASK 0x07000000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_SHIFT 24 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_REPEAT 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_MIRRORED 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_CLAMP 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_MASK 0x70000000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_SHIFT 28 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_REPEAT 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_MIRRORED 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_CLAMP 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER 0x0000030c /* Parameters: magfilter minfilter lodbias */ -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_MASK 0x70000000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_SHIFT 28 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_NEAREST 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_LINEAR 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_MASK 0x07000000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_SHIFT 24 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_NEAREST 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_LINEAR 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_LODBIAS_MASK 0x00ff0000 -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_LODBIAS_SHIFT 16 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND 0x00000310 /* Parameters: texture benable dst src */ -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MASK 0x0000000f -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE_MASK 0x00100000 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE (1 << 20) -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE_TRUE 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE_FALSE 0x0000 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_0 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_1 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_src_col 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_inv_src_col 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_src_a 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_inv_src_a 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_dst_col 0x0009 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_inv_dst_col 0x000a -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_0 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_1 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_src_col 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_inv_src_col 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_src_a 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_inv_src_a 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_dst_col 0x0009 -# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_inv_dst_col 0x000a -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL 0x00000314 /* Parameters: alpharef alphafunc alphaenable zenable zwrite zfunc cullmode */ -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAREF_MASK 0x000000ff -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_MASK 0x00000f00 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_SHIFT 8 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_NEVER 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_LESS 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_EQUAL 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_LEQUAL 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_GREATER 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_NOTEQUAL 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_GEQUAL 0x0007 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_ALWAYS 0x0008 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE_MASK 0x00001000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE (1 << 12) -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE_TRUE 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE_FALSE 0x0000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE_MASK 0x00004000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE (1 << 14) -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE_TRUE 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE_FALSE 0x0000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE_MASK 0x01000000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE (1 << 24) -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE_TRUE 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE_FALSE 0x0000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_MASK 0x000f0000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_SHIFT 16 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_NEVER 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_LESS 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_EQUAL 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_LEQUAL 0x0004 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_GREATER 0x0005 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_NOTEQUAL 0x0006 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_GEQUAL 0x0007 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_ALWAYS 0x0008 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_MASK 0x00300000 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_SHIFT 20 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_NONE 0x0001 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_CW 0x0002 -# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_CCW 0x0003 -# define NV04_DX5_TEXTURED_TRIANGLE_FOG_COLOR 0x00000318 -# define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX( d) (0x00000400 + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY( d) (0x00000404 + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ( d) (0x00000408 + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_INV_W( d) (0x0000040c + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_COLOR( d) (0x00000410 + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_SPECULAR( d) (0x00000414 + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_S( d) (0x00000418 + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_T( d) (0x0000041c + (d) * 0x0020) -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW 0x00000600 /* Parameters: v0 v1 v2 v3 v4 v5 */ -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V0_MASK 0x0000000f -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V1_MASK 0x000000f0 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V1_SHIFT 4 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V2_MASK 0x00000f00 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V2_SHIFT 8 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V3_MASK 0x0000f000 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V3_SHIFT 12 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V4_MASK 0x000f0000 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V4_SHIFT 16 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V5_MASK 0x00f00000 -# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V5_SHIFT 20 - -/****************************************** -Object NV04_DX6_MULTITEX_TRIANGLE used on: NV04 NV10 NV15 -*/ -#define NV04_DX6_MULTITEX_TRIANGLE 0x00000055 -# define NV04_DX6_MULTITEX_TRIANGLE_NOP 0x00000100 -# define NV04_DX6_MULTITEX_TRIANGLE_NOTIFY 0x00000104 -# define NV04_DX6_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180 -# define NV04_DX6_MULTITEX_TRIANGLE_DMA_1 0x00000184 -# define NV04_DX6_MULTITEX_TRIANGLE_DMA_2 0x00000188 -# define NV04_DX6_MULTITEX_TRIANGLE_SURFACE 0x0000018c -# define NV04_DX6_MULTITEX_TRIANGLE_OFFSET0 0x00000308 -# define NV04_DX6_MULTITEX_TRIANGLE_OFFSET1 0x0000030c -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0 0x00000310 /* Parameters: color mipmaps log_u log_v wrap_s wrap_t */ -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_MASK 0x00000f00 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_SHIFT 8 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_Y8 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_A1R5G5B5 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_X1R5G5B5 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_A4R4G4B4 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_R5G6B5 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_A8R8G8B8 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_X8R8G8B8 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_MIPMAPS_MASK 0x0000f000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_MIPMAPS_SHIFT 12 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_U_MASK 0x000f0000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_U_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_V_MASK 0x00f00000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_V_SHIFT 20 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_MASK 0x07000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_SHIFT 24 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_REPEAT 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_MIRRORED 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_CLAMP 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_MASK 0x70000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_SHIFT 28 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_REPEAT 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_MIRRORED 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_CLAMP 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1 0x00000314 /* Parameters: color mipmaps log_u log_v wrap_s wrap_t */ -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_MASK 0x00000f00 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_SHIFT 8 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_Y8 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_A1R5G5B5 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_X1R5G5B5 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_A4R4G4B4 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_R5G6B5 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_A8R8G8B8 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_X8R8G8B8 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_MIPMAPS_MASK 0x0000f000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_MIPMAPS_SHIFT 12 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_U_MASK 0x000f0000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_U_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_V_MASK 0x00f00000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_V_SHIFT 20 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_MASK 0x07000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_SHIFT 24 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_REPEAT 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_MIRRORED 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_CLAMP 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_MASK 0x70000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_SHIFT 28 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_REPEAT 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_MIRRORED 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_CLAMP 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0 0x00000318 /* Parameters: magfilter minfilter lodbias */ -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_MASK 0x70000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_SHIFT 28 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_NEAREST 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_LINEAR 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_MASK 0x07000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_SHIFT 24 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_NEAREST 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_LINEAR 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_LODBIAS_MASK 0x00ff0000 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_LODBIAS_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1 0x0000031c /* Parameters: magfilter minfilter lodbias */ -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_MASK 0x70000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_SHIFT 28 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_NEAREST 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_LINEAR 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_MASK 0x07000000 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_SHIFT 24 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_NEAREST 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_LINEAR 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_LODBIAS_MASK 0x00ff0000 -# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_LODBIAS_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA 0x00000320 -# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR 0x00000324 -# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA 0x0000032c -# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR 0x00000330 -# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND 0x00000338 /* Parameters: benable dst src */ -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE_MASK 0x00100000 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE (1 << 20) -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_0 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_1 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_src_col 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_inv_src_col 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_src_a 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_inv_src_a 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_dst_col 0x0009 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_inv_dst_col 0x000a -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_0 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_1 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_src_col 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_inv_src_col 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_src_a 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_inv_src_a 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_dst_col 0x0009 -# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_inv_dst_col 0x000a -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0 0x0000033c /* Parameters: red_write green_write blue_write alpha_write alpha_write stencil_write alpharef alphafunc alphaenable zenable zwrite zfunc cullmode */ -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_MASK 0x08000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE (1 << 27) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_MASK 0x10000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE (1 << 28) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_MASK 0x20000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE (1 << 29) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_MASK 0x04000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_MASK 0x04000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_MASK 0x02000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE (1 << 25) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAREF_MASK 0x000000ff -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_MASK 0x00000f00 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_SHIFT 8 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_NEVER 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_LESS 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_EQUAL 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_LEQUAL 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_GREATER 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_NOTEQUAL 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_GEQUAL 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_ALWAYS 0x0008 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE_MASK 0x00001000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE (1 << 12) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE_MASK 0x00004000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE (1 << 14) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE_MASK 0x01000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE (1 << 24) -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE_TRUE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE_FALSE 0x0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_MASK 0x000f0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_NEVER 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_LESS 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_EQUAL 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_LEQUAL 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_GREATER 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_NOTEQUAL 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_GEQUAL 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_ALWAYS 0x0008 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_MASK 0x00300000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_SHIFT 20 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_NONE 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_CW 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_CCW 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1 0x00000340 /* Parameters: stencil_enable stencil_mask_write stencil_mask_read stencilref stencilfunc */ -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE_MASK 0x00000001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILREF_MASK 0x0000ff00 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILREF_SHIFT 8 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_MASK 0x000000f0 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_SHIFT 4 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_NEVER 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_LESS 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_EQUAL 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_LEQUAL 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_GREATER 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_NOTEQUAL 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_GEQUAL 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_ALWAYS 0x0008 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2 0x00000344 /* Parameters: stencil_fail stencil_zfail stencil_zpass */ -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_FAIL_MASK 0x0000000f -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_MASK 0x000000f0 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_SHIFT 4 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_KEEP 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_ZERO 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_REPLACE 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_INCR 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_DECR 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_INVERT 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_INCR_WRAP 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_DECR_WRAP 0x0008 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_MASK 0x00000f00 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_SHIFT 8 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_KEEP 0x0001 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_ZERO 0x0002 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_REPLACE 0x0003 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_INCR 0x0004 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_DECR 0x0005 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_INVERT 0x0006 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_INCR_WRAP 0x0007 -# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_DECR_WRAP 0x0008 -# define NV04_DX6_MULTITEX_TRIANGLE_FOG_COLOR 0x00000348 -# define NV04_DX6_MULTITEX_TRIANGLE_TLVERTEX_SX( d) (0x00000400 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_TLVERTEX_SY( d) (0x00000404 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_TLVERTEX_SZ( d) (0x00000408 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_INV_W( d) (0x0000040c + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_COLOR( d) (0x00000410 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_SPECULAR( d) (0x00000414 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE0_S( d) (0x00000418 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE0_T( d) (0x0000041c + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE1_S( d) (0x00000420 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE1_T( d) (0x00000424 + (d) * 0x0028) -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW 0x00000540 /* Parameters: v0 v1 v2 v3 v4 v5 */ -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V0_MASK 0x0000000f -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V1_MASK 0x000000f0 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V1_SHIFT 4 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V2_MASK 0x00000f00 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V2_SHIFT 8 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V3_MASK 0x0000f000 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V3_SHIFT 12 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V4_MASK 0x000f0000 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V4_SHIFT 16 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V5_MASK 0x00f00000 -# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V5_SHIFT 20 - -/****************************************** -Object NV04_COLOR_KEY used on: NV04 NV10 NV15 NV20 NV40 -*/ -#define NV04_COLOR_KEY 0x00000057 -# define NV04_COLOR_KEY_SET_DMA_NOTIFY 0x00000180 -# define NV04_COLOR_KEY_FORMAT 0x00000300 -# define NV04_COLOR_KEY_VALUE 0x00000304 - -/****************************************** -Object NV04_SOLID_LINE used on: NV04 -*/ -#define NV04_SOLID_LINE 0x0000005c -# define NV04_SOLID_LINE_CLIP_RECTANGLE 0x00000184 -# define NV04_SOLID_LINE_PATTERN 0x00000188 -# define NV04_SOLID_LINE_ROP 0x0000018c -# define NV04_SOLID_LINE_SURFACE 0x00000198 -# define NV04_SOLID_LINE_OPERATION 0x000002fc -# define NV04_SOLID_LINE_COLOR_FORMAT 0x00000300 -# define NV04_SOLID_LINE_COLOR_VALUE 0x00000304 -# define NV04_SOLID_LINE_START 0x00000400 /* Parameters: x y */ -# define NV04_SOLID_LINE_START_X_MASK 0x0000ffff -# define NV04_SOLID_LINE_START_Y_MASK 0xffff0000 -# define NV04_SOLID_LINE_START_Y_SHIFT 16 -# define NV04_SOLID_LINE_END 0x00000400 /* Parameters: x y */ -# define NV04_SOLID_LINE_END_X_MASK 0x0000ffff -# define NV04_SOLID_LINE_END_Y_MASK 0xffff0000 -# define NV04_SOLID_LINE_END_Y_SHIFT 16 - -/****************************************** -Object NV04_UNK005E used on: NV04 -*/ -#define NV04_UNK005E 0x0000005e -# define NV04_UNK005E_SET_SURFACE 0x00000198 -# define NV04_UNK005E_UNK02fc 0x000002fc -# define NV04_UNK005E_UNK0300 0x00000300 -# define NV04_UNK005E_COUNTER 0x00000304 - -/****************************************** -Object NV05_SCALED_IMAGE_FROM_MEMORY used on: NV04 -*/ -#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063 -# define NV05_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 -# define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc -# define NV05_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 - -/****************************************** -Object NV04_SCALED_IMAGE_FROM_MEMORY used on: NV04 -*/ -#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077 -# define NV04_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100 -# define NV04_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184 -# define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188 -# define NV04_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c -# define NV04_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190 -# define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194 -# define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198 -# define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300 -# define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS 0x00000308 /* Parameters: x y */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_X_MASK 0x0000ffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_MASK 0xffff0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c /* Parameters: width height */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_WIDTH_MASK 0x0000ffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_MASK 0xffff0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS 0x00000310 /* Parameters: x y */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS_X_MASK 0x0000ffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_MASK 0xffff0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 /* Parameters: width height */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_WIDTH_MASK 0x0000ffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_MASK 0xffff0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318 /* Parameters: int frac_mul_0x100000 */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX_INT_MASK 0xfff00000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX_INT_SHIFT 20 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX_FRAC_MUL_0X100000_MASK 0x000fffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c /* Parameters: int frac_mul_0x100000 */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY_INT_MASK 0xfff00000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY_INT_SHIFT 20 -# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY_FRAC_MUL_0X100000_MASK 0x000fffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 /* Parameters: width height */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_WIDTH_MASK 0x0000ffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_MASK 0xffff0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 /* Parameters: pitch origin filter */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x0001 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x0002 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x0001 -# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x0002 -# define NV04_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c /* Parameters: u_int u_frac_mul_0x10 v_int v_frac_mul_0x10 */ -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_MASK 0xfff00000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_SHIFT 20 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_MASK 0x000f0000 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_SHIFT 16 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_MASK 0x0000fff0 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_SHIFT 4 -# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_V_FRAC_MUL_0X10_MASK 0x0000000f - -/****************************************** -Object NV_IMAGE_FROM_CPU used on: NV04 -*/ -#define NV_IMAGE_FROM_CPU 0x00000061 -# define NV_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 -# define NV_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188 -# define NV_IMAGE_FROM_CPU_PATTERN 0x0000018c -# define NV_IMAGE_FROM_CPU_ROP 0x00000190 -# define NV_IMAGE_FROM_CPU_SURFACE 0x0000019c -# define NV_IMAGE_FROM_CPU_OPERATION 0x000002fc -# define NV_IMAGE_FROM_CPU_FORMAT 0x00000300 - -/****************************************** -Object NV05_IMAGE_FROM_CPU used on: NV04 -*/ -#define NV05_IMAGE_FROM_CPU 0x00000065 -# define NV05_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180 -# define NV05_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188 -# define NV05_IMAGE_FROM_CPU_PATTERN 0x0000018c -# define NV05_IMAGE_FROM_CPU_ROP 0x00000190 -# define NV05_IMAGE_FROM_CPU_BETA1 0x00000194 -# define NV05_IMAGE_FROM_CPU_BETA4 0x00000198 -# define NV05_IMAGE_FROM_CPU_SURFACE 0x0000019c -# define NV05_IMAGE_FROM_CPU_OPERATION 0x000002fc -# define NV05_IMAGE_FROM_CPU_FORMAT 0x00000300 -# define NV05_IMAGE_FROM_CPU_POINT 0x00000304 /* Parameters: x y */ -# define NV05_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff -# define NV05_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000 -# define NV05_IMAGE_FROM_CPU_POINT_Y_SHIFT 16 -# define NV05_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 /* Parameters: x y */ -# define NV05_IMAGE_FROM_CPU_SIZE_OUT_X_MASK 0x0000ffff -# define NV05_IMAGE_FROM_CPU_SIZE_OUT_Y_MASK 0xffff0000 -# define NV05_IMAGE_FROM_CPU_SIZE_OUT_Y_SHIFT 16 -# define NV05_IMAGE_FROM_CPU_SIZE_IN 0x0000030c /* Parameters: x y */ -# define NV05_IMAGE_FROM_CPU_SIZE_IN_X_MASK 0x0000ffff -# define NV05_IMAGE_FROM_CPU_SIZE_IN_Y_MASK 0xffff0000 -# define NV05_IMAGE_FROM_CPU_SIZE_IN_Y_SHIFT 16 -# define NV05_IMAGE_FROM_CPU_COLOR( d) (0x00000400 + (d) * 0x0004) - -/****************************************** -Object NV_IMAGE_BLIT used on: NV04 NV10 NV15 NV20 -*/ -#define NV_IMAGE_BLIT 0x0000005f -# define NV_IMAGE_BLIT_SET_DMA_NOTIFY 0x00000180 -# define NV_IMAGE_BLIT_SET_COLOR_KEY 0x00000184 -# define NV_IMAGE_BLIT_SET_CLIP_RECTANGLE 0x00000188 -# define NV_IMAGE_BLIT_SET_PATTERN 0x0000018c -# define NV_IMAGE_BLIT_SET_ROP5 0x00000190 -# define NV_IMAGE_BLIT_SET_SURFACES_2D 0x0000019c -# define NV_IMAGE_BLIT_OPERATION 0x000002fc -# define NV_IMAGE_BLIT_POINT_IN 0x00000300 /* Parameters: x y */ -# define NV_IMAGE_BLIT_POINT_IN_X_MASK 0x0000ffff -# define NV_IMAGE_BLIT_POINT_IN_Y_MASK 0xffff0000 -# define NV_IMAGE_BLIT_POINT_IN_Y_SHIFT 16 -# define NV_IMAGE_BLIT_POINT_OUT 0x00000304 /* Parameters: x y */ -# define NV_IMAGE_BLIT_POINT_OUT_X_MASK 0x0000ffff -# define NV_IMAGE_BLIT_POINT_OUT_Y_MASK 0xffff0000 -# define NV_IMAGE_BLIT_POINT_OUT_Y_SHIFT 16 -# define NV_IMAGE_BLIT_SIZE 0x00000308 /* Parameters: width height */ -# define NV_IMAGE_BLIT_SIZE_WIDTH_MASK 0x0000ffff -# define NV_IMAGE_BLIT_SIZE_HEIGHT_MASK 0xffff0000 -# define NV_IMAGE_BLIT_SIZE_HEIGHT_SHIFT 16 - -/****************************************** -Object NV11_IMAGE_BLIT used on: NV15 NV20 -*/ -#define NV11_IMAGE_BLIT 0x0000009f - -/****************************************** -Object NV30_IMAGE_BLIT used on: NV30 NV40 G70 -*/ -#define NV30_IMAGE_BLIT 0x0000009f - -/****************************************** -Object NV10_TCL_PRIMITIVE_3D used on: NV10 -*/ -#define NV10_TCL_PRIMITIVE_3D 0x00000056 -# define NV10_TCL_PRIMITIVE_3D_NOP 0x00000100 -# define NV10_TCL_PRIMITIVE_3D_NOTIFY 0x00000104 -# define NV10_TCL_PRIMITIVE_3D_SET_DMA_NOTIFY 0x00000180 -# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY0 0x00000184 -# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY1 0x00000188 -# define NV10_TCL_PRIMITIVE_3D_SET_DISPLAY_LIST 0x0000018c -# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY2 0x00000194 -# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY3 0x00000198 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ 0x00000200 /* Parameters: width x */ -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT 0x00000204 /* Parameters: height y */ -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT 0x00000208 /* Parameters: type color */ -# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_pitch 0x0001 -# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_swizzle 0x0002 -# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_COLOR_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH 0x0000020c /* Parameters: depth/stencil buffer pitch color buffer pitch */ -# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_DEPTH_STENCIL_BUFFER_PITCH_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_DEPTH_STENCIL_BUFFER_PITCH_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_COLOR_BUFFER_PITCH_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_COLOR_OFFSET 0x00000210 -# define NV10_TCL_PRIMITIVE_3D_DEPTH_OFFSET 0x00000214 -# define NV10_TCL_PRIMITIVE_3D_TX_OFFSET(d) (0x00000218 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT(d) (0x00000220 + (d) * 0x0004) /* Parameters: wrap_t wrap_s log2_height log2_width lod npot format cube_map */ -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_MASK 0xf0000000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_SHIFT 28 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_REPEAT 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_MIRRORED_REPEAT 0x0002 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE 0x0003 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER 0x0004 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP 0x0005 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_MASK 0x0f000000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_REPEAT 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_MIRRORED_REPEAT 0x0002 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE 0x0003 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER 0x0004 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP 0x0005 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_MASK 0x00f00000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_SHIFT 20 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_MASK 0x000f0000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_MASK 0x0000f000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_SHIFT 12 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT_MASK 0x00000800 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT (1 << 11) -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_MASK 0x00000780 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_SHIFT 7 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8 0x0000 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1 0x0002 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT 0x0003 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4 0x0004 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8 0x0006 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_INDEX8 0x000b -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT1 0x000c -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT3 0x000e -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT5 0x000f -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1_RECT 0x0010 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8_RECT 0x0012 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8_RECT 0x0013 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8 0x001a -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT_2 0x001b -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4_RECT 0x001d -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8_RECT 0x0020 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_MASK 0x00000004 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP (1 << 2) -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE(d) (0x00000228 + (d) * 0x0004) /* Parameters: enable anisotropy */ -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_MASK 0x40000000 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE (1 << 30) -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_MASK 0x00000030 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_1 0x0000 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_2 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_4 0x0002 -# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_8 0x0003 -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH(d) (0x00000230 + (d) * 0x0004) /* Parameters: pitch */ -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE(d) (0x00000240 + (d) * 0x0004) /* Parameters: width height */ -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_HEIGHT_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER(d) (0x00000248 + (d) * 0x0004) /* Parameters: mag_filter min_filter */ -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_MASK 0xf0000000 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_SHIFT 28 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR 0x0002 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_MASK 0x0f000000 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST 0x0001 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR 0x0002 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV10_TCL_PRIMITIVE_3D_TX_PALETTE_OFFSET(d) (0x00000250 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(d) (0x000003e0 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_TX_MATRIX(x,y) (0x00000540 + (y) * 0x0010 + (x) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA(d) (0x00000260 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_MASK 0xe0000000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SHIFT 29 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE (1 << 28) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_BLUE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_MASK 0x0f000000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_MASK 0x00e00000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SHIFT 21 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE (1 << 20) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_BLUE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_MASK 0x000f0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_MASK 0x0000e000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SHIFT 13 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_BLUE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_MASK 0x00000f00 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_MASK 0x000000e0 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SHIFT 5 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE (1 << 4) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_BLUE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_INPUT_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB(d) (0x00000268 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_MASK 0xe0000000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SHIFT 29 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE (1 << 28) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_MASK 0x0f000000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_MASK 0x00e00000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SHIFT 21 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE (1 << 20) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_MASK 0x000f0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_MASK 0x0000e000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SHIFT 13 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_MASK 0x00000f00 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_MASK 0x000000e0 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SHIFT 5 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE (1 << 4) -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_INPUT_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(d) (0x00000278 + (d) * 0x0004) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */ -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK 0x00030000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_MASK 0x00008000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS (1 << 15) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_MASK 0x00004000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM (1 << 14) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_MASK 0x00002000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB(d) (0x00000280 + (d) * 0x0004) /* Parameters: rc1_tx_units_enabled rc1_rc_enabled scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */ -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_TX_UNITS_ENABLED_MASK 0x30000000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_TX_UNITS_ENABLED_SHIFT 28 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED_MASK 0x08000000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED (1 << 27) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK 0x00030000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_MASK 0x00008000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS (1 << 15) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_MASK 0x00004000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM (1 << 14) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_MASK 0x00002000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0 0x00000270 /* Parameters: a r g b */ -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_R_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_R_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_B_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1 0x00000274 /* Parameters: a r g b */ -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_R_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_R_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_B_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0 0x00000288 /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_MASK 0xe0000000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SHIFT 29 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE (1 << 28) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_MASK 0x0f000000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_MASK 0x00e00000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SHIFT 21 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE (1 << 20) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_MASK 0x000f0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_MASK 0x0000e000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SHIFT 13 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_MASK 0x00000f00 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_MASK 0x000000e0 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SHIFT 5 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE (1 << 4) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_INPUT_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1 0x0000028c /* Parameters: vare_mapping vare_component_usage vare_input varf_mapping varf_component_usage varf_input varg_mapping varg_component_usage varg_input color_sum_clamp */ -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_MASK 0xe0000000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SHIFT 29 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_MASK 0x10000000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE (1 << 28) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_MASK 0x0f000000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_MASK 0x00e00000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SHIFT 21 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_MASK 0x00100000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE (1 << 20) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_MASK 0x000f0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_MASK 0x0000e000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SHIFT 13 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_RGB 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_ALPHA 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_MASK 0x00000f00 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_ZERO 0x0000 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_FOG 0x0003 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE1_ARB 0x0008 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE0_ARB 0x0009 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_NV 0x000c -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE1_NV 0x000d -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_E_TIMES_F_NV 0x000f -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_MASK 0x00000080 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL 0x00000294 /* Parameters: local_viewer color_control */ -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER_MASK 0x00010000 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER (1 << 16) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL_MASK 0x00000002 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL 1 // Nothing to shift -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL_SINGLE_COLOR 0x0000 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL_SEPARATE_SPECULAR_COLOR 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE 0x00000298 /* Parameters: specular diffuse ambient emission */ -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR_MASK 0x00000008 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR (1 << 3) -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE_MASK 0x00000004 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE (1 << 2) -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT_MASK 0x00000002 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT 1 // Nothing to shift -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_EMISSION_MASK 0x00000001 -# define NV10_TCL_PRIMITIVE_3D_FOG_MODE 0x0000029c -# define NV10_TCL_PRIMITIVE_3D_FOG_COORD_DIST 0x000002a0 -# define NV10_TCL_PRIMITIVE_3D_FOG_ENABLE 0x000002a4 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR 0x000002a8 /* Parameters: a b g r */ -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE 0x000002b4 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(d) (0x000002c0 + (d) * 0x0004) /* Parameters: enable clip at x2 x2 enable clip at x1 x1 */ -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2_MASK 0x08000000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2 (1 << 27) -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_MASK 0x07ff0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1_MASK 0x00000800 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1 (1 << 11) -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X1_MASK 0x000007ff -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(d) (0x000002e0 + (d) * 0x0004) /* Parameters: enable clip at y2 y2 enable clip at y1 y1 */ -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2_MASK 0x08000000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2 (1 << 27) -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_MASK 0x07ff0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1_MASK 0x00000800 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1 (1 << 11) -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y1_MASK 0x000007ff -# define NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x00000300 -# define NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE 0x00000304 -# define NV10_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x00000308 -# define NV10_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x0000030c -# define NV10_TCL_PRIMITIVE_3D_DITHER_ENABLE 0x00000310 -# define NV10_TCL_PRIMITIVE_3D_LIGHTING_ENABLE 0x00000314 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE 0x00000318 -# define NV10_TCL_PRIMITIVE_3D_POINT_SMOOTH_ENABLE 0x0000031c -# define NV10_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x00000320 -# define NV10_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00000324 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_WEIGHT_ENABLE 0x00000328 -# define NV10_TCL_PRIMITIVE_3D_STENCIL_ENABLE 0x0000032c -# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000330 -# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000334 -# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000338 -# define NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x0000033c -# define NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x00000340 -# define NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC 0x00000344 -# define NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST 0x00000348 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR 0x0000034c /* Parameters: a r g b */ -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION 0x00000350 -# define NV10_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x00000354 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK 0x00000358 /* Parameters: a r g b */ -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x0000035c -# define NV10_TCL_PRIMITIVE_3D_STENCIL_MASK 0x00000360 -# define NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC 0x00000364 -# define NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_REF 0x00000368 -# define NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_MASK 0x0000036c -# define NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL 0x00000370 -# define NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL 0x00000374 -# define NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS 0x00000378 -# define NV10_TCL_PRIMITIVE_3D_SHADE_MODEL 0x0000037c -# define NV10_TCL_PRIMITIVE_3D_LINE_WIDTH 0x00000380 -# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x00000384 -# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x00000388 -# define NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x0000038c -# define NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x00000390 -# define NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000394 -# define NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000398 -# define NV10_TCL_PRIMITIVE_3D_CULL_FACE 0x0000039c -# define NV10_TCL_PRIMITIVE_3D_FRONT_FACE 0x000003a0 -# define NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE 0x000003a4 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_R 0x000003a8 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_G 0x000003ac -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_B 0x000003b0 -# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_A 0x000003b4 -# define NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL 0x000003b8 /* Parameters: color_control */ -# define NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL_COLOR_CONTROL_MASK 0x00000001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS 0x000003bc /* Parameters: light 7 light 6 light 5 light 4 light 3 light 2 light 1 light 0 */ -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_MASK 0x00004000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7 (1 << 14) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_MASK 0x00001000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6 (1 << 12) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_MASK 0x00000400 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5 (1 << 10) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_MASK 0x00000100 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4 (1 << 8) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_MASK 0x00000040 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3 (1 << 6) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_MASK 0x00000010 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2 (1 << 4) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_MASK 0x00000004 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1 (1 << 2) -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_MASK 0x00000001 -# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE( d) (0x000003c0 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE 0x000003e8 /* Parameters: projection modelview0 modelview1 */ -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION_MASK 0x00000004 -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION (1 << 2) -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0_MASK 0x00000002 -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0 1 // Nothing to shift -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0_TRUE 0x0001 -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0_FALSE 0x0000 -# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW1_MASK 0x00000001 -# define NV10_TCL_PRIMITIVE_3D_POINT_SIZE 0x000003ec -# define NV10_TCL_PRIMITIVE_3D_MODELVIEW0_MATRIX( d) (0x00000400 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_MODELVIEW1_MATRIX( d) (0x00000440 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW0_MATRIX( d) (0x00000480 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW1_MATRIX( d) (0x000004c0 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX( d) (0x00000500 + (d) * 0x0004) -# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_A(d) (0x00000600 + (d) * 0x0010) -# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_B(d) (0x00000604 + (d) * 0x0010) -# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_C(d) (0x00000608 + (d) * 0x0010) -# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_D(d) (0x0000060c + (d) * 0x0010) -# define NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT 0x00000680 -# define NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR 0x00000684 -# define NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC 0x00000688 -# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_A 0x000006a0 -# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_B 0x000006a4 -# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_C 0x000006a8 -# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_D 0x000006ac -# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_E 0x000006b0 -# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_F 0x000006b4 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000006c4 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000006c8 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000006cc -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X 0x000006e8 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_Y 0x000006ec -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_Z 0x000006f0 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_W 0x000006f4 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_A 0x000006f8 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_B 0x000006fc -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_C 0x00000700 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_D 0x00000704 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_E 0x00000708 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_F 0x0000070c -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_G 0x00000710 -# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_H 0x00000714 -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(d) (0x00000800 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(d) (0x00000804 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(d) (0x00000808 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(d) (0x0000080c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(d) (0x00000810 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(d) (0x00000814 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(d) (0x00000818 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(d) (0x0000081c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(d) (0x00000820 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(d) (0x00000828 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(d) (0x0000082c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(d) (0x00000830 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(d) (0x00000834 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(d) (0x00000838 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(d) (0x0000083c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(d) (0x00000840 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_EXPONENT(d) (0x00000844 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(d) (0x00000848 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(d) (0x0000084c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(d) (0x00000850 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(d) (0x00000854 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(d) (0x00000858 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(d) (0x0000085c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(d) (0x00000860 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(d) (0x00000864 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(d) (0x00000868 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(d) (0x0000086c + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(d) (0x00000870 + (d) * 0x0080) -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X 0x00000c00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y 0x00000c04 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z 0x00000c08 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X 0x00000c18 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y 0x00000c1c -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z 0x00000c20 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W 0x00000c24 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X 0x00000c30 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y 0x00000c34 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z 0x00000c38 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00000c40 /* Parameters: y x */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00000c44 /* Parameters: z */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R 0x00000c50 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G 0x00000c54 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B 0x00000c58 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A 0x00000c5c -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R 0x00000c60 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G 0x00000c64 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B 0x00000c68 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x00000c6c /* Parameters: a b g r */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R 0x00000c80 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G 0x00000c84 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B 0x00000c88 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x00000c8c /* Parameters: a b g r */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S 0x00000c90 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T 0x00000c94 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I 0x00000c98 /* Parameters: t s */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S 0x00000ca0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T 0x00000ca4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R 0x00000ca8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q 0x00000cac -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x00000cb0 /* Parameters: t s */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x00000cb4 /* Parameters: q r */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S 0x00000cb8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T 0x00000cbc -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I 0x00000cc0 /* Parameters: t s */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S 0x00000cc8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T 0x00000ccc -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R 0x00000cd0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q 0x00000cd4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x00000cd8 /* Parameters: t s */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x00000cdc /* Parameters: q r */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00000ce0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_WGH_1F 0x00000ce4 -# define NV10_TCL_PRIMITIVE_3D_EDGEFLAG_ENABLE 0x00000cec -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR( d) (0x00000d04 + (d) * 0x0008) /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_VALIDATE 0x00000cf0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_POS 0x00000d00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS 0x00000d04 /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_COL 0x00000d08 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL 0x00000d0c /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_COL2 0x00000d10 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2 0x00000d14 /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_TX0 0x00000d18 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0 0x00000d1c /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_TX1 0x00000d20 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1 0x00000d24 /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_NOR 0x00000d28 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR 0x00000d2c /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_WGH 0x00000d30 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH 0x00000d34 /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_FOG 0x00000d38 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG 0x00000d3c /* Parameters: stride fields type */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_STRIDE_MASK 0x0000ff00 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_STRIDE_SHIFT 8 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_FIELDS_MASK 0x000000f0 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_FIELDS_SHIFT 4 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_TYPE_MASK 0x0000000f -# define NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE 0x00000d40 -# define NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP 0x00000d44 -# define NV10_TCL_PRIMITIVE_3D_BEGIN_END 0x00000dfc -# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA 0x00000e00 /* Parameters: index1 index0 */ -# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_MASK 0xffff0000 -# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_SHIFT 16 -# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX0_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END 0x000013fc -# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS 0x00001400 /* Parameters: count_minus_1 first */ -# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_COUNT_MINUS_1_MASK 0xff000000 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_COUNT_MINUS_1_SHIFT 24 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK 0x0000ffff -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_X 0x00001638 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Y 0x0000163c -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Z 0x00001640 -# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_W 0x00001644 -# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_DATA 0x00001800 - -/****************************************** -Object NV11_TCL_PRIMITIVE_3D used on: NV15 -*/ -#define NV11_TCL_PRIMITIVE_3D 0x00000096 - -/****************************************** -Object NV17_TCL_PRIMITIVE_3D used on: NV15 -*/ -#define NV17_TCL_PRIMITIVE_3D 0x00000099 -# define NV17_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY4 0x000001ac -# define NV17_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY5 0x000001b0 -# define NV17_TCL_PRIMITIVE_3D_COLOR_MASK_ENABLE 0x000002bc -# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH 0x00000d5c /* Parameters: pitch */ -# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH_PITCH_MASK 0x0000ffff -# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET 0x00000d60 -# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_FILL_VALUE 0x00000d68 -# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_CLEAR_ENABLE 0x00000d6c -# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_ENABLE 0x00001658 - -/****************************************** -Object NV10_IMAGE_FROM_CPU used on: NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV10_IMAGE_FROM_CPU 0x0000008a -# define NV10_IMAGE_FROM_CPU_SET_DMA_NOTIFY 0x00000180 -# define NV10_IMAGE_FROM_CPU_SET_CONTEXT_CLIP_RECTANGLE 0x00000188 -# define NV10_IMAGE_FROM_CPU_SET_IMAGE_PATTERN 0x0000018c -# define NV10_IMAGE_FROM_CPU_SET_RASTER_OP 0x00000190 -# define NV10_IMAGE_FROM_CPU_SET_CONTEXT_SURFACES_2D 0x0000019c -# define NV10_IMAGE_FROM_CPU_OPERATION 0x000002fc -# define NV10_IMAGE_FROM_CPU_FORMAT 0x00000300 -# define NV10_IMAGE_FROM_CPU_POINT 0x00000304 /* Parameters: x y */ -# define NV10_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff -# define NV10_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000 -# define NV10_IMAGE_FROM_CPU_POINT_Y_SHIFT 16 -# define NV10_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 /* Parameters: width height */ -# define NV10_IMAGE_FROM_CPU_SIZE_OUT_WIDTH_MASK 0x0000ffff -# define NV10_IMAGE_FROM_CPU_SIZE_OUT_HEIGHT_MASK 0xffff0000 -# define NV10_IMAGE_FROM_CPU_SIZE_OUT_HEIGHT_SHIFT 16 -# define NV10_IMAGE_FROM_CPU_SIZE_IN 0x0000030c /* Parameters: width height */ -# define NV10_IMAGE_FROM_CPU_SIZE_IN_WIDTH_MASK 0x0000ffff -# define NV10_IMAGE_FROM_CPU_SIZE_IN_HEIGHT_MASK 0xffff0000 -# define NV10_IMAGE_FROM_CPU_SIZE_IN_HEIGHT_SHIFT 16 -# define NV10_IMAGE_FROM_CPU_HLINE 0x00000400 - -/****************************************** -Object NV10_PRIMITIVE_2D used on: NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV10_PRIMITIVE_2D 0x0000007b -# define NV10_PRIMITIVE_2D_SET_DMA_NOTIFY 0x00000180 -# define NV10_PRIMITIVE_2D_SET_SURFACE 0x00000184 -# define NV10_PRIMITIVE_2D_SET_FORMAT 0x00000300 -# define NV10_PRIMITIVE_2D_SET_POINT 0x00000304 /* Parameters: x y */ -# define NV10_PRIMITIVE_2D_SET_POINT_X_MASK 0x0000ffff -# define NV10_PRIMITIVE_2D_SET_POINT_Y_MASK 0xffff0000 -# define NV10_PRIMITIVE_2D_SET_POINT_Y_SHIFT 16 -# define NV10_PRIMITIVE_2D_SET_SIZE 0x00000308 /* Parameters: width height */ -# define NV10_PRIMITIVE_2D_SET_SIZE_WIDTH_MASK 0x0000ffff -# define NV10_PRIMITIVE_2D_SET_SIZE_HEIGHT_MASK 0xffff0000 -# define NV10_PRIMITIVE_2D_SET_SIZE_HEIGHT_SHIFT 16 -# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ 0x0000030c /* Parameters: width x */ -# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ_WIDTH_MASK 0xffff0000 -# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ_WIDTH_SHIFT 16 -# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ_X_MASK 0x0000ffff -# define NV10_PRIMITIVE_2D_SET_CLIP_VERT 0x00000310 /* Parameters: height y */ -# define NV10_PRIMITIVE_2D_SET_CLIP_VERT_HEIGHT_MASK 0xffff0000 -# define NV10_PRIMITIVE_2D_SET_CLIP_VERT_HEIGHT_SHIFT 16 -# define NV10_PRIMITIVE_2D_SET_CLIP_VERT_Y_MASK 0x0000ffff -# define NV10_PRIMITIVE_2D_SET_DATA( d) (0x00000400 + (d) * 0x0004) - -/****************************************** -Object NV10_VIDEO_DISPLAY used on: NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV10_VIDEO_DISPLAY 0x0000007c -# define NV10_VIDEO_DISPLAY_COUNTER 0x00000050 -# define NV10_VIDEO_DISPLAY_SET_DMA_FROM_MEMORY 0x00000180 -# define NV10_VIDEO_DISPLAY_SET_DMA_IN_MEMORY0 0x00000184 -# define NV10_VIDEO_DISPLAY_SET_DMA_IN_MEMORY1 0x00000188 -# define NV10_VIDEO_DISPLAY_SET_OBJECT3 0x0000019c -# define NV10_VIDEO_DISPLAY_SIZE 0x000002f8 /* Parameters: height width */ -# define NV10_VIDEO_DISPLAY_SIZE_HEIGHT_MASK 0xffff0000 -# define NV10_VIDEO_DISPLAY_SIZE_HEIGHT_SHIFT 16 -# define NV10_VIDEO_DISPLAY_SIZE_WIDTH_MASK 0x0000ffff -# define NV10_VIDEO_DISPLAY_OFFSET 0x00000300 - -/****************************************** -Object NV10_UNK0072 used on: NV10 NV15 NV20 NV40 G70 -*/ -#define NV10_UNK0072 0x00000072 -# define NV10_UNK0072_COUNTER 0x00000050 -# define NV40_UNK0072_SET_OBJECT 0x00000060 -# define NV10_UNK0072_SET_DMA_NOTIFY 0x00000180 - -/****************************************** -Object NV10_SCALED_IMAGE_FROM_MEMORY used on: NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089 -# define NV10_SCALED_IMAGE_FROM_MEMORY_COUNTER 0x00000050 -# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_DMA_IN_MEMORY 0x00000184 -# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_RASTER_OP 0x0000018c -# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_IMAGE_PATTERN 0x00000188 -# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_SURFACE 0x00000198 -# define NV10_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304 -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS 0x00000308 /* Parameters: x y */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_X_MASK 0x0000ffff -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_MASK 0xffff0000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_SHIFT 16 -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c /* Parameters: width height */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_WIDTH_MASK 0x0000ffff -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_MASK 0xffff0000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_SHIFT 16 -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS 0x00000310 /* Parameters: x y */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS_X_MASK 0x0000ffff -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_MASK 0xffff0000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_SHIFT 16 -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 /* Parameters: width height */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_WIDTH_MASK 0x0000ffff -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_MASK 0xffff0000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_SHIFT 16 -# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 /* Parameters: width height */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE_WIDTH_MASK 0x0000ffff -# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_MASK 0xffff0000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_SHIFT 16 -# define NV10_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 /* Parameters: pitch */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff -# define NV10_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c /* Parameters: u_int u_frac_mul_0x10 v_int v_frac_mul_0x10 */ -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_MASK 0xfff00000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_SHIFT 20 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_MASK 0x000f0000 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_SHIFT 16 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_MASK 0x0000fff0 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_SHIFT 4 -# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_V_FRAC_MUL_0X10_MASK 0x0000000f - -/****************************************** -Object NV10_CONTEXT_SURFACES_2D used on: NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV10_CONTEXT_SURFACES_2D 0x00000062 -# define NV10_CONTEXT_SURFACES_2D_SET_DMA_NOTIFY 0x00000180 -# define NV10_CONTEXT_SURFACES_2D_SET_DMA_IN_MEMORY0 0x00000184 -# define NV10_CONTEXT_SURFACES_2D_SET_DMA_IN_MEMORY1 0x00000188 -# define NV10_CONTEXT_SURFACES_2D_FORMAT 0x00000300 /* Parameters: color type width height */ -# define NV10_CONTEXT_SURFACES_2D_FORMAT_COLOR_MASK 0x000000ff -# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_MASK 0x0000ff80 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_SHIFT 7 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_pitch 0x0001 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_swizzle 0x0002 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_WIDTH_MASK 0x00ff0000 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_WIDTH_SHIFT 16 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_HEIGHT_MASK 0xff000000 -# define NV10_CONTEXT_SURFACES_2D_FORMAT_HEIGHT_SHIFT 24 -# define NV10_CONTEXT_SURFACES_2D_PITCH 0x00000304 /* Parameters: src dst */ -# define NV10_CONTEXT_SURFACES_2D_PITCH_SRC_MASK 0x0000ffff -# define NV10_CONTEXT_SURFACES_2D_PITCH_DST_MASK 0xffff0000 -# define NV10_CONTEXT_SURFACES_2D_PITCH_DST_SHIFT 16 -# define NV10_CONTEXT_SURFACES_2D_OFFSET_SRC 0x00000308 -# define NV10_CONTEXT_SURFACES_2D_OFFSET_DST 0x0000030c - -/****************************************** -Object NV04_CONTEXT_SURFACES_2D used on: NV04 NV10 NV15 -*/ -#define NV04_CONTEXT_SURFACES_2D 0x00000042 -# define NV04_CONTEXT_SURFACES_2D_NOTIFY 0x00000104 -# define NV04_CONTEXT_SURFACES_2D_SET_DMA_NOTIFY 0x00000180 -# define NV04_CONTEXT_SURFACES_2D_SET_DMA_IMAGE_SRC 0x00000184 -# define NV04_CONTEXT_SURFACES_2D_SET_DMA_IMAGE_DST 0x00000188 -# define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300 -# define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304 /* Parameters: src dst */ -# define NV04_CONTEXT_SURFACES_2D_PITCH_SRC_MASK 0x0000ffff -# define NV04_CONTEXT_SURFACES_2D_PITCH_DST_MASK 0xffff0000 -# define NV04_CONTEXT_SURFACES_2D_PITCH_DST_SHIFT 16 -# define NV04_CONTEXT_SURFACES_2D_OFFSET_SRC 0x00000308 -# define NV04_CONTEXT_SURFACES_2D_OFFSET_DST 0x0000030c - -/****************************************** -Object NV04_IMAGE_PATTERN used on: NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV04_IMAGE_PATTERN 0x00000044 -# define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300 -# define NV04_IMAGE_PATTERN_MONO_FORMAT 0x00000304 -# define NV04_IMAGE_PATTERN_SELECT 0x0000030c -# define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308 -# define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310 -# define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314 -# define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318 -# define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c - -/****************************************** -Object NV20_SWIZZLED_SURFACE used on: NV20 NV30 NV40 G70 -*/ -#define NV20_SWIZZLED_SURFACE 0x0000009e -# define NV20_SWIZZLED_SURFACE_SET_OBJECT0 0x00000180 -# define NV20_SWIZZLED_SURFACE_SET_OBJECT1 0x00000184 -# define NV20_SWIZZLED_SURFACE_FORMAT 0x00000300 /* Parameters: log2_height log2_width color */ -# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_MASK 0xff000000 -# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_SHIFT 24 -# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_MASK 0x00ff0000 -# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_SHIFT 16 -# define NV20_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x0000ffff -# define NV20_SWIZZLED_SURFACE_OFFSET 0x00000304 - -/****************************************** -Object NV20_TCL_PRIMITIVE_3D used on: NV20 -*/ -#define NV20_TCL_PRIMITIVE_3D 0x00000097 -# define NV20_TCL_PRIMITIVE_3D_NOP 0x00000100 -# define NV20_TCL_PRIMITIVE_3D_NOTIFY 0x00000104 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT0 0x00000180 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT1 0x00000184 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT2 0x00000188 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT3 0x00000194 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT4 0x00000198 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT5 0x0000019c -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT6 0x000001a0 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT7 0x000001a4 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT8 0x000001a8 -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT9 0x000001ac -# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT10 0x000001b0 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ 0x00000200 /* Parameters: width x */ -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT 0x00000204 /* Parameters: height y */ -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT 0x00000208 /* Parameters: type color */ -# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_pitch 0x0001 -# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_swizzle 0x0002 -# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_COLOR_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH 0x0000020c /* Parameters: zs_pitch color_pitch */ -# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH_ZS_PITCH_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH_ZS_PITCH_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH_COLOR_PITCH_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_COLOR_OFFSET 0x00000210 -# define NV20_TCL_PRIMITIVE_3D_DEPTH_OFFSET 0x00000214 -# define NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH 0x0000022c /* Parameters: pitch */ -# define NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH_PITCH_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET 0x00000230 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_CONTROL 0x00000294 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL 0x00000298 /* Parameters: back_specular back_ambient back_diffuse back_emission front_specular front_ambient front_diffuse front_emission */ -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR_MASK 0x00004000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR (1 << 14) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE_MASK 0x00000400 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE (1 << 10) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION_MASK 0x00000100 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION (1 << 8) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR_MASK 0x00000040 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR (1 << 6) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT_MASK 0x00000010 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT (1 << 4) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE_MASK 0x00000004 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE (1 << 2) -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_EMISSION_MASK 0x00000001 -# define NV20_TCL_PRIMITIVE_3D_FOG_MODE 0x0000029c -# define NV20_TCL_PRIMITIVE_3D_FOG_COORD_DIST 0x000002a0 -# define NV20_TCL_PRIMITIVE_3D_FOG_ENABLE 0x000002a4 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR 0x000002a8 /* Parameters: a b g r */ -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE 0x000002b4 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(d) (0x000002c0 + (d) * 0x0004) /* Parameters: x2 x1 */ -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X1_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(d) (0x000002e0 + (d) * 0x0004) /* Parameters: y2 y1 */ -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y1_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x00000300 -# define NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE 0x00000304 -# define NV20_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x00000308 -# define NV20_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x0000030c -# define NV20_TCL_PRIMITIVE_3D_DITHER_ENABLE 0x00000310 -# define NV20_TCL_PRIMITIVE_3D_LIGHTING_ENABLE 0x00000314 -# define NV20_TCL_PRIMITIVE_3D_POINT_SMOOTH_ENABLE 0x0000031c -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE 0x00000318 -# define NV20_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x00000320 -# define NV20_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00000324 -# define NV20_TCL_PRIMITIVE_3D_STENCIL_ENABLE 0x0000032c -# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000330 -# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000334 -# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000338 -# define NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x0000033c -# define NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x00000340 -# define NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC 0x00000344 -# define NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST 0x00000348 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR 0x0000034c /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION 0x00000350 -# define NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x00000354 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK 0x00000358 /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x0000035c -# define NV20_TCL_PRIMITIVE_3D_STENCIL_MASK 0x00000360 -# define NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC 0x00000364 -# define NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_REF 0x00000368 -# define NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_MASK 0x0000036c -# define NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL 0x00000370 -# define NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL 0x00000374 -# define NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS 0x00000378 -# define NV20_TCL_PRIMITIVE_3D_SHADE_MODEL 0x0000037c -# define NV20_TCL_PRIMITIVE_3D_LINE_WIDTH 0x00000380 -# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x00000384 -# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x00000388 -# define NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x0000038c -# define NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x00000390 -# define NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000394 -# define NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000398 -# define NV20_TCL_PRIMITIVE_3D_CULL_FACE 0x0000039c -# define NV20_TCL_PRIMITIVE_3D_FRONT_FACE 0x000003a0 -# define NV20_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE 0x000003a4 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_R 0x000003a8 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_G 0x000003ac -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_B 0x000003b0 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_A 0x000003b4 -# define NV20_TCL_PRIMITIVE_3D_SEPARATE_SPECULAR_ENABLE 0x000003b8 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS 0x000003bc /* Parameters: light 7 light 6 light 5 light 4 light 3 light 2 light 1 light 0 */ -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_MASK 0x00002000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7 (1 << 13) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_MASK 0x00008000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6 (1 << 15) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_MASK 0x00000200 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5 (1 << 9) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_MASK 0x00000800 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4 (1 << 11) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_MASK 0x00000020 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3 (1 << 5) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_MASK 0x00000080 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2 (1 << 7) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_MASK 0x00000002 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1 1 // Nothing to shift -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_MASK 0x00000008 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0 (1 << 3) -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(d) (0x000003c0 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(d) (0x00000420 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_POINT_SIZE 0x0000043c -# define NV20_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX( d) (0x00000480 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW_MATRIX( d) (0x00000580 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_PROJECTION_MATRIX( d) (0x00000680 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_TX_MATRIX(x,y) (0x000006c0 + (y) * 0x0010 + (x) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_A(d) (0x00000840 + (d) * 0x0010) -# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_B(d) (0x00000844 + (d) * 0x0010) -# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_C(d) (0x00000848 + (d) * 0x0010) -# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_D(d) (0x0000084c + (d) * 0x0010) -# define NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT 0x000009c0 -# define NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR 0x000009c4 -# define NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC 0x000009c8 -# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_A 0x000009e0 -# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_B 0x000009e4 -# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_C 0x000009e8 -# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_D 0x000009ec -# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_E 0x000009f0 -# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_F 0x000009f4 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE 0x00000a1c /* Parameters: coord_replace r_mode enable */ -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_MASK 0x00000800 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE (1 << 11) -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_MASK 0x00000006 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_SHIFT 1 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_R 0x0001 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_S 0x0002 -# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_ENABLE_MASK 0x00000001 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_OX 0x00000a20 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_OY 0x00000a24 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_DEPTH_AVG_S 0x00000a28 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_UNKNOWN_A 0x00000a2c -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_A 0x00000a30 -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_B 0x00000a34 -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_C 0x00000a38 -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_D 0x00000a3c -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_E 0x00000a40 -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_F 0x00000a44 -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_G 0x00000a48 -# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_H 0x00000a4c -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_PX_DIV2 0x00000af0 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_PY_DIV2 0x00000af4 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_DEPTH_HALF_S 0x00000af8 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_UNKNOWN_B 0x00000afc -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0 0x00000b00 -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST1 0x00000b04 -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST2 0x00000b08 -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST3 0x00000b0c -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_X 0x00000b80 -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Y 0x00000b84 -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Z 0x00000b88 -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_W 0x00000b8c -# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID 0x00001ea4 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18 -# define NV20_TCL_PRIMITIVE_3D_TX_OFFSET(d) (0x00001b00 + (d) * 0x0040) -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT(d) (0x00001b04 + (d) * 0x0040) /* Parameters: log2_height log2_width lod format cube_map */ -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_MASK 0x0f000000 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_MASK 0x00f00000 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_SHIFT 20 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_MASK 0x000f0000 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8 0x0006 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_INDEX8 0x000b -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT1 0x000c -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT3 0x000e -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT5 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1_RECT 0x0010 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8_RECT 0x0012 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8_RECT 0x0013 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8 0x001a -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT_2 0x001b -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4_RECT 0x001d -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8_RECT 0x0020 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_MASK 0x00000004 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP (1 << 2) -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP(d) (0x00001b08 + (d) * 0x0040) /* Parameters: wrap_s wrap_t wrap_r */ -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_S_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_REPEAT 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_MIRRORED_REPEAT 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_CLAMP_TO_EDGE 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_CLAMP_TO_BORDER 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_CLAMP 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_REPEAT 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_MIRRORED_REPEAT 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_CLAMP_TO_EDGE 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_CLAMP_TO_BORDER 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_CLAMP 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE(d) (0x00001b0c + (d) * 0x0040) /* Parameters: enable anisotropy */ -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_MASK 0x40000000 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE (1 << 30) -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_MASK 0x00000030 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_1 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_2 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_4 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_8 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_PITCH(d) (0x00001b10 + (d) * 0x0040) /* Parameters: pitch */ -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER(d) (0x00001b14 + (d) * 0x0040) /* Parameters: mag_filter min_filter */ -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE(d) (0x00001b1c + (d) * 0x0040) /* Parameters: width height */ -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_HEIGHT_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_TX_PALETTE_OFFSET(d) (0x00001b20 + (d) * 0x0040) -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR(d) (0x00001b24 + (d) * 0x0040) /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_RC_ENABLE 0x00001e60 /* Parameters: number of rc enabled */ -# define NV20_TCL_PRIMITIVE_3D_RC_ENABLE_NUMBER_OF_RC_ENABLED_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP 0x00001e70 /* Parameters: op0 op1 op2 op3 */ -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP0_MASK 0x0000001f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_MASK 0x000003e0 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_SHIFT 5 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_TEXTURE_2D 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_PASS_THROUGH 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_CULL_FRAGMENT 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DOT_PRODUCT_TEXTURE_2D 0x0009 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DEPENDANT_AR 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DEPENDANT_GB 0x0010 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DOT_PRODUCT 0x0011 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_MASK 0x00007c00 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_SHIFT 10 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_TEXTURE_2D 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_PASS_THROUGH 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_CULL_FRAGMENT 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DOT_PRODUCT_TEXTURE_2D 0x0009 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DEPENDANT_AR 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DEPENDANT_GB 0x0010 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DOT_PRODUCT 0x0011 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_MASK 0x000f8000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_SHIFT 15 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_TEXTURE_2D 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_PASS_THROUGH 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_CULL_FRAGMENT 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DOT_PRODUCT_TEXTURE_2D 0x0009 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DEPENDANT_AR 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DEPENDANT_GB 0x0010 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DOT_PRODUCT 0x0011 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE 0x000017f8 /* Parameters: cull0 cull1 cull2 cull3 */ -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL0_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gggg 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lggg 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_glgg 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_llgg 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gglg 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lglg 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gllg 0x0006 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lllg 0x0007 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gggl 0x0008 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lggl 0x0009 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_glgl 0x000a -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_llgl 0x000b -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_ggll 0x000c -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lgll 0x000d -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_glll 0x000e -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_llll 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gggg 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lggg 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_glgg 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_llgg 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gglg 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lglg 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gllg 0x0006 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lllg 0x0007 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gggl 0x0008 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lggl 0x0009 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_glgl 0x000a -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_llgl 0x000b -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_ggll 0x000c -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lgll 0x000d -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_glll 0x000e -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_llll 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_MASK 0x0000f000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_SHIFT 12 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gggg 0x0000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lggg 0x0001 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_glgg 0x0002 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_llgg 0x0003 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gglg 0x0004 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lglg 0x0005 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gllg 0x0006 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lllg 0x0007 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gggl 0x0008 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lggl 0x0009 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_glgl 0x000a -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_llgl 0x000b -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_ggll 0x000c -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lgll 0x000d -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_glll 0x000e -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_llll 0x000f -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS 0x00001e78 /* Parameters: prev2 prev3 */ -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV2_MASK 0x00030000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV2_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV3_MASK 0x00300000 -# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV3_SHIFT 20 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0 0x00001e20 /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1 0x00001e24 /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0 0x00000288 /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_MASK 0xe0000000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SHIFT 29 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE (1 << 28) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_MASK 0x0f000000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_MASK 0x00e00000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SHIFT 21 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE (1 << 20) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_MASK 0x000f0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_MASK 0x0000e000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SHIFT 13 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_MASK 0x000000e0 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SHIFT 5 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE (1 << 4) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_INPUT_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1 0x0000028c /* Parameters: vare_mapping vare_component_usage vare_input varf_mapping varf_component_usage varf_input varg_mapping varg_component_usage varg_input color_sum_clamp */ -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_MASK 0xe0000000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SHIFT 29 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_MASK 0x10000000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE (1 << 28) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_MASK 0x0f000000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_MASK 0x00e00000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SHIFT 21 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_MASK 0x00100000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE (1 << 20) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_MASK 0x000f0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_MASK 0x0000e000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SHIFT 13 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_MASK 0x00000080 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA(d) (0x00000260 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_MASK 0xe0000000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SHIFT 29 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE (1 << 28) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_BLUE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_MASK 0x0f000000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_MASK 0x00e00000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SHIFT 21 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE (1 << 20) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_BLUE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_MASK 0x000f0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_MASK 0x0000e000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SHIFT 13 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_BLUE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_MASK 0x000000e0 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SHIFT 5 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE (1 << 4) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_BLUE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_INPUT_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB(d) (0x00000ac0 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_MASK 0xe0000000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SHIFT 29 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE (1 << 28) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_MASK 0x0f000000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_MASK 0x00e00000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SHIFT 21 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE (1 << 20) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_MASK 0x000f0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_MASK 0x0000e000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SHIFT 13 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_MASK 0x000000e0 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SHIFT 5 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE (1 << 4) -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_RGB 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_INPUT_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0(d) (0x00000a60 + (d) * 0x0004) /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1(d) (0x00000a80 + (d) * 0x0004) /* Parameters: a r g b */ -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_B_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(d) (0x00000aa0 + (d) * 0x0004) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */ -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK 0x00030000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_MASK 0x00008000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS (1 << 15) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_MASK 0x00004000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM (1 << 14) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_MASK 0x00002000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB(d) (0x00001e40 + (d) * 0x0004) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */ -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK 0x00030000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_MASK 0x00008000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS (1 << 15) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_MASK 0x00004000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM (1 << 14) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_MASK 0x00002000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_MASK 0x00001000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x0000 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x0003 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000c -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000d -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000f -# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(d) (0x0000105c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(d) (0x00001060 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(d) (0x00001064 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(d) (0x00001028 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(d) (0x0000102c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(d) (0x00001030 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(d) (0x00001034 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(d) (0x00001038 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(d) (0x0000103c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(d) (0x00001000 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(d) (0x00001004 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(d) (0x00001008 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(d) (0x0000100c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(d) (0x00001010 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(d) (0x00001014 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(d) (0x00001018 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(d) (0x0000101c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(d) (0x00001020 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_BACK_SIDE_PRODUCT_AMBIENT(d) (0x00000c00 + (d) * 0x0040) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_BACK_SIDE_PRODUCT_DIFFUSE(d) (0x00000c0c + (d) * 0x0040) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_BACK_SIDE_PRODUCT_SPECULAR(d) (0x00000c18 + (d) * 0x0040) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(d) (0x00001068 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(d) (0x0000106c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(d) (0x00001070 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(d) (0x00001040 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_EXPONENT(d) (0x00001044 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(d) (0x00001048 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(d) (0x0000104c + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(d) (0x00001050 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(d) (0x00001054 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(d) (0x00001058 + (d) * 0x0080) -# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_A 0x00001e28 -# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_B 0x00001e2c -# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_C 0x00001e30 -# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_D 0x00001e34 -# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_E 0x00001e38 -# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_F 0x00001e3c -# define NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE 0x0000147c -# define NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(d) (0x00001480 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X 0x00001500 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y 0x00001504 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z 0x00001508 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X 0x00001518 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y 0x0000151c -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z 0x00001520 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W 0x00001524 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY 0x00001528 /* Parameters: y x */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_X_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW 0x0000152c /* Parameters: w z */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_Z_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X 0x00001530 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y 0x00001534 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z 0x00001538 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00001540 /* Parameters: y x */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00001544 /* Parameters: z */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R 0x00001550 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G 0x00001554 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B 0x00001558 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A 0x0000155c -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R 0x00001560 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G 0x00001564 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B 0x00001568 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x0000156c /* Parameters: a b g r */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R 0x00001580 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G 0x00001584 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B 0x00001588 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x0000158c /* Parameters: a b g r */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S 0x00001590 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T 0x00001594 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I 0x00001598 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S 0x000015a0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T 0x000015a4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R 0x000015a8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q 0x000015ac -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x000015b0 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x000015b4 /* Parameters: q r */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S 0x000015b8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T 0x000015bc -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I 0x000015c0 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S 0x000015c8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T 0x000015cc -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R 0x000015d0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q 0x000015d4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x000015d8 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x000015dc /* Parameters: q r */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_S 0x000015e0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_T 0x000015e4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I 0x000015e8 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_S 0x000015f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_T 0x000015f4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_R 0x000015f8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_Q 0x000015fc -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST 0x00001600 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ 0x00001604 /* Parameters: q r */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_S 0x00001608 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_T 0x0000160c -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I 0x00001610 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_S 0x00001620 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_T 0x00001624 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_R 0x00001628 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_Q 0x0000162c -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST 0x00001630 /* Parameters: t s */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ 0x00001634 /* Parameters: q r */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00001698 -# define NV20_TCL_PRIMITIVE_3D_EDGE_FLAG 0x000016bc -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS 0x00001720 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH 0x00001724 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR 0x00001728 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL 0x0000172c /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2 0x00001730 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG 0x00001734 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6 0x00001738 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7 0x0000173c /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0 0x00001740 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1 0x00001744 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2 0x00001748 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3 0x0000174c /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4 0x00001750 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5 0x00001754 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6 0x00001758 /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7 0x0000175c /* Parameters: enabled offset */ -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED_MASK 0x80000000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED (1 << 31) -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED_TRUE 0x0001 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED_FALSE 0x0000 -# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_OFFSET_MASK 0x1fffffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR( d) (0x00001760 + (d) * 0x0004) -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS 0x00001760 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH 0x00001764 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR 0x00001768 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL 0x0000176c /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2 0x00001770 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG 0x00001774 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6 0x00001778 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7 0x0000177c /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0 0x00001780 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1 0x00001784 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2 0x00001788 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3 0x0000178c /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4 0x00001790 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5 0x00001794 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6 0x00001798 /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7 0x0000179c /* Parameters: stride fields type */ -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_STRIDE_MASK 0x0000ff00 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_STRIDE_SHIFT 8 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_FIELDS_MASK 0x000000f0 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_FIELDS_SHIFT 4 -# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_TYPE_MASK 0x0000000f -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_A 0x000017ac -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_R 0x000017b0 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_G 0x000017b4 -# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_B 0x000017b8 -# define NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE 0x000017bc -# define NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP 0x000017c0 -# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_TWO_SIDE_ENABLE 0x000017c4 -# define NV20_TCL_PRIMITIVE_3D_BEGIN_END 0x000017fc -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1 0x00001c30 /* Parameters: x2 x1 */ -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1_X2_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1_X2_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1_X1_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1 0x00001c50 /* Parameters: y2 y1 */ -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1_Y2_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1_Y2_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1_Y1_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH 0x00001d8c -# define NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB 0x00001d90 -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS 0x00001d94 /* Parameters: clear color a clear color b clear color g clear color r clear depth clear stencil */ -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_A_MASK 0x00000080 -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_A (1 << 7) -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_B_MASK 0x00000040 -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_B (1 << 6) -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_G_MASK 0x00000020 -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_G (1 << 5) -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_R_MASK 0x00000010 -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_R (1 << 4) -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_DEPTH_MASK 0x00000002 -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_DEPTH 1 // Nothing to shift -# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_STENCIL_MASK 0x00000001 -# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA 0x00001800 /* Parameters: index1 index0 */ -# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_MASK 0xffff0000 -# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_SHIFT 16 -# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX0_MASK 0x0000ffff -# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH 0x00001810 /* Parameters: count_vertices offset_vertices */ -# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_MASK 0xff000000 -# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_SHIFT 24 -# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_OFFSET_VERTICES_MASK 0x00ffffff -# define NV20_TCL_PRIMITIVE_3D_VERTEX_DATA 0x00001818 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_X 0x00001f00 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Y 0x00001f04 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Z 0x00001f08 -# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_W 0x00001f0c - -/****************************************** -Object NV30_TCL_PRIMITIVE_3D used on: NV30 -*/ -#define NV30_TCL_PRIMITIVE_3D 0x00000097 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT0 0x00000180 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT1 0x00000184 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT2 0x00000188 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT3 0x0000018c -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT4 0x00000194 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT5 0x00000198 -# define NV30_TCL_PRIMITIVE_3D_SET_VB_SRC0_OBJECT 0x0000019c -# define NV30_TCL_PRIMITIVE_3D_SET_VB_SRC1_OBJECT 0x000001a0 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT6 0x000001a4 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT7 0x000001a8 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT8 0x000001ac -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT8B 0x000001b0 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT9 0x000001b4 -# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT10 0x000001b8 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0 0x00000200 /* Parameters: width x_offset */ -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0_WIDTH_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0_WIDTH_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0_X_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1 0x00000204 /* Parameters: height y_offset */ -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1_HEIGHT_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1_HEIGHT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1_Y_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH 0x0000020c /* Parameters: zs_pitch color0_pitch */ -# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH_ZS_PITCH_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH_ZS_PITCH_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH_COLOR0_PITCH_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_COLOR0_OFFSET 0x00000210 -# define NV30_TCL_PRIMITIVE_3D_DEPTH_OFFSET 0x00000214 -# define NV30_TCL_PRIMITIVE_3D_COLOR1_OFFSET 0x00000218 -# define NV30_TCL_PRIMITIVE_3D_BUFFER1_PITCH 0x0000021c /* Parameters: color1 buffer pitch */ -# define NV30_TCL_PRIMITIVE_3D_BUFFER1_PITCH_COLOR1_BUFFER_PITCH_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS 0x00000220 /* Parameters: BUF0 BUF1 BUF2 BUF3 */ -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF0_MASK 0x00000001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1_MASK 0x00000002 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1 1 // Nothing to shift -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2_MASK 0x00000004 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2 (1 << 2) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3_MASK 0x00000008 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3 (1 << 3) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH 0x0000022c /* Parameters: pitch */ -# define NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH_PITCH_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET 0x00000230 -# define NV30_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(d) (0x00000240 + (d) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_BUFFER2_PITCH 0x00000280 -# define NV30_TCL_PRIMITIVE_3D_BUFFER3_PITCH 0x00000284 -# define NV30_TCL_PRIMITIVE_3D_BUFFER2_OFFSET 0x00000288 -# define NV30_TCL_PRIMITIVE_3D_BUFFER3_OFFSET 0x0000028c -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0 0x000002c0 /* Parameters: width x_offset */ -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0_WIDTH_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0_WIDTH_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0_X_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1 0x000002c4 /* Parameters: height y_offset */ -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1_HEIGHT_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1_HEIGHT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1_Y_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_DITHER_ENABLE 0x00000300 -# define NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x00000304 -# define NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x00000308 -# define NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x0000030c -# define NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE 0x00000310 -# define NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC 0x00000314 -# define NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_DST 0x00000318 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR 0x0000031c /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_BLEND_EQUATION 0x00000320 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK 0x00000324 /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE 0x00000328 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK 0x0000032c -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC 0x00000330 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_REF 0x00000334 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK 0x00000338 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL 0x0000033c -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL 0x00000340 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS 0x00000344 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE 0x00000348 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK 0x0000034c -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC 0x00000350 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF 0x00000354 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK 0x00000358 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL 0x0000035c -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL 0x00000360 -# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS 0x00000364 -# define NV30_TCL_PRIMITIVE_3D_SHADE_MODEL 0x00000368 -# define NV30_TCL_PRIMITIVE_3D_FOG_ENABLE 0x0000036c -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR 0x00000370 /* Parameters: a b g r */ -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE 0x00000374 -# define NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP 0x00000378 -# define NV30_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE 0x0000037c -# define NV30_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000394 -# define NV30_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000398 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_R 0x000003a0 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_G 0x000003a4 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_B 0x000003a8 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_A 0x000003b4 -# define NV30_TCL_PRIMITIVE_3D_LINE_WIDTH_SMOOTH 0x000003b8 -# define NV30_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x000003bc -# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(d) (0x00000400 + (d) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX( d) (0x00000480 + (d) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW_MATRIX( d) (0x00000580 + (d) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_PROJECTION_MATRIX( d) (0x00000680 + (d) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_TX_MATRIX(x,y) (0x000006c0 + (y) * 0x0010 + (x) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS 0x000008c0 /* Parameters: width x_offset */ -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_WIDTH_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_WIDTH_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_X_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS 0x000008c4 /* Parameters: height y_offset */ -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_HEIGHT_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_HEIGHT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_Y_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_FOG_COORD_DIST 0x000008c8 -# define NV30_TCL_PRIMITIVE_3D_FOG_MODE 0x000008cc -# define NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT 0x000008d0 -# define NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR 0x000008d4 -# define NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC 0x000008d8 -# define NV30_TCL_PRIMITIVE_3D_FP_ACTIVE_PROGRAM 0x000008e4 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0 0x000008ec /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1 0x000008f0 /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0 0x000008f4 /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_MASK 0xe0000000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SHIFT 29 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE (1 << 28) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_MASK 0x0f000000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_MASK 0x00e00000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SHIFT 21 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE (1 << 20) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_MASK 0x000f0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_MASK 0x0000e000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SHIFT 13 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_MASK 0x00000f00 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_MASK 0x000000e0 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SHIFT 5 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE (1 << 4) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_INPUT_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1 0x000008f8 /* Parameters: vare_mapping vare_component_usage vare_input varf_mapping varf_component_usage varf_input varg_mapping varg_component_usage varg_input color_sum_clamp */ -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_MASK 0xe0000000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SHIFT 29 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_MASK 0x10000000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE (1 << 28) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_MASK 0x0f000000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_MASK 0x00e00000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SHIFT 21 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_MASK 0x00100000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE (1 << 20) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_MASK 0x000f0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_MASK 0x0000e000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SHIFT 13 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_MASK 0x00000f00 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_MASK 0x00000080 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7) -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_ENABLE 0x000008fc /* Parameters: number of rc enabled */ -# define NV30_TCL_PRIMITIVE_3D_RC_ENABLE_NUMBER_OF_RC_ENABLED_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA(d) (0x00000900 + (d) * 0x0020) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_MASK 0xe0000000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SHIFT 29 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE (1 << 28) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_BLUE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_MASK 0x0f000000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_MASK 0x00e00000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SHIFT 21 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE (1 << 20) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_BLUE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_MASK 0x000f0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_MASK 0x0000e000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SHIFT 13 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_BLUE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_MASK 0x00000f00 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_MASK 0x000000e0 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SHIFT 5 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE (1 << 4) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_BLUE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_INPUT_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB(d) (0x00000904 + (d) * 0x0020) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */ -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_MASK 0xe0000000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SHIFT 29 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_MASK 0x10000000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE (1 << 28) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_MASK 0x0f000000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_MASK 0x00e00000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SHIFT 21 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_MASK 0x00100000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE (1 << 20) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_MASK 0x000f0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_MASK 0x0000e000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SHIFT 13 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_MASK 0x00000f00 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_MASK 0x000000e0 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SHIFT 5 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_MASK 0x00000010 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE (1 << 4) -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_RGB 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_ALPHA 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_INPUT_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0(d) (0x00000908 + (d) * 0x0020) /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1(d) (0x0000090c + (d) * 0x0020) /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(d) (0x00000910 + (d) * 0x0020) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */ -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK 0x00030000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_MASK 0x00008000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS (1 << 15) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_MASK 0x00004000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM (1 << 14) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_MASK 0x00002000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB(d) (0x00000914 + (d) * 0x0020) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */ -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK 0x00030000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_MASK 0x00008000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS (1 << 15) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_MASK 0x00004000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM (1 << 14) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_MASK 0x00002000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT 4 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x0003 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x0008 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x0009 -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000c -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000d -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000f -# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0 0x00000a00 /* Parameters: width x_offset */ -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_X_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1 0x00000a04 /* Parameters: height y_offset */ -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_Y_OFFSET_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10 -# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14 -# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_OX 0x00000a20 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_OY 0x00000a24 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_NPF_DIV2 0x00000a28 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_UNK0_0x0 0x00000a2c -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_PX_DIV2 0x00000a30 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_PY_DIV2 0x00000a34 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_FMN_DIV2 0x00000a38 -# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_UNK1_0x0 0x00000a3c -# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000a60 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000a64 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000a68 -# define NV30_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x00000a6c -# define NV30_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x00000a70 -# define NV30_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x00000a74 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x00000a78 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x00000a7c -# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00000a90 /* Parameters: y x */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00000a94 /* Parameters: z */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0 0x00000b80 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST1 0x00000b84 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST2 0x00000b88 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST3 0x00000b8c -# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_A(d) (0x00000e00 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_B(d) (0x00000e04 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_C(d) (0x00000e08 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_D(d) (0x00000e0c + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(d) (0x00001000 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(d) (0x00001004 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(d) (0x00001008 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(d) (0x0000100c + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(d) (0x00001010 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(d) (0x00001014 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(d) (0x00001018 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(d) (0x0000101c + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(d) (0x00001020 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(d) (0x00001028 + (d) * 0x0080) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(d) (0x0000102c + (d) * 0x0080) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(d) (0x00001030 + (d) * 0x0080) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(d) (0x00001034 + (d) * 0x0080) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(d) (0x00001038 + (d) * 0x0080) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(d) (0x0000103c + (d) * 0x0080) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(d) (0x00001200 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_EXPONENT(d) (0x00001204 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(d) (0x00001208 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(d) (0x0000120c + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(d) (0x00001210 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(d) (0x00001214 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(d) (0x00001218 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(d) (0x0000121c + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(d) (0x00001220 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(d) (0x00001224 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(d) (0x00001228 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(d) (0x0000122c + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(d) (0x00001230 + (d) * 0x0040) -# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_A 0x00001400 -# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_B 0x00001404 -# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_C 0x00001408 -# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_D 0x0000140c -# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_E 0x00001410 -# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_F 0x00001414 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS 0x00001420 /* Parameters: light 7 light 6 light 5 light 4 light 3 light 2 light 1 light 0 */ -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_MASK 0x00008000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7 (1 << 15) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_MASK 0x00002000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6 (1 << 13) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_MASK 0x00000800 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5 (1 << 11) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_MASK 0x00000200 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4 (1 << 9) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_MASK 0x00000080 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3 (1 << 7) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_MASK 0x00000020 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2 (1 << 5) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_MASK 0x00000008 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1 (1 << 3) -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_MASK 0x00000001 -# define NV30_TCL_PRIMITIVE_3D_SET_CLIPPING_PLANES 0x00001478 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE 0x0000147c -# define NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN( d) (0x00001480 + (d) * 0x0004) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_X( d) (0x00001500 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_Y( d) (0x00001504 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_Z( d) (0x00001508 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_W( d) (0x0000150c + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VB_POINTER( d) (0x00001680 + (d) * 0x0004) /* Parameters: source offset */ -# define NV30_TCL_PRIMITIVE_3D_VB_POINTER_SOURCE_MASK 0x80000000 -# define NV30_TCL_PRIMITIVE_3D_VB_POINTER_SOURCE (1 << 31) -# define NV30_TCL_PRIMITIVE_3D_VB_POINTER_OFFSET_MASK 0x1fffffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0 0x00001718 -# define NV30_TCL_PRIMITIVE_3D_VTXFMT( d) (0x00001740 + (d) * 0x0004) /* Parameters: stride ncomp type */ -# define NV30_TCL_PRIMITIVE_3D_VTXFMT_STRIDE_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_VTXFMT_STRIDE_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_VTXFMT_NCOMP_MASK 0x000000f0 -# define NV30_TCL_PRIMITIVE_3D_VTXFMT_NCOMP_SHIFT 4 -# define NV30_TCL_PRIMITIVE_3D_VTXFMT_TYPE_MASK 0x0000000f -# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0 -# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4 -# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_R 0x000017b0 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_G 0x000017b4 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_B 0x000017b8 -# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_A 0x000017c0 -# define NV30_TCL_PRIMITIVE_3D_OCC_QUERY_OR_COLOR_BUFF_ENABLE 0x000017c8 -# define NV30_TCL_PRIMITIVE_3D_STORE_RESULT 0x00001800 -# define NV30_TCL_PRIMITIVE_3D_BEGIN_END 0x00001808 -# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16 0x0000180c /* Parameters: 1 0 */ -# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16_1_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16_1_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16_0_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U32 0x00001810 -# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH 0x00001814 /* Parameters: count_vertices offset_vertices */ -# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_OFFSET_VERTICES_MASK 0x00ffffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_DATA 0x00001818 -# define NV30_TCL_PRIMITIVE_3D_SET_DISPLAY_LIST_MEM_OFFSET 0x0000181c -# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST 0x00001824 /* Parameters: length start offset */ -# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST_LENGTH_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST_LENGTH_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST_START_OFFSET_MASK 0x00ffffff -# define NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x00001828 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x0000182c -# define NV30_TCL_PRIMITIVE_3D_CULL_FACE 0x00001830 -# define NV30_TCL_PRIMITIVE_3D_FRONT_FACE 0x00001834 -# define NV30_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00001838 -# define NV30_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x0000183c -# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT( d) (0x00001840 + (d) * 0x0004) /* Parameters: depth NPOT pitch */ -# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT_DEPTH_MASK 0xfff00000 -# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT_DEPTH_SHIFT 20 -# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT_NPOT_PITCH_MASK 0x000fffff -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2F_X( d) (0x00001880 + (d) * 0x0008) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2F_Y( d) (0x00001884 + (d) * 0x0008) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I( d) (0x00001900 + (d) * 0x0004) /* Parameters: x y */ -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I_X_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I_Y_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I_Y_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x0000194c /* Parameters: a b g r */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x00001950 /* Parameters: a b g r */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x000019c0 /* Parameters: t s */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x000019c4 /* Parameters: q r */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x000019c8 /* Parameters: t s */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x000019cc /* Parameters: q r */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST 0x000019d0 /* Parameters: t s */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ 0x000019d4 /* Parameters: q r */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST 0x000019d8 /* Parameters: t s */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ 0x000019dc /* Parameters: q r */ -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_TX_ADDRESS_UNIT( d) (0x00001a00 + (d) * 0x0020) -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT( d) (0x00001a04 + (d) * 0x0020) /* Parameters: mipmap type format ncomp cubic */ -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_MIPMAP_MASK 0x000f0000 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_MIPMAP_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_MASK 0x00006000 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_SHIFT 13 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_POT 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_NPOT 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_RECT 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_MASK 0x00001f00 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L8 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_A1R5G5B5 0x0002 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_A4R4G4B4 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_R5G6B5 0x0004 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_A8R8G8B8 0x0005 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_DXT1 0x0006 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_DXT3 0x0007 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_DXT5 0x0008 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L16 0x0014 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L16A16 0x0015 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L8A8 0x0018 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_SL8A8 0x0019 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_RGBA_F16 0x001a -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_RGBA_F32 0x001b -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L_F32 0x001c -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_LA_F16 0x001f -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_NCOMP_MASK 0x000000f0 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_NCOMP_SHIFT 4 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC_MASK 0x00000004 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC (1 << 2) -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT( d) (0x00001a08 + (d) * 0x0020) /* Parameters: wrap_s wrap_t wrap_r */ -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_S_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_REPEAT 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_MIRRORED_REPEAT 0x0002 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_CLAMP_TO_EDGE 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_CLAMP_TO_BORDER 0x0004 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_CLAMP 0x0005 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_REPEAT 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_MIRRORED_REPEAT 0x0002 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_CLAMP_TO_EDGE 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_CLAMP_TO_BORDER 0x0004 -# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_CLAMP 0x0005 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT( d) (0x00001a0c + (d) * 0x0020) /* Parameters: nv40_enable nv30_enable anisotropy */ -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE_MASK 0x80000000 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE (1 << 31) -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE_MASK 0x40000000 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE (1 << 30) -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_MASK 0x00000070 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_SHIFT 4 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_1 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_2 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_4 0x0002 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_NV40_6_NV30_8 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_8 0x0004 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_10 0x0005 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_12 0x0006 -# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_16 0x0007 -# define NV30_TCL_PRIMITIVE_3D_TX_SWIZZLE_UNIT( d) (0x00001a10 + (d) * 0x0020) -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT( d) (0x00001a14 + (d) * 0x0020) /* Parameters: filter_min filter_mag */ -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_MASK 0x000f0000 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_NEAREST 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_LINEAR 0x0002 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_MASK 0x0f000000 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_NEAREST 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_LINEAR 0x0002 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_NEAREST_MIPMAP_NEAREST 0x0003 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_LINEAR_MIPMAP_NEAREST 0x0004 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_NEAREST_MIPMAP_LINEAR 0x0005 -# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_LINEAR_MIPMAP_LINEAR 0x0006 -# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT( d) (0x00001a18 + (d) * 0x0020) /* Parameters: width height */ -# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT_WIDTH_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT_WIDTH_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT_HEIGHT_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT( d) (0x00001a1c + (d) * 0x0020) /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_X( d) (0x00001c00 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_Y( d) (0x00001c04 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_Z( d) (0x00001c08 + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_W( d) (0x00001c0c + (d) * 0x0010) -# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL 0x00001d60 /* Parameters: uses_kil */ -# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL_MASK 0x00000080 -# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL (1 << 7) -# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_UNK1D6C_OFFSET 0x00001d6c -# define NV30_TCL_PRIMITIVE_3D_UNK1D70_VALUE 0x00001d70 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH 0x00001d8c -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB 0x00001d90 /* Parameters: a r g b */ -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_A_MASK 0xff000000 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_A_SHIFT 24 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_R_MASK 0x00ff0000 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_R_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_G_MASK 0x0000ff00 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_G_SHIFT 8 -# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_B_MASK 0x000000ff -# define NV30_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS 0x00001d94 -# define NV30_TCL_PRIMITIVE_3D_DO_VERTICES 0x00001dac -# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE 0x00001db4 -# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN 0x00001db8 /* Parameters: factor pattern */ -# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff -# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000 -# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16 -# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_A 0x00001e20 -# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_B 0x00001e24 -# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_C 0x00001e28 -# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_D 0x00001e2c -# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_E 0x00001e30 -# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_F 0x00001e34 -# define NV30_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00001e54 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_FROM_ID 0x00001e9c -# define NV30_TCL_PRIMITIVE_3D_VP_PROGRAM_START_ID 0x00001ea0 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_A 0x00001ec0 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_B 0x00001ec4 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_C 0x00001ec8 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_D 0x00001ecc -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_E 0x00001ed0 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_F 0x00001ed4 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_G 0x00001ed8 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_H 0x00001edc -# define NV30_TCL_PRIMITIVE_3D_POINT_SIZE 0x00001ee0 -# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE 0x00001ee4 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE 0x00001ee8 /* Parameters: coord_replace r_mode enable */ -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_MASK 0x00000800 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE (1 << 11) -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_MASK 0x00000006 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_SHIFT 1 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_ZERO 0x0000 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_R 0x0001 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_S 0x0002 -# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_ENABLE_MASK 0x00000001 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID 0x00001efc -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_X 0x00001f00 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_Y 0x00001f04 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_Z 0x00001f08 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_W 0x00001f0c -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_X 0x00001f10 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_Y 0x00001f14 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_Z 0x00001f18 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_W 0x00001f1c -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_X 0x00001f20 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_Y 0x00001f24 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_Z 0x00001f28 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_W 0x00001f2c -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_X 0x00001f30 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_Y 0x00001f34 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_Z 0x00001f38 -# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_W 0x00001f3c -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG 0x00001ff0 /* Parameters: POS WEIGHT NORMAL COL0 COL1 FOGC TEX0 TEX1 TEX2 TEX3 TEX4 TEX5 TEX6 TEX7 */ -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_POS_MASK 0x00000001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT_MASK 0x00000002 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT 1 // Nothing to shift -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL_MASK 0x00000004 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL (1 << 2) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0_MASK 0x00000008 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0 (1 << 3) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1_MASK 0x00000010 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1 (1 << 4) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC_MASK 0x00000020 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC (1 << 5) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0_MASK 0x00000100 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0 (1 << 8) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1_MASK 0x00000200 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1 (1 << 9) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2_MASK 0x00000400 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2 (1 << 10) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3_MASK 0x00000800 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3 (1 << 11) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4_MASK 0x00001000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4 (1 << 12) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5_MASK 0x00002000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5 (1 << 13) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6_MASK 0x00004000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6 (1 << 14) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7_MASK 0x00008000 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7 (1 << 15) -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG 0x00001ff4 /* Parameters: COL0 COL1 BFC0 BFC1 FOGC PSZ CLP0 CLP1 CLP2 CLP3 CLP4 CLP5 TEX0 TEX1 TEX2 TEX3 TEX4 TEX5 TEX6 TEX7 */ -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL0_MASK 0x00000001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1_MASK 0x00000002 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1 1 // Nothing to shift -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0_MASK 0x00000004 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0 (1 << 2) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1_MASK 0x00000008 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1 (1 << 3) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC_MASK 0x00000010 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC (1 << 4) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ_MASK 0x00000020 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ (1 << 5) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0_MASK 0x00000040 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0 (1 << 6) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1_MASK 0x00000080 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1 (1 << 7) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2_MASK 0x00000100 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2 (1 << 8) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3_MASK 0x00000200 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3 (1 << 9) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4_MASK 0x00000400 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4 (1 << 10) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5_MASK 0x00000800 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5 (1 << 11) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0_MASK 0x00004000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0 (1 << 14) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1_MASK 0x00008000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1 (1 << 15) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2_MASK 0x00010000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2 (1 << 16) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3_MASK 0x00020000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3 (1 << 17) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4_MASK 0x00040000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4 (1 << 18) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5_MASK 0x00080000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5 (1 << 19) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6_MASK 0x00100000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6 (1 << 20) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6_FALSE 0x0000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7_MASK 0x00200000 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7 (1 << 21) -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7_TRUE 0x0001 -# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7_FALSE 0x0000 - -/****************************************** -Object NV40_TCL_PRIMITIVE_3D used on: NV40 G70 -*/ -#define NV40_TCL_PRIMITIVE_3D 0x00000097 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123 0x00000370 /* Parameters: buffer3 b buffer3 g buffer3 r buffer3 a buffer2 b buffer2 g buffer2 r buffer2 a buffer1 b buffer1 g buffer1 r buffer1 a */ -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B_MASK 0x00008000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B (1 << 15) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G_MASK 0x00004000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G (1 << 14) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R_MASK 0x00002000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R (1 << 13) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A_MASK 0x00001000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A (1 << 12) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B_MASK 0x00000800 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B (1 << 11) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G_MASK 0x00000400 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G (1 << 10) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R_MASK 0x00000200 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R (1 << 9) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A_MASK 0x00000100 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A (1 << 8) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B_MASK 0x00000080 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B (1 << 7) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G_MASK 0x00000040 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G (1 << 6) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R_MASK 0x00000020 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R (1 << 5) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R_FALSE 0x0000 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A_MASK 0x00000010 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A (1 << 4) -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A_TRUE 0x0001 -# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A_FALSE 0x0000 - -/****************************************** -Object NV30_CLEAR_BUFFER used on: NV30 NV40 G70 -*/ -#define NV30_CLEAR_BUFFER 0x00000066 -# define NV30_CLEAR_BUFFER_SET_DMA_NOTIFY 0x00000180 -# define NV30_CLEAR_BUFFER_SET_IMAGE_PATTERN 0x00000188 -# define NV30_CLEAR_BUFFER_SET_RASTER_OP 0x0000018c -# define NV30_CLEAR_BUFFER_SET_CONTEXT_SURFACE_2D 0x00000198 -# define NV30_CLEAR_BUFFER_UNK002fc 0x000002fc - -/****************************************** -Object NV50_TCL_PRIMITIVE_3D used on: -*/ -#define NV50_TCL_PRIMITIVE_3D 0x00000097 -# define NV50_TCL_PRIMITIVE_3D_SET_OBJECT_0( d) (0x00000180 + (d) * 0x0004) -# define NV50_TCL_PRIMITIVE_3D_SET_OBJECT_1( d) (0x000001c0 + (d) * 0x0004) -# define NV50_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00000314 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_2F_X 0x00000380 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_2F_Y 0x00000384 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S 0x000003c0 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T 0x000003c4 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S 0x000003c8 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T 0x000003cc -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_S 0x000003d0 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_T 0x000003d4 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_S 0x000003d8 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_T 0x000003dc -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X 0x00000400 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y 0x00000404 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z 0x00000408 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X 0x00000420 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y 0x00000424 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z 0x00000428 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R 0x00000430 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G 0x00000434 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B 0x00000438 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R 0x00000440 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G 0x00000444 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B 0x00000448 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X 0x00000500 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y 0x00000504 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z 0x00000508 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W 0x0000050c -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R 0x00000530 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G 0x00000534 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B 0x00000538 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A 0x0000053c -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S 0x00000580 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T 0x00000584 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R 0x00000588 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q 0x0000058c -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S 0x00000590 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T 0x00000594 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R 0x00000598 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q 0x0000059c -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_S 0x000005a0 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_T 0x000005a4 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_R 0x000005a8 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_Q 0x000005ac -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_S 0x000005b0 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_T 0x000005b4 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_R 0x000005b8 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_Q 0x000005bc -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I 0x000006a0 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I 0x000006a4 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I 0x000006a8 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I 0x000006ac /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY 0x00000700 /* Parameters: y x */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_X_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW 0x00000704 /* Parameters: w z */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_Z_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x00000740 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x00000744 /* Parameters: q r */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x00000748 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x0000074c /* Parameters: q r */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST 0x00000750 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ 0x00000754 /* Parameters: q r */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST 0x00000758 /* Parameters: t s */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ 0x0000075c /* Parameters: q r */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00000790 /* Parameters: y x */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00000794 /* Parameters: z */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x0000088c /* Parameters: a b g r */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x00000890 /* Parameters: a b g r */ -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0_X 0x00000a00 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0_Y 0x00000a04 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0_Z 0x00000a08 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1_X 0x00000a0c -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1_Y 0x00000a10 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1_Z 0x00000a14 -# define NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000c08 -# define NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000c0c -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(d) (0x00000d00 + (d) * 0x0008) /* Parameters: x2 x1 */ -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X1_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(d) (0x00000d04 + (d) * 0x0008) /* Parameters: y2 y1 */ -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y1_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VERTEX_BUFFER_FIRST 0x00000d74 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_BUFFER_COUNT 0x00000d78 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_R 0x00000d80 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_G 0x00000d84 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_B 0x00000d88 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_A 0x00000d8c -# define NV50_TCL_PRIMITIVE_3D_CLEAR_DEPTH 0x00000d90 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_STENCIL 0x00000da0 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x00000dac -# define NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x00000db0 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00000db4 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8 -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS 0x00000e04 /* Parameters: w x */ -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_W_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_W_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_X_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS 0x00000e08 /* Parameters: h y */ -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_H_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_H_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_Y_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID 0x00000f00 -# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_X 0x00000f04 -# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Y 0x00000f08 -# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Z 0x00000f0c -# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_W 0x00000f10 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF 0x00000f54 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK 0x00000f58 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK 0x00000f5c -# define NV50_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x000012cc -# define NV50_TCL_PRIMITIVE_3D_SHADE_MODEL 0x000012d4 -# define NV50_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x000012e8 -# define NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x000012ec -# define NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x0000130c -# define NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x00001310 -# define NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x00001314 -# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_R 0x0000131c -# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_G 0x00001320 -# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_B 0x00001324 -# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_A 0x00001328 -# define NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB 0x00001340 -# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB 0x00001344 -# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB 0x00001348 -# define NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA 0x0000134c -# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA 0x00001350 -# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA 0x00001358 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE 0x00001380 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL 0x00001384 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL 0x00001388 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS 0x0000138c -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC 0x00001390 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_REF 0x00001394 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK 0x00001398 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK 0x0000139c -# define NV50_TCL_PRIMITIVE_3D_LINE_WIDTH 0x000013b0 -# define NV50_TCL_PRIMITIVE_3D_POINT_SIZE 0x00001518 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x0000156c -# define NV50_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x00001570 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE 0x00001594 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL 0x00001598 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL 0x0000159c -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS 0x000015a0 -# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC 0x000015a4 -# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x000015bc -# define NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN 0x000015dc -# define NV50_TCL_PRIMITIVE_3D_VERTEX_END 0x000015e0 -# define NV50_TCL_PRIMITIVE_3D_VERTEX_DATA 0x00001640 -# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE 0x0000166c -# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN 0x00001680 /* Parameters: pattern factor */ -# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_MASK 0x00ffff00 -# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 8 -# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x000000ff -# define NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE 0x0000168c -# define NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN( d) (0x00001700 + (d) * 0x0004) -# define NV50_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x00001918 -# define NV50_TCL_PRIMITIVE_3D_FRONT_FACE 0x0000191c -# define NV50_TCL_PRIMITIVE_3D_CULL_FACE 0x00001920 -# define NV50_TCL_PRIMITIVE_3D_LOGIC_OP_ENABLE 0x000019c4 -# define NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP 0x000019c8 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS 0x000019d0 /* Parameters: color stencil depth */ -# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_COLOR_MASK 0x0000003c -# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_COLOR_SHIFT 2 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_STENCIL_MASK 0x00000002 -# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_STENCIL 1 // Nothing to shift -# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_DEPTH_MASK 0x00000001 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK( d) (0x00001a00 + (d) * 0x0004) /* Parameters: a b g r */ -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0x0000f000 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 12 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x00000f00 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_SHIFT 8 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_TRUE 0x0001 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_FALSE 0x0000 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x000000f0 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 4 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000 -# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x0000000f -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0 0x00000c00 /* Parameters: width x_offset */ -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_X_OFFSET_MASK 0x0000ffff -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1 0x00000c04 /* Parameters: height y_offset */ -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_MASK 0xffff0000 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_SHIFT 16 -# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_Y_OFFSET_MASK 0x0000ffff - -/****************************************** -Object NV_DMA_FROM_MEMORY used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV_DMA_FROM_MEMORY 0x00000002 - -/****************************************** -Object NV_DMA_TO_MEMORY used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV_DMA_TO_MEMORY 0x00000003 - -/****************************************** -Object NV_DMA_IN_MEMORY used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70 -*/ -#define NV_DMA_IN_MEMORY 0x0000003d - -/****************************************** -Object NvType0046 used on: NV04 -*/ -#define NvType0046 0x00000046 -# define NvType0046_DMA_NOTIFY 0x00000180 -# define NvType0046_DMA_MEM_1 0x00000184 -# define NvType0046_DMA_MEM_2 0x00000188 -# define NvType0046_DMA_3 0x0000018c -# define NvType0046_DMA_4 0x00000190 -# define NvType0046_OBJ_5 0x00000194 -# define NvType0046_OBJ_6 0x00000198 -# define NvType0046_PITCH1 0x00000304 -# define NvType0046_PITCH2 0x0000030c -# define NvType0046_SIZE 0x00000340 /* Parameters: width height */ -# define NvType0046_SIZE_WIDTH_MASK 0x0000ffff -# define NvType0046_SIZE_HEIGHT_MASK 0xffff0000 -# define NvType0046_SIZE_HEIGHT_SHIFT 16 -# define NvType0046_WIDTH 0x00000344 /* Parameters: visible_width blank_width */ -# define NvType0046_WIDTH_VISIBLE_WIDTH_MASK 0x0000ffff -# define NvType0046_WIDTH_BLANK_WIDTH_MASK 0xffff0000 -# define NvType0046_WIDTH_BLANK_WIDTH_SHIFT 16 -# define NvType0046_HSYNC 0x00000348 /* Parameters: hsync_start hsync_len */ -# define NvType0046_HSYNC_HSYNC_START_MASK 0x0000ffff -# define NvType0046_HSYNC_HSYNC_LEN_MASK 0xffff0000 -# define NvType0046_HSYNC_HSYNC_LEN_SHIFT 16 -# define NvType0046_HEIGHT 0x0000034c /* Parameters: visible_height blank_height */ -# define NvType0046_HEIGHT_VISIBLE_HEIGHT_MASK 0x0000ffff -# define NvType0046_HEIGHT_BLANK_HEIGHT_MASK 0xffff0000 -# define NvType0046_HEIGHT_BLANK_HEIGHT_SHIFT 16 -# define NvType0046_VSYNC 0x00000350 /* Parameters: vsync_start vsync_len */ -# define NvType0046_VSYNC_VSYNC_START_MASK 0x0000ffff -# define NvType0046_VSYNC_VSYNC_LEN_MASK 0xffff0000 -# define NvType0046_VSYNC_VSYNC_LEN_SHIFT 16 -# define NvType0046_FULL_SIZE 0x00000354 /* Parameters: full_width full_height */ -# define NvType0046_FULL_SIZE_FULL_WIDTH_MASK 0x0000ffff -# define NvType0046_FULL_SIZE_FULL_HEIGHT_MASK 0xffff0000 -# define NvType0046_FULL_SIZE_FULL_HEIGHT_SHIFT 16 -# define NvType0046_PIXEL_CLK 0x00000358 -# define NvType0046_FLAGS 0x0000035c /* Parameters: doublescan neg_hsync neg_vsync depth */ -# define NvType0046_FLAGS_DOUBLESCAN_MASK 0x00000002 -# define NvType0046_FLAGS_DOUBLESCAN 1 // Nothing to shift -# define NvType0046_FLAGS_DOUBLESCAN_TRUE 0x0001 -# define NvType0046_FLAGS_DOUBLESCAN_FALSE 0x0000 -# define NvType0046_FLAGS_NEG_HSYNC_MASK 0x00000008 -# define NvType0046_FLAGS_NEG_HSYNC (1 << 3) -# define NvType0046_FLAGS_NEG_HSYNC_TRUE 0x0001 -# define NvType0046_FLAGS_NEG_HSYNC_FALSE 0x0000 -# define NvType0046_FLAGS_NEG_VSYNC_MASK 0x00000010 -# define NvType0046_FLAGS_NEG_VSYNC (1 << 4) -# define NvType0046_FLAGS_NEG_VSYNC_TRUE 0x0001 -# define NvType0046_FLAGS_NEG_VSYNC_FALSE 0x0000 -# define NvType0046_FLAGS_DEPTH_MASK 0x00030000 -# define NvType0046_FLAGS_DEPTH_SHIFT 16 -# define NvType0046_FLAGS_DEPTH_8 bpp 0x0000 -# define NvType0046_FLAGS_DEPTH_16 bpp 0x0001 -# define NvType0046_FLAGS_DEPTH_15 bpp 0x0002 -# define NvType0046_FLAGS_DEPTH_24 bpp 0x0003 - -/****************************************** -Object NvType0047 used on: NV04 -*/ -#define NvType0047 0x00000047 -# define NvType0047_DMA_NOTIFY 0x00000180 -# define NvType0047_UNK19C 0x0000019c -# define NvType0047_UNK1A0 0x000001a0 - -/****************************************** -Object NvType0049 used on: NV04 -*/ -#define NvType0049 0x00000049 -# define NvType0049_DMA_NOTIFY 0x00000180 -# define NvType0049_DMA_MEM_1 0x00000184 -# define NvType0049_DMA_MEM_2 0x00000188 - -/****************************************** -Object NvType004D used on: NV04 -*/ -#define NvType004D 0x0000004d -# define NvType004D_DMA_NOTIFY 0x00000180 -# define NvType004D_DMA_MEM_1 0x00000184 -# define NvType004D_DMA_MEM_2 0x00000188 -# define NvType004D_DMA_MEM_3 0x0000018c -# define NvType004D_DMA_MEM_4 0x00000190 - -#endif /* _NOUVEAU_REG_H */ diff --git a/src/mesa/drivers/dri/nouveau/nouveau_screen.c b/src/mesa/drivers/dri/nouveau/nouveau_screen.c deleted file mode 100644 index e4463fb31a1..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_screen.c +++ /dev/null @@ -1,325 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "glheader.h" -#include "imports.h" -#include "mtypes.h" -#include "framebuffer.h" -#include "renderbuffer.h" - -#include "nouveau_context.h" -#include "nouveau_screen.h" -#include "nouveau_object.h" -#include "nouveau_span.h" -#include "nouveau_msg.h" - -#include "utils.h" -#include "context.h" -#include "vblank.h" -#include "drirenderbuffer.h" - -#include "GL/internal/dri_interface.h" - -#include "xmlpool.h" - -PUBLIC const char __driConfigOptions[] = -DRI_CONF_BEGIN - DRI_CONF_SECTION_DEBUG - DRI_CONF_NO_RAST(false) - DRI_CONF_SECTION_END -DRI_CONF_END; -static const GLuint __driNConfigOptions = 1; - -extern const struct dri_extension common_extensions[]; -extern const struct dri_extension nv10_extensions[]; -extern const struct dri_extension nv20_extensions[]; -extern const struct dri_extension nv30_extensions[]; -extern const struct dri_extension nv40_extensions[]; -extern const struct dri_extension nv50_extensions[]; - -static nouveauScreenPtr nouveauCreateScreen(__DRIscreenPrivate *sPriv) -{ - nouveauScreenPtr screen; - NOUVEAUDRIPtr dri_priv=(NOUVEAUDRIPtr)sPriv->pDevPriv; - - /* allocate screen */ - screen = (nouveauScreenPtr) CALLOC( sizeof(*screen) ); - if ( !screen ) { - __driUtilMessage("%s: Could not allocate memory for screen structure",__FUNCTION__); - return NULL; - } - - screen->card=nouveau_card_lookup(dri_priv->device_id); - if (!screen->card) { - __driUtilMessage("%s: Unknown card type 0x%04x:0x%04x\n", - __func__, dri_priv->device_id >> 16, dri_priv->device_id & 0xFFFF); - FREE(screen); - return NULL; - } - - /* parse information in __driConfigOptions */ - driParseOptionInfo (&screen->optionCache,__driConfigOptions, __driNConfigOptions); - - screen->fbFormat = dri_priv->bpp / 8; - screen->frontOffset = dri_priv->front_offset; - screen->frontPitch = dri_priv->front_pitch; - screen->backOffset = dri_priv->back_offset; - screen->backPitch = dri_priv->back_pitch; - screen->depthOffset = dri_priv->depth_offset; - screen->depthPitch = dri_priv->depth_pitch; - - screen->driScreen = sPriv; - return screen; -} - -static void -nouveauDestroyScreen(__DRIscreenPrivate *sPriv) -{ - nouveauScreenPtr screen = (nouveauScreenPtr)sPriv->private; - - if (!screen) return; - - /* free all option information */ - driDestroyOptionInfo (&screen->optionCache); - - FREE(screen); - sPriv->private = NULL; -} - -static GLboolean nouveauInitDriver(__DRIscreenPrivate *sPriv) -{ - sPriv->private = (void *) nouveauCreateScreen( sPriv ); - if ( !sPriv->private ) { - nouveauDestroyScreen( sPriv ); - return GL_FALSE; - } - - return GL_TRUE; -} - -/** - * Create the Mesa framebuffer and renderbuffers for a given window/drawable. - * - * \todo This function (and its interface) will need to be updated to support - * pbuffers. - */ -static GLboolean -nouveauCreateBuffer(__DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, - const __GLcontextModes *mesaVis, - GLboolean isPixmap) -{ - nouveauScreenPtr screen = (nouveauScreenPtr) driScrnPriv->private; - nouveau_renderbuffer_t *nrb; - struct gl_framebuffer *fb; - const GLboolean swAccum = mesaVis->accumRedBits > 0; - const GLboolean swStencil = (mesaVis->stencilBits > 0 && - mesaVis->depthBits != 24); - GLenum color_format = screen->fbFormat == 4 ? GL_RGBA8 : GL_RGB5; - - if (isPixmap) - return GL_FALSE; /* not implemented */ - - fb = _mesa_create_framebuffer(mesaVis); - if (!fb) - return GL_FALSE; - - /* Front buffer */ - nrb = nouveau_renderbuffer_new(color_format); - _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &nrb->mesa); - - if (mesaVis->doubleBufferMode) { - nrb = nouveau_renderbuffer_new(color_format); - _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &nrb->mesa); - } - - if (mesaVis->depthBits == 24 && mesaVis->stencilBits == 8) { - nrb = nouveau_renderbuffer_new(GL_DEPTH24_STENCIL8_EXT); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &nrb->mesa); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &nrb->mesa); - } else - if (mesaVis->depthBits == 24) { - nrb = nouveau_renderbuffer_new(GL_DEPTH_COMPONENT24); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &nrb->mesa); - } else - if (mesaVis->depthBits == 16) { - nrb = nouveau_renderbuffer_new(GL_DEPTH_COMPONENT16); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &nrb->mesa); - } - - _mesa_add_soft_renderbuffers(fb, - GL_FALSE, /* color */ - GL_FALSE, /* depth */ - swStencil, - swAccum, - GL_FALSE, /* alpha */ - GL_FALSE /* aux */); - - driDrawPriv->driverPrivate = (void *) fb; - return (driDrawPriv->driverPrivate != NULL); -} - - -static void -nouveauDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) -{ - _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); -} - -static int -nouveauGetSwapInfo(__DRIdrawablePrivate *dpriv, __DRIswapInfo *sInfo) -{ - return -1; -} - -static __DRIconfig ** -nouveauFillInModes( __DRIscreenPrivate *psp, - unsigned pixel_bits, unsigned depth_bits, - unsigned stencil_bits, GLboolean have_back_buffer ) -{ - unsigned depth_buffer_factor; - unsigned back_buffer_factor; - - /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't - * support pageflipping at all. - */ - static const GLenum back_buffer_modes[] = { - GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML - }; - - u_int8_t depth_bits_array[4] = { 0, 16, 24, 24 }; - u_int8_t stencil_bits_array[4] = { 0, 0, 0, 8 }; - - depth_buffer_factor = 4; - back_buffer_factor = (have_back_buffer) ? 3 : 1; - - if (pixel_bits == 16) - return driCreateConfigs(GL_RGB, - GL_UNSIGNED_SHORT_5_6_5, - depth_bits_array, - stencil_bits_array, - depth_buffer_factor, - back_buffer_modes, - back_buffer_factor); - else - return driCreateConfigs(GL_RGBA, - GL_UNSIGNED_INT_8_8_8_8_REV, - depth_bits_array, - stencil_bits_array, - depth_buffer_factor, - back_buffer_modes, - back_buffer_factor); -} - - -/** - * This is the driver specific part of the createNewScreen entry point. - * - * \todo maybe fold this into intelInitDriver - * - * \return the __GLcontextModes supported by this driver - */ -static const __DRIconfig ** -nouveauInitScreen(__DRIscreenPrivate *psp) -{ - static const __DRIversion ddx_expected = { 0, 0, NOUVEAU_DRM_HEADER_PATCHLEVEL }; - static const __DRIversion dri_expected = { 4, 0, 0 }; - static const __DRIversion drm_expected = { 0, 0, NOUVEAU_DRM_HEADER_PATCHLEVEL }; - NOUVEAUDRIPtr dri_priv = (NOUVEAUDRIPtr)psp->pDevPriv; - - WARN_ONCE("\nThis driver is not currently maintained\n\n" - "Current work on 3D is in the gallium-0.1 branch of:\n" - " git://anongit.freedesktop.org/git/nouveau/mesa\n"); - -#if NOUVEAU_DRM_HEADER_PATCHLEVEL != 10 -#error nouveau_drm.h version does not match expected version -#endif - - if (!driCheckDriDdxDrmVersions2("nouveau", - &psp->dri_version, & dri_expected, - &psp->ddx_version, & ddx_expected, - &psp->drm_version, & drm_expected)) - return NULL; - - // temporary lock step versioning - if (drm_expected.patch != psp->drm_version.patch) { - __driUtilMessage("%s: wrong DRM version, expected %d, got %d\n", - __func__, - drm_expected.patch, psp->drm_version.patch); - return NULL; - } - - /* Calling driInitExtensions here, with a NULL context - * pointer, does not actually enable the extensions. It just - * makes sure that all the dispatch offsets for all the - * extensions that *might* be enables are known. This is - * needed because the dispatch offsets need to be known when - * _mesa_context_create is called, but we can't enable the - * extensions until we have a context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, common_extensions, GL_FALSE ); - driInitExtensions( NULL, nv10_extensions, GL_FALSE ); - driInitExtensions( NULL, nv10_extensions, GL_FALSE ); - driInitExtensions( NULL, nv30_extensions, GL_FALSE ); - driInitExtensions( NULL, nv40_extensions, GL_FALSE ); - driInitExtensions( NULL, nv50_extensions, GL_FALSE ); - - if (!nouveauInitDriver(psp)) - return NULL; - - return (const __DRIconfig **) - nouveauFillInModes(psp, - dri_priv->bpp, - (dri_priv->bpp == 16) ? 16 : 24, - (dri_priv->bpp == 16) ? 0 : 8, - 1); -} - -const struct __DriverAPIRec driDriverAPI = { - .InitScreen = nouveauInitScreen, - .DestroyScreen = nouveauDestroyScreen, - .CreateContext = nouveauCreateContext, - .DestroyContext = nouveauDestroyContext, - .CreateBuffer = nouveauCreateBuffer, - .DestroyBuffer = nouveauDestroyBuffer, - .SwapBuffers = nouveauSwapBuffers, - .MakeCurrent = nouveauMakeCurrent, - .UnbindContext = nouveauUnbindContext, - .GetSwapInfo = nouveauGetSwapInfo, - .GetDrawableMSC = driDrawableGetMSC32, - .WaitForMSC = driWaitForMSC32, - .WaitForSBC = NULL, - .SwapBuffersMSC = NULL, - .CopySubBuffer = nouveauCopySubBuffer -}; - -const __DRIextension *__driDriverExtensions[] = { - &driCoreExtension.base, - &driLegacyExtension.base, - NULL -}; diff --git a/src/mesa/drivers/dri/nouveau/nouveau_screen.h b/src/mesa/drivers/dri/nouveau/nouveau_screen.h deleted file mode 100644 index decdafa86d5..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_screen.h +++ /dev/null @@ -1,61 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#ifndef __NOUVEAU_SCREEN_H__ -#define __NOUVEAU_SCREEN_H__ - -#include "xmlconfig.h" - -#include "nouveau_dri.h" -#include "nouveau_card.h" - -typedef struct { - nouveau_card* card; - u_int32_t bus_type; - u_int32_t agp_mode; - - GLint fbFormat; - - GLuint frontOffset; - GLuint frontPitch; - GLuint backOffset; - GLuint backPitch; - - GLuint depthOffset; - GLuint depthPitch; - GLuint spanOffset; - - __DRIscreenPrivate *driScreen; - unsigned int sarea_priv_offset; - - /* Configuration cache with default values for all contexts */ - driOptionCache optionCache; - -} nouveauScreenRec, *nouveauScreenPtr; - - -#endif /* __NOUVEAU_SCREEN_H__ */ diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.c b/src/mesa/drivers/dri/nouveau/nouveau_shader.c deleted file mode 100644 index b6837c5de14..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader.c +++ /dev/null @@ -1,833 +0,0 @@ -/* - * Copyright (C) 2006 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Ben Skeggs <[email protected]> - */ - -#include "glheader.h" -#include "macros.h" -#include "enums.h" -#include "extensions.h" - -#include "shader/program.h" -#include "shader/prog_instruction.h" -/*#include "shader/arbprogparse.h"*/ -#include "tnl/tnl.h" - -#include "nouveau_context.h" -#include "nouveau_shader.h" - -/***************************************************************************** - * Mesa entry points - */ -static void -nouveauBindProgram(GLcontext *ctx, GLenum target, struct gl_program *prog) -{ - NVSDBG("target=%s, prog=%p\n", _mesa_lookup_enum_by_nr(target), prog); -} - -static struct gl_program * -nouveauNewProgram(GLcontext *ctx, GLenum target, GLuint id) -{ - nouveauShader *nvs; - - NVSDBG("target=%s, id=%d\n", _mesa_lookup_enum_by_nr(target), id); - - nvs = CALLOC_STRUCT(_nouveauShader); - NVSDBG("prog=%p\n", nvs); - switch (target) { - case GL_VERTEX_PROGRAM_ARB: - return _mesa_init_vertex_program(ctx, &nvs->mesa.vp, target, id); - case GL_FRAGMENT_PROGRAM_ARB: - return _mesa_init_fragment_program(ctx, &nvs->mesa.fp, target, id); - default: - _mesa_problem(ctx, "Unsupported shader target"); - break; - } - - FREE(nvs); - return NULL; -} - -static void -nouveauDeleteProgram(GLcontext *ctx, struct gl_program *prog) -{ - nouveauShader *nvs = (nouveauShader *)prog; - - NVSDBG("prog=%p\n", prog); - - if (nvs->translated) - FREE(nvs->program); - _mesa_delete_program(ctx, prog); -} - -static void -nouveauProgramStringNotify(GLcontext *ctx, GLenum target, - struct gl_program *prog) -{ - nouveauShader *nvs = (nouveauShader *)prog; - - NVSDBG("target=%s, prog=%p\n", _mesa_lookup_enum_by_nr(target), prog); - - if (nvs->translated) - FREE(nvs->program); - - nvs->error = GL_FALSE; - nvs->translated = GL_FALSE; - - _tnl_program_string(ctx, target, prog); -} - -static GLboolean -nouveauIsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) -{ - nouveauShader *nvs = (nouveauShader *)prog; - - NVSDBG("target=%s, prog=%p\n", _mesa_lookup_enum_by_nr(target), prog); - - return nvs->translated; -} - -GLboolean -nvsUpdateShader(GLcontext *ctx, nouveauShader *nvs) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - struct gl_program_parameter_list *plist; - int i; - - NVSDBG("prog=%p\n", nvs); - - /* Translate to HW format now if necessary */ - if (!nvs->translated) { - /* Mesa ASM shader -> nouveauShader */ - if (!nouveau_shader_pass0(ctx, nvs)) - return GL_FALSE; - /* Basic dead code elimination + register usage info */ - if (!nouveau_shader_pass1(nvs)) - return GL_FALSE; - /* nouveauShader -> HW bytecode, HW register alloc */ - if (!nouveau_shader_pass2(nvs)) - return GL_FALSE; - assert(nvs->translated); - assert(nvs->program); - } - - /* Update state parameters */ - plist = nvs->mesa.vp.Base.Parameters; - _mesa_load_state_parameters(ctx, plist); - for (i=0; i<nvs->param_high; i++) { - if (!nvs->params[i].in_use) - continue; - - if (!nvs->on_hardware) { - /* if we've been kicked off the hardware there's no guarantee our - * consts are still there.. reupload them all - */ - nvs->func->UpdateConst(ctx, nvs, i); - } else if (nvs->params[i].source_val) { - /* update any changed state parameters */ - if (!TEST_EQ_4V(nvs->params[i].val, nvs->params[i].source_val)) - nvs->func->UpdateConst(ctx, nvs, i); - } - } - - /* Upload program to hardware, this must come after state param update - * as >=NV30 fragprogs inline consts into the bytecode. - */ - if (!nvs->on_hardware) { - nouveauShader **current; - - if (nvs->mesa.vp.Base.Target == GL_VERTEX_PROGRAM_ARB) - current = &nmesa->current_vertprog; - else - current = &nmesa->current_fragprog; - if (*current) (*current)->on_hardware = 0; - - nvs->func->UploadToHW(ctx, nvs); - nvs->on_hardware = 1; - - *current = nvs; - } - - return GL_TRUE; -} - -nouveauShader * -nvsBuildTextShader(GLcontext *ctx, GLenum target, const char *text) -{ - nouveauShader *nvs; - - nvs = CALLOC_STRUCT(_nouveauShader); - if (!nvs) - return NULL; - - if (target == GL_VERTEX_PROGRAM_ARB) { - _mesa_init_vertex_program(ctx, &nvs->mesa.vp, GL_VERTEX_PROGRAM_ARB, 0); - _mesa_parse_arb_vertex_program(ctx, - GL_VERTEX_PROGRAM_ARB, - text, - strlen(text), - &nvs->mesa.vp); - } else if (target == GL_FRAGMENT_PROGRAM_ARB) { - _mesa_init_fragment_program(ctx, &nvs->mesa.fp, GL_FRAGMENT_PROGRAM_ARB, 0); - _mesa_parse_arb_fragment_program(ctx, - GL_FRAGMENT_PROGRAM_ARB, - text, - strlen(text), - &nvs->mesa.fp); - } - - nouveau_shader_pass0(ctx, nvs); - nouveau_shader_pass1(nvs); - nouveau_shader_pass2(nvs); - - return nvs; -} - -static void -nvsBuildPassthroughVP(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - const char *vp_text = - "!!ARBvp1.0\n" - "OPTION ARB_position_invariant;" - "" - "MOV result.color, vertex.color;\n" - "MOV result.texcoord[0], vertex.texcoord[0];\n" - "MOV result.texcoord[1], vertex.texcoord[1];\n" - "MOV result.texcoord[2], vertex.texcoord[2];\n" - "MOV result.texcoord[3], vertex.texcoord[3];\n" - "MOV result.texcoord[4], vertex.texcoord[4];\n" - "MOV result.texcoord[5], vertex.texcoord[5];\n" - "MOV result.texcoord[6], vertex.texcoord[6];\n" - "MOV result.texcoord[7], vertex.texcoord[7];\n" - "END"; - - nmesa->passthrough_vp = nvsBuildTextShader(ctx, - GL_VERTEX_PROGRAM_ARB, - vp_text); -} - -static void -nvsBuildPassthroughFP(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - const char *fp_text = - "!!ARBfp1.0\n" - "MOV result.color, fragment.color;\n" - "END"; - - nmesa->passthrough_fp = nvsBuildTextShader(ctx, - GL_FRAGMENT_PROGRAM_ARB, - fp_text); -} - -void -nouveauShaderInitFuncs(GLcontext * ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - switch (nmesa->screen->card->type) { - case NV_20: - NV20VPInitShaderFuncs(&nmesa->VPfunc); - break; - case NV_30: - NV30VPInitShaderFuncs(&nmesa->VPfunc); - NV30FPInitShaderFuncs(&nmesa->FPfunc); - break; - case NV_40: - case NV_44: - NV40VPInitShaderFuncs(&nmesa->VPfunc); - NV40FPInitShaderFuncs(&nmesa->FPfunc); - break; - case NV_50: - default: - return; - } - - /* Build a vertex program that simply passes through all attribs. - * Needed to do swtcl on nv40 - */ - if (nmesa->screen->card->type >= NV_40) - nvsBuildPassthroughVP(ctx); - - /* Needed on NV30, even when using swtcl, if you want to get colours */ - if (nmesa->screen->card->type >= NV_30) - nvsBuildPassthroughFP(ctx); - - ctx->Const.VertexProgram.MaxNativeInstructions = nmesa->VPfunc.MaxInst; - ctx->Const.VertexProgram.MaxNativeAluInstructions = nmesa->VPfunc.MaxInst; - ctx->Const.VertexProgram.MaxNativeTexInstructions = nmesa->VPfunc.MaxInst; - ctx->Const.VertexProgram.MaxNativeTexIndirections = - ctx->Const.VertexProgram.MaxNativeTexInstructions; - ctx->Const.VertexProgram.MaxNativeAttribs = nmesa->VPfunc.MaxAttrib; - ctx->Const.VertexProgram.MaxNativeTemps = nmesa->VPfunc.MaxTemp; - ctx->Const.VertexProgram.MaxNativeAddressRegs = nmesa->VPfunc.MaxAddress; - ctx->Const.VertexProgram.MaxNativeParameters = nmesa->VPfunc.MaxConst; - - if (nmesa->screen->card->type >= NV_30) { - ctx->Const.FragmentProgram.MaxNativeInstructions = nmesa->FPfunc.MaxInst; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = nmesa->FPfunc.MaxInst; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = nmesa->FPfunc.MaxInst; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = - ctx->Const.FragmentProgram.MaxNativeTexInstructions; - ctx->Const.FragmentProgram.MaxNativeAttribs = nmesa->FPfunc.MaxAttrib; - ctx->Const.FragmentProgram.MaxNativeTemps = nmesa->FPfunc.MaxTemp; - ctx->Const.FragmentProgram.MaxNativeAddressRegs = nmesa->FPfunc.MaxAddress; - ctx->Const.FragmentProgram.MaxNativeParameters = nmesa->FPfunc.MaxConst; - } - - ctx->Driver.NewProgram = nouveauNewProgram; - ctx->Driver.BindProgram = nouveauBindProgram; - ctx->Driver.DeleteProgram = nouveauDeleteProgram; - ctx->Driver.ProgramStringNotify = nouveauProgramStringNotify; - ctx->Driver.IsProgramNative = nouveauIsProgramNative; -} - - -/***************************************************************************** - * Disassembly support structs - */ -#define CHECK_RANGE(idx, arr) ((idx)<sizeof(_##arr)/sizeof(const char *)) \ - ? _##arr[(idx)] : #arr"_OOB" - -#define NODS (1<<0) -#define BRANCH_TR (1<<1) -#define BRANCH_EL (1<<2) -#define BRANCH_EN (1<<3) -#define BRANCH_RE (1<<4) -#define BRANCH_ALL (BRANCH_TR|BRANCH_EL|BRANCH_EN) -#define COUNT_INC (1<<4) -#define COUNT_IND (1<<5) -#define COUNT_NUM (1<<6) -#define COUNT_ALL (COUNT_INC|COUNT_IND|COUNT_NUM) -#define TI_UNIT (1<<7) -struct _opcode_info -{ - const char *name; - int numsrc; - int flags; -}; - -static struct _opcode_info ops[] = { - [NVS_OP_ABS] = {"ABS", 1, 0}, - [NVS_OP_ADD] = {"ADD", 2, 0}, - [NVS_OP_ARA] = {"ARA", 1, 0}, - [NVS_OP_ARL] = {"ARL", 1, 0}, - [NVS_OP_ARR] = {"ARR", 1, 0}, - [NVS_OP_BRA] = {"BRA", 0, NODS | BRANCH_TR}, - [NVS_OP_BRK] = {"BRK", 0, NODS}, - [NVS_OP_CAL] = {"CAL", 0, NODS | BRANCH_TR}, - [NVS_OP_CMP] = {"CMP", 2, 0}, - [NVS_OP_COS] = {"COS", 1, 0}, - [NVS_OP_DIV] = {"DIV", 2, 0}, - [NVS_OP_DDX] = {"DDX", 1, 0}, - [NVS_OP_DDY] = {"DDY", 1, 0}, - [NVS_OP_DP2] = {"DP2", 2, 0}, - [NVS_OP_DP2A] = {"DP2A", 3, 0}, - [NVS_OP_DP3] = {"DP3", 2, 0}, - [NVS_OP_DP4] = {"DP4", 2, 0}, - [NVS_OP_DPH] = {"DPH", 2, 0}, - [NVS_OP_DST] = {"DST", 2, 0}, - [NVS_OP_EX2] = {"EX2", 1, 0}, - [NVS_OP_EXP] = {"EXP", 1, 0}, - [NVS_OP_FLR] = {"FLR", 1, 0}, - [NVS_OP_FRC] = {"FRC", 1, 0}, - [NVS_OP_IF] = {"IF", 0, NODS | BRANCH_EL | BRANCH_EN}, - [NVS_OP_KIL] = {"KIL", 1, 0}, - [NVS_OP_LG2] = {"LG2", 1, 0}, - [NVS_OP_LIT] = {"LIT", 1, 0}, - [NVS_OP_LOG] = {"LOG", 1, 0}, - [NVS_OP_LOOP] = {"LOOP", 0, NODS | COUNT_ALL | BRANCH_EN}, - [NVS_OP_LRP] = {"LRP", 3, 0}, - [NVS_OP_MAD] = {"MAD", 3, 0}, - [NVS_OP_MAX] = {"MAX", 2, 0}, - [NVS_OP_MIN] = {"MIN", 2, 0}, - [NVS_OP_MOV] = {"MOV", 1, 0}, - [NVS_OP_MUL] = {"MUL", 2, 0}, - [NVS_OP_NRM] = {"NRM", 1, 0}, - [NVS_OP_PK2H] = {"PK2H", 1, 0}, - [NVS_OP_PK2US] = {"PK2US", 1, 0}, - [NVS_OP_PK4B] = {"PK4B", 1, 0}, - [NVS_OP_PK4UB] = {"PK4UB", 1, 0}, - [NVS_OP_POW] = {"POW", 2, 0}, - [NVS_OP_POPA] = {"POPA", 0, 0}, - [NVS_OP_PUSHA] = {"PUSHA", 1, NODS}, - [NVS_OP_RCC] = {"RCC", 1, 0}, - [NVS_OP_RCP] = {"RCP", 1, 0}, - [NVS_OP_REP] = {"REP", 0, NODS | BRANCH_EN | COUNT_NUM}, - [NVS_OP_RET] = {"RET", 0, NODS}, - [NVS_OP_RFL] = {"RFL", 1, 0}, - [NVS_OP_RSQ] = {"RSQ", 1, 0}, - [NVS_OP_SCS] = {"SCS", 1, 0}, - [NVS_OP_SEQ] = {"SEQ", 2, 0}, - [NVS_OP_SFL] = {"SFL", 2, 0}, - [NVS_OP_SGE] = {"SGE", 2, 0}, - [NVS_OP_SGT] = {"SGT", 2, 0}, - [NVS_OP_SIN] = {"SIN", 1, 0}, - [NVS_OP_SLE] = {"SLE", 2, 0}, - [NVS_OP_SLT] = {"SLT", 2, 0}, - [NVS_OP_SNE] = {"SNE", 2, 0}, - [NVS_OP_SSG] = {"SSG", 1, 0}, - [NVS_OP_STR] = {"STR", 2, 0}, - [NVS_OP_SUB] = {"SUB", 2, 0}, - [NVS_OP_TEX] = {"TEX", 1, TI_UNIT}, - [NVS_OP_TXB] = {"TXB", 1, TI_UNIT}, - [NVS_OP_TXD] = {"TXD", 3, TI_UNIT}, - [NVS_OP_TXL] = {"TXL", 1, TI_UNIT}, - [NVS_OP_TXP] = {"TXP", 1, TI_UNIT}, - [NVS_OP_UP2H] = {"UP2H", 1, 0}, - [NVS_OP_UP2US] = {"UP2US", 1, 0}, - [NVS_OP_UP4B] = {"UP4B", 1, 0}, - [NVS_OP_UP4UB] = {"UP4UB", 1, 0}, - [NVS_OP_X2D] = {"X2D", 3, 0}, - [NVS_OP_XPD] = {"XPD", 2, 0}, - [NVS_OP_NOP] = {"NOP", 0, NODS}, -}; - -static struct _opcode_info * -_get_op_info(int op) -{ - if (op >= (sizeof(ops) / sizeof(struct _opcode_info))) - return NULL; - if (ops[op].name == NULL) - return NULL; - return &ops[op]; -} - -static const char *_SFR_STRING[] = { - [NVS_FR_POSITION] = "position", - [NVS_FR_WEIGHT] = "weight", - [NVS_FR_NORMAL] = "normal", - [NVS_FR_COL0] = "color", - [NVS_FR_COL1] = "color.secondary", - [NVS_FR_BFC0] = "bfc", - [NVS_FR_BFC1] = "bfc.secondary", - [NVS_FR_FOGCOORD] = "fogcoord", - [NVS_FR_POINTSZ] = "pointsize", - [NVS_FR_TEXCOORD0] = "texcoord[0]", - [NVS_FR_TEXCOORD1] = "texcoord[1]", - [NVS_FR_TEXCOORD2] = "texcoord[2]", - [NVS_FR_TEXCOORD3] = "texcoord[3]", - [NVS_FR_TEXCOORD4] = "texcoord[4]", - [NVS_FR_TEXCOORD5] = "texcoord[5]", - [NVS_FR_TEXCOORD6] = "texcoord[6]", - [NVS_FR_TEXCOORD7] = "texcoord[7]", - [NVS_FR_FRAGDATA0] = "data[0]", - [NVS_FR_FRAGDATA1] = "data[1]", - [NVS_FR_FRAGDATA2] = "data[2]", - [NVS_FR_FRAGDATA3] = "data[3]", - [NVS_FR_CLIP0] = "clip_plane[0]", - [NVS_FR_CLIP1] = "clip_plane[1]", - [NVS_FR_CLIP2] = "clip_plane[2]", - [NVS_FR_CLIP3] = "clip_plane[3]", - [NVS_FR_CLIP4] = "clip_plane[4]", - [NVS_FR_CLIP5] = "clip_plane[5]", - [NVS_FR_CLIP6] = "clip_plane[6]", - [NVS_FR_FACING] = "facing", -}; - -#define SFR_STRING(idx) CHECK_RANGE((idx), SFR_STRING) - -static const char *_SWZ_STRING[] = { - [NVS_SWZ_X] = "x", - [NVS_SWZ_Y] = "y", - [NVS_SWZ_Z] = "z", - [NVS_SWZ_W] = "w" -}; - -#define SWZ_STRING(idx) CHECK_RANGE((idx), SWZ_STRING) - -static const char *_NVS_PREC_STRING[] = { - [NVS_PREC_FLOAT32] = "R", - [NVS_PREC_FLOAT16] = "H", - [NVS_PREC_FIXED12] = "X", - [NVS_PREC_UNKNOWN] = "?" -}; - -#define NVS_PREC_STRING(idx) CHECK_RANGE((idx), NVS_PREC_STRING) - -static const char *_NVS_COND_STRING[] = { - [NVS_COND_FL] = "FL", - [NVS_COND_LT] = "LT", - [NVS_COND_EQ] = "EQ", - [NVS_COND_LE] = "LE", - [NVS_COND_GT] = "GT", - [NVS_COND_NE] = "NE", - [NVS_COND_GE] = "GE", - [NVS_COND_TR] = "TR", - [NVS_COND_UNKNOWN] = "??" -}; - -#define NVS_COND_STRING(idx) CHECK_RANGE((idx), NVS_COND_STRING) - -/***************************************************************************** - * ShaderFragment dumping - */ -static void -nvsDumpIndent(int lvl) -{ - while (lvl--) - printf(" "); -} - -static void -nvsDumpSwizzle(nvsSwzComp *swz) -{ - printf(".%s%s%s%s", - SWZ_STRING(swz[0]), - SWZ_STRING(swz[1]), SWZ_STRING(swz[2]), SWZ_STRING(swz[3]) - ); -} - -static void -nvsDumpReg(nvsInstruction * inst, nvsRegister * reg) -{ - if (reg->negate) - printf("-"); - if (reg->abs) - printf("abs("); - - switch (reg->file) { - case NVS_FILE_TEMP: - printf("R%d", reg->index); - nvsDumpSwizzle(reg->swizzle); - break; - case NVS_FILE_ATTRIB: - printf("attrib.%s", SFR_STRING(reg->index)); - nvsDumpSwizzle(reg->swizzle); - break; - case NVS_FILE_ADDRESS: - printf("A%d", reg->index); - break; - case NVS_FILE_CONST: - if (reg->indexed) - printf("const[A%d.%s + %d]", - reg->addr_reg, SWZ_STRING(reg->addr_comp), reg->index); - else - printf("const[%d]", reg->index); - nvsDumpSwizzle(reg->swizzle); - break; - default: - printf("UNKNOWN_FILE"); - break; - } - - if (reg->abs) - printf(")"); -} - -static void -nvsDumpInstruction(nvsInstruction * inst, int slot, int lvl) -{ - struct _opcode_info *opr = &ops[inst->op]; - int i; - - nvsDumpIndent(lvl); - printf("%s ", opr->name); - - if (!opr->flags & NODS) { - switch (inst->dest.file) { - case NVS_FILE_RESULT: - printf("result.%s", SFR_STRING(inst->dest.index)); - break; - case NVS_FILE_TEMP: - printf("R%d", inst->dest.index); - break; - case NVS_FILE_ADDRESS: - printf("A%d", inst->dest.index); - break; - default: - printf("UNKNOWN_DST_FILE"); - break; - } - - if (inst->mask != SMASK_ALL) { - printf("."); - if (inst->mask & SMASK_X) - printf("x"); - if (inst->mask & SMASK_Y) - printf("y"); - if (inst->mask & SMASK_Z) - printf("z"); - if (inst->mask & SMASK_W) - printf("w"); - } - - if (opr->numsrc) - printf(", "); - } - - for (i = 0; i < opr->numsrc; i++) { - nvsDumpReg(inst, &inst->src[i]); - if (i != opr->numsrc - 1) - printf(", "); - } - if (opr->flags & TI_UNIT) - printf(", texture[%d]", inst->tex_unit); - - printf("\n"); -} - -void -nvsDumpFragmentList(nvsFragmentHeader *f, int lvl) -{ - while (f) { - switch (f->type) { - case NVS_INSTRUCTION: - nvsDumpInstruction((nvsInstruction*)f, 0, lvl); - break; - default: - fprintf(stderr, "%s: Only NVS_INSTRUCTION fragments can be in" - "nvsFragmentList!\n", __func__); - return; - } - f = f->next; - } -} - -/***************************************************************************** - * HW shader disassembly - */ -static void -nvsDisasmHWShaderOp(nvsFunc * shader, int merged) -{ - struct _opcode_info *opi; - nvsOpcode op; - nvsRegFile file; - nvsSwzComp swz[4]; - int i; - - op = shader->GetOpcode(shader, merged); - opi = _get_op_info(op); - if (!opi) { - printf("NO OPINFO!"); - return; - } - - printf("%s", opi->name); - if (shader->GetPrecision && - (!(opi->flags & BRANCH_ALL)) && (!(opi->flags * NODS)) && - (op != NVS_OP_NOP)) - printf("%s", NVS_PREC_STRING(shader->GetPrecision(shader))); - if (shader->SupportsConditional && shader->SupportsConditional(shader)) { - if (shader->GetConditionUpdate(shader)) { - printf("C%d", shader->GetCondRegID(shader)); - } - } - if (shader->GetSaturate && shader->GetSaturate(shader)) - printf("_SAT"); - - if (!(opi->flags & NODS)) { - int mask = shader->GetDestMask(shader, merged); - - switch (shader->GetDestFile(shader, merged)) { - case NVS_FILE_ADDRESS: - printf(" A%d", shader->GetDestID(shader, merged)); - break; - case NVS_FILE_TEMP: - printf(" R%d", shader->GetDestID(shader, merged)); - break; - case NVS_FILE_RESULT: - printf(" result.%s", (SFR_STRING(shader->GetDestID(shader, merged)))); - break; - default: - printf(" BAD_RESULT_FILE"); - break; - } - - if (mask != SMASK_ALL) { - printf("."); - if (mask & SMASK_X) printf("x"); - if (mask & SMASK_Y) printf("y"); - if (mask & SMASK_Z) printf("z"); - if (mask & SMASK_W) printf("w"); - } - } - - if (shader->SupportsConditional && shader->SupportsConditional(shader) && - shader->GetConditionTest(shader)) { - shader->GetCondRegSwizzle(shader, swz); - - printf(" (%s%d.%s%s%s%s)", - NVS_COND_STRING(shader->GetCondition(shader)), - shader->GetCondRegID(shader), - SWZ_STRING(swz[NVS_SWZ_X]), - SWZ_STRING(swz[NVS_SWZ_Y]), - SWZ_STRING(swz[NVS_SWZ_Z]), - SWZ_STRING(swz[NVS_SWZ_W]) - ); - } - - /* looping */ - if (opi->flags & COUNT_ALL) { - printf(" { "); - if (opi->flags & COUNT_NUM) { - printf("%d", shader->GetLoopCount(shader)); - } - if (opi->flags & COUNT_IND) { - printf(", %d", shader->GetLoopInitial(shader)); - } - if (opi->flags & COUNT_INC) { - printf(", %d", shader->GetLoopIncrement(shader)); - } - printf(" }"); - } - - /* branching */ - if (opi->flags & BRANCH_TR) - printf(" %d", shader->GetBranch(shader)); - if (opi->flags & BRANCH_EL) - printf(" ELSE %d", shader->GetBranchElse(shader)); - if (opi->flags & BRANCH_EN) - printf(" END %d", shader->GetBranchEnd(shader)); - - if (!(opi->flags & NODS) && opi->numsrc) - printf(","); - printf(" "); - - for (i = 0; i < opi->numsrc; i++) { - if (shader->GetSourceAbs(shader, merged, i)) - printf("abs("); - if (shader->GetSourceNegate(shader, merged, i)) - printf("-"); - - file = shader->GetSourceFile(shader, merged, i); - switch (file) { - case NVS_FILE_TEMP: - printf("R%d", shader->GetSourceID(shader, merged, i)); - break; - case NVS_FILE_CONST: - if (shader->GetSourceIndexed(shader, merged, i)) { - printf("c[A%d.%s + 0x%x]", - shader->GetRelAddressRegID(shader), - SWZ_STRING(shader->GetRelAddressSwizzle(shader)), - shader->GetSourceID(shader, merged, i) - ); - } else { - float val[4]; - - if (shader->GetSourceConstVal) { - shader->GetSourceConstVal(shader, merged, i, val); - printf("{ %.02f, %.02f, %.02f, %.02f }", - val[0], val[1], val[2], val[3]); - } else { - printf("c[0x%x]", shader->GetSourceID(shader, merged, i)); - } - } - break; - case NVS_FILE_ATTRIB: - if (shader->GetSourceIndexed(shader, merged, i)) { - printf("attrib[A%d.%s + %d]", - shader->GetRelAddressRegID(shader), - SWZ_STRING(shader->GetRelAddressSwizzle(shader)), - shader->GetSourceID(shader, merged, i) - ); - } - else { - printf("attrib.%s", - SFR_STRING(shader->GetSourceID(shader, merged, i)) - ); - } - break; - case NVS_FILE_ADDRESS: - printf("A%d", shader->GetRelAddressRegID(shader)); - break; - default: - printf("UNKNOWN_SRC_FILE"); - break; - } - - shader->GetSourceSwizzle(shader, merged, i, swz); - if (file != NVS_FILE_ADDRESS && - (swz[NVS_SWZ_X] != NVS_SWZ_X || swz[NVS_SWZ_Y] != NVS_SWZ_Y || - swz[NVS_SWZ_Z] != NVS_SWZ_Z || swz[NVS_SWZ_W] != NVS_SWZ_W)) { - printf(".%s%s%s%s", SWZ_STRING(swz[NVS_SWZ_X]), - SWZ_STRING(swz[NVS_SWZ_Y]), - SWZ_STRING(swz[NVS_SWZ_Z]), - SWZ_STRING(swz[NVS_SWZ_W])); - } - - if (shader->GetSourceAbs(shader, merged, i)) - printf(")"); - if (shader->GetSourceScale) { - int scale = shader->GetSourceScale(shader, merged, i); - if (scale > 1) - printf("{scaled %dx}", scale); - } - if (i < (opi->numsrc - 1)) - printf(", "); - } - - if (shader->IsLastInst(shader)) - printf(" + END"); -} - -void -nvsDisasmHWShader(nvsPtr nvs) -{ - nvsFunc *shader = nvs->func; - unsigned int iaddr = 0; - - if (!nvs->program) { - fprintf(stderr, "No HW program present"); - return; - } - - shader->inst = nvs->program; - while (1) { - if (shader->inst >= (nvs->program + nvs->program_size)) { - fprintf(stderr, "Reached end of program, but HW inst has no END"); - break; - } - - printf("\t0x%08x:\n", shader->inst[0]); - printf("\t0x%08x:\n", shader->inst[1]); - printf("\t0x%08x:\n", shader->inst[2]); - printf("\t0x%08x:", shader->inst[3]); - - printf("\n\t\tINST %d.0: ", iaddr); - nvsDisasmHWShaderOp(shader, 0); - if (shader->HasMergedInst(shader)) { - printf("\n\t\tINST %d.1: ", iaddr); - nvsDisasmHWShaderOp(shader, 1); - } - printf("\n"); - - if (shader->IsLastInst(shader)) - break; - - shader->inst += shader->GetOffsetNext(shader); - iaddr++; - } - - printf("\n"); -} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.h b/src/mesa/drivers/dri/nouveau/nouveau_shader.h deleted file mode 100644 index 636bcaa72b2..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader.h +++ /dev/null @@ -1,454 +0,0 @@ -#ifndef __SHADER_COMMON_H__ -#define __SHADER_COMMON_H__ - -#include "mtypes.h" -#include "bufferobj.h" - -#define NVSDBG(fmt, args...) do { \ - if (NOUVEAU_DEBUG & DEBUG_SHADERS) { \ - fprintf(stderr, "%s: "fmt, __func__, ##args); \ - } \ -} while(0) - -typedef struct _nvsFunc nvsFunc; - -#define NVS_MAX_TEMPS 32 -#define NVS_MAX_ATTRIBS 16 -#define NVS_MAX_CONSTS 256 -#define NVS_MAX_ADDRESS 2 -#define NVS_MAX_INSNS 4096 - -typedef struct _nvs_fragment_header { - struct _nvs_fragment_header *parent; - struct _nvs_fragment_header *prev; - struct _nvs_fragment_header *next; - enum { - NVS_INSTRUCTION, - NVS_BRANCH, - NVS_LOOP, - NVS_SUBROUTINE - } type; -} nvsFragmentHeader; - -typedef union { - struct { - GLboolean uses_kil; - GLuint num_regs; - } NV30FP; - struct { - uint32_t vp_in_reg; - uint32_t vp_out_reg; - uint32_t clip_enables; - } NV30VP; -} nvsCardPriv; - -typedef struct _nouveauShader { - union { - struct gl_vertex_program vp; - struct gl_fragment_program fp; - } mesa; - GLcontext *ctx; - nvsFunc *func; - - /* State of the final program */ - GLboolean error; - GLboolean translated; - GLboolean on_hardware; - unsigned int *program; - unsigned int program_size; - unsigned int program_alloc_size; - unsigned int program_start_id; - unsigned int program_current; - struct gl_buffer_object *program_buffer; - int inst_count; - - nvsCardPriv card_priv; - int vp_attrib_map[NVS_MAX_ATTRIBS]; - - struct { - GLboolean in_use; - - GLfloat *source_val; /* NULL if invariant */ - float val[4]; - /* Hardware-specific tracking, currently only nv30_fragprog - * makes use of it. - */ - int *hw_index; - int hw_index_cnt; - } params[NVS_MAX_CONSTS]; - int param_high; - - /* Pass-private data */ - void *pass_rec; - - nvsFragmentHeader *program_tree; -} nouveauShader, *nvsPtr; - -typedef enum { - NVS_FILE_NONE, - NVS_FILE_TEMP, - NVS_FILE_ATTRIB, - NVS_FILE_CONST, - NVS_FILE_RESULT, - NVS_FILE_ADDRESS, - NVS_FILE_UNKNOWN -} nvsRegFile; - -typedef enum { - NVS_OP_UNKNOWN = 0, - NVS_OP_NOP, - NVS_OP_ABS, NVS_OP_ADD, NVS_OP_ARA, NVS_OP_ARL, NVS_OP_ARR, - NVS_OP_BRA, NVS_OP_BRK, - NVS_OP_CAL, NVS_OP_CMP, NVS_OP_COS, - NVS_OP_DDX, NVS_OP_DDY, NVS_OP_DIV, NVS_OP_DP2, NVS_OP_DP2A, NVS_OP_DP3, - NVS_OP_DP4, NVS_OP_DPH, NVS_OP_DST, - NVS_OP_EX2, NVS_OP_EXP, - NVS_OP_FLR, NVS_OP_FRC, - NVS_OP_IF, - NVS_OP_KIL, - NVS_OP_LG2, NVS_OP_LIT, NVS_OP_LOG, NVS_OP_LOOP, NVS_OP_LRP, - NVS_OP_MAD, NVS_OP_MAX, NVS_OP_MIN, NVS_OP_MOV, NVS_OP_MUL, - NVS_OP_NRM, - NVS_OP_PK2H, NVS_OP_PK2US, NVS_OP_PK4B, NVS_OP_PK4UB, NVS_OP_POW, - NVS_OP_POPA, NVS_OP_PUSHA, - NVS_OP_RCC, NVS_OP_RCP, NVS_OP_REP, NVS_OP_RET, NVS_OP_RFL, NVS_OP_RSQ, - NVS_OP_SCS, NVS_OP_SEQ, NVS_OP_SFL, NVS_OP_SGE, NVS_OP_SGT, NVS_OP_SIN, - NVS_OP_SLE, NVS_OP_SLT, NVS_OP_SNE, NVS_OP_SSG, NVS_OP_STR, NVS_OP_SUB, - NVS_OP_SWZ, - NVS_OP_TEX, NVS_OP_TXB, NVS_OP_TXD, NVS_OP_TXL, NVS_OP_TXP, - NVS_OP_UP2H, NVS_OP_UP2US, NVS_OP_UP4B, NVS_OP_UP4UB, - NVS_OP_X2D, NVS_OP_XPD, - NVS_OP_EMUL -} nvsOpcode; - -typedef enum { - NVS_PREC_FLOAT32, - NVS_PREC_FLOAT16, - NVS_PREC_FIXED12, - NVS_PREC_UNKNOWN -} nvsPrecision; - -typedef enum { - NVS_SWZ_X = 0, - NVS_SWZ_Y = 1, - NVS_SWZ_Z = 2, - NVS_SWZ_W = 3 -} nvsSwzComp; - -typedef enum { - NVS_FR_POSITION = 0, - NVS_FR_WEIGHT = 1, - NVS_FR_NORMAL = 2, - NVS_FR_COL0 = 3, - NVS_FR_COL1 = 4, - NVS_FR_FOGCOORD = 5, - NVS_FR_TEXCOORD0 = 8, - NVS_FR_TEXCOORD1 = 9, - NVS_FR_TEXCOORD2 = 10, - NVS_FR_TEXCOORD3 = 11, - NVS_FR_TEXCOORD4 = 12, - NVS_FR_TEXCOORD5 = 13, - NVS_FR_TEXCOORD6 = 14, - NVS_FR_TEXCOORD7 = 15, - NVS_FR_BFC0 = 16, - NVS_FR_BFC1 = 17, - NVS_FR_POINTSZ = 18, - NVS_FR_FRAGDATA0 = 19, - NVS_FR_FRAGDATA1 = 20, - NVS_FR_FRAGDATA2 = 21, - NVS_FR_FRAGDATA3 = 22, - NVS_FR_CLIP0 = 23, - NVS_FR_CLIP1 = 24, - NVS_FR_CLIP2 = 25, - NVS_FR_CLIP3 = 26, - NVS_FR_CLIP4 = 27, - NVS_FR_CLIP5 = 28, - NVS_FR_CLIP6 = 29, - NVS_FR_FACING = 30, - NVS_FR_UNKNOWN -} nvsFixedReg; - -typedef enum { - NVS_COND_FL, NVS_COND_LT, NVS_COND_EQ, NVS_COND_LE, NVS_COND_GT, - NVS_COND_NE, NVS_COND_GE, NVS_COND_TR, NVS_COND_UN, - NVS_COND_UNKNOWN -} nvsCond; - -typedef struct { - nvsRegFile file; - unsigned int index; - - unsigned int indexed; - unsigned int addr_reg; - nvsSwzComp addr_comp; - - nvsSwzComp swizzle[4]; - int negate; - int abs; -} nvsRegister; - -static const nvsRegister nvr_unused = { - .file = NVS_FILE_ATTRIB, - .index = 0, - .indexed = 0, - .addr_reg = 0, - .addr_comp = NVS_SWZ_X, - .swizzle = {NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W}, - .negate = 0, - .abs = 0, -}; - -typedef enum { - NVS_TEX_TARGET_1D, - NVS_TEX_TARGET_2D, - NVS_TEX_TARGET_3D, - NVS_TEX_TARGET_CUBE, - NVS_TEX_TARGET_RECT, - NVS_TEX_TARGET_UNKNOWN = 0 -} nvsTexTarget; - -typedef enum { - NVS_SCALE_1X = 0, - NVS_SCALE_2X = 1, - NVS_SCALE_4X = 2, - NVS_SCALE_8X = 3, - NVS_SCALE_INV_2X = 5, - NVS_SCALE_INV_4X = 6, - NVS_SCALE_INV_8X = 7, -} nvsScale; - -/* Arith/TEX instructions */ -typedef struct nvs_instruction { - nvsFragmentHeader header; - - nvsOpcode op; - unsigned int saturate; - - nvsRegister dest; - unsigned int mask; - nvsScale dest_scale; - - nvsRegister src[3]; - - unsigned int tex_unit; - nvsTexTarget tex_target; - - nvsCond cond; - nvsSwzComp cond_swizzle[4]; - int cond_reg; - int cond_test; - int cond_update; -} nvsInstruction; - -/* BRA, CAL, IF */ -typedef struct nvs_branch { - nvsFragmentHeader header; - - nvsOpcode op; - - nvsCond cond; - nvsSwzComp cond_swizzle[4]; - int cond_test; - - nvsFragmentHeader *target_head; - nvsFragmentHeader *target_tail; - nvsFragmentHeader *else_head; - nvsFragmentHeader *else_tail; -} nvsBranch; - -/* LOOP+ENDLOOP */ -typedef struct { - nvsFragmentHeader header; - - int count; - int initial; - int increment; - - nvsFragmentHeader *insn_head; - nvsFragmentHeader *insn_tail; -} nvsLoop; - -/* label+following instructions */ -typedef struct nvs_subroutine { - nvsFragmentHeader header; - - char * label; - nvsFragmentHeader *insn_head; - nvsFragmentHeader *insn_tail; -} nvsSubroutine; - -#define SMASK_X (1<<0) -#define SMASK_Y (1<<1) -#define SMASK_Z (1<<2) -#define SMASK_W (1<<3) -#define SMASK_ALL (SMASK_X|SMASK_Y|SMASK_Z|SMASK_W) - -#define SPOS_ADDRESS 3 -struct _op_xlat { - unsigned int NV; - nvsOpcode SOP; - int srcpos[3]; -}; -#define MOD_OPCODE(t,hw,sop,s0,s1,s2) do { \ - t[hw].NV = hw; \ - t[hw].SOP = sop; \ - t[hw].srcpos[0] = s0; \ - t[hw].srcpos[1] = s1; \ - t[hw].srcpos[2] = s2; \ -} while(0) - -extern unsigned int NVVP_TX_VOP_COUNT; -extern unsigned int NVVP_TX_NVS_OP_COUNT; -extern struct _op_xlat NVVP_TX_VOP[]; -extern struct _op_xlat NVVP_TX_SOP[]; - -extern unsigned int NVFP_TX_AOP_COUNT; -extern unsigned int NVFP_TX_BOP_COUNT; -extern struct _op_xlat NVFP_TX_AOP[]; -extern struct _op_xlat NVFP_TX_BOP[]; - -extern void NV20VPTXSwizzle(int hwswz, nvsSwzComp *swz); -extern nvsSwzComp NV20VP_TX_SWIZZLE[4]; - -#define SCAP_SRC_ABS (1<<0) - -struct _nvsFunc { - nvsCardPriv *card_priv; - - unsigned int MaxInst; - unsigned int MaxAttrib; - unsigned int MaxTemp; - unsigned int MaxAddress; - unsigned int MaxConst; - unsigned int caps; - - unsigned int *inst; - void (*UploadToHW) (GLcontext *, nouveauShader *); - void (*UpdateConst) (GLcontext *, nouveauShader *, int); - - struct _op_xlat*(*GetOPTXRec) (nvsFunc *, int merged); - struct _op_xlat*(*GetOPTXFromSOP) (nvsOpcode, int *id); - - void (*InitInstruction) (nvsFunc *); - int (*SupportsOpcode) (nvsFunc *, nvsOpcode); - int (*SupportsResultScale) (nvsFunc *, nvsScale); - void (*SetOpcode) (nvsFunc *, unsigned int opcode, - int slot); - void (*SetCCUpdate) (nvsFunc *); - void (*SetCondition) (nvsFunc *, int on, nvsCond, int reg, - nvsSwzComp *swizzle); - void (*SetResult) (nvsFunc *, nvsRegister *, - unsigned int mask, int slot); - void (*SetResultScale) (nvsFunc *, nvsScale); - void (*SetSource) (nvsFunc *, nvsRegister *, int pos); - void (*SetTexImageUnit) (nvsFunc *, int unit); - void (*SetSaturate) (nvsFunc *); - void (*SetLastInst) (nvsFunc *); - - void (*SetBranchTarget) (nvsFunc *, int addr); - void (*SetBranchElse) (nvsFunc *, int addr); - void (*SetBranchEnd) (nvsFunc *, int addr); - void (*SetLoopParams) (nvsFunc *, int cnt, int init, int inc); - - int (*HasMergedInst) (nvsFunc *); - int (*IsLastInst) (nvsFunc *); - int (*GetOffsetNext) (nvsFunc *); - - int (*GetOpcodeSlot) (nvsFunc *, int merged); - unsigned int (*GetOpcodeHW) (nvsFunc *, int slot); - nvsOpcode (*GetOpcode) (nvsFunc *, int merged); - - nvsPrecision (*GetPrecision) (nvsFunc *); - int (*GetSaturate) (nvsFunc *); - - nvsRegFile (*GetDestFile) (nvsFunc *, int merged); - unsigned int (*GetDestID) (nvsFunc *, int merged); - unsigned int (*GetDestMask) (nvsFunc *, int merged); - - unsigned int (*GetSourceHW) (nvsFunc *, int merged, int pos); - nvsRegFile (*GetSourceFile) (nvsFunc *, int merged, int pos); - int (*GetSourceID) (nvsFunc *, int merged, int pos); - int (*GetTexImageUnit) (nvsFunc *); - int (*GetSourceNegate) (nvsFunc *, int merged, int pos); - int (*GetSourceAbs) (nvsFunc *, int merged, int pos); - void (*GetSourceSwizzle) (nvsFunc *, int merged, int pos, - nvsSwzComp *swz); - int (*GetSourceIndexed) (nvsFunc *, int merged, int pos); - void (*GetSourceConstVal) (nvsFunc *, int merged, int pos, - float *val); - int (*GetSourceScale) (nvsFunc *, int merged, int pos); - - int (*GetRelAddressRegID) (nvsFunc *); - nvsSwzComp (*GetRelAddressSwizzle) (nvsFunc *); - - int (*SupportsConditional) (nvsFunc *); - int (*GetConditionUpdate) (nvsFunc *); - int (*GetConditionTest) (nvsFunc *); - nvsCond (*GetCondition) (nvsFunc *); - void (*GetCondRegSwizzle) (nvsFunc *, nvsSwzComp *swz); - int (*GetCondRegID) (nvsFunc *); - int (*GetBranch) (nvsFunc *); - int (*GetBranchElse) (nvsFunc *); - int (*GetBranchEnd) (nvsFunc *); - - int (*GetLoopCount) (nvsFunc *); - int (*GetLoopInitial) (nvsFunc *); - int (*GetLoopIncrement) (nvsFunc *); -}; - -static INLINE nvsRegister -nvsNegate(nvsRegister reg) -{ - reg.negate = !reg.negate; - return reg; -} - -static INLINE nvsRegister -nvsAbs(nvsRegister reg) -{ - reg.abs = 1; - return reg; -} - -static INLINE nvsRegister -nvsSwizzle(nvsRegister reg, nvsSwzComp x, nvsSwzComp y, - nvsSwzComp z, nvsSwzComp w) -{ - nvsSwzComp sc[4] = { x, y, z, w }; - nvsSwzComp oc[4]; - int i; - - for (i=0;i<4;i++) - oc[i] = reg.swizzle[i]; - for (i=0;i<4;i++) - reg.swizzle[i] = oc[sc[i]]; - return reg; -} - -#define nvsProgramError(nvs,fmt,args...) do { \ - fprintf(stderr, "nvsProgramError (%s): "fmt, __func__, ##args); \ - (nvs)->error = GL_TRUE; \ - (nvs)->translated = GL_FALSE; \ -} while(0) - -extern GLboolean nvsUpdateShader(GLcontext *ctx, nouveauShader *nvs); -extern void nvsDisasmHWShader(nvsPtr); -extern void nvsDumpFragmentList(nvsFragmentHeader *f, int lvl); -extern nouveauShader *nvsBuildTextShader(GLcontext *ctx, GLenum target, - const char *text); - -extern void NV20VPInitShaderFuncs(nvsFunc *); -extern void NV30VPInitShaderFuncs(nvsFunc *); -extern void NV40VPInitShaderFuncs(nvsFunc *); - -extern void NV30FPInitShaderFuncs(nvsFunc *); -extern void NV40FPInitShaderFuncs(nvsFunc *); - -extern void nouveauShaderInitFuncs(GLcontext *ctx); - -extern GLboolean nouveau_shader_pass0(GLcontext *ctx, nouveauShader *nvs); -extern GLboolean nouveau_shader_pass1(nvsPtr nvs); -extern GLboolean nouveau_shader_pass2(nvsPtr nvs); - -#endif - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c deleted file mode 100644 index 8c203cc664b..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c +++ /dev/null @@ -1,1050 +0,0 @@ -/* - * Copyright (C) 2006 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Ben Skeggs <[email protected]> - */ - -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "shader/prog_instruction.h" -#include "shader/prog_parameter.h" -#include "shader/prog_statevars.h" -#include "shader/programopt.h" - -#include "nouveau_context.h" -#include "nouveau_shader.h" -#include "nouveau_msg.h" - -static nvsFixedReg _tx_mesa_vp_dst_reg[VERT_RESULT_MAX] = { - NVS_FR_POSITION, NVS_FR_COL0, NVS_FR_COL1, NVS_FR_FOGCOORD, - NVS_FR_TEXCOORD0, NVS_FR_TEXCOORD1, NVS_FR_TEXCOORD2, NVS_FR_TEXCOORD3, - NVS_FR_TEXCOORD4, NVS_FR_TEXCOORD5, NVS_FR_TEXCOORD6, NVS_FR_TEXCOORD7, - NVS_FR_POINTSZ, NVS_FR_BFC0, NVS_FR_BFC1, NVS_FR_UNKNOWN /* EDGE */ -}; - -static nvsFixedReg _tx_mesa_fp_dst_reg[FRAG_RESULT_MAX] = { - NVS_FR_FRAGDATA0 /* COLR */, NVS_FR_FRAGDATA0 /* COLH */, - NVS_FR_UNKNOWN /* DEPR */ -}; - -static nvsFixedReg _tx_mesa_fp_src_reg[FRAG_ATTRIB_MAX] = { - NVS_FR_POSITION, NVS_FR_COL0, NVS_FR_COL1, NVS_FR_FOGCOORD, - NVS_FR_TEXCOORD0, NVS_FR_TEXCOORD1, NVS_FR_TEXCOORD2, NVS_FR_TEXCOORD3, - NVS_FR_TEXCOORD4, NVS_FR_TEXCOORD5, NVS_FR_TEXCOORD6, NVS_FR_TEXCOORD7 -}; - -static nvsSwzComp _tx_mesa_swizzle[4] = { - NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W -}; - -static nvsOpcode _tx_mesa_opcode[] = { - [OPCODE_ABS] = NVS_OP_ABS, [OPCODE_ADD] = NVS_OP_ADD, - [OPCODE_ARA] = NVS_OP_ARA, [OPCODE_ARL] = NVS_OP_ARL, - [OPCODE_ARL_NV] = NVS_OP_ARL, [OPCODE_ARR] = NVS_OP_ARR, - [OPCODE_CMP] = NVS_OP_CMP, [OPCODE_COS] = NVS_OP_COS, - [OPCODE_DDX] = NVS_OP_DDX, [OPCODE_DDY] = NVS_OP_DDY, - [OPCODE_DP3] = NVS_OP_DP3, [OPCODE_DP4] = NVS_OP_DP4, - [OPCODE_DPH] = NVS_OP_DPH, [OPCODE_DST] = NVS_OP_DST, - [OPCODE_EX2] = NVS_OP_EX2, [OPCODE_EXP] = NVS_OP_EXP, - [OPCODE_FLR] = NVS_OP_FLR, [OPCODE_FRC] = NVS_OP_FRC, - [OPCODE_KIL] = NVS_OP_EMUL, [OPCODE_KIL_NV] = NVS_OP_KIL, - [OPCODE_LG2] = NVS_OP_LG2, [OPCODE_LIT] = NVS_OP_LIT, - [OPCODE_LOG] = NVS_OP_LOG, - [OPCODE_LRP] = NVS_OP_LRP, - [OPCODE_MAD] = NVS_OP_MAD, [OPCODE_MAX] = NVS_OP_MAX, - [OPCODE_MIN] = NVS_OP_MIN, [OPCODE_MOV] = NVS_OP_MOV, - [OPCODE_MUL] = NVS_OP_MUL, - [OPCODE_PK2H] = NVS_OP_PK2H, [OPCODE_PK2US] = NVS_OP_PK2US, - [OPCODE_PK4B] = NVS_OP_PK4B, [OPCODE_PK4UB] = NVS_OP_PK4UB, - [OPCODE_POW] = NVS_OP_POW, [OPCODE_POPA] = NVS_OP_POPA, - [OPCODE_PUSHA] = NVS_OP_PUSHA, - [OPCODE_RCC] = NVS_OP_RCC, [OPCODE_RCP] = NVS_OP_RCP, - [OPCODE_RFL] = NVS_OP_RFL, [OPCODE_RSQ] = NVS_OP_RSQ, - [OPCODE_SCS] = NVS_OP_SCS, [OPCODE_SEQ] = NVS_OP_SEQ, - [OPCODE_SFL] = NVS_OP_SFL, [OPCODE_SGE] = NVS_OP_SGE, - [OPCODE_SGT] = NVS_OP_SGT, [OPCODE_SIN] = NVS_OP_SIN, - [OPCODE_SLE] = NVS_OP_SLE, [OPCODE_SLT] = NVS_OP_SLT, - [OPCODE_SNE] = NVS_OP_SNE, [OPCODE_SSG] = NVS_OP_SSG, - [OPCODE_STR] = NVS_OP_STR, [OPCODE_SUB] = NVS_OP_SUB, - [OPCODE_SWZ] = NVS_OP_MOV, - [OPCODE_TEX] = NVS_OP_TEX, [OPCODE_TXB] = NVS_OP_TXB, - [OPCODE_TXD] = NVS_OP_TXD, - [OPCODE_TXL] = NVS_OP_TXL, [OPCODE_TXP] = NVS_OP_TXP, - [OPCODE_TXP_NV] = NVS_OP_TXP, - [OPCODE_UP2H] = NVS_OP_UP2H, [OPCODE_UP2US] = NVS_OP_UP2US, - [OPCODE_UP4B] = NVS_OP_UP4B, [OPCODE_UP4UB] = NVS_OP_UP4UB, - [OPCODE_X2D] = NVS_OP_X2D, - [OPCODE_XPD] = NVS_OP_XPD -}; - -static nvsCond _tx_mesa_condmask[] = { - NVS_COND_TR, /* workaround mesa not filling a valid value */ - NVS_COND_GT, NVS_COND_LT, NVS_COND_UN, NVS_COND_GE, - NVS_COND_LE, NVS_COND_NE, NVS_COND_NE, NVS_COND_TR, NVS_COND_FL -}; - -struct pass0_rec { - int nvs_ipos; - int next_temp; - - int mesa_const_base; - int mesa_const_last; - - int swzconst_done; - int swzconst_id; - nvsRegister const_half; -}; - -#define X NVS_SWZ_X -#define Y NVS_SWZ_Y -#define Z NVS_SWZ_Z -#define W NVS_SWZ_W - -#define FILL_CONDITION_FLAGS(fragment) do { \ - (fragment)->cond = \ - pass0_make_condmask(inst->DstReg.CondMask); \ - if ((fragment)->cond != NVS_COND_TR) \ - (fragment)->cond_test = 1; \ - (fragment)->cond_reg = inst->CondDst; \ - pass0_make_swizzle((fragment)->cond_swizzle, inst->DstReg.CondSwizzle);\ -} while(0) - -#define ARITH(op,dest,mask,sat,s0,s1,s2) do { \ - nvsinst = pass0_emit(nvs, parent, fpos, (op), \ - (dest), (mask), (sat), (s0), (s1), (s2));\ - FILL_CONDITION_FLAGS(nvsinst); \ -} while(0) - -#define ARITHu(op,dest,mask,sat,s0,s1,s2) do { \ - nvsinst = pass0_emit(nvs, parent, fpos, (op), \ - (dest), (mask), (sat), (s0), (s1), (s2));\ -} while(0) - -static void -pass0_append_fragment(nvsFragmentHeader *parent, - nvsFragmentHeader *fragment, - int pos) -{ - nvsFragmentHeader **head, **tail; - assert(parent && fragment); - - switch (parent->type) { - case NVS_BRANCH: - if (pos == 0) { - head = &((nvsBranch *)parent)->target_head; - tail = &((nvsBranch *)parent)->target_tail; - } else { - head = &((nvsBranch *)parent)->else_head; - tail = &((nvsBranch *)parent)->else_tail; - } - break; - case NVS_LOOP: - head = &((nvsLoop *)parent)->insn_head; - tail = &((nvsLoop *)parent)->insn_tail; - break; - case NVS_SUBROUTINE: - head = &((nvsSubroutine *)parent)->insn_head; - tail = &((nvsSubroutine *)parent)->insn_tail; - break; - default: - assert(0); - break; - } - - fragment->parent = parent; - fragment->prev = *tail; - fragment->next = NULL; - if (!(*head)) - *head = fragment; - else - (*tail)->next = fragment; - *tail = fragment; - -} - -static nvsSubroutine * -pass0_create_subroutine(nouveauShader *nvs, const char *label) -{ - nvsSubroutine *sub; - - sub = CALLOC_STRUCT(nvs_subroutine); - if (sub) { - sub->header.type = NVS_SUBROUTINE; - sub->label = strdup(label); - if (!nvs->program_tree) - nvs->program_tree = &sub->header; - else - pass0_append_fragment(nvs->program_tree, - &sub->header, 0); - } - - return sub; -} - -static void -pass0_make_reg(nouveauShader *nvs, nvsRegister *reg, - nvsRegFile file, unsigned int index) -{ - struct pass0_rec *rec = nvs->pass_rec; - - /* defaults */ - *reg = nvr_unused; - /* -1 == quick-and-dirty temp alloc */ - if (file == NVS_FILE_TEMP && index == -1) { - index = rec->next_temp++; - assert(index < NVS_MAX_TEMPS); - } - reg->file = file; - reg->index = index; -} - -static void -pass0_make_swizzle(nvsSwzComp *swz, unsigned int mesa) -{ - int i; - - for (i=0;i<4;i++) - swz[i] = _tx_mesa_swizzle[GET_SWZ(mesa, i)]; -} - -static nvsOpcode -pass0_make_opcode(enum prog_opcode op) -{ - if (op > MAX_OPCODE) - return NVS_OP_UNKNOWN; - return _tx_mesa_opcode[op]; -} - -static nvsCond -pass0_make_condmask(GLuint mesa) -{ - if (mesa > COND_FL) - return NVS_COND_UNKNOWN; - return _tx_mesa_condmask[mesa]; -} - -static unsigned int -pass0_make_mask(GLuint mesa_mask) -{ - unsigned int mask = 0; - - if (mesa_mask & WRITEMASK_X) mask |= SMASK_X; - if (mesa_mask & WRITEMASK_Y) mask |= SMASK_Y; - if (mesa_mask & WRITEMASK_Z) mask |= SMASK_Z; - if (mesa_mask & WRITEMASK_W) mask |= SMASK_W; - - return mask; -} - -static GLboolean -pass0_opcode_is_tex(enum prog_opcode op) -{ - switch (op) { - case OPCODE_TEX: - case OPCODE_TXB: - case OPCODE_TXD: - case OPCODE_TXL: - case OPCODE_TXP: - return GL_TRUE; - default: - break; - } - - return GL_FALSE; -} - -static nvsTexTarget -pass0_make_tex_target(GLuint mesa) -{ - switch (mesa) { - case TEXTURE_1D_INDEX: return NVS_TEX_TARGET_1D; - case TEXTURE_2D_INDEX: return NVS_TEX_TARGET_2D; - case TEXTURE_3D_INDEX: return NVS_TEX_TARGET_3D; - case TEXTURE_CUBE_INDEX: return NVS_TEX_TARGET_CUBE; - case TEXTURE_RECT_INDEX: return NVS_TEX_TARGET_RECT; - default: - return NVS_TEX_TARGET_UNKNOWN; - } -} - -static void -pass0_make_dst_reg(nvsPtr nvs, nvsRegister *reg, - struct prog_dst_register *dst) -{ - struct gl_program *mesa = (struct gl_program*)&nvs->mesa.vp; - nvsFixedReg sfr; - - switch (dst->File) { - case PROGRAM_OUTPUT: - if (mesa->Target == GL_VERTEX_PROGRAM_ARB) { - sfr = (dst->Index < VERT_RESULT_MAX) ? - _tx_mesa_vp_dst_reg[dst->Index] : - NVS_FR_UNKNOWN; - } else { - sfr = (dst->Index < FRAG_RESULT_MAX) ? - _tx_mesa_fp_dst_reg[dst->Index] : - NVS_FR_UNKNOWN; - } - pass0_make_reg(nvs, reg, NVS_FILE_RESULT, sfr); - break; - case PROGRAM_TEMPORARY: - pass0_make_reg(nvs, reg, NVS_FILE_TEMP, dst->Index); - break; - case PROGRAM_ADDRESS: - pass0_make_reg(nvs, reg, NVS_FILE_ADDRESS, dst->Index); - break; - default: - fprintf(stderr, "Unknown dest file %d\n", dst->File); - assert(0); - } -} - -static void -pass0_make_src_reg(nvsPtr nvs, nvsRegister *reg, struct prog_src_register *src) -{ - struct pass0_rec *rec = nvs->pass_rec; - struct gl_program *mesa = (struct gl_program *)&nvs->mesa.vp.Base; - int i; - - *reg = nvr_unused; - - switch (src->File) { - case PROGRAM_INPUT: - reg->file = NVS_FILE_ATTRIB; - if (mesa->Target == GL_VERTEX_PROGRAM_ARB) { - for (i=0; i<NVS_MAX_ATTRIBS; i++) { - if (nvs->vp_attrib_map[i] == src->Index) { - reg->index = i; - break; - } - } - if (i==NVS_MAX_ATTRIBS) - reg->index = NVS_FR_UNKNOWN; - } else { - reg->index = (src->Index < FRAG_ATTRIB_MAX) ? - _tx_mesa_fp_src_reg[src->Index] : - NVS_FR_UNKNOWN; - } - break; - case PROGRAM_STATE_VAR: - case PROGRAM_NAMED_PARAM: - case PROGRAM_CONSTANT: - reg->file = NVS_FILE_CONST; - reg->index = src->Index + rec->mesa_const_base; - reg->indexed = src->RelAddr; - if (reg->indexed) { - reg->addr_reg = 0; - reg->addr_comp = NVS_SWZ_X; - } - break; - case PROGRAM_TEMPORARY: - reg->file = NVS_FILE_TEMP; - reg->index = src->Index; - break; - default: - fprintf(stderr, "Unknown source type %d\n", src->File); - assert(0); - } - - /* per-component negate handled elsewhere */ - reg->negate = src->NegateBase != 0; - reg->abs = src->Abs; - pass0_make_swizzle(reg->swizzle, src->Swizzle); -} - -static nvsInstruction * -pass0_emit(nouveauShader *nvs, nvsFragmentHeader *parent, int fpos, - nvsOpcode op, nvsRegister dst, - unsigned int mask, int saturate, - nvsRegister src0, nvsRegister src1, nvsRegister src2) -{ - nvsInstruction *sif; - - sif = CALLOC_STRUCT(nvs_instruction); - if (!sif) - return NULL; - - /* Seems mesa doesn't explicitly 0 this.. */ - if (nvs->mesa.vp.Base.Target == GL_VERTEX_PROGRAM_ARB) - saturate = 0; - - sif->op = op; - sif->saturate = saturate; - sif->dest = dst; - sif->mask = mask; - sif->dest_scale = NVS_SCALE_1X; - sif->src[0] = src0; - sif->src[1] = src1; - sif->src[2] = src2; - sif->cond = COND_TR; - sif->cond_reg = 0; - sif->cond_test = 0; - sif->cond_update= 0; - pass0_make_swizzle(sif->cond_swizzle, SWIZZLE_NOOP); - pass0_append_fragment(parent, &sif->header, fpos); - - return sif; -} - -static void -pass0_fixup_swizzle(nvsPtr nvs, nvsFragmentHeader *parent, int fpos, - struct prog_src_register *src, - unsigned int sm1, - unsigned int sm2) -{ - static const float sc[4] = { 1.0, 0.0, -1.0, 0.0 }; - struct pass0_rec *rec = nvs->pass_rec; - int fixup_1, fixup_2; - nvsInstruction *nvsinst; - nvsRegister sr, dr = nvr_unused; - nvsRegister sm1const, sm2const; - - if (!rec->swzconst_done) { - struct gl_program *prog = &nvs->mesa.vp.Base; - GLuint swizzle; - rec->swzconst_id = _mesa_add_unnamed_constant(prog->Parameters, - sc, 4, &swizzle); - /* XXX what about swizzle? */ - rec->swzconst_done = 1; - COPY_4V(nvs->params[rec->swzconst_id].val, sc); - } - - fixup_1 = (sm1 != MAKE_SWIZZLE4(0,0,0,0) && - sm2 != MAKE_SWIZZLE4(2,2,2,2)); - fixup_2 = (sm2 != MAKE_SWIZZLE4(2,2,2,2)); - - if (src->File != PROGRAM_TEMPORARY && src->File != PROGRAM_INPUT) { - /* We can't use more than one const in an instruction, - * so move the const into a temp, and swizzle from there. - * - * TODO: should just emit the swizzled const, instead of - * swizzling it in the shader.. would need to reswizzle - * any state params when they change however.. - */ - pass0_make_reg(nvs, &dr, NVS_FILE_TEMP, -1); - pass0_make_src_reg(nvs, &sr, src); - ARITHu(NVS_OP_MOV, dr, SMASK_ALL, 0, - sr, nvr_unused, nvr_unused); - pass0_make_reg(nvs, &sr, NVS_FILE_TEMP, dr.index); - } else { - if (fixup_1) - src->NegateBase = 0; - pass0_make_src_reg(nvs, &sr, src); - pass0_make_reg(nvs, &dr, NVS_FILE_TEMP, -1); - } - - pass0_make_reg(nvs, &sm1const, NVS_FILE_CONST, rec->swzconst_id); - pass0_make_swizzle(sm1const.swizzle, sm1); - if (fixup_1 && fixup_2) { - /* Any combination with SWIZZLE_ONE */ - pass0_make_reg(nvs, &sm2const, - NVS_FILE_CONST, rec->swzconst_id); - pass0_make_swizzle(sm2const.swizzle, sm2); - ARITHu(NVS_OP_MAD, dr, SMASK_ALL, 0, sr, sm1const, sm2const); - } else { - /* SWIZZLE_ZERO || arbitrary negate */ - ARITHu(NVS_OP_MUL, dr, SMASK_ALL, 0, sr, sm1const, nvr_unused); - } - - src->File = PROGRAM_TEMPORARY; - src->Index = dr.index; - src->Swizzle = SWIZZLE_NOOP; -} - -#define SET_SWZ(fs, cp, c) fs = (fs & ~(0x7<<(cp*3))) | (c<<(cp*3)) -static void -pass0_check_sources(nvsPtr nvs, nvsFragmentHeader *parent, int fpos, - struct prog_instruction *inst) -{ - unsigned int insrc = -1, constsrc = -1; - int i; - - for (i=0;i<_mesa_num_inst_src_regs(inst->Opcode);i++) { - struct prog_src_register *src = &inst->SrcReg[i]; - unsigned int sm_1 = 0, sm_2 = 0; - nvsRegister sr, dr; - int do_mov = 0, c; - - /* Build up swizzle masks as if we were going to use - * "MAD new, src, const1, const2" to support arbitrary negation - * and SWIZZLE_ZERO/SWIZZLE_ONE. - */ - for (c=0;c<4;c++) { - if (GET_SWZ(src->Swizzle, c) == SWIZZLE_ZERO) { - SET_SWZ(sm_1, c, SWIZZLE_Y); /* 0.0 */ - SET_SWZ(sm_2, c, SWIZZLE_Y); - SET_SWZ(src->Swizzle, c, SWIZZLE_X); - } else if (GET_SWZ(src->Swizzle, c) == SWIZZLE_ONE) { - SET_SWZ(sm_1, c, SWIZZLE_Y); - if (src->NegateBase & (1<<c)) - SET_SWZ(sm_2, c, SWIZZLE_Z); /* -1.0 */ - else - SET_SWZ(sm_2, c, SWIZZLE_X); /* 1.0 */ - SET_SWZ(src->Swizzle, c, SWIZZLE_X); - } else { - if (src->NegateBase & (1<<c)) - SET_SWZ(sm_1, c, SWIZZLE_Z); /* -[xyzw] */ - else - SET_SWZ(sm_1, c, SWIZZLE_X); /*[xyzw]*/ - SET_SWZ(sm_2, c, SWIZZLE_Y); - } - } - - /* Unless we're multiplying by 1.0 or -1.0 on all components, - * and we're adding nothing to any component we have to - * emulate the swizzle. - */ - if ((sm_1 != MAKE_SWIZZLE4(0,0,0,0) && - sm_1 != MAKE_SWIZZLE4(2,2,2,2)) || - sm_2 != MAKE_SWIZZLE4(1,1,1,1)) { - pass0_fixup_swizzle(nvs, parent, fpos, src, sm_1, sm_2); - /* The source is definitely in a temp now, so don't - * bother checking for multiple ATTRIB/CONST regs. - */ - continue; - } - - /* HW can't use more than one ATTRIB or PARAM in a single - * instruction */ - switch (src->File) { - case PROGRAM_INPUT: - if (insrc != -1 && insrc != src->Index) - do_mov = 1; - else insrc = src->Index; - break; - case PROGRAM_STATE_VAR: - if (constsrc != -1 && constsrc != src->Index) - do_mov = 1; - else constsrc = src->Index; - break; - default: - break; - } - - /* Emit any extra ATTRIB/CONST to a temp, and modify the Mesa - * instruction to point at the temp. - */ - if (do_mov) { - pass0_make_src_reg(nvs, &sr, src); - pass0_make_reg(nvs, &dr, NVS_FILE_TEMP, -1); - pass0_emit(nvs, parent, fpos, NVS_OP_MOV, - dr, SMASK_ALL, 0, - sr, nvr_unused, nvr_unused); - - src->File = PROGRAM_TEMPORARY; - src->Index = dr.index; - src->Swizzle= SWIZZLE_NOOP; - } - } -} - -static GLboolean -pass0_emulate_instruction(nouveauShader *nvs, - nvsFragmentHeader *parent, int fpos, - struct prog_instruction *inst) -{ - nvsFunc *shader = nvs->func; - nvsRegister src[3], dest, temp; - nvsInstruction *nvsinst; - unsigned int mask = pass0_make_mask(inst->DstReg.WriteMask); - int i, sat; - - sat = (inst->SaturateMode == SATURATE_ZERO_ONE); - - /* Build all the "real" regs for the instruction */ - for (i=0; i<_mesa_num_inst_src_regs(inst->Opcode); i++) - pass0_make_src_reg(nvs, &src[i], &inst->SrcReg[i]); - if (inst->Opcode != OPCODE_KIL) - pass0_make_dst_reg(nvs, &dest, &inst->DstReg); - - switch (inst->Opcode) { - case OPCODE_ABS: - if (shader->caps & SCAP_SRC_ABS) - ARITH(NVS_OP_MOV, dest, mask, sat, - nvsAbs(src[0]), nvr_unused, nvr_unused); - else - ARITH(NVS_OP_MAX, dest, mask, sat, - src[0], nvsNegate(src[0]), nvr_unused); - break; - case OPCODE_CMP: - /*XXX: this will clobber CC0... */ - ARITH (NVS_OP_MOV, dest, mask, sat, - src[2], nvr_unused, nvr_unused); - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - ARITHu(NVS_OP_MOV, temp, SMASK_ALL, 0, - src[0], nvr_unused, nvr_unused); - nvsinst->cond_update = 1; - nvsinst->cond_reg = 0; - ARITH (NVS_OP_MOV, dest, mask, sat, - src[1], nvr_unused, nvr_unused); - nvsinst->cond = COND_LT; - nvsinst->cond_reg = 0; - nvsinst->cond_test = 1; - break; - case OPCODE_DPH: - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - ARITHu(NVS_OP_DP3, temp, SMASK_X, 0, - src[0], src[1], nvr_unused); - ARITH (NVS_OP_ADD, dest, mask, sat, - nvsSwizzle(temp, X, X, X, X), - nvsSwizzle(src[1], W, W, W, W), - nvr_unused); - break; - case OPCODE_KIL: - /* This is only in ARB shaders, so we don't have to worry - * about clobbering a CC reg as they aren't supported anyway. - *XXX: might have to worry with GLSL however... - */ - /* MOVC0 temp, src */ - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - ARITHu(NVS_OP_MOV, temp, SMASK_ALL, 0, - src[0], nvr_unused, nvr_unused); - nvsinst->cond_update = 1; - nvsinst->cond_reg = 0; - /* KIL_NV (LT0.xyzw) temp */ - ARITHu(NVS_OP_KIL, nvr_unused, 0, 0, - nvr_unused, nvr_unused, nvr_unused); - nvsinst->cond = COND_LT; - nvsinst->cond_reg = 0; - nvsinst->cond_test = 1; - pass0_make_swizzle(nvsinst->cond_swizzle, SWIZZLE_NOOP); - break; - case OPCODE_LRP: - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - ARITHu(NVS_OP_MAD, temp, mask, 0, - nvsNegate(src[0]), src[2], src[2]); - ARITH (NVS_OP_MAD, dest, mask, sat, src[0], src[1], temp); - break; - case OPCODE_POW: - if (shader->SupportsOpcode(shader, NVS_OP_LG2) && - shader->SupportsOpcode(shader, NVS_OP_EX2)) { - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - /* LG2 temp.x, src0.c */ - ARITHu(NVS_OP_LG2, temp, SMASK_X, 0, - nvsSwizzle(src[0], X, X, X, X), - nvr_unused, nvr_unused); - /* MUL temp.x, temp.x, src1.c */ - ARITHu(NVS_OP_MUL, temp, SMASK_X, 0, - nvsSwizzle(temp, X, X, X, X), - nvsSwizzle(src[1], X, X, X, X), - nvr_unused); - /* EX2 dest, temp.x */ - ARITH (NVS_OP_EX2, dest, mask, sat, - nvsSwizzle(temp, X, X, X, X), - nvr_unused, nvr_unused); - } else { - /* can we use EXP/LOG instead of EX2/LG2?? */ - fprintf(stderr, "Implement POW for NV20 vtxprog!\n"); - return GL_FALSE; - } - break; - case OPCODE_RSQ: - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - ARITHu(NVS_OP_LG2, temp, SMASK_X, 0, - nvsAbs(nvsSwizzle(src[0], X, X, X, X)), - nvr_unused, nvr_unused); - nvsinst->dest_scale = NVS_SCALE_INV_2X; - ARITH (NVS_OP_EX2, dest, mask, sat, - nvsNegate(nvsSwizzle(temp, X, X, X, X)), - nvr_unused, nvr_unused); - break; - case OPCODE_SCS: - if (mask & SMASK_X) - ARITH(NVS_OP_COS, dest, SMASK_X, sat, - nvsSwizzle(src[0], X, X, X, X), - nvr_unused, nvr_unused); - if (mask & SMASK_Y) - ARITH(NVS_OP_SIN, dest, SMASK_Y, sat, - nvsSwizzle(src[0], X, X, X, X), - nvr_unused, nvr_unused); - break; - case OPCODE_SUB: - ARITH(NVS_OP_ADD, dest, mask, sat, - src[0], nvsNegate(src[1]), nvr_unused); - break; - case OPCODE_XPD: - pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1); - ARITHu(NVS_OP_MUL, temp, SMASK_ALL, 0, - nvsSwizzle(src[0], Z, X, Y, Y), - nvsSwizzle(src[1], Y, Z, X, X), - nvr_unused); - ARITH (NVS_OP_MAD, dest, (mask & ~SMASK_W), sat, - nvsSwizzle(src[0], Y, Z, X, X), - nvsSwizzle(src[1], Z, X, Y, Y), - nvsNegate(temp)); - break; - default: - WARN_ONCE("hw doesn't support opcode \"%s\"," - "and no emulation found\n", - _mesa_opcode_string(inst->Opcode)); - return GL_FALSE; - } - - return GL_TRUE; -} - -static GLboolean -pass0_translate_arith(nouveauShader *nvs, struct gl_program *prog, - int ipos, int fpos, - nvsFragmentHeader *parent) -{ - struct prog_instruction *inst = &prog->Instructions[ipos]; - nvsFunc *shader = nvs->func; - nvsInstruction *nvsinst; - GLboolean ret; - - /* Deal with multiple ATTRIB/PARAM in a single instruction */ - pass0_check_sources(nvs, parent, fpos, inst); - - /* Now it's safe to do the prog_instruction->nvsInstruction - * conversion - */ - if (shader->SupportsOpcode(shader, - pass0_make_opcode(inst->Opcode))) { - nvsRegister src[3], dest; - int i; - - for (i=0; i<_mesa_num_inst_src_regs(inst->Opcode); i++) - pass0_make_src_reg(nvs, &src[i], &inst->SrcReg[i]); - pass0_make_dst_reg(nvs, &dest, &inst->DstReg); - - ARITH(pass0_make_opcode(inst->Opcode), dest, - pass0_make_mask(inst->DstReg.WriteMask), - (inst->SaturateMode != SATURATE_OFF), - src[0], src[1], src[2]); - nvsinst->tex_unit = inst->TexSrcUnit; - if (pass0_opcode_is_tex(inst->Opcode)) - nvsinst->tex_target = - pass0_make_tex_target(inst->TexSrcTarget); - else - nvsinst->tex_target = NVS_TEX_TARGET_UNKNOWN; - - ret = GL_TRUE; - } else - ret = pass0_emulate_instruction(nvs, parent, fpos, inst); - - return ret; -} - -static GLboolean -pass0_translate_instructions(nouveauShader *nvs, int ipos, int fpos, - nvsFragmentHeader *parent) -{ - struct gl_program *prog = (struct gl_program *)&nvs->mesa.vp; - - while (1) { - struct prog_instruction *inst = &prog->Instructions[ipos]; - - switch (inst->Opcode) { - case OPCODE_END: - return GL_TRUE; - case OPCODE_BRA: - case OPCODE_CAL: - case OPCODE_RET: - //case OPCODE_LOOP: - //case OPCODE_ENDLOOP: - //case OPCODE_IF: - //case OPCODE_ELSE: - //case OPCODE_ENDIF: - WARN_ONCE("branch ops unimplemented\n"); - return GL_FALSE; - break; - default: - if (!pass0_translate_arith(nvs, prog, - ipos, fpos, parent)) - return GL_FALSE; - break; - } - - ipos++; - } - - return GL_TRUE; -} - -static void -pass0_build_attrib_map(nouveauShader *nvs, struct gl_vertex_program *vp) -{ - GLuint inputs_read = vp->Base.InputsRead; - GLuint input_alloc = ~0xFFFF; - int i; - - for (i=0; i<NVS_MAX_ATTRIBS; i++) - nvs->vp_attrib_map[i] = -1; - - while (inputs_read) { - int in = ffs(inputs_read) - 1; - int hw; - inputs_read &= ~(1<<in); - - if (vp->IsNVProgram) { - /* NVvp: must alias */ - if (in >= VERT_ATTRIB_GENERIC0) - hw = in - VERT_ATTRIB_GENERIC0; - else - hw = in; - } else { - /* ARBvp: may alias (but we won't) - * GL2.0: must not alias - */ - if (in >= VERT_ATTRIB_GENERIC0) - hw = ffs(~input_alloc) - 1; - else - hw = in; - input_alloc |= (1<<hw); - } - - nvs->vp_attrib_map[hw] = in; - } - - if (NOUVEAU_DEBUG & DEBUG_SHADERS) { - printf("vtxprog attrib map:\n"); - for (i=0; i<NVS_MAX_ATTRIBS; i++) { - printf(" hw:%d = attrib:%d\n", - i, nvs->vp_attrib_map[i]); - } - } -} - -static void -pass0_vp_insert_ff_clip_planes(GLcontext *ctx, nouveauShader *nvs) -{ - struct gl_program *prog = &nvs->mesa.vp.Base; - nvsFragmentHeader *parent = nvs->program_tree; - nvsInstruction *nvsinst; - GLuint fpos = 0; - nvsRegister opos, epos, eqn, mv[4]; - gl_state_index tokens[STATE_LENGTH] - = { STATE_MODELVIEW_MATRIX, 0, 0, 0, 0 }; - GLint id; - int i; - - /* modelview transform */ - pass0_make_reg(nvs, &opos, NVS_FILE_ATTRIB, NVS_FR_POSITION); - pass0_make_reg(nvs, &epos, NVS_FILE_TEMP , -1); - for (i=0; i<4; i++) { - tokens[2] = tokens[3] = i; - id = _mesa_add_state_reference(prog->Parameters, tokens); - pass0_make_reg(nvs, &mv[i], NVS_FILE_CONST, id); - } - ARITHu(NVS_OP_DP4, epos, SMASK_X, 0, opos, mv[0], nvr_unused); - ARITHu(NVS_OP_DP4, epos, SMASK_Y, 0, opos, mv[1], nvr_unused); - ARITHu(NVS_OP_DP4, epos, SMASK_Z, 0, opos, mv[2], nvr_unused); - ARITHu(NVS_OP_DP4, epos, SMASK_W, 0, opos, mv[3], nvr_unused); - - /* Emit code to emulate fixed-function glClipPlane */ - for (i=0; i<6; i++) { - GLuint clipmask = SMASK_X; - nvsRegister clip; - - if (!(ctx->Transform.ClipPlanesEnabled & (1<<i))) - continue; - - /* Point a const at a user clipping plane */ - tokens[0] = STATE_CLIPPLANE; - tokens[1] = i; - id = _mesa_add_state_reference(prog->Parameters, tokens); - pass0_make_reg(nvs, &eqn , NVS_FILE_CONST , id); - pass0_make_reg(nvs, &clip, NVS_FILE_RESULT, NVS_FR_CLIP0 + i); - - /*XXX: something else needs to take care of modifying the - * instructions to write to the correct hw clip register. - */ - switch (i) { - case 0: case 3: clipmask = SMASK_Y; break; - case 1: case 4: clipmask = SMASK_Z; break; - case 2: case 5: clipmask = SMASK_W; break; - } - - /* Emit transform */ - ARITHu(NVS_OP_DP4, clip, clipmask, 0, epos, eqn, nvr_unused); - } -} - -static void -pass0_rebase_mesa_consts(nouveauShader *nvs) -{ - struct pass0_rec *rec = nvs->pass_rec; - struct gl_program *prog = &nvs->mesa.vp.Base; - struct prog_instruction *inst = prog->Instructions; - int i; - - /*XXX: not a good idea, params->hw_index is malloc'd */ - memset(nvs->params, 0x00, sizeof(nvs->params)); - - /* When doing relative addressing on constants, the hardware needs us - * to fill the "const id" field with a positive value. Determine the - * most negative index that is used so that all accesses to a - * mesa-provided constant can be rebased to a positive index. - */ - while (inst->Opcode != OPCODE_END) { - for (i=0; i<_mesa_num_inst_src_regs(inst->Opcode); i++) { - struct prog_src_register *src = &inst->SrcReg[i]; - - switch (src->File) { - case PROGRAM_STATE_VAR: - case PROGRAM_CONSTANT: - case PROGRAM_NAMED_PARAM: - if (src->RelAddr && src->Index < 0) { - int base = src->Index * -1; - if (rec->mesa_const_base < base) - rec->mesa_const_base = base; - } - break; - default: - break; - } - } - - inst++; - } -} - -static GLboolean -pass0_resolve_mesa_consts(nouveauShader *nvs) -{ - struct pass0_rec *rec = nvs->pass_rec; - struct gl_program *prog = &nvs->mesa.vp.Base; - struct gl_program_parameter_list *plist = prog->Parameters; - int i; - - /* Init all const tracking/alloc info from the parameter list, rather - * than doing it as we translate the program. Otherwise: - * 1) we can't get at the correct constant info when relative - * addressing is being used due to src->Index not pointing - * at the exact const; - * 2) as we add extra consts to the program, mesa will call realloc() - * and we get invalid pointers to the const data. - */ - rec->mesa_const_last = plist->NumParameters + rec->mesa_const_base; - nvs->param_high = rec->mesa_const_last; - for (i=0; i<plist->NumParameters; i++) { - int hw = rec->mesa_const_base + i; - - if (hw > NVS_MAX_CONSTS) { - nvsProgramError(nvs, "hw = %d > NVS_MAX_CONSTS!\n", hw); - return GL_FALSE; - } - - switch (plist->Parameters[i].Type) { - case PROGRAM_NAMED_PARAM: - case PROGRAM_STATE_VAR: - nvs->params[hw].in_use = GL_TRUE; - nvs->params[hw].source_val = plist->ParameterValues[i]; - COPY_4V(nvs->params[hw].val, plist->ParameterValues[i]); - break; - case PROGRAM_CONSTANT: - nvs->params[hw].in_use = GL_TRUE; - nvs->params[hw].source_val = NULL; - COPY_4V(nvs->params[hw].val, plist->ParameterValues[i]); - break; - default: - nvsProgramError(nvs, "hit bad type=%d on param %d\n", - plist->Parameters[i].Type, i); - return GL_FALSE; - } - } - - return GL_TRUE; -} - -GLboolean -nouveau_shader_pass0(GLcontext *ctx, nouveauShader *nvs) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - struct gl_program *prog = (struct gl_program*)nvs; - struct gl_vertex_program *vp = (struct gl_vertex_program *)prog; - struct gl_fragment_program *fp = (struct gl_fragment_program *)prog; - struct pass0_rec *rec; - int ret = GL_FALSE; - - NVSDBG("start: nvs=%p\n", nvs); - - /* Previously detected an error, and haven't recieved new program - * string, so fail immediately. - */ - if (nvs->error) { - NVSDBG("failed previous compile attempt, not retrying\n"); - return GL_FALSE; - } - - rec = CALLOC_STRUCT(pass0_rec); - if (!rec) - return GL_FALSE; - - rec->next_temp = prog->NumTemporaries; - nvs->pass_rec = rec; - - nvs->program_tree = (nvsFragmentHeader*) - pass0_create_subroutine(nvs, "program body"); - if (!nvs->program_tree) { - FREE(rec); - return GL_FALSE; - } - - switch (prog->Target) { - case GL_VERTEX_PROGRAM_ARB: - nvs->func = &nmesa->VPfunc; - - if (vp->IsPositionInvariant) - _mesa_insert_mvp_code(ctx, vp); - pass0_rebase_mesa_consts(nvs); - - if (!prog->String && ctx->Transform.ClipPlanesEnabled) - pass0_vp_insert_ff_clip_planes(ctx, nvs); - - pass0_build_attrib_map(nvs, vp); - break; - case GL_FRAGMENT_PROGRAM_ARB: - nvs->func = &nmesa->FPfunc; - - if (fp->FogOption != GL_NONE) - _mesa_append_fog_code(ctx, fp); - pass0_rebase_mesa_consts(nvs); - break; - default: - fprintf(stderr, "Unknown program type %d", prog->Target); - FREE(rec); - /* DESTROY TREE!! */ - return GL_FALSE; - } - nvs->func->card_priv = &nvs->card_priv; - - ret = pass0_translate_instructions(nvs, 0, 0, nvs->program_tree); - if (ret) - ret = pass0_resolve_mesa_consts(nvs); - - /*XXX: if (!ret) DESTROY TREE!!! */ - - FREE(rec); - return ret; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_1.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_1.c deleted file mode 100644 index 78c1401f7db..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader_1.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "nouveau_context.h" -#include "nouveau_shader.h" - -GLboolean -nouveau_shader_pass1(nvsPtr nvs) -{ - NVSDBG("start: nvs=%p\n", nvs); - - return GL_TRUE; -} - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c deleted file mode 100644 index cd27daca88b..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (C) 2006 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/* - * Authors: - * Ben Skeggs <[email protected]> - */ - -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "shader/prog_parameter.h" -#include "shader/prog_print.h" - -#include "nouveau_context.h" -#include "nouveau_shader.h" -#include "nouveau_msg.h" - -struct pass2_rec { - /* Map nvsRegister temp ID onto hw temp ID */ - unsigned int temps[NVS_MAX_TEMPS]; - /* Track free hw registers */ - unsigned int hw_temps[NVS_MAX_TEMPS]; -}; - -static int -pass2_alloc_hw_temp(nvsPtr nvs) -{ - struct pass2_rec *rec = nvs->pass_rec; - int i; - - for (i=0; i<nvs->func->MaxTemp; i++) { - /* This is a *horrible* hack.. R0 is both temp0 and result.color - * in NV30/40 fragprogs, we can use R0 as a temp before result - * is written however.. - */ - if (nvs->mesa.vp.Base.Target == GL_FRAGMENT_PROGRAM_ARB && i==0) - continue; - if (rec->hw_temps[i] == 0) { - rec->hw_temps[i] = 1; - return i; - } - } - - return -1; -} - -static nvsRegister -pass2_mangle_reg(nvsPtr nvs, nvsInstruction *inst, nvsRegister reg) -{ - struct pass2_rec *rec = nvs->pass_rec; - - if (reg.file == NVS_FILE_TEMP) { - if (rec->temps[reg.index] == -1) - rec->temps[reg.index] = pass2_alloc_hw_temp(nvs); - reg.index = rec->temps[reg.index]; - } - - return reg; -} - -static void -pass2_add_instruction(nvsPtr nvs, nvsInstruction *inst, - struct _op_xlat *op, int slot) -{ - nvsSwzComp default_swz[4] = { NVS_SWZ_X, NVS_SWZ_Y, - NVS_SWZ_Z, NVS_SWZ_W }; - nvsFunc *shader = nvs->func; - nvsRegister reg; - int i; - - shader->SetOpcode(shader, op->NV, slot); - if (inst->saturate ) shader->SetSaturate(shader); - if (inst->cond_update ) shader->SetCCUpdate(shader); - if (inst->cond_test ) shader->SetCondition(shader, 1, inst->cond, - inst->cond_reg, - inst->cond_swizzle); - else shader->SetCondition(shader, 0, NVS_COND_TR, - 0, - default_swz); - switch (inst->op) { - case NVS_OP_TEX: - case NVS_OP_TXB: - case NVS_OP_TXL: - case NVS_OP_TXP: - case NVS_OP_TXD: - shader->SetTexImageUnit(shader, inst->tex_unit); - break; - default: - break; - } - - for (i = 0; i < 3; i++) { - if (op->srcpos[i] != -1) { - reg = pass2_mangle_reg(nvs, inst, inst->src[i]); - - shader->SetSource(shader, ®, op->srcpos[i]); - - if (reg.file == NVS_FILE_CONST && - shader->GetSourceConstVal) { - int idx_slot = - nvs->params[reg.index].hw_index_cnt++; - nvs->params[reg.index].hw_index = realloc( - nvs->params[reg.index].hw_index, - sizeof(int) * idx_slot+1); - nvs->params[reg.index].hw_index[idx_slot] = - nvs->program_current + 4; - } - } - } - - reg = pass2_mangle_reg(nvs, inst, inst->dest); - shader->SetResult(shader, ®, inst->mask, slot); - - if (inst->dest_scale != NVS_SCALE_1X) { - shader->SetResultScale(shader, inst->dest_scale); - } -} - -static int -pass2_assemble_instruction(nvsPtr nvs, nvsInstruction *inst, int last) -{ - nvsFunc *shader = nvs->func; - struct _op_xlat *op; - unsigned int hw_inst[8]; - int slot; - int instsz; - int i; - - shader->inst = hw_inst; - - /* Assemble this instruction */ - if (!(op = shader->GetOPTXFromSOP(inst->op, &slot))) - return 0; - shader->InitInstruction(shader); - pass2_add_instruction(nvs, inst, op, slot); - if (last) - shader->SetLastInst(shader); - - instsz = shader->GetOffsetNext(nvs->func); - if (nvs->program_size + instsz >= nvs->program_alloc_size) { - nvs->program_alloc_size *= 2; - nvs->program = realloc(nvs->program, - nvs->program_alloc_size * - sizeof(uint32_t)); - } - - for (i=0; i<instsz; i++) - nvs->program[nvs->program_current++] = hw_inst[i]; - nvs->program_size = nvs->program_current; - return 1; -} - -static GLboolean -pass2_translate(nvsPtr nvs, nvsFragmentHeader *f) -{ - nvsFunc *shader = nvs->func; - GLboolean last; - - while (f) { - last = (f == ((nvsSubroutine*)nvs->program_tree)->insn_tail); - - switch (f->type) { - case NVS_INSTRUCTION: - if (!pass2_assemble_instruction(nvs, - (nvsInstruction *)f, - last)) - return GL_FALSE; - break; - default: - WARN_ONCE("Unimplemented fragment type\n"); - return GL_FALSE; - } - - f = f->next; - } - - return GL_TRUE; -} - -/* Translate program into hardware format */ -GLboolean -nouveau_shader_pass2(nvsPtr nvs) -{ - struct pass2_rec *rec; - int i; - - NVSDBG("start: nvs=%p\n", nvs); - - rec = calloc(1, sizeof(struct pass2_rec)); - for (i=0; i<NVS_MAX_TEMPS; i++) - rec->temps[i] = -1; - nvs->pass_rec = rec; - - /* Start off with allocating 4 uint32_t's for each inst, will be grown - * if necessary.. - */ - nvs->program_alloc_size = nvs->mesa.vp.Base.NumInstructions * 4; - nvs->program = calloc(nvs->program_alloc_size, sizeof(uint32_t)); - nvs->program_size = 0; - nvs->program_current = 0; - - if (!pass2_translate(nvs, - ((nvsSubroutine*)nvs->program_tree)->insn_head)) { - free(nvs->program); - nvs->program = NULL; - return GL_FALSE; - } - - /* Shrink allocated memory to only what we need */ - nvs->program = realloc(nvs->program, - nvs->program_size * sizeof(uint32_t)); - nvs->program_alloc_size = nvs->program_size; - - nvs->translated = 1; - nvs->on_hardware = 0; - - if (NOUVEAU_DEBUG & DEBUG_SHADERS) { - fflush(stdout); fflush(stderr); - fprintf(stderr, "-----------MESA PROGRAM target=%s, id=0x%x\n", - _mesa_lookup_enum_by_nr( - nvs->mesa.vp.Base.Target), - nvs->mesa.vp.Base.Id); - fflush(stdout); fflush(stderr); - _mesa_print_program(&nvs->mesa.vp.Base); - fflush(stdout); fflush(stderr); - fprintf(stderr, "^^^^^^^^^^^^^^^^MESA PROGRAM\n"); - fflush(stdout); fflush(stderr); - fprintf(stderr, "----------------NV PROGRAM\n"); - fflush(stdout); fflush(stderr); - nvsDisasmHWShader(nvs); - fflush(stdout); fflush(stderr); - fprintf(stderr, "^^^^^^^^^^^^^^^^NV PROGRAM\n"); - fflush(stdout); fflush(stderr); - } - - return GL_TRUE; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_span.c b/src/mesa/drivers/dri/nouveau/nouveau_span.c deleted file mode 100644 index d62830ff53e..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_span.c +++ /dev/null @@ -1,123 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#include "nouveau_context.h" -#include "nouveau_span.h" -#include "nouveau_fifo.h" -#include "nouveau_lock.h" - -#include "swrast/swrast.h" - -#define HAVE_HW_DEPTH_SPANS 0 -#define HAVE_HW_DEPTH_PIXELS 0 -#define HAVE_HW_STENCIL_SPANS 0 -#define HAVE_HW_STENCIL_PIXELS 0 - -#define HW_CLIPLOOP() \ - do { \ - int _nc = nmesa->numClipRects; \ - while ( _nc-- ) { \ - int minx = nmesa->pClipRects[_nc].x1 - nmesa->drawX; \ - int miny = nmesa->pClipRects[_nc].y1 - nmesa->drawY; \ - int maxx = nmesa->pClipRects[_nc].x2 - nmesa->drawX; \ - int maxy = nmesa->pClipRects[_nc].y2 - nmesa->drawY; - -#define LOCAL_VARS \ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); \ - nouveau_renderbuffer_t *nrb = (nouveau_renderbuffer_t *)rb; \ - GLuint height = nrb->mesa.Height; \ - GLubyte *map = (GLubyte *)(nrb->map ? nrb->map : nrb->mem->map) + \ - (nmesa->drawY * nrb->pitch) + (nmesa->drawX * nrb->cpp); \ - GLuint p; \ - (void) p; - -#define Y_FLIP( _y ) (height - _y - 1) - -#define HW_LOCK() - -#define HW_UNLOCK() - - - -/* ================================================================ - * Color buffers - */ - -/* RGB565 */ -#define SPANTMP_PIXEL_FMT GL_RGB -#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 - -#define TAG(x) nouveau##x##_RGB565 -#define TAG2(x,y) nouveau##x##_RGB565##y -#define GET_PTR(X,Y) (map + (Y)*nrb->pitch + (X)*nrb->cpp) -#include "spantmp2.h" - - -/* ARGB8888 */ -#define SPANTMP_PIXEL_FMT GL_BGRA -#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV - -#define TAG(x) nouveau##x##_ARGB8888 -#define TAG2(x,y) nouveau##x##_ARGB8888##y -#define GET_PTR(X,Y) (map + (Y)*nrb->pitch + (X)*nrb->cpp) -#include "spantmp2.h" - -static void nouveauSpanRenderStart(GLcontext * ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - FIRE_RING(); - LOCK_HARDWARE(nmesa); - nouveauWaitForIdleLocked(nmesa); -} - -static void nouveauSpanRenderFinish(GLcontext * ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - _swrast_flush(ctx); - nouveauWaitForIdleLocked(nmesa); - UNLOCK_HARDWARE(nmesa); -} - -void nouveauSpanInitFunctions(GLcontext * ctx) -{ - struct swrast_device_driver *swdd = - _swrast_GetDeviceDriverReference(ctx); - swdd->SpanRenderStart = nouveauSpanRenderStart; - swdd->SpanRenderFinish = nouveauSpanRenderFinish; -} - - -/** - * Plug in the Get/Put routines for the given driRenderbuffer. - */ -void nouveauSpanSetFunctions(nouveau_renderbuffer_t * nrb) -{ - if (nrb->mesa._ActualFormat == GL_RGBA8) - nouveauInitPointers_ARGB8888(&nrb->mesa); - else // if (nrb->mesa._ActualFormat == GL_RGB5) - nouveauInitPointers_RGB565(&nrb->mesa); -} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_span.h b/src/mesa/drivers/dri/nouveau/nouveau_span.h deleted file mode 100644 index d3f31c9cb23..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_span.h +++ /dev/null @@ -1,39 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - -#ifndef __NOUVEAU_SPAN_H__ -#define __NOUVEAU_SPAN_H__ - -#include "drirenderbuffer.h" -#include "nouveau_fbo.h" - -extern void nouveauSpanInitFunctions(GLcontext *ctx); -extern void nouveauSpanSetFunctions(nouveau_renderbuffer_t *nrb); - -#endif /* __NOUVEAU_SPAN_H__ */ - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state.c b/src/mesa/drivers/dri/nouveau/nouveau_state.c deleted file mode 100644 index 1eb6069e34c..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_state.c +++ /dev/null @@ -1,368 +0,0 @@ -/************************************************************************** - -Copyright 2006 Jeremy Kolb -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -#include "nouveau_state.h" -#include "nouveau_swtcl.h" -#include "nouveau_fifo.h" - -#include "swrast/swrast.h" -#include "tnl/tnl.h" -#include "swrast_setup/swrast_setup.h" - -#include "tnl/t_pipeline.h" - -#include "mtypes.h" -#include "colormac.h" - -static INLINE GLuint nouveauPackColor(GLuint format, - GLubyte r, GLubyte g, - GLubyte b, GLubyte a) -{ - switch (format) { - case 2: - return PACK_COLOR_565( r, g, b ); - case 4: - return PACK_COLOR_8888( r, g, b, a); - default: - fprintf(stderr, "unknown format %d\n", (int)format); - return 0; - } -} - -static void nouveauCalcViewport(GLcontext *ctx) -{ - /* Calculate the Viewport Matrix */ - - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - const GLfloat *v = ctx->Viewport._WindowMap.m; - GLfloat *m = nmesa->viewport.m; - GLfloat xoffset = nmesa->drawX, yoffset = nmesa->drawY + nmesa->drawH; - - nmesa->depth_scale = 1.0 / ctx->DrawBuffer->_DepthMaxF; - - m[MAT_SX] = v[MAT_SX]; - m[MAT_TX] = v[MAT_TX] + xoffset + SUBPIXEL_X; - m[MAT_SY] = - v[MAT_SY]; - m[MAT_TY] = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; - m[MAT_SZ] = v[MAT_SZ] * nmesa->depth_scale; - m[MAT_TZ] = v[MAT_TZ] * nmesa->depth_scale; - - nmesa->hw_func.WindowMoved(nmesa); -} - -static void nouveauViewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - /* - * Need to send (at least on an nv35 the following: - * cons = 4 (this may be bytes per pixel) - * - * The viewport: - * 445 0x0000bee0 {size: 0x0 channel: 0x1 cmd: 0x00009ee0} <-- VIEWPORT_SETUP/HEADER ? - * 446 0x00000000 {size: 0x0 channel: 0x0 cmd: 0x00000000} <-- x * cons - * 447 0x00000c80 {size: 0x0 channel: 0x0 cmd: 0x00000c80} <-- (height + x) * cons - * 448 0x00000000 {size: 0x0 channel: 0x0 cmd: 0x00000000} <-- y * cons - * 449 0x00000960 {size: 0x0 channel: 0x0 cmd: 0x00000960} <-- (width + y) * cons - * 44a 0x00082a00 {size: 0x2 channel: 0x1 cmd: 0x00000a00} <-- VIEWPORT_DIMS - * 44b 0x04000000 <-- (Width_from_glViewport << 16) | x - * 44c 0x03000000 <-- (Height_from_glViewport << 16) | (win_height - height - y) - * - */ - - nouveauCalcViewport(ctx); -} - -static void nouveauDepthRange(GLcontext *ctx, GLclampd near, GLclampd far) -{ - nouveauCalcViewport(ctx); -} - -static void nouveauUpdateProjectionMatrix(GLcontext *ctx) -{ -} - -static void nouveauUpdateModelviewMatrix(GLcontext *ctx) -{ -} - -static void nouveauDDUpdateHWState(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - int new_state = nmesa->new_state; - - if ( new_state || nmesa->new_render_state & _NEW_TEXTURE ) - { - nmesa->new_state = 0; - - /* Update the various parts of the context's state. - */ - /* - if ( new_state & NOUVEAU_NEW_ALPHA ) - nouveauUpdateAlphaMode( ctx ); - - if ( new_state & NOUVEAU_NEW_DEPTH ) - nouveauUpdateZMode( ctx ); - - if ( new_state & NOUVEAU_NEW_FOG ) - nouveauUpdateFogAttrib( ctx ); - - if ( new_state & NOUVEAU_NEW_CLIP ) - nouveauUpdateClipping( ctx ); - - if ( new_state & NOUVEAU_NEW_CULL ) - nouveauUpdateCull( ctx ); - - if ( new_state & NOUVEAU_NEW_MASKS ) - nouveauUpdateMasks( ctx ); - - if ( new_state & NOUVEAU_NEW_WINDOW ) - nouveauUpdateWindow( ctx ); - - if ( nmesa->new_render_state & _NEW_TEXTURE ) { - nouveauUpdateTextureState( ctx ); - }*/ - } -} - -static void nouveauDDInvalidateState(GLcontext *ctx, GLuint new_state) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if ( new_state & _NEW_PROJECTION ) { - nmesa->hw_func.UpdateProjectionMatrix(ctx); - } - if ( new_state & _NEW_MODELVIEW ) { - nmesa->hw_func.UpdateModelviewMatrix(ctx); - } - - _swrast_InvalidateState( ctx, new_state ); - _swsetup_InvalidateState( ctx, new_state ); - _vbo_InvalidateState( ctx, new_state ); - _tnl_InvalidateState( ctx, new_state ); - NOUVEAU_CONTEXT(ctx)->new_render_state |= new_state; -} - -/* Initialize the context's hardware state. */ -void nouveauDDInitState(nouveauContextPtr nmesa) -{ - uint32_t type = nmesa->screen->card->type; - switch(type) - { - case NV_04: - case NV_05: - nv04InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver); - break; - case NV_10: - case NV_11: - case NV_17: - nv10InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver); - break; - case NV_20: - nv20InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver); - break; - case NV_30: - case NV_40: - case NV_44: - nv30InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver); - break; - case NV_50: - nv50InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver); - break; - default: - break; - } - nouveau_state_cache_init(nmesa); -} - -/* Initialize the driver's state functions */ -void nouveauDDInitStateFuncs(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - ctx->Driver.UpdateState = nouveauDDInvalidateState; - - ctx->Driver.ClearIndex = NULL; - ctx->Driver.ClearColor = NULL; //nouveauDDClearColor; - ctx->Driver.ClearStencil = NULL; //nouveauDDClearStencil; - ctx->Driver.DrawBuffer = NULL; //nouveauDDDrawBuffer; - ctx->Driver.ReadBuffer = NULL; //nouveauDDReadBuffer; - - ctx->Driver.IndexMask = NULL; - ctx->Driver.ColorMask = NULL; //nouveauDDColorMask; - ctx->Driver.AlphaFunc = NULL; //nouveauDDAlphaFunc; - ctx->Driver.BlendEquationSeparate = NULL; //nouveauDDBlendEquationSeparate; - ctx->Driver.BlendFuncSeparate = NULL; //nouveauDDBlendFuncSeparate; - ctx->Driver.ClearDepth = NULL; //nouveauDDClearDepth; - ctx->Driver.CullFace = NULL; //nouveauDDCullFace; - ctx->Driver.FrontFace = NULL; //nouveauDDFrontFace; - ctx->Driver.DepthFunc = NULL; //nouveauDDDepthFunc; - ctx->Driver.DepthMask = NULL; //nouveauDDDepthMask; - ctx->Driver.Enable = NULL; //nouveauDDEnable; - ctx->Driver.Fogfv = NULL; //nouveauDDFogfv; - ctx->Driver.Hint = NULL; - ctx->Driver.Lightfv = NULL; - ctx->Driver.LightModelfv = NULL; //nouveauDDLightModelfv; - ctx->Driver.LogicOpcode = NULL; //nouveauDDLogicOpCode; - ctx->Driver.PolygonMode = NULL; - ctx->Driver.PolygonStipple = NULL; //nouveauDDPolygonStipple; - ctx->Driver.RenderMode = NULL; //nouveauDDRenderMode; - ctx->Driver.Scissor = NULL; //nouveauDDScissor; - ctx->Driver.ShadeModel = NULL; //nouveauDDShadeModel; - ctx->Driver.StencilFuncSeparate = NULL; //nouveauDDStencilFuncSeparate; - ctx->Driver.StencilMaskSeparate = NULL; //nouveauDDStencilMaskSeparate; - ctx->Driver.StencilOpSeparate = NULL; //nouveauDDStencilOpSeparate; - - ctx->Driver.DepthRange = nouveauDepthRange; - ctx->Driver.Viewport = nouveauViewport; - - /* Pixel path fallbacks. - */ - ctx->Driver.Accum = _swrast_Accum; - ctx->Driver.Bitmap = _swrast_Bitmap; - ctx->Driver.CopyPixels = _swrast_CopyPixels; - ctx->Driver.DrawPixels = _swrast_DrawPixels; - ctx->Driver.ReadPixels = _swrast_ReadPixels; - - /* Swrast hooks for imaging extensions: - */ - ctx->Driver.CopyColorTable = _swrast_CopyColorTable; - ctx->Driver.CopyColorSubTable = _swrast_CopyColorSubTable; - ctx->Driver.CopyConvolutionFilter1D = _swrast_CopyConvolutionFilter1D; - ctx->Driver.CopyConvolutionFilter2D = _swrast_CopyConvolutionFilter2D; - - /* Matrix updates */ - nmesa->hw_func.UpdateProjectionMatrix = nouveauUpdateProjectionMatrix; - nmesa->hw_func.UpdateModelviewMatrix = nouveauUpdateModelviewMatrix; -} - -#define STATE_INIT(a) if (ctx->Driver.a) ctx->Driver.a - -void nouveauInitState(GLcontext *ctx) -{ - /* - * Mesa should do this for us: - */ - - STATE_INIT(AlphaFunc)( ctx, - ctx->Color.AlphaFunc, - ctx->Color.AlphaRef); - - STATE_INIT(BlendColor)( ctx, - ctx->Color.BlendColor ); - - STATE_INIT(BlendEquationSeparate)( ctx, - ctx->Color.BlendEquationRGB, - ctx->Color.BlendEquationA); - - STATE_INIT(BlendFuncSeparate)( ctx, - ctx->Color.BlendSrcRGB, - ctx->Color.BlendDstRGB, - ctx->Color.BlendSrcA, - ctx->Color.BlendDstA); - - STATE_INIT(ClearColor)( ctx, ctx->Color.ClearColor); - STATE_INIT(ClearDepth)( ctx, ctx->Depth.Clear); - STATE_INIT(ClearStencil)( ctx, ctx->Stencil.Clear); - - STATE_INIT(ColorMask)( ctx, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); - - STATE_INIT(CullFace)( ctx, ctx->Polygon.CullFaceMode ); - STATE_INIT(DepthFunc)( ctx, ctx->Depth.Func ); - STATE_INIT(DepthMask)( ctx, ctx->Depth.Mask ); - STATE_INIT(DepthRange)( ctx, ctx->Viewport.Near, ctx->Viewport.Far ); - - STATE_INIT(Enable)( ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled ); - STATE_INIT(Enable)( ctx, GL_BLEND, ctx->Color.BlendEnabled ); - STATE_INIT(Enable)( ctx, GL_COLOR_LOGIC_OP, ctx->Color.ColorLogicOpEnabled ); - STATE_INIT(Enable)( ctx, GL_COLOR_SUM, ctx->Fog.ColorSumEnabled ); - STATE_INIT(Enable)( ctx, GL_CULL_FACE, ctx->Polygon.CullFlag ); - STATE_INIT(Enable)( ctx, GL_DEPTH_TEST, ctx->Depth.Test ); - STATE_INIT(Enable)( ctx, GL_DITHER, ctx->Color.DitherFlag ); - STATE_INIT(Enable)( ctx, GL_FOG, ctx->Fog.Enabled ); - STATE_INIT(Enable)( ctx, GL_LIGHTING, ctx->Light.Enabled ); - STATE_INIT(Enable)( ctx, GL_LINE_SMOOTH, ctx->Line.SmoothFlag ); - STATE_INIT(Enable)( ctx, GL_LINE_STIPPLE, ctx->Line.StippleFlag ); - STATE_INIT(Enable)( ctx, GL_POINT_SMOOTH, ctx->Point.SmoothFlag ); - STATE_INIT(Enable)( ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill); - STATE_INIT(Enable)( ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine); - STATE_INIT(Enable)( ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint); - STATE_INIT(Enable)( ctx, GL_POLYGON_SMOOTH, ctx->Polygon.SmoothFlag ); - STATE_INIT(Enable)( ctx, GL_POLYGON_STIPPLE, ctx->Polygon.StippleFlag ); - STATE_INIT(Enable)( ctx, GL_SCISSOR_TEST, ctx->Scissor.Enabled ); - STATE_INIT(Enable)( ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled ); - STATE_INIT(Enable)( ctx, GL_TEXTURE_1D, GL_FALSE ); - STATE_INIT(Enable)( ctx, GL_TEXTURE_2D, GL_FALSE ); - STATE_INIT(Enable)( ctx, GL_TEXTURE_RECTANGLE_NV, GL_FALSE ); - STATE_INIT(Enable)( ctx, GL_TEXTURE_3D, GL_FALSE ); - STATE_INIT(Enable)( ctx, GL_TEXTURE_CUBE_MAP, GL_FALSE ); - - STATE_INIT(Fogfv)( ctx, GL_FOG_COLOR, ctx->Fog.Color ); - STATE_INIT(Fogfv)( ctx, GL_FOG_MODE, 0 ); - STATE_INIT(Fogfv)( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); - STATE_INIT(Fogfv)( ctx, GL_FOG_START, &ctx->Fog.Start ); - STATE_INIT(Fogfv)( ctx, GL_FOG_END, &ctx->Fog.End ); - - STATE_INIT(FrontFace)( ctx, ctx->Polygon.FrontFace ); - - { - GLfloat f = (GLfloat)ctx->Light.Model.ColorControl; - STATE_INIT(LightModelfv)( ctx, GL_LIGHT_MODEL_COLOR_CONTROL, &f ); - } - - STATE_INIT(LineStipple)( ctx, ctx->Line.StippleFactor, ctx->Line.StipplePattern ); - STATE_INIT(LineWidth)( ctx, ctx->Line.Width ); - STATE_INIT(LogicOpcode)( ctx, ctx->Color.LogicOp ); - STATE_INIT(PointSize)( ctx, ctx->Point.Size ); - STATE_INIT(PolygonMode)( ctx, GL_FRONT, ctx->Polygon.FrontMode ); - STATE_INIT(PolygonMode)( ctx, GL_BACK, ctx->Polygon.BackMode ); - STATE_INIT(PolygonOffset)( ctx, - ctx->Polygon.OffsetFactor, - ctx->Polygon.OffsetUnits ); - STATE_INIT(PolygonStipple)( ctx, (const GLubyte *)ctx->PolygonStipple ); - STATE_INIT(ShadeModel)( ctx, ctx->Light.ShadeModel ); - STATE_INIT(StencilFuncSeparate)( ctx, GL_FRONT, - ctx->Stencil.Function[0], - ctx->Stencil.Ref[0], - ctx->Stencil.ValueMask[0] ); - STATE_INIT(StencilFuncSeparate)( ctx, GL_BACK, - ctx->Stencil.Function[1], - ctx->Stencil.Ref[1], - ctx->Stencil.ValueMask[1] ); - STATE_INIT(StencilMaskSeparate)( ctx, GL_FRONT, ctx->Stencil.WriteMask[0] ); - STATE_INIT(StencilMaskSeparate)( ctx, GL_BACK, ctx->Stencil.WriteMask[1] ); - STATE_INIT(StencilOpSeparate)( ctx, GL_FRONT, - ctx->Stencil.FailFunc[0], - ctx->Stencil.ZFailFunc[0], - ctx->Stencil.ZPassFunc[0]); - STATE_INIT(StencilOpSeparate)( ctx, GL_BACK, - ctx->Stencil.FailFunc[1], - ctx->Stencil.ZFailFunc[1], - ctx->Stencil.ZPassFunc[1]); -} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state.h b/src/mesa/drivers/dri/nouveau/nouveau_state.h deleted file mode 100644 index dbac71760b6..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_state.h +++ /dev/null @@ -1,50 +0,0 @@ -/************************************************************************** - -Copyright 2006 Jeremy Kolb -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#ifndef __NOUVEAU_STATE_H__ -#define __NOUVEAU_STATE_H__ - -#include "nouveau_context.h" - -extern void nouveauDDInitState(nouveauContextPtr nmesa); -extern void nouveauDDInitStateFuncs(GLcontext *ctx); - -extern void nv04InitStateFuncs(GLcontext *ctx, struct dd_function_table *func); -extern void nv10InitStateFuncs(GLcontext *ctx, struct dd_function_table *func); -extern void nv20InitStateFuncs(GLcontext *ctx, struct dd_function_table *func); -extern void nv30InitStateFuncs(GLcontext *ctx, struct dd_function_table *func); -extern void nv50InitStateFuncs(GLcontext *ctx, struct dd_function_table *func); - -extern void nouveauInitState(GLcontext *ctx); - -/* -extern void nouveauDDUpdateState(GLcontext *ctx); -extern void nouveauDDUpdateHWState(GLcontext *ctx); - -extern void nouveauEmitHwStateLocked(nouveauContextPtr nmesa); -*/ -#endif - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.c b/src/mesa/drivers/dri/nouveau/nouveau_state_cache.c deleted file mode 100644 index cb4b9d30270..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.c +++ /dev/null @@ -1,69 +0,0 @@ - -#include "nouveau_state_cache.h" -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" - -#define BEGIN_RING_NOFLUSH(subchannel,tag,size) do { \ - if (nmesa->fifo.free <= (size)) \ - WAIT_RING(nmesa,(size)); \ - OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \ - nmesa->fifo.free -= ((size) + 1); \ -}while(0) - -// flush all the dirty state -void nouveau_state_cache_flush(nouveauContextPtr nmesa) -{ - int i=0; - int run=0; - - // fast-path no state changes - if (!nmesa->state_cache.dirty) - return; - nmesa->state_cache.dirty=0; - - do - { - // jump to a dirty state - while((nmesa->state_cache.hdirty[i/NOUVEAU_STATE_CACHE_HIER_SIZE]==0)&&(i<NOUVEAU_STATE_CACHE_ENTRIES)) - i=(i&~(NOUVEAU_STATE_CACHE_HIER_SIZE-1))+NOUVEAU_STATE_CACHE_HIER_SIZE; - while((nmesa->state_cache.atoms[i].dirty==0)&&(i<NOUVEAU_STATE_CACHE_ENTRIES)) - i++; - - // figure out a run of dirty values - run=0; - while((nmesa->state_cache.atoms[i+run].dirty)&&(i+run<NOUVEAU_STATE_CACHE_ENTRIES)) - run++; - - // output everything as a single run - if (run>0) { - int j; - - BEGIN_RING_NOFLUSH(NvSub3D, i*4, run); - for(j=0;j<run;j++) - { - OUT_RING(nmesa->state_cache.atoms[i+j].value); - nmesa->state_cache.atoms[i+j].dirty=0; - if ((i+j)%NOUVEAU_STATE_CACHE_HIER_SIZE==0) - nmesa->state_cache.hdirty[(i+j)/NOUVEAU_STATE_CACHE_HIER_SIZE-1]=0; - } - i+=run; - } - } - while(i<NOUVEAU_STATE_CACHE_ENTRIES); - nmesa->state_cache.hdirty[NOUVEAU_STATE_CACHE_HIER_SIZE/NOUVEAU_STATE_CACHE_HIER_SIZE-1]=0; -} - - -// inits the state cache -void nouveau_state_cache_init(nouveauContextPtr nmesa) -{ - int i; - for(i=0;i<NOUVEAU_STATE_CACHE_ENTRIES;i++) - { - nmesa->state_cache.atoms[i].dirty=0; - nmesa->state_cache.atoms[i].value=0xDEADBEEF; // nvidia cards like beef - } - nmesa->state_cache.dirty=0; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.h b/src/mesa/drivers/dri/nouveau/nouveau_state_cache.h deleted file mode 100644 index 5f9d426450b..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.h +++ /dev/null @@ -1,29 +0,0 @@ - -#ifndef __NOUVEAU_STATE_CACHE_H__ -#define __NOUVEAU_STATE_CACHE_H__ - -#include "mtypes.h" - -#define NOUVEAU_STATE_CACHE_ENTRIES 2048 -// size of a dirty requests block -// you can play with that and tune the value to increase/decrease performance -// but keep it a power of 2 ! -#define NOUVEAU_STATE_CACHE_HIER_SIZE 32 - -typedef struct nouveau_state_atom_t{ - uint32_t value; - uint32_t dirty; -}nouveau_state_atom; - -typedef struct nouveau_state_cache_t{ - nouveau_state_atom atoms[NOUVEAU_STATE_CACHE_ENTRIES]; - uint32_t current_pos; - // hierarchical dirty flags - uint8_t hdirty[NOUVEAU_STATE_CACHE_ENTRIES/NOUVEAU_STATE_CACHE_HIER_SIZE]; - // master dirty flag - uint8_t dirty; -}nouveau_state_cache; - - -#endif - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.c b/src/mesa/drivers/dri/nouveau/nouveau_swtcl.c deleted file mode 100644 index 8a013bd9995..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.c +++ /dev/null @@ -1,127 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* Common software TCL code */ - -#include "nouveau_context.h" -#include "nouveau_swtcl.h" -#include "nv10_swtcl.h" -#include "nouveau_span.h" -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" - -/* Common tri functions */ - -/* The fallbacks */ -void nouveau_fallback_tri(struct nouveau_context *nmesa, - nouveauVertex *v0, - nouveauVertex *v1, - nouveauVertex *v2) -{ - GLcontext *ctx = nmesa->glCtx; - SWvertex v[3]; - _swsetup_Translate(ctx, v0, &v[0]); - _swsetup_Translate(ctx, v1, &v[1]); - _swsetup_Translate(ctx, v2, &v[2]); - _swrast_Triangle(ctx, &v[0], &v[1], &v[2]); -} - - -void nouveau_fallback_line(struct nouveau_context *nmesa, - nouveauVertex *v0, - nouveauVertex *v1) -{ - GLcontext *ctx = nmesa->glCtx; - SWvertex v[2]; - _swsetup_Translate(ctx, v0, &v[0]); - _swsetup_Translate(ctx, v1, &v[1]); - _swrast_Line(ctx, &v[0], &v[1]); -} - - -void nouveau_fallback_point(struct nouveau_context *nmesa, - nouveauVertex *v0) -{ - GLcontext *ctx = nmesa->glCtx; - SWvertex v[1]; - _swsetup_Translate(ctx, v0, &v[0]); - _swrast_Point(ctx, &v[0]); -} - -void nouveauFallback(struct nouveau_context *nmesa, GLuint bit, GLboolean mode) -{ - GLcontext *ctx = nmesa->glCtx; - GLuint oldfallback = nmesa->Fallback; - - if (mode) { - nmesa->Fallback |= bit; - if (oldfallback == 0) { - if (nmesa->screen->card->type<NV_10) { - //nv04FinishPrimitive(nmesa); - } else { - //nv10FinishPrimitive(nmesa); - } - - _swsetup_Wakeup(ctx); - nmesa->render_index = ~0; - } - } - else { - nmesa->Fallback &= ~bit; - if (oldfallback == bit) { - _swrast_flush( ctx ); - - if (nmesa->screen->card->type<NV_10) { - nv04TriInitFunctions(ctx); - } else { - nv10TriInitFunctions(ctx); - } - - _tnl_invalidate_vertex_state( ctx, ~0 ); - _tnl_invalidate_vertices( ctx, ~0 ); - _tnl_install_attrs( ctx, - nmesa->vertex_attrs, - nmesa->vertex_attr_count, - nmesa->viewport.m, 0 ); - } - } -} - - -void nouveauRunPipeline( GLcontext *ctx ) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - - if (nmesa->new_state) { - nmesa->new_render_state |= nmesa->new_state; - } - - _tnl_run_pipeline( ctx ); -} - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.h b/src/mesa/drivers/dri/nouveau/nouveau_swtcl.h deleted file mode 100644 index ba4d8725a65..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.h +++ /dev/null @@ -1,55 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - -#ifndef __NOUVEAU_SWTCL_H__ -#define __NOUVEAU_SWTCL_H__ - -#include "nouveau_context.h" - -extern void nouveau_fallback_tri(struct nouveau_context *nmesa, - nouveauVertex *v0, - nouveauVertex *v1, - nouveauVertex *v2); - -extern void nouveau_fallback_line(struct nouveau_context *nmesa, - nouveauVertex *v0, - nouveauVertex *v1); - -extern void nouveau_fallback_point(struct nouveau_context *nmesa, - nouveauVertex *v0); - -extern void nouveauFallback(struct nouveau_context *nmesa, GLuint bit, GLboolean mode); - -extern void nouveauRunPipeline( GLcontext *ctx ); - -extern void nouveauTriInitFunctions( GLcontext *ctx ); - - -#endif /* __NOUVEAU_SWTCL_H__ */ - - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_sync.c b/src/mesa/drivers/dri/nouveau/nouveau_sync.c deleted file mode 100644 index 2ca038f4f8e..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_sync.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "vblank.h" /* for DO_USLEEP */ - -#include "nouveau_context.h" -#include "nouveau_fifo.h" -#include "nouveau_mem.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" -#include "nouveau_reg.h" -#include "nouveau_sync.h" - -#define NOTIFIER(__v) \ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); \ - volatile uint32_t *__v = (void*)nmesa->fifo.notifier_block + \ - notifier->offset - -struct drm_nouveau_notifierobj_alloc * -nouveau_notifier_new(GLcontext *ctx, GLuint handle, GLuint count) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - struct drm_nouveau_notifierobj_alloc *notifier; - int ret; - -#ifdef NOUVEAU_RING_DEBUG - return NULL; -#endif - notifier = CALLOC_STRUCT(drm_nouveau_notifierobj_alloc); - if (!notifier) - return NULL; - - notifier->channel = nmesa->fifo.drm.channel; - notifier->handle = handle; - notifier->count = count; - ret = drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, - notifier, sizeof(*notifier)); - if (ret) { - MESSAGE("Failed to create notifier 0x%08x: %d\n", handle, ret); - FREE(notifier); - return NULL; - } - - return notifier; -} - -void -nouveau_notifier_destroy(GLcontext *ctx, - struct drm_nouveau_notifierobj_alloc *notifier) -{ - /*XXX: free notifier object.. */ - FREE(notifier); -} - -void -nouveau_notifier_reset(GLcontext *ctx, - struct drm_nouveau_notifierobj_alloc *notifier, - GLuint id) -{ - NOTIFIER(n); - -#ifdef NOUVEAU_RING_DEBUG - return; -#endif - - n[NV_NOTIFY_TIME_0 /4] = 0x00000000; - n[NV_NOTIFY_TIME_1 /4] = 0x00000000; - n[NV_NOTIFY_RETURN_VALUE/4] = 0x00000000; - n[NV_NOTIFY_STATE /4] = (NV_NOTIFY_STATE_STATUS_IN_PROCESS << - NV_NOTIFY_STATE_STATUS_SHIFT); -} - -GLuint -nouveau_notifier_status(GLcontext *ctx, - struct drm_nouveau_notifierobj_alloc *notifier, - GLuint id) -{ - NOTIFIER(n); - - return n[NV_NOTIFY_STATE/4] >> NV_NOTIFY_STATE_STATUS_SHIFT; -} - -GLuint -nouveau_notifier_return_val(GLcontext *ctx, - struct drm_nouveau_notifierobj_alloc *notifier, - GLuint id) -{ - NOTIFIER(n); - - return n[NV_NOTIFY_RETURN_VALUE/4]; -} - -GLboolean -nouveau_notifier_wait_status(GLcontext *ctx, - struct drm_nouveau_notifierobj_alloc *notifier, - GLuint id, GLuint status, GLuint timeout) -{ - NOTIFIER(n); - unsigned int time = 0; - -#ifdef NOUVEAU_RING_DEBUG - return GL_TRUE; -#endif - - while (time <= timeout) { - if (n[NV_NOTIFY_STATE/4] & NV_NOTIFY_STATE_ERROR_CODE_MASK) { - MESSAGE("Notifier returned error: 0x%04x\n", - n[NV_NOTIFY_STATE/4] & - NV_NOTIFY_STATE_ERROR_CODE_MASK); - return GL_FALSE; - } - - if (((n[NV_NOTIFY_STATE/4] & NV_NOTIFY_STATE_STATUS_MASK) >> - NV_NOTIFY_STATE_STATUS_SHIFT) == status) - return GL_TRUE; - - if (timeout) { - DO_USLEEP(1); - time++; - } - } - - MESSAGE("Notifier timed out\n"); - return GL_FALSE; -} - -void -nouveau_notifier_wait_nop(GLcontext *ctx, - struct drm_nouveau_notifierobj_alloc *notifier, - GLuint subc) -{ - NOTIFIER(n); - GLboolean ret; - - nouveau_notifier_reset(ctx, notifier, 0); - - BEGIN_RING_SIZE(subc, NV_NOTIFY, 1); - OUT_RING (NV_NOTIFY_STYLE_WRITE_ONLY); - BEGIN_RING_SIZE(subc, NV_NOP, 1); - OUT_RING (0); - FIRE_RING(); - - ret = nouveau_notifier_wait_status(ctx, notifier, 0, - NV_NOTIFY_STATE_STATUS_COMPLETED, - 0 /* no timeout */); - if (ret == GL_FALSE) MESSAGE("wait on notifier failed\n"); -} - -GLboolean nouveauSyncInitFuncs(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -#ifdef NOUVEAU_RING_DEBUG - return GL_TRUE; -#endif - - nmesa->syncNotifier = nouveau_notifier_new(ctx, NvSyncNotify, 1); - if (!nmesa->syncNotifier) { - MESSAGE("Failed to create channel sync notifier\n"); - return GL_FALSE; - } - - /* 0x180 is SET_DMA_NOTIFY, should be correct for all supported 3D - * object classes - */ - BEGIN_RING_CACHE(NvSub3D, 0x180, 1); - OUT_RING_CACHE (NvSyncNotify); - BEGIN_RING_SIZE(NvSubMemFormat, - NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); - OUT_RING (NvSyncNotify); - - return GL_TRUE; -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_sync.h b/src/mesa/drivers/dri/nouveau/nouveau_sync.h deleted file mode 100644 index fc37efbe6b2..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_sync.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2007 Ben Skeggs. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __NOUVEAU_SYNC_H__ -#define __NOUVEAU_SYNC_H__ - -#define NV_NOTIFIER_SIZE 32 -#define NV_NOTIFY_TIME_0 0x00000000 -#define NV_NOTIFY_TIME_1 0x00000004 -#define NV_NOTIFY_RETURN_VALUE 0x00000008 -#define NV_NOTIFY_STATE 0x0000000C -#define NV_NOTIFY_STATE_STATUS_MASK 0xFF000000 -#define NV_NOTIFY_STATE_STATUS_SHIFT 24 -#define NV_NOTIFY_STATE_STATUS_COMPLETED 0x00 -#define NV_NOTIFY_STATE_STATUS_IN_PROCESS 0x01 -#define NV_NOTIFY_STATE_ERROR_CODE_MASK 0x0000FFFF -#define NV_NOTIFY_STATE_ERROR_CODE_SHIFT 0 - -/* Methods that (hopefully) all objects have */ -#define NV_NOP 0x00000100 -#define NV_NOTIFY 0x00000104 -#define NV_NOTIFY_STYLE_WRITE_ONLY 0 - -extern struct drm_nouveau_notifierobj_alloc * -nouveau_notifier_new(GLcontext *, GLuint handle, GLuint count); -extern void -nouveau_notifier_destroy(GLcontext *, struct drm_nouveau_notifierobj_alloc *); -extern void -nouveau_notifier_reset(GLcontext *, struct drm_nouveau_notifierobj_alloc *, - GLuint id); -extern GLuint -nouveau_notifier_status(GLcontext *, struct drm_nouveau_notifierobj_alloc *, - GLuint id); -extern GLuint -nouveau_notifier_return_val(GLcontext *, struct drm_nouveau_notifierobj_alloc *, - GLuint id); -extern GLboolean -nouveau_notifier_wait_status(GLcontext *, struct drm_nouveau_notifierobj_alloc *, - GLuint id, GLuint status, GLuint timeout); -extern void -nouveau_notifier_wait_nop(GLcontext *ctx, struct drm_nouveau_notifierobj_alloc *, - GLuint subc); - -extern GLboolean nouveauSyncInitFuncs(GLcontext *ctx); -#endif diff --git a/src/mesa/drivers/dri/nouveau/nouveau_tex.c b/src/mesa/drivers/dri/nouveau/nouveau_tex.c deleted file mode 100644 index 0a8d2796695..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_tex.c +++ /dev/null @@ -1,49 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#include "nouveau_tex.h" - -// XXX needs some love -void nouveauTexInitFunctions( struct dd_function_table *functions ) -{ -/* - functions->TexEnv = nouveauTexEnv; - functions->ChooseTextureFormat = nouveauChooseTextureFormat; - functions->TexImage1D = nouveauTexImage1D; - functions->TexSubImage1D = nouveauTexSubImage1D; - functions->TexImage2D = nouveauTexImage2D; - functions->TexSubImage2D = nouveauTexSubImage2D; - functions->TexParameter = nouveauTexParameter; - functions->BindTexture = nouveauBindTexture; - functions->NewTextureObject = nouveauNewTextureObject; - functions->DeleteTexture = nouveauDeleteTexture; - functions->IsTextureResident = driIsTextureResident; - - driInitTextureFormats(); -*/ -} - diff --git a/src/mesa/drivers/dri/nouveau/nouveau_tex.h b/src/mesa/drivers/dri/nouveau/nouveau_tex.h deleted file mode 100644 index 7ac71f8300b..00000000000 --- a/src/mesa/drivers/dri/nouveau/nouveau_tex.h +++ /dev/null @@ -1,38 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - -#ifndef __NOUVEAU_TEX_H__ -#define __NOUVEAU_TEX_H__ - -#include <errno.h> -#include "mtypes.h" -#include "macros.h" -#include "dd.h" - -extern void nouveauTexInitFunctions( struct dd_function_table *functions ); - -#endif /* __NOUVEAU_TEX_H__ */ diff --git a/src/mesa/drivers/dri/nouveau/nv04_state.c b/src/mesa/drivers/dri/nouveau/nv04_state.c deleted file mode 100644 index d3031aa5b19..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv04_state.c +++ /dev/null @@ -1,540 +0,0 @@ -/************************************************************************** - -Copyright 2007 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" -#include "nouveau_msg.h" - -#include "tnl/t_pipeline.h" - -#include "mtypes.h" -#include "colormac.h" - -static uint32_t nv04_compare_func(GLuint f) -{ - switch ( f ) { - case GL_NEVER: return 1; - case GL_LESS: return 2; - case GL_EQUAL: return 3; - case GL_LEQUAL: return 4; - case GL_GREATER: return 5; - case GL_NOTEQUAL: return 6; - case GL_GEQUAL: return 7; - case GL_ALWAYS: return 8; - } - WARN_ONCE("Unable to find the function\n"); - return 0; -} - -static uint32_t nv04_blend_func(GLuint f) -{ - switch ( f ) { - case GL_ZERO: return 0x1; - case GL_ONE: return 0x2; - case GL_SRC_COLOR: return 0x3; - case GL_ONE_MINUS_SRC_COLOR: return 0x4; - case GL_SRC_ALPHA: return 0x5; - case GL_ONE_MINUS_SRC_ALPHA: return 0x6; - case GL_DST_ALPHA: return 0x7; - case GL_ONE_MINUS_DST_ALPHA: return 0x8; - case GL_DST_COLOR: return 0x9; - case GL_ONE_MINUS_DST_COLOR: return 0xA; - case GL_SRC_ALPHA_SATURATE: return 0xB; - } - WARN_ONCE("Unable to find the function 0x%x\n",f); - return 0; -} - -static void nv04_emit_control(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - uint32_t control,cull; - GLubyte alpha_ref; - - CLAMPED_FLOAT_TO_UBYTE(alpha_ref, ctx->Color.AlphaRef); - control=alpha_ref; - control|=(nv04_compare_func(ctx->Color.AlphaFunc)<<8); - control|=(ctx->Color.AlphaEnabled<<12); - control|=(1<<13); - control|=(ctx->Depth.Test<<14); - control|=(nv04_compare_func(ctx->Depth.Func)<<16); - if ((ctx->Polygon.CullFlag)&&(ctx->Polygon.CullFaceMode!=GL_FRONT_AND_BACK)) - { - if ((ctx->Polygon.FrontFace==GL_CW)&&(ctx->Polygon.CullFaceMode==GL_FRONT)) - cull=2; - if ((ctx->Polygon.FrontFace==GL_CW)&&(ctx->Polygon.CullFaceMode==GL_BACK)) - cull=3; - if ((ctx->Polygon.FrontFace==GL_CCW)&&(ctx->Polygon.CullFaceMode==GL_FRONT)) - cull=3; - if ((ctx->Polygon.FrontFace==GL_CCW)&&(ctx->Polygon.CullFaceMode==GL_BACK)) - cull=2; - } - else - if (ctx->Polygon.CullFaceMode==GL_FRONT_AND_BACK) - cull=0; - else - cull=1; - control|=(cull<<20); - control|=(ctx->Color.DitherFlag<<22); - if ((ctx->Depth.Test)&&(ctx->Depth.Mask)) - control|=(1<<24); - - control|=(1<<30); // integer zbuffer format - - BEGIN_RING_CACHE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_CONTROL, 1); - OUT_RING_CACHE(control); -} - -static void nv04_emit_blend(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - uint32_t blend; - - blend=0x4; // texture MODULATE_ALPHA - blend|=0x20; // alpha is MSB - switch(ctx->Light.ShadeModel) { - case GL_SMOOTH:blend|=(1<<6);break; - case GL_FLAT: blend|=(2<<6);break; - default:break; - } - if (ctx->Hint.PerspectiveCorrection!=GL_FASTEST) - blend|=(1<<8); - blend|=(ctx->Fog.Enabled<<16); - blend|=(ctx->Color.BlendEnabled<<20); - blend|=(nv04_blend_func(ctx->Color.BlendSrcRGB)<<24); - blend|=(nv04_blend_func(ctx->Color.BlendDstRGB)<<28); - - BEGIN_RING_CACHE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_BLEND, 1); - OUT_RING_CACHE(blend); -} - -static void nv04_emit_fog_color(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte c[4]; - c[0] = FLOAT_TO_UBYTE( ctx->Fog.Color[0] ); - c[1] = FLOAT_TO_UBYTE( ctx->Fog.Color[1] ); - c[2] = FLOAT_TO_UBYTE( ctx->Fog.Color[2] ); - c[3] = FLOAT_TO_UBYTE( ctx->Fog.Color[3] ); - BEGIN_RING_CACHE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_FOG_COLOR, 1); - OUT_RING_CACHE(PACK_COLOR_8888_REV(c[0],c[1],c[2],c[3])); -} - -static void nv04AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref) -{ - nv04_emit_control(ctx); -} - -static void nv04BlendColor(GLcontext *ctx, const GLfloat color[4]) -{ - nv04_emit_blend(ctx); -} - -static void nv04BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA) -{ - nv04_emit_blend(ctx); -} - - -static void nv04BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA) -{ - nv04_emit_blend(ctx); -} - -static void nv04Clear(GLcontext *ctx, GLbitfield mask) -{ - /* TODO */ -} - -static void nv04ClearColor(GLcontext *ctx, const GLfloat color[4]) -{ - /* TODO */ -} - -static void nv04ClearDepth(GLcontext *ctx, GLclampd d) -{ - /* TODO */ -} - -static void nv04ClearStencil(GLcontext *ctx, GLint s) -{ - /* TODO */ -} - -static void nv04ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation) -{ - /* TODO */ -} - -static void nv04ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask, - GLboolean bmask, GLboolean amask ) -{ - /* TODO */ -} - -static void nv04ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode) -{ - /* TODO I need love */ -} - -static void nv04CullFace(GLcontext *ctx, GLenum mode) -{ - nv04_emit_control(ctx); -} - -static void nv04FrontFace(GLcontext *ctx, GLenum mode) -{ - /* TODO */ -} - -static void nv04DepthFunc(GLcontext *ctx, GLenum func) -{ - nv04_emit_control(ctx); -} - -static void nv04DepthMask(GLcontext *ctx, GLboolean flag) -{ - /* TODO */ -} - -static void nv04DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval) -{ - /* TODO */ -} - -/** Specify the current buffer for writing */ -//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer ); -/** Specify the buffers for writing for fragment programs*/ -//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers ); - -static void nv04Enable(GLcontext *ctx, GLenum cap, GLboolean state) -{ - switch(cap) - { - case GL_ALPHA_TEST: - nv04_emit_control(ctx); - break; -// case GL_AUTO_NORMAL: - case GL_BLEND: - nv04_emit_blend(ctx); - break; -// case GL_CLIP_PLANE0: -// case GL_CLIP_PLANE1: -// case GL_CLIP_PLANE2: -// case GL_CLIP_PLANE3: -// case GL_CLIP_PLANE4: -// case GL_CLIP_PLANE5: -// case GL_COLOR_LOGIC_OP: -// case GL_COLOR_MATERIAL: -// case GL_COLOR_SUM_EXT: -// case GL_COLOR_TABLE: -// case GL_CONVOLUTION_1D: -// case GL_CONVOLUTION_2D: - case GL_CULL_FACE: - nv04_emit_control(ctx); - break; - case GL_DEPTH_TEST: - nv04_emit_control(ctx); - break; - case GL_DITHER: - nv04_emit_control(ctx); - break; - case GL_FOG: - nv04_emit_blend(ctx); - nv04_emit_fog_color(ctx); - break; -// case GL_HISTOGRAM: -// case GL_INDEX_LOGIC_OP: -// case GL_LIGHT0: -// case GL_LIGHT1: -// case GL_LIGHT2: -// case GL_LIGHT3: -// case GL_LIGHT4: -// case GL_LIGHT5: -// case GL_LIGHT6: -// case GL_LIGHT7: -// case GL_LIGHTING: -// case GL_LINE_SMOOTH: -// case GL_LINE_STIPPLE: -// case GL_MAP1_COLOR_4: -// case GL_MAP1_INDEX: -// case GL_MAP1_NORMAL: -// case GL_MAP1_TEXTURE_COORD_1: -// case GL_MAP1_TEXTURE_COORD_2: -// case GL_MAP1_TEXTURE_COORD_3: -// case GL_MAP1_TEXTURE_COORD_4: -// case GL_MAP1_VERTEX_3: -// case GL_MAP1_VERTEX_4: -// case GL_MAP2_COLOR_4: -// case GL_MAP2_INDEX: -// case GL_MAP2_NORMAL: -// case GL_MAP2_TEXTURE_COORD_1: -// case GL_MAP2_TEXTURE_COORD_2: -// case GL_MAP2_TEXTURE_COORD_3: -// case GL_MAP2_TEXTURE_COORD_4: -// case GL_MAP2_VERTEX_3: -// case GL_MAP2_VERTEX_4: -// case GL_MINMAX: -// case GL_NORMALIZE: -// case GL_POINT_SMOOTH: -// case GL_POLYGON_OFFSET_POINT: -// case GL_POLYGON_OFFSET_LINE: -// case GL_POLYGON_OFFSET_FILL: -// case GL_POLYGON_SMOOTH: -// case GL_POLYGON_STIPPLE: -// case GL_POST_COLOR_MATRIX_COLOR_TABLE: -// case GL_POST_CONVOLUTION_COLOR_TABLE: -// case GL_RESCALE_NORMAL: -// case GL_SCISSOR_TEST: -// case GL_SEPARABLE_2D: -// case GL_STENCIL_TEST: -// case GL_TEXTURE_GEN_Q: -// case GL_TEXTURE_GEN_R: -// case GL_TEXTURE_GEN_S: -// case GL_TEXTURE_GEN_T: -// case GL_TEXTURE_1D: -// case GL_TEXTURE_2D: -// case GL_TEXTURE_3D: - } -} - -static void nv04Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - nv04_emit_blend(ctx); - nv04_emit_fog_color(ctx); -} - -static void nv04Hint(GLcontext *ctx, GLenum target, GLenum mode) -{ - switch(target) - { - case GL_PERSPECTIVE_CORRECTION_HINT:nv04_emit_blend(ctx);break; - default:break; - } -} - -static void nv04LineStipple(GLcontext *ctx, GLint factor, GLushort pattern ) -{ - /* TODO not even in your dreams */ -} - -static void nv04LineWidth(GLcontext *ctx, GLfloat width) -{ - /* TODO */ -} - -static void nv04LogicOpcode(GLcontext *ctx, GLenum opcode) -{ - /* TODO */ -} - -static void nv04PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - /* TODO */ -} - -static void nv04PointSize(GLcontext *ctx, GLfloat size) -{ - /* TODO */ -} - -static void nv04PolygonMode(GLcontext *ctx, GLenum face, GLenum mode) -{ - /* TODO */ -} - -/** Set the scale and units used to calculate depth values */ -static void nv04PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units) -{ - /* TODO */ -} - -/** Set the polygon stippling pattern */ -static void nv04PolygonStipple(GLcontext *ctx, const GLubyte *mask ) -{ - /* TODO */ -} - -/* Specifies the current buffer for reading */ -void (*ReadBuffer)( GLcontext *ctx, GLenum buffer ); -/** Set rasterization mode */ -void (*RenderMode)(GLcontext *ctx, GLenum mode ); - -/** Define the scissor box */ -static void nv04Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - /* TODO */ -} - -/** Select flat or smooth shading */ -static void nv04ShadeModel(GLcontext *ctx, GLenum mode) -{ - nv04_emit_blend(ctx); -} - -/** OpenGL 2.0 two-sided StencilFunc */ -static void nv04StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, - GLint ref, GLuint mask) -{ - /* TODO */ -} - -/** OpenGL 2.0 two-sided StencilMask */ -static void nv04StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask) -{ - /* TODO */ -} - -/** OpenGL 2.0 two-sided StencilOp */ -static void nv04StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, - GLenum zfail, GLenum zpass) -{ - /* TODO */ -} - -/** Control the generation of texture coordinates */ -void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname, - const GLfloat *params); -/** Set texture environment parameters */ -void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname, - const GLfloat *param); -/** Set texture parameters */ -void (*TexParameter)(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat *params); - -/* Update anything that depends on the window position/size */ -static void nv04WindowMoved(nouveauContextPtr nmesa) -{ -} - -/* Initialise any card-specific non-GL related state */ -static GLboolean nv04InitCard(nouveauContextPtr nmesa) -{ - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); - nouveauObjectOnSubchannel(nmesa, NvSubCtxSurf3D, NvCtxSurf3D); - - BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY, 3); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_SURFACE, 1); - OUT_RING(NvCtxSurf3D); - return GL_TRUE; -} - -/* Update buffer offset/pitch/format */ -static GLboolean nv04BindBuffers(nouveauContextPtr nmesa, int num_color, - nouveau_renderbuffer_t **color, - nouveau_renderbuffer_t *depth) -{ - GLuint x, y, w, h; - uint32_t depth_pitch=(depth?depth->pitch:0+15)&~15+16; - if (depth_pitch<256) depth_pitch=256; - - w = color[0]->mesa.Width; - h = color[0]->mesa.Height; - x = nmesa->drawX; - y = nmesa->drawY; - - BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_FORMAT, 1); - if (color[0]->mesa._ActualFormat == GL_RGBA8) - OUT_RING(0x108/*A8R8G8B8*/); - else - OUT_RING(0x103/*R5G6B5*/); - - /* FIXME pitches have to be aligned ! */ - BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_PITCH, 2); - OUT_RING(color[0]->pitch|(depth_pitch<<16)); - OUT_RING(color[0]->offset); - if (depth) { - BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA, 1); - OUT_RING(depth->offset); - } - -// BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL, 2); -// OUT_RING((w<<16)|x); -// OUT_RING((h<<16)|y); - - - /* FIXME not sure... */ -/* BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_SIZE, 1); - OUT_RING((h<<16)|w);*/ - - return GL_TRUE; -} - -void nv04InitStateFuncs(GLcontext *ctx, struct dd_function_table *func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - func->AlphaFunc = nv04AlphaFunc; - func->BlendColor = nv04BlendColor; - func->BlendEquationSeparate = nv04BlendEquationSeparate; - func->BlendFuncSeparate = nv04BlendFuncSeparate; - func->Clear = nv04Clear; - func->ClearColor = nv04ClearColor; - func->ClearDepth = nv04ClearDepth; - func->ClearStencil = nv04ClearStencil; - func->ClipPlane = nv04ClipPlane; - func->ColorMask = nv04ColorMask; - func->ColorMaterial = nv04ColorMaterial; - func->CullFace = nv04CullFace; - func->FrontFace = nv04FrontFace; - func->DepthFunc = nv04DepthFunc; - func->DepthMask = nv04DepthMask; - func->DepthRange = nv04DepthRange; - func->Enable = nv04Enable; - func->Fogfv = nv04Fogfv; - func->Hint = nv04Hint; -/* func->Lightfv = nv04Lightfv;*/ -/* func->LightModelfv = nv04LightModelfv; */ - func->LineStipple = nv04LineStipple; /* Not for NV04 */ - func->LineWidth = nv04LineWidth; - func->LogicOpcode = nv04LogicOpcode; - func->PointParameterfv = nv04PointParameterfv; - func->PointSize = nv04PointSize; - func->PolygonMode = nv04PolygonMode; - func->PolygonOffset = nv04PolygonOffset; - func->PolygonStipple = nv04PolygonStipple; /* Not for NV04 */ -/* func->ReadBuffer = nv04ReadBuffer;*/ -/* func->RenderMode = nv04RenderMode;*/ - func->Scissor = nv04Scissor; - func->ShadeModel = nv04ShadeModel; - func->StencilFuncSeparate = nv04StencilFuncSeparate; - func->StencilMaskSeparate = nv04StencilMaskSeparate; - func->StencilOpSeparate = nv04StencilOpSeparate; -/* func->TexGen = nv04TexGen;*/ -/* func->TexParameter = nv04TexParameter;*/ -/* func->TextureMatrix = nv04TextureMatrix;*/ - - nmesa->hw_func.InitCard = nv04InitCard; - nmesa->hw_func.BindBuffers = nv04BindBuffers; - nmesa->hw_func.WindowMoved = nv04WindowMoved; -} diff --git a/src/mesa/drivers/dri/nouveau/nv04_swtcl.c b/src/mesa/drivers/dri/nouveau/nv04_swtcl.c deleted file mode 100644 index 1b73d0be6fb..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv04_swtcl.c +++ /dev/null @@ -1,619 +0,0 @@ -/* - * Copyright 2007 Stephane Marchesin. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* Software TCL for NV04, NV05, NV06 */ - -#include <stdio.h> -#include <math.h> - -#include "glheader.h" -#include "context.h" -#include "mtypes.h" -#include "macros.h" -#include "colormac.h" -#include "enums.h" - -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "tnl/t_context.h" -#include "tnl/t_pipeline.h" - -#include "nouveau_swtcl.h" -#include "nv04_swtcl.h" -#include "nouveau_context.h" -#include "nouveau_span.h" -#include "nouveau_reg.h" -#include "nouveau_tex.h" -#include "nouveau_fifo.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" - -static void nv04RasterPrimitive( GLcontext *ctx, GLenum rprim, GLuint hwprim ); -static void nv04RenderPrimitive( GLcontext *ctx, GLenum prim ); -static void nv04ResetLineStipple( GLcontext *ctx ); - - -static INLINE void nv04_2triangles(struct nouveau_context *nmesa,nouveauVertex* v0,nouveauVertex* v1,nouveauVertex* v2,nouveauVertex* v3,nouveauVertex* v4,nouveauVertex* v5) -{ - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xA),49); - OUT_RINGp(v0,8); - OUT_RINGp(v1,8); - OUT_RINGp(v2,8); - OUT_RINGp(v3,8); - OUT_RINGp(v4,8); - OUT_RINGp(v5,8); - OUT_RING(0xFEDCBA); -} - -static INLINE void nv04_1triangle(struct nouveau_context *nmesa,nouveauVertex* v0,nouveauVertex* v1,nouveauVertex* v2) -{ - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xD),25); - OUT_RINGp(v0,8); - OUT_RINGp(v1,8); - OUT_RINGp(v2,8); - OUT_RING(0xFED); -} - -static INLINE void nv04_1quad(struct nouveau_context *nmesa,nouveauVertex* v0,nouveauVertex* v1,nouveauVertex* v2,nouveauVertex* v3) -{ - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xC),33); - OUT_RINGp(v0,8); - OUT_RINGp(v1,8); - OUT_RINGp(v2,8); - OUT_RINGp(v3,8); - OUT_RING(0xFECEDC); -} - -static INLINE void nv04_render_points(GLcontext *ctx,GLuint first,GLuint last) -{ - WARN_ONCE("Unimplemented\n"); -} - -static INLINE void nv04_render_line(GLcontext *ctx,GLuint v1,GLuint v2) -{ - WARN_ONCE("Unimplemented\n"); -} - -static INLINE void nv04_render_triangle(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - - nv04_1triangle(nmesa, - (nouveauVertex*)(vertptr+v1*vertsize), - (nouveauVertex*)(vertptr+v2*vertsize), - (nouveauVertex*)(vertptr+v3*vertsize) - ); -} - -static INLINE void nv04_render_quad(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3,GLuint v4) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - - nv04_1quad(nmesa, - (nouveauVertex*)(vertptr+v1*vertsize), - (nouveauVertex*)(vertptr+v2*vertsize), - (nouveauVertex*)(vertptr+v3*vertsize), - (nouveauVertex*)(vertptr+v4*vertsize) - ); -} - -/**********************************************************************/ -/* Render unclipped begin/end objects */ -/**********************************************************************/ - -static void nv04_render_points_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // erm -} - -static void nv04_render_lines_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // umm -} - -static void nv04_render_line_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // yeah -} - -static void nv04_render_line_loop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // right -} - -static void nv04_render_triangles_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - int i; - - for(i=start;i<count-5;i+=6) - nv04_2triangles(nmesa, - (nouveauVertex*)(vertptr+(i+0)*vertsize), - (nouveauVertex*)(vertptr+(i+1)*vertsize), - (nouveauVertex*)(vertptr+(i+2)*vertsize), - (nouveauVertex*)(vertptr+(i+3)*vertsize), - (nouveauVertex*)(vertptr+(i+4)*vertsize), - (nouveauVertex*)(vertptr+(i+5)*vertsize) - ); - if (i!=count) - { - nv04_1triangle(nmesa, - (nouveauVertex*)(vertptr+(i+0)*vertsize), - (nouveauVertex*)(vertptr+(i+1)*vertsize), - (nouveauVertex*)(vertptr+(i+2)*vertsize) - ); - i+=3; - } - if (i!=count) - printf("oops\n"); -} - -static void nv04_render_tri_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - uint32_t striptbl[]={0x321210,0x543432,0x765654,0x987876,0xBA9A98,0xDCBCBA,0xFEDEDC}; - int i,j; - - for(i=start;i<count;i+=14) - { - int numvert=MIN2(16,count-i); - int numtri=numvert-2; - if (numvert<3) - break; - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0),numvert*8); - for(j=0;j<numvert;j++) - OUT_RINGp((nouveauVertex*)(vertptr+(i+j)*vertsize),8); - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_DRAW|NONINC_METHOD,(numtri+1)/2); - for(j=0;j<numtri/2;j++) - OUT_RING(striptbl[j]); - if (numtri%2) - OUT_RING(striptbl[numtri/2]&0xFFF); - } -} - -static void nv04_render_tri_fan_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - uint32_t fantbl[]={0x320210,0x540430,0x760650,0x980870,0xBA0A90,0xDC0CB0,0xFE0ED0}; - int i,j; - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0),8); - OUT_RINGp((nouveauVertex*)(vertptr+start*vertsize),8); - - for(i=start+1;i<count;i+=14) - { - int numvert=MIN2(15,count-i); - int numtri=numvert-1; - if (numvert<3) - break; - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x1),numvert*8); - - for(j=0;j<numvert;j++) - OUT_RINGp((nouveauVertex*)(vertptr+(i+j)*vertsize),8); - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_DRAW|NONINC_METHOD,(numtri+1)/2); - for(j=0;j<numtri/2;j++) - OUT_RING(fantbl[j]); - if (numtri%2) - OUT_RING(fantbl[numtri/2]&0xFFF); - } -} - -static void nv04_render_quads_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - int i; - - for(i=start;i<count;i+=4) - nv04_1quad(nmesa, - (nouveauVertex*)(vertptr+(i+0)*vertsize), - (nouveauVertex*)(vertptr+(i+1)*vertsize), - (nouveauVertex*)(vertptr+(i+2)*vertsize), - (nouveauVertex*)(vertptr+(i+3)*vertsize) - ); -} - -static void nv04_render_noop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ -} - -static void (*nv04_render_tab_verts[GL_POLYGON+2])(GLcontext *, - GLuint, - GLuint, - GLuint) = -{ - nv04_render_points_verts, - nv04_render_lines_verts, - nv04_render_line_loop_verts, - nv04_render_line_strip_verts, - nv04_render_triangles_verts, - nv04_render_tri_strip_verts, - nv04_render_tri_fan_verts, - nv04_render_quads_verts, - nv04_render_tri_strip_verts, //nv04_render_quad_strip_verts - nv04_render_tri_fan_verts, //nv04_render_poly_verts - nv04_render_noop_verts, -}; - - -static void nv04_render_points_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // erm -} - -static void nv04_render_lines_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // umm -} - -static void nv04_render_line_strip_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // yeah -} - -static void nv04_render_line_loop_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - // right -} - -static void nv04_render_triangles_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; - int i; - - for(i=start;i<count-5;i+=6) - nv04_2triangles(nmesa, - (nouveauVertex*)(vertptr+elt[i+0]*vertsize), - (nouveauVertex*)(vertptr+elt[i+1]*vertsize), - (nouveauVertex*)(vertptr+elt[i+2]*vertsize), - (nouveauVertex*)(vertptr+elt[i+3]*vertsize), - (nouveauVertex*)(vertptr+elt[i+4]*vertsize), - (nouveauVertex*)(vertptr+elt[i+5]*vertsize) - ); - if (i!=count) - { - nv04_1triangle(nmesa, - (nouveauVertex*)(vertptr+elt[i+0]*vertsize), - (nouveauVertex*)(vertptr+elt[i+1]*vertsize), - (nouveauVertex*)(vertptr+elt[i+2]*vertsize) - ); - i+=3; - } - if (i!=count) - printf("oops\n"); -} - -static void nv04_render_tri_strip_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - uint32_t striptbl[]={0x321210,0x543432,0x765654,0x987876,0xBA9A98,0xDCBCBA,0xFEDEDC}; - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; - int i,j; - - for(i=start;i<count;i+=14) - { - int numvert=MIN2(16,count-i); - int numtri=numvert-2; - if (numvert<3) - break; - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0),numvert*8); - for(j=0;j<numvert;j++) - OUT_RINGp((nouveauVertex*)(vertptr+elt[i+j]*vertsize),8); - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_DRAW|NONINC_METHOD,(numtri+1)/2); - for(j=0;j<numtri/2;j++) - OUT_RING(striptbl[j]); - if (numtri%2) - OUT_RING(striptbl[numtri/2]&0xFFF); - } -} - -static void nv04_render_tri_fan_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - uint32_t fantbl[]={0x320210,0x540430,0x760650,0x980870,0xBA0A90,0xDC0CB0,0xFE0ED0}; - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; - int i,j; - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0),8); - OUT_RINGp((nouveauVertex*)(vertptr+elt[start]*vertsize),8); - - for(i=start+1;i<count;i+=14) - { - int numvert=MIN2(15,count-i); - int numtri=numvert-2; - if (numvert<3) - break; - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x1),numvert*8); - - for(j=0;j<numvert;j++) - OUT_RINGp((nouveauVertex*)(vertptr+elt[i+j]*vertsize),8); - - BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_DRAW|NONINC_METHOD,(numtri+1)/2); - for(j=0;j<numtri/2;j++) - OUT_RING(fantbl[j]); - if (numtri%2) - OUT_RING(fantbl[numtri/2]&0xFFF); - } -} - -static void nv04_render_quads_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte *vertptr = (GLubyte *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; - int i; - - for(i=start;i<count;i+=4) - nv04_1quad(nmesa, - (nouveauVertex*)(vertptr+elt[i+0]*vertsize), - (nouveauVertex*)(vertptr+elt[i+1]*vertsize), - (nouveauVertex*)(vertptr+elt[i+2]*vertsize), - (nouveauVertex*)(vertptr+elt[i+3]*vertsize) - ); -} - -static void nv04_render_noop_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ -} - -static void (*nv04_render_tab_elts[GL_POLYGON+2])(GLcontext *, - GLuint, - GLuint, - GLuint) = -{ - nv04_render_points_elts, - nv04_render_lines_elts, - nv04_render_line_loop_elts, - nv04_render_line_strip_elts, - nv04_render_triangles_elts, - nv04_render_tri_strip_elts, - nv04_render_tri_fan_elts, - nv04_render_quads_elts, - nv04_render_tri_strip_elts, // nv04_render_quad_strip_elts, - nv04_render_tri_fan_elts, // nv04_render_poly_elts, - nv04_render_noop_elts, -}; - - -/**********************************************************************/ -/* Choose render functions */ -/**********************************************************************/ - - -#define EMIT_ATTR( ATTR, STYLE ) \ -do { \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].attrib = (ATTR); \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].format = (STYLE); \ - nmesa->vertex_attr_count++; \ -} while (0) - -#define EMIT_PAD( N ) \ -do { \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].attrib = 0; \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].format = EMIT_PAD; \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].offset = (N); \ - nmesa->vertex_attr_count++; \ -} while (0) - -static void nv04_render_clipped_line(GLcontext *ctx,GLuint ii,GLuint jj) -{ -} - -static void nv04_render_clipped_poly(GLcontext *ctx,const GLuint *elts,GLuint n) -{ -} - -static void nv04ChooseRenderState(GLcontext *ctx) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - - tnl->Driver.Render.PrimTabVerts = nv04_render_tab_verts; - tnl->Driver.Render.PrimTabElts = nv04_render_tab_elts; - tnl->Driver.Render.ClippedLine = nv04_render_clipped_line; - tnl->Driver.Render.ClippedPolygon = nv04_render_clipped_poly; - tnl->Driver.Render.Points = nv04_render_points; - tnl->Driver.Render.Line = nv04_render_line; - tnl->Driver.Render.Triangle = nv04_render_triangle; - tnl->Driver.Render.Quad = nv04_render_quad; -} - - - -static INLINE void nv04OutputVertexFormat(struct nouveau_context* nmesa) -{ - GLcontext* ctx=nmesa->glCtx; - DECLARE_RENDERINPUTS(index); - - /* - * Tell t_vertex about the vertex format - */ - nmesa->vertex_attr_count = 0; - RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset); - - // SX SY SZ INVW - // FIXME : we use W instead of INVW, but since W=1 it doesn't matter - if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_POS)) - EMIT_ATTR(_TNL_ATTRIB_POS,EMIT_4F_VIEWPORT); - else - EMIT_PAD(4*sizeof(float)); - - // COLOR - if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_COLOR0)) - EMIT_ATTR(_TNL_ATTRIB_COLOR0,EMIT_4UB_4F_ABGR); - else - EMIT_PAD(4); - - // SPECULAR - if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_COLOR1)) - EMIT_ATTR(_TNL_ATTRIB_COLOR1,EMIT_4UB_4F_ABGR); - else - EMIT_PAD(4); - - // TEXTURE - if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_TEX0)) - EMIT_ATTR(_TNL_ATTRIB_TEX0,EMIT_2F); - else - EMIT_PAD(2*sizeof(float)); - - nmesa->vertex_size=_tnl_install_attrs( ctx, - nmesa->vertex_attrs, - nmesa->vertex_attr_count, - nmesa->viewport.m, 0 ); -} - - -static void nv04ChooseVertexState( GLcontext *ctx ) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - DECLARE_RENDERINPUTS(index); - - RENDERINPUTS_COPY(index, tnl->render_inputs_bitset); - if (!RENDERINPUTS_EQUAL(index, nmesa->render_inputs_bitset)) - { - RENDERINPUTS_COPY(nmesa->render_inputs_bitset, index); - nv04OutputVertexFormat(nmesa); - } -} - - -/**********************************************************************/ -/* High level hooks for t_vb_render.c */ -/**********************************************************************/ - - -static void nv04RenderStart(GLcontext *ctx) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - - if (nmesa->new_state) { - nmesa->new_render_state |= nmesa->new_state; - } - - if (nmesa->new_render_state) { - nv04ChooseVertexState(ctx); - nv04ChooseRenderState(ctx); - nmesa->new_render_state = 0; - } -} - -static void nv04RenderFinish(GLcontext *ctx) -{ -} - - -/* System to flush dma and emit state changes based on the rasterized - * primitive. - */ -void nv04RasterPrimitive(GLcontext *ctx, - GLenum glprim, - GLuint hwprim) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - - assert (!nmesa->new_state); - - if (hwprim != nmesa->current_primitive) - { - nmesa->current_primitive=hwprim; - - } -} - -static const GLuint hw_prim[GL_POLYGON+1] = { - GL_POINTS+1, - GL_LINES+1, - GL_LINE_STRIP+1, - GL_LINE_LOOP+1, - GL_TRIANGLES+1, - GL_TRIANGLE_STRIP+1, - GL_TRIANGLE_FAN+1, - GL_QUADS+1, - GL_QUAD_STRIP+1, - GL_POLYGON+1 -}; - -/* Callback for mesa: - */ -static void nv04RenderPrimitive( GLcontext *ctx, GLuint prim ) -{ - nv04RasterPrimitive( ctx, prim, hw_prim[prim] ); -} - -static void nv04ResetLineStipple( GLcontext *ctx ) -{ - /* FIXME do something here */ - WARN_ONCE("Unimplemented nv04ResetLineStipple\n"); -} - - -/**********************************************************************/ -/* Initialization. */ -/**********************************************************************/ - -void nv04TriInitFunctions(GLcontext *ctx) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - - tnl->Driver.RunPipeline = nouveauRunPipeline; - tnl->Driver.Render.Start = nv04RenderStart; - tnl->Driver.Render.Finish = nv04RenderFinish; - tnl->Driver.Render.PrimitiveNotify = nv04RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = nv04ResetLineStipple; - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 32 ); - - nmesa->verts = (GLubyte *)tnl->clipspace.vertex_buf; -} - - diff --git a/src/mesa/drivers/dri/nouveau/nv04_swtcl.h b/src/mesa/drivers/dri/nouveau/nv04_swtcl.h deleted file mode 100644 index 42dde5383eb..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv04_swtcl.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __NV04_SWTCL_H__ -#define __NV04_SWTCL_H__ - -#include "mtypes.h" - -extern void nv04Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ); -extern void nv04FinishPrimitive(struct nouveau_context *nmesa); -extern void nv04TriInitFunctions(GLcontext *ctx); -#define FALLBACK( nmesa, bit, mode ) nouveauFallback( nmesa->glCtx, bit, mode ) - -#endif /* __NV04_SWTCL_H__ */ - diff --git a/src/mesa/drivers/dri/nouveau/nv10_state.c b/src/mesa/drivers/dri/nouveau/nv10_state.c deleted file mode 100644 index 3e5bfe093f9..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv10_state.c +++ /dev/null @@ -1,1009 +0,0 @@ -/************************************************************************** - -Copyright 2006 Nouveau -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" - -#include "tnl/t_pipeline.h" - -#include "mtypes.h" -#include "colormac.h" - -static void nv10ViewportScale(nouveauContextPtr nmesa) -{ - GLcontext *ctx = nmesa->glCtx; - GLfloat w = ((GLfloat) ctx->Viewport.Width) * 0.5; - GLfloat h = ((GLfloat) ctx->Viewport.Height) * 0.5; - GLfloat max_depth = (ctx->Viewport.Near + ctx->Viewport.Far) * 0.5; - - if (ctx->DrawBuffer) { - if (ctx->DrawBuffer->_DepthBuffer) { - switch (ctx->DrawBuffer->_DepthBuffer->DepthBits) { - case 16: - max_depth *= 32767.0; - break; - case 24: - max_depth *= 16777215.0; - break; - } - } - } - - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X, 4); - OUT_RINGf (w - 2048.0); - OUT_RINGf (h - 2048.0); - OUT_RINGf (max_depth); - OUT_RINGf (0.0); -} - -static void nv10AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte ubRef; - CLAMPED_FLOAT_TO_UBYTE(ubRef, ref); - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC, 2); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ubRef); -} - -static void nv10BlendColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte cf[4]; - - CLAMPED_FLOAT_TO_UBYTE(cf[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(cf[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(cf[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(cf[3], color[3]); - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_COLOR, 1); - OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0])); -} - -static void nv10BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - assert( modeRGB == modeA ); - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION, 1); - OUT_RING_CACHE(modeRGB); -} - - -static void nv10BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - assert( sfactorRGB == sfactorA ); - assert( dfactorRGB == dfactorA ); - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC, 2); - OUT_RING_CACHE(sfactorRGB); - OUT_RING_CACHE(dfactorRGB); -} - -static void nv10ClearColor(GLcontext *ctx, const GLfloat color[4]) -{ - /* Not for NV10 */ -} - -static void nv10ClearDepth(GLcontext *ctx, GLclampd d) -{ - /* Not for NV10 */ -} - -static void nv10ClearStencil(GLcontext *ctx, GLint s) -{ - /* Not for NV10 */ -} - -static void nv10ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_A(plane - GL_CLIP_PLANE0), 4); - OUT_RING_CACHEf(equation[0]); - OUT_RING_CACHEf(equation[1]); - OUT_RING_CACHEf(equation[2]); - OUT_RING_CACHEf(equation[3]); -} - -static void nv10ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask, - GLboolean bmask, GLboolean amask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_MASK, 1); - OUT_RING_CACHE(((amask && 0x01) << 24) | ((rmask && 0x01) << 16) | ((gmask && 0x01)<< 8) | ((bmask && 0x01) << 0)); -} - -static void nv10ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode) -{ - /* TODO I need love */ -} - -static void nv10CullFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CULL_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv10FrontFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FRONT_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv10DepthFunc(GLcontext *ctx, GLenum func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1); - OUT_RING_CACHE(func); -} - -static void nv10DepthMask(GLcontext *ctx, GLboolean flag) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1); - OUT_RING_CACHE(flag); -} - -static void nv10DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - GLfloat depth_scale = 16777216.0; - if (ctx->DrawBuffer) { - if (ctx->DrawBuffer->_DepthBuffer) { - if (ctx->DrawBuffer->_DepthBuffer->DepthBits == 16) { - depth_scale = 32768.0; - } - } - } - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2); - OUT_RING_CACHEf(nearval * depth_scale); - OUT_RING_CACHEf(farval * depth_scale); - - nv10ViewportScale(nmesa); -} - -/** Specify the current buffer for writing */ -//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer ); -/** Specify the buffers for writing for fragment programs*/ -//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers ); - -static void nv10Enable(GLcontext *ctx, GLenum cap, GLboolean state) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - switch(cap) - { - case GL_ALPHA_TEST: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_AUTO_NORMAL: - case GL_BLEND: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_CLIP_PLANE0: - case GL_CLIP_PLANE1: - case GL_CLIP_PLANE2: - case GL_CLIP_PLANE3: - case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(cap-GL_CLIP_PLANE0), 1); - OUT_RING_CACHE(state); - break; - case GL_COLOR_LOGIC_OP: - if (nmesa->screen->card->type >= NV_11) { - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE, 1); - OUT_RING_CACHE(state); - } - break; -// case GL_COLOR_MATERIAL: -// case GL_COLOR_SUM_EXT: -// case GL_COLOR_TABLE: -// case GL_CONVOLUTION_1D: -// case GL_CONVOLUTION_2D: - case GL_CULL_FACE: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DEPTH_TEST: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DITHER: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DITHER_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_FOG: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_HISTOGRAM: -// case GL_INDEX_LOGIC_OP: -#if 0 - /* light is broken, the hardware seem to only allow to use light - * in order : ie GL_LIGHT0 & GL_LIGHT2 is invalid - * In this case the blob remap GL_LIGHT2 to hw light 1 - */ - case GL_LIGHT0: - case GL_LIGHT1: - case GL_LIGHT2: - case GL_LIGHT3: - case GL_LIGHT4: - case GL_LIGHT5: - case GL_LIGHT6: - case GL_LIGHT7: - { - uint32_t mask=1<<(2*(cap-GL_LIGHT0)); - if (state) - nmesa->enabled_lights |= mask; - else - nmesa->enabled_lights &= ~mask; - - if (nmesa->lighting_enabled) - { - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1); - OUT_RING_CACHE(nmesa->enabled_lights); - } - break; - } - case GL_LIGHTING: - nmesa->lighting_enabled=state; - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1); - if (nmesa->lighting_enabled) - OUT_RING_CACHE(nmesa->enabled_lights); - else - OUT_RING_CACHE(0x0); - break; -#endif - case GL_LINE_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_LINE_STIPPLE: -// case GL_MAP1_COLOR_4: -// case GL_MAP1_INDEX: -// case GL_MAP1_NORMAL: -// case GL_MAP1_TEXTURE_COORD_1: -// case GL_MAP1_TEXTURE_COORD_2: -// case GL_MAP1_TEXTURE_COORD_3: -// case GL_MAP1_TEXTURE_COORD_4: -// case GL_MAP1_VERTEX_3: -// case GL_MAP1_VERTEX_4: -// case GL_MAP2_COLOR_4: -// case GL_MAP2_INDEX: -// case GL_MAP2_NORMAL: -// case GL_MAP2_TEXTURE_COORD_1: -// case GL_MAP2_TEXTURE_COORD_2: -// case GL_MAP2_TEXTURE_COORD_3: -// case GL_MAP2_TEXTURE_COORD_4: -// case GL_MAP2_VERTEX_3: -// case GL_MAP2_VERTEX_4: -// case GL_MINMAX: - case GL_NORMALIZE: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_POINT_SMOOTH: - case GL_POLYGON_OFFSET_POINT: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_LINE: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_FILL: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_POLYGON_STIPPLE: -// case GL_POST_COLOR_MATRIX_COLOR_TABLE: -// case GL_POST_CONVOLUTION_COLOR_TABLE: -// case GL_RESCALE_NORMAL: -// case GL_SCISSOR_TEST: -// case GL_SEPARABLE_2D: - case GL_STENCIL_TEST: - // TODO BACK and FRONT ? - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_TEXTURE_GEN_Q: -// case GL_TEXTURE_GEN_R: -// case GL_TEXTURE_GEN_S: -// case GL_TEXTURE_GEN_T: -// case GL_TEXTURE_1D: -// case GL_TEXTURE_2D: -// case GL_TEXTURE_3D: - } -} - -static void nv10Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte cf[4]; - switch(pname) - { - case GL_FOG_MODE: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_MODE, 1); - OUT_RING_CACHE (ctx->Fog.Mode); /* can we extract it from params ??? */ - break; - case GL_FOG_COLOR: - CLAMPED_FLOAT_TO_UBYTE(cf[0], params[0]); - CLAMPED_FLOAT_TO_UBYTE(cf[1], params[1]); - CLAMPED_FLOAT_TO_UBYTE(cf[2], params[2]); - CLAMPED_FLOAT_TO_UBYTE(cf[3], params[3]); - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_COLOR, 1); - OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0])); - break; - /* TODO: unsure about the rest.*/ - default: - break; - } - -} - -static void nv10Hint(GLcontext *ctx, GLenum target, GLenum mode) -{ - /* TODO I need love (fog and line_smooth hints) */ -} - -// void (*IndexMask)(GLcontext *ctx, GLuint mask); - -enum { - SPOTLIGHT_NO_UPDATE, - SPOTLIGHT_UPDATE_EXPONENT, - SPOTLIGHT_UPDATE_DIRECTION, - SPOTLIGHT_UPDATE_ALL -}; - -static void nv10Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLint p = light - GL_LIGHT0; - struct gl_light *l = &ctx->Light.Light[p]; - int spotlight_update = SPOTLIGHT_NO_UPDATE; - - switch(pname) - { - case GL_AMBIENT: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_DIFFUSE: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_SPECULAR: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_POSITION: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_SPOT_DIRECTION: - spotlight_update = SPOTLIGHT_UPDATE_DIRECTION; - break; - case GL_SPOT_EXPONENT: - spotlight_update = SPOTLIGHT_UPDATE_EXPONENT; - break; - case GL_SPOT_CUTOFF: - spotlight_update = SPOTLIGHT_UPDATE_ALL; - break; - case GL_CONSTANT_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - case GL_LINEAR_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - case GL_QUADRATIC_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - default: - break; - } - - switch(spotlight_update) { - case SPOTLIGHT_UPDATE_DIRECTION: - { - GLfloat x,y,z; - GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0); - x = spot_light_coef_a * l->_NormDirection[0]; - y = spot_light_coef_a * l->_NormDirection[1]; - z = spot_light_coef_a * l->_NormDirection[2]; - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(p), 3); - OUT_RING_CACHEf(x); - OUT_RING_CACHEf(y); - OUT_RING_CACHEf(z); - } - break; - case SPOTLIGHT_UPDATE_EXPONENT: - { - GLfloat cc,lc,qc; - cc = 1.0; /* FIXME: These need to be correctly computed */ - lc = 0.0; - qc = 2.0; - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 3); - OUT_RING_CACHEf(cc); - OUT_RING_CACHEf(lc); - OUT_RING_CACHEf(qc); - } - break; - case SPOTLIGHT_UPDATE_ALL: - { - GLfloat cc,lc,qc, x,y,z, c; - GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0); - cc = 1.0; /* FIXME: These need to be correctly computed */ - lc = 0.0; - qc = 2.0; - x = spot_light_coef_a * l->_NormDirection[0]; - y = spot_light_coef_a * l->_NormDirection[1]; - z = spot_light_coef_a * l->_NormDirection[2]; - c = spot_light_coef_a + 1.0; - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 7); - OUT_RING_CACHEf(cc); - OUT_RING_CACHEf(lc); - OUT_RING_CACHEf(qc); - OUT_RING_CACHEf(x); - OUT_RING_CACHEf(y); - OUT_RING_CACHEf(z); - OUT_RING_CACHEf(c); - } - break; - default: - break; - } -} - -/** Set the lighting model parameters */ -static void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params); - - -static void nv10LineStipple(GLcontext *ctx, GLint factor, GLushort pattern ) -{ - /* Not for NV10 */ -} - -static void nv10LineWidth(GLcontext *ctx, GLfloat width) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LINE_WIDTH, 1); - OUT_RING_CACHE(((int) (width * 8.0)) & -4); -} - -static void nv10LogicOpcode(GLcontext *ctx, GLenum opcode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (nmesa->screen->card->type < NV_11) { - return; - } - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP, 1); - OUT_RING_CACHE(opcode); -} - -static void nv10PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - /*TODO: not sure what goes here. */ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -} - -static void nv10PointSize(GLcontext *ctx, GLfloat size) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POINT_SIZE, 1); - OUT_RING_CACHE(((int) (size * 8.0)) & -4); -} - -static void nv10PolygonMode(GLcontext *ctx, GLenum face, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1); - OUT_RING_CACHE(mode); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1); - OUT_RING_CACHE(mode); - } -} - -/** Set the scale and units used to calculate depth values */ -static void nv10PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 2); - OUT_RING_CACHEf(factor); - OUT_RING_CACHEf(units); -} - -/** Set the polygon stippling pattern */ -static void nv10PolygonStipple(GLcontext *ctx, const GLubyte *mask ) -{ - /* Not for NV10 */ -} - -/* Specifies the current buffer for reading */ -void (*ReadBuffer)( GLcontext *ctx, GLenum buffer ); -/** Set rasterization mode */ -void (*RenderMode)(GLcontext *ctx, GLenum mode ); - -/* Translate GL coords to window coords, clamping w/h to the - * dimensions of the window. - */ -static void nv10WindowCoords(nouveauContextPtr nmesa, - GLuint x, GLuint y, GLuint w, GLuint h, - GLuint *wX, GLuint *wY, GLuint *wW, GLuint *wH) -{ - if ((x+w) > nmesa->drawW) - w = nmesa->drawW - x; - (*wX) = x + nmesa->drawX; - (*wW) = w; - - if ((y+h) > nmesa->drawH) - h = nmesa->drawH - y; - (*wY) = (nmesa->drawH - y) - h + nmesa->drawY; - (*wH) = h; -} - -/** Define the scissor box */ -static void nv10Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLuint wX, wY, wW, wH; - - /* There's no scissor enable bit, so adjust the scissor to cover the - * maximum draw buffer bounds - */ - if (!ctx->Scissor.Enabled) { - wX = nmesa->drawX; - wY = nmesa->drawY; - wW = nmesa->drawW; - wH = nmesa->drawH; - } else { - nv10WindowCoords(nmesa, x, y, w, h, &wX, &wY, &wW, &wH); - } - - if (!wW || !wH) { - return; - } - - BEGIN_RING_SIZE(NvSub3D, - NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 1); - OUT_RING(((wW+wX-1) << 16) | wX | 0x08000800); - BEGIN_RING_SIZE(NvSub3D, - NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(0), 1); - OUT_RING(((wH+wY-1) << 16) | wY | 0x08000800); -} - -/** Select flat or smooth shading */ -static void nv10ShadeModel(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_SHADE_MODEL, 1); - OUT_RING_CACHE(mode); -} - -/** OpenGL 2.0 two-sided StencilFunc */ -static void nv10StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, - GLint ref, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* NV10 do not have separate FRONT and BACK stencils */ - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC, 3); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ref); - OUT_RING_CACHE(mask); -} - -/** OpenGL 2.0 two-sided StencilMask */ -static void nv10StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* NV10 do not have separate FRONT and BACK stencils */ - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_MASK, 1); - OUT_RING_CACHE(mask); -} - -/** OpenGL 2.0 two-sided StencilOp */ -static void nv10StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, - GLenum zfail, GLenum zpass) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* NV10 do not have separate FRONT and BACK stencils */ - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL, 3); - OUT_RING_CACHE(fail); - OUT_RING_CACHE(zfail); - OUT_RING_CACHE(zpass); -} - -/** Control the generation of texture coordinates */ -void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname, - const GLfloat *params); -/** Set texture environment parameters */ -void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname, - const GLfloat *param); -/** Set texture parameters */ -void (*TexParameter)(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat *params); - -static void nv10TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_TX_MATRIX(unit, 0), 16); - /*XXX: This SHOULD work.*/ - OUT_RING_CACHEp(mat->m, 16); -} - -static void nv10UpdateProjectionMatrix(GLcontext *ctx) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat w = ((GLfloat) ctx->Viewport.Width) * 0.5; - GLfloat h = ((GLfloat) ctx->Viewport.Height) * 0.5; - GLfloat max_depth = (ctx->Viewport.Near + ctx->Viewport.Far) * 0.5; - GLfloat projection[16]; - int i; - - if (ctx->DrawBuffer) { - if (ctx->DrawBuffer->_DepthBuffer) { - switch (ctx->DrawBuffer->_DepthBuffer->DepthBits) { - case 16: - max_depth *= 32767.0; - break; - case 24: - max_depth *= 16777215.0; - break; - } - } - } - - /* Transpose and rescale for viewport */ - for (i=0; i<4; i++) { - projection[i] = w * ctx->_ModelProjectMatrix.m[i*4]; - } - for (i=0; i<4; i++) { - projection[i+4] = -h * ctx->_ModelProjectMatrix.m[i*4+1]; - } - for (i=0; i<4; i++) { - projection[i+8] = max_depth * ctx->_ModelProjectMatrix.m[i*4+2]; - } - for (i=0; i<4; i++) { - projection[i+12] = ctx->_ModelProjectMatrix.m[i*4+3]; - } - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(0), 16); - OUT_RING_CACHE_FORCEp(projection, 16); -} - -static void nv10UpdateModelviewMatrix(GLcontext *ctx) -{ - /* TODO update modelview if lighting or vertex weight enabled - update inverse modelview if lighting enabled - or update projection if lighting and vertex weight disabled - */ - - nv10UpdateProjectionMatrix(ctx); -} - -/* Update anything that depends on the window position/size */ -static void nv10WindowMoved(nouveauContextPtr nmesa) -{ - GLcontext *ctx = nmesa->glCtx; - GLfloat *v = nmesa->viewport.m; - GLuint wX, wY, wW, wH; - - nv10WindowCoords(nmesa, ctx->Viewport.X, ctx->Viewport.Y, - ctx->Viewport.Width, ctx->Viewport.Height, - &wX, &wY, &wW, &wH); - - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 2); - OUT_RING((wW << 16) | wX); - OUT_RING((wH << 16) | wY); - - nv10ViewportScale(nmesa); - - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); -} - -/* Initialise any card-specific non-GL related state */ -static GLboolean nv10InitCard(nouveauContextPtr nmesa) -{ - int i; - GLfloat projection[16]; - - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); - - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY0, 2); - OUT_RING(NvDmaFB); /* 184 dma_in_memory0 */ - OUT_RING(NvDmaTT); /* 188 dma_in_memory1 */ - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY2, 2); - OUT_RING(NvDmaFB); /* 194 dma_in_memory2 */ - OUT_RING(NvDmaFB); /* 198 dma_in_memory3 */ - - /* 0x0 viewport size */ - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 2); - OUT_RING(0); - OUT_RING(0); - - /* Clipping regions */ - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE, 1); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, - NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 1); - OUT_RING(0x07ff0800); - BEGIN_RING_SIZE(NvSub3D, - NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(0), 1); - OUT_RING(0x07ff0800); - for (i=1; i<8; i++) { - BEGIN_RING_SIZE(NvSub3D, - NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(i), 1); - OUT_RING(0); - BEGIN_RING_SIZE(NvSub3D, - NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(i), 1); - OUT_RING(0); - } - - BEGIN_RING_SIZE(NvSub3D, 0x0290, 1); - OUT_RING(0x00100001); - BEGIN_RING_SIZE(NvSub3D, 0x03f4, 1); - OUT_RING(0); - - if (nmesa->screen->card->type >= NV_11) { - BEGIN_RING_SIZE(NvSub3D, 0x120, 3); - OUT_RING(0); - OUT_RING(1); - OUT_RING(2); - - BEGIN_RING_SIZE(NvSubImageBlit, 0x120, 3); - OUT_RING(0); - OUT_RING(1); - OUT_RING(2); - } - - /* Set state for stuff not initialized in nouveau_state.c */ - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_TX_ENABLE(0), 2); - OUT_RING (0); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA(0), 12); - OUT_RING (0x30141010); - OUT_RING (0); - OUT_RING (0x20040000); - OUT_RING (0); - OUT_RING (0); - OUT_RING (0); - OUT_RING (0x00000c00); - OUT_RING (0); - OUT_RING (0x00000c00); - OUT_RING (0x18000000); - OUT_RING (0x300e0300); - OUT_RING (0x0c091c80); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_WEIGHT_ENABLE, 1); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL, 1); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL, 1); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POINT_SIZE, 1); - OUT_RING (8); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE, 1); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LINE_WIDTH, 1); - OUT_RING (8); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(0), 8); - for (i=0;i<8;i++) { - OUT_RING (0); - } - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT, 3); - OUT_RINGf (-1.50); - OUT_RINGf (-0.09); - OUT_RINGf ( 0.00); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_MODE, 2); - OUT_RING (0x802); - OUT_RING (2); - - /* Projection and modelview matrix */ - memset(projection, 0, sizeof(projection)); - projection[0*4+0] = 1.0; - projection[1*4+1] = 1.0; - projection[2*4+2] = 1.0; - projection[3*4+3] = 1.0; - - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE, 1); - OUT_RING (6); /* enable projection and modelview0 matrix */ - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(0), 16); - for (i=0; i<16; i++) { - OUT_RINGf (projection[i]); - } - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_MODELVIEW0_MATRIX(0), 16); - for (i=0; i<16; i++) { - OUT_RINGf (projection[i]); - } - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2); - OUT_RINGf (0.0); - OUT_RINGf (1.0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X, 4); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - - /* Set per-vertex component */ - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R, 4); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R, 3); - OUT_RING (0); - OUT_RING (0); - OUT_RING (0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X, 3); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (1.0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S, 4); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (1.0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S, 4); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (1.0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_FOG_1F, 1); - OUT_RINGf (0.0); - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_EDGEFLAG_ENABLE, 1); - OUT_RING (1); - - return GL_TRUE; -} - -/* Update buffer offset/pitch/format */ -static GLboolean nv10BindBuffers(nouveauContextPtr nmesa, int num_color, - nouveau_renderbuffer_t **color, - nouveau_renderbuffer_t *depth) -{ - GLuint x, y, w, h; - GLuint pitch, format, depth_pitch; - - /* Store buffer pointers in context */ - nmesa->color_buffer = color[0]; - nmesa->depth_buffer = depth; - - w = color[0]->mesa.Width; - h = color[0]->mesa.Height; - x = nmesa->drawX; - y = nmesa->drawY; - - if (num_color != 1) - return GL_FALSE; - - BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 6); - OUT_RING((w << 16) | x); - OUT_RING((h << 16) | y); - depth_pitch = (depth ? depth->pitch : color[0]->pitch); - pitch = (depth_pitch<<16) | color[0]->pitch; - format = 0x108; - if (color[0]->mesa._ActualFormat != GL_RGBA8) { - format = 0x103; /* R5G6B5 color buffer */ - } - OUT_RING(format); - OUT_RING(pitch); - OUT_RING(color[0]->offset); - OUT_RING(depth ? depth->offset : color[0]->offset); - - return GL_TRUE; -} - -void nv10InitStateFuncs(GLcontext *ctx, struct dd_function_table *func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - func->AlphaFunc = nv10AlphaFunc; - func->BlendColor = nv10BlendColor; - func->BlendEquationSeparate = nv10BlendEquationSeparate; - func->BlendFuncSeparate = nv10BlendFuncSeparate; -/* func->Clear = nv10Clear;*/ /* Not for NV10 */ - func->ClearColor = nv10ClearColor; /* Not for NV10 */ - func->ClearDepth = nv10ClearDepth; /* Not for NV10 */ - func->ClearStencil = nv10ClearStencil; /* Not for NV10 */ - func->ClipPlane = nv10ClipPlane; - func->ColorMask = nv10ColorMask; - func->ColorMaterial = nv10ColorMaterial; - func->CullFace = nv10CullFace; - func->FrontFace = nv10FrontFace; - func->DepthFunc = nv10DepthFunc; - func->DepthMask = nv10DepthMask; - func->DepthRange = nv10DepthRange; - func->Enable = nv10Enable; - func->Fogfv = nv10Fogfv; - func->Hint = nv10Hint; - func->Lightfv = nv10Lightfv; -/* func->LightModelfv = nv10LightModelfv; */ - func->LineStipple = nv10LineStipple; /* Not for NV10 */ - func->LineWidth = nv10LineWidth; - func->LogicOpcode = nv10LogicOpcode; - func->PointParameterfv = nv10PointParameterfv; - func->PointSize = nv10PointSize; - func->PolygonMode = nv10PolygonMode; - func->PolygonOffset = nv10PolygonOffset; - func->PolygonStipple = nv10PolygonStipple; /* Not for NV10 */ -/* func->ReadBuffer = nv10ReadBuffer;*/ -/* func->RenderMode = nv10RenderMode;*/ - func->Scissor = nv10Scissor; - func->ShadeModel = nv10ShadeModel; - func->StencilFuncSeparate = nv10StencilFuncSeparate; - func->StencilMaskSeparate = nv10StencilMaskSeparate; - func->StencilOpSeparate = nv10StencilOpSeparate; -/* func->TexGen = nv10TexGen;*/ -/* func->TexParameter = nv10TexParameter;*/ - func->TextureMatrix = nv10TextureMatrix; - - nmesa->hw_func.InitCard = nv10InitCard; - nmesa->hw_func.BindBuffers = nv10BindBuffers; - nmesa->hw_func.WindowMoved = nv10WindowMoved; - nmesa->hw_func.UpdateProjectionMatrix = nv10UpdateProjectionMatrix; - nmesa->hw_func.UpdateModelviewMatrix = nv10UpdateModelviewMatrix; -} diff --git a/src/mesa/drivers/dri/nouveau/nv10_swtcl.c b/src/mesa/drivers/dri/nouveau/nv10_swtcl.c deleted file mode 100644 index a55d597ab42..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv10_swtcl.c +++ /dev/null @@ -1,714 +0,0 @@ -/* - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. - * Copyright 2006 Stephane Marchesin. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* Software TCL for NV10, NV20, NV30, NV40, NV50 */ - -#include <stdio.h> -#include <math.h> - -#include "glheader.h" -#include "context.h" -#include "mtypes.h" -#include "macros.h" -#include "colormac.h" -#include "enums.h" - -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "tnl/t_context.h" -#include "tnl/t_pipeline.h" - -#include "nouveau_swtcl.h" -#include "nv10_swtcl.h" -#include "nouveau_context.h" -#include "nouveau_span.h" -#include "nouveau_reg.h" -#include "nouveau_tex.h" -#include "nouveau_fifo.h" -#include "nouveau_msg.h" -#include "nouveau_object.h" - -static void nv10RasterPrimitive( GLcontext *ctx, GLenum rprim, GLuint hwprim ); -static void nv10RenderPrimitive( GLcontext *ctx, GLenum prim ); -static void nv10ResetLineStipple( GLcontext *ctx ); - -static const int default_attr_size[8]={3,3,3,4,3,1,4,4}; - -/* Mesa requires us to put pos attribute as the first attribute of the - * vertex, but on NV10 it is the last attribute. - * To fix that we put the pos attribute first, and we swap the pos - * attribute before sending it to the card. - * Speed cost of the swap seems negligeable - */ -#if 0 -/* old stuff where pos attribute isn't put first for mesa. - * Usefull for speed comparaison - */ -#define INV_VERT(i) i -#define OUT_RING_VERTp(nmesa, ptr,sz, vertex_size) OUT_RINGp(ptr,sz) -#define OUT_RING_VERT(nmesa, ptr, vertex_size) OUT_RINGp(ptr,vertex_size) -#else - -#define INV_VERT(i) (i==0?7:i-1) - -#define OUT_RING_VERT_RAW(ptr,vertex_size) do{ \ - /* if the vertex size is not null, we have at least pos attribute */ \ - OUT_RINGp((GLfloat *)(ptr) + default_attr_size[_TNL_ATTRIB_POS], (vertex_size) - default_attr_size[_TNL_ATTRIB_POS]); \ - OUT_RINGp((GLfloat *)(ptr), default_attr_size[_TNL_ATTRIB_POS]); \ -}while(0) - -#define OUT_RING_VERT(nmesa,ptr,vertex_size) do{ \ - if (nmesa->screen->card->type>=NV_20) \ - OUT_RINGp(ptr, vertex_size); \ - else \ - OUT_RING_VERT_RAW(ptr, vertex_size); \ -}while(0) - - -#define OUT_RING_VERTp(nmesa, ptr,sz, vertex_size) do{ \ - int nb_vert; \ - if (nmesa->screen->card->type>=NV_20) \ - OUT_RINGp(ptr, sz); \ - else \ - for (nb_vert = 0; nb_vert < (sz)/(vertex_size); nb_vert++) { \ - OUT_RING_VERT_RAW((GLfloat*)(ptr)+nb_vert*(vertex_size), vertex_size); \ - } \ -}while(0) - -#endif - - -static INLINE void nv10StartPrimitive(struct nouveau_context* nmesa,GLuint primitive,GLuint size) -{ - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) - BEGIN_RING_SIZE(NvSub3D,NV10_TCL_PRIMITIVE_3D_BEGIN_END,1); - else if (nmesa->screen->card->type==NV_20) - BEGIN_RING_SIZE(NvSub3D,NV20_TCL_PRIMITIVE_3D_BEGIN_END,1); - else - BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_BEGIN_END,1); - OUT_RING(primitive); - - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) - BEGIN_RING_SIZE(NvSub3D,NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_DATA|NONINC_METHOD,size); - else if (nmesa->screen->card->type==NV_20) - BEGIN_RING_SIZE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VERTEX_DATA|NONINC_METHOD,size); - else - BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_DATA|NONINC_METHOD,size); -} - -void nv10FinishPrimitive(struct nouveau_context *nmesa) -{ - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) - BEGIN_RING_SIZE(NvSub3D,NV10_TCL_PRIMITIVE_3D_BEGIN_END,1); - else if (nmesa->screen->card->type==NV_20) - BEGIN_RING_SIZE(NvSub3D,NV20_TCL_PRIMITIVE_3D_BEGIN_END,1); - else - BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_BEGIN_END,1); - OUT_RING(0x0); - FIRE_RING(); -} - - -static INLINE void nv10ExtendPrimitive(struct nouveau_context* nmesa, int size) -{ - /* make sure there's enough room. if not, wait */ - if (RING_AVAILABLE()<size) - { - WAIT_RING(nmesa,size); - } -} - -/**********************************************************************/ -/* Render unclipped begin/end objects */ -/**********************************************************************/ - -static INLINE void nv10_render_generic_primitive_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags,GLuint prim) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *vertptr = (GLfloat *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - GLuint size_dword = vertsize*(count-start); - - nv10ExtendPrimitive(nmesa, size_dword); - nv10StartPrimitive(nmesa,prim+1,size_dword); - OUT_RING_VERTp(nmesa, (nouveauVertex*)(vertptr+(start*vertsize)),size_dword, vertsize); - nv10FinishPrimitive(nmesa); -} - -static void nv10_render_points_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_POINTS); -} - -static void nv10_render_lines_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_LINES); -} - -static void nv10_render_line_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_LINE_STRIP); -} - -static void nv10_render_line_loop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_LINE_LOOP); -} - -static void nv10_render_triangles_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_TRIANGLES); -} - -static void nv10_render_tri_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_TRIANGLE_STRIP); -} - -static void nv10_render_tri_fan_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_TRIANGLE_FAN); -} - -static void nv10_render_quads_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_QUADS); -} - -static void nv10_render_quad_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_QUAD_STRIP); -} - -static void nv10_render_poly_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_POLYGON); -} - -static void nv10_render_noop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ -} - -static void (*nv10_render_tab_verts[GL_POLYGON+2])(GLcontext *, - GLuint, - GLuint, - GLuint) = -{ - nv10_render_points_verts, - nv10_render_lines_verts, - nv10_render_line_loop_verts, - nv10_render_line_strip_verts, - nv10_render_triangles_verts, - nv10_render_tri_strip_verts, - nv10_render_tri_fan_verts, - nv10_render_quads_verts, - nv10_render_quad_strip_verts, - nv10_render_poly_verts, - nv10_render_noop_verts, -}; - - -static INLINE void nv10_render_generic_primitive_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags,GLuint prim) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *vertptr = (GLfloat *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - GLuint size_dword = vertsize*(count-start); - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; - GLuint j; - - nv10ExtendPrimitive(nmesa, size_dword); - nv10StartPrimitive(nmesa,prim+1,size_dword); - for (j=start; j<count; j++ ) { - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(elt[j]*vertsize)),vertsize); - } - nv10FinishPrimitive(nmesa); -} - -static void nv10_render_points_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_POINTS); -} - -static void nv10_render_lines_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_LINES); -} - -static void nv10_render_line_strip_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_LINE_STRIP); -} - -static void nv10_render_line_loop_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_LINE_LOOP); -} - -static void nv10_render_triangles_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_TRIANGLES); -} - -static void nv10_render_tri_strip_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_TRIANGLE_STRIP); -} - -static void nv10_render_tri_fan_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_TRIANGLE_FAN); -} - -static void nv10_render_quads_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_QUADS); -} - -static void nv10_render_quad_strip_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_QUAD_STRIP); -} - -static void nv10_render_poly_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ - nv10_render_generic_primitive_elts(ctx,start,count,flags,GL_POLYGON); -} - -static void nv10_render_noop_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags) -{ -} - -static void (*nv10_render_tab_elts[GL_POLYGON+2])(GLcontext *, - GLuint, - GLuint, - GLuint) = -{ - nv10_render_points_elts, - nv10_render_lines_elts, - nv10_render_line_loop_elts, - nv10_render_line_strip_elts, - nv10_render_triangles_elts, - nv10_render_tri_strip_elts, - nv10_render_tri_fan_elts, - nv10_render_quads_elts, - nv10_render_quad_strip_elts, - nv10_render_poly_elts, - nv10_render_noop_elts, -}; - - -/**********************************************************************/ -/* Choose render functions */ -/**********************************************************************/ - - -#define EMIT_ATTR( ATTR, STYLE ) \ -do { \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].attrib = (ATTR); \ - nmesa->vertex_attrs[nmesa->vertex_attr_count].format = (STYLE); \ - nmesa->vertex_attr_count++; \ -} while (0) - -static INLINE void nv10_render_point(GLcontext *ctx, GLfloat *vertptr) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLuint vertsize = nmesa->vertex_size; - GLuint size_dword = vertsize; - - nv10ExtendPrimitive(nmesa, size_dword); - nv10StartPrimitive(nmesa,GL_POINTS+1,size_dword); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr),vertsize); - nv10FinishPrimitive(nmesa); -} - -static INLINE void nv10_render_points(GLcontext *ctx,GLuint first,GLuint last) -{ - struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *vertptr = (GLfloat *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - GLuint i; - - if (VB->Elts) { - for (i = first; i < last; i++) - if (VB->ClipMask[VB->Elts[i]] == 0) - nv10_render_point(ctx, vertptr + (VB->Elts[i]*vertsize)); - } - else { - for (i = first; i < last; i++) - if (VB->ClipMask[i] == 0) - nv10_render_point(ctx, vertptr + (i*vertsize)); - } -} - -static INLINE void nv10_render_line(GLcontext *ctx,GLuint v1,GLuint v2) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *vertptr = (GLfloat *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - GLuint size_dword = vertsize*2; - - nv10ExtendPrimitive(nmesa, size_dword); - nv10StartPrimitive(nmesa,GL_LINES+1,size_dword); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v1*vertsize)),vertsize); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v2*vertsize)),vertsize); - nv10FinishPrimitive(nmesa); -} - -static INLINE void nv10_render_triangle(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *vertptr = (GLfloat *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - GLuint size_dword = vertsize*3; - - nv10ExtendPrimitive(nmesa, size_dword); - nv10StartPrimitive(nmesa,GL_TRIANGLES+1,size_dword); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v1*vertsize)),vertsize); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v2*vertsize)),vertsize); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v3*vertsize)),vertsize); - nv10FinishPrimitive(nmesa); -} - -static INLINE void nv10_render_quad(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3,GLuint v4) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *vertptr = (GLfloat *)nmesa->verts; - GLuint vertsize = nmesa->vertex_size; - GLuint size_dword = vertsize*4; - - nv10ExtendPrimitive(nmesa, size_dword); - nv10StartPrimitive(nmesa,GL_QUADS+1,size_dword); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v1*vertsize)),vertsize); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v2*vertsize)),vertsize); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v3*vertsize)),vertsize); - OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v4*vertsize)),vertsize); - nv10FinishPrimitive(nmesa); -} - - - -static void nv10ChooseRenderState(GLcontext *ctx) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - - tnl->Driver.Render.PrimTabVerts = nv10_render_tab_verts; - tnl->Driver.Render.PrimTabElts = nv10_render_tab_elts; - tnl->Driver.Render.ClippedLine = _tnl_RenderClippedLine; - tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; - tnl->Driver.Render.Points = nv10_render_points; - tnl->Driver.Render.Line = nv10_render_line; - tnl->Driver.Render.Triangle = nv10_render_triangle; - tnl->Driver.Render.Quad = nv10_render_quad; -} - - - -static INLINE void nv10OutputVertexFormat(struct nouveau_context* nmesa) -{ - GLcontext* ctx=nmesa->glCtx; - TNLcontext *tnl = TNL_CONTEXT(ctx); - DECLARE_RENDERINPUTS(index); - struct vertex_buffer *VB = &tnl->vb; - int attr_size[16]; - const int nv10_vtx_attribs[8]={ - _TNL_ATTRIB_FOG, _TNL_ATTRIB_WEIGHT, - _TNL_ATTRIB_NORMAL, _TNL_ATTRIB_TEX1, - _TNL_ATTRIB_TEX0, _TNL_ATTRIB_COLOR1, - _TNL_ATTRIB_COLOR0, _TNL_ATTRIB_POS - }; - int i; - int slots=0; - int total_size=0; - - nmesa->vertex_attr_count = 0; - RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset); - - /* - * Determine attribute sizes - */ - for(i=0;i<8;i++) - { - if (RENDERINPUTS_TEST(index, i)) - attr_size[i]=default_attr_size[i]; - else - attr_size[i]=0; - } - for(i=8;i<16;i++) - { - if (RENDERINPUTS_TEST(index, i)) - attr_size[i]=VB->TexCoordPtr[i-8]->size; - else - attr_size[i]=0; - } - - /* - * Tell t_vertex about the vertex format - */ - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) { - for(i=0;i<8;i++) { - int j = nv10_vtx_attribs[INV_VERT(i)]; - if (RENDERINPUTS_TEST(index, j)) { - switch(attr_size[j]) - { - case 1: - EMIT_ATTR(j,EMIT_1F); - break; - case 2: - EMIT_ATTR(j,EMIT_2F); - break; - case 3: - EMIT_ATTR(j,EMIT_3F); - break; - case 4: - EMIT_ATTR(j,EMIT_4F); - break; - } - total_size+=attr_size[j]; - } - } - } else { - for(i=0;i<16;i++) - { - if (RENDERINPUTS_TEST(index, i)) - { - slots=i+1; - switch(attr_size[i]) - { - case 1: - EMIT_ATTR(i,EMIT_1F); - break; - case 2: - EMIT_ATTR(i,EMIT_2F); - break; - case 3: - EMIT_ATTR(i,EMIT_3F); - break; - case 4: - EMIT_ATTR(i,EMIT_4F); - break; - } - if (i==_TNL_ATTRIB_COLOR0) - nmesa->color_offset=total_size; - if (i==_TNL_ATTRIB_COLOR1) - nmesa->specular_offset=total_size; - total_size+=attr_size[i]; - } - } - } - - nmesa->vertex_size=_tnl_install_attrs( ctx, - nmesa->vertex_attrs, - nmesa->vertex_attr_count, - NULL, 0 ); - /* OUT_RINGp wants size in DWORDS */ - nmesa->vertex_size = nmesa->vertex_size / 4; - assert(nmesa->vertex_size==total_size); - - /* - * Tell the hardware about the vertex format - */ - if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) { - int total_stride = 0; - -#define NV_VERTEX_ATTRIBUTE_TYPE_FLOAT 2 - - for(i=0;i<8;i++) { - int j = nv10_vtx_attribs[i]; - int size; - int stride = attr_size[j] << 2; - if (j==_TNL_ATTRIB_POS) { - stride += total_stride; - } - size = attr_size[j] << 4; - size |= stride << 8; - size |= NV_VERTEX_ATTRIBUTE_TYPE_FLOAT; - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR((7-i)),1); - OUT_RING_CACHE(size); - total_stride += stride; - } - - BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_VALIDATE,1); - OUT_RING_CACHE(0); - } else if (nmesa->screen->card->type==NV_20) { - for(i=0;i<16;i++) - { - int size=attr_size[i]; - BEGIN_RING_CACHE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR(i),1); - OUT_RING_CACHE(NV_VERTEX_ATTRIBUTE_TYPE_FLOAT|(size*0x10)); - } - } else { - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DO_VERTICES, 1); - OUT_RING(0); - BEGIN_RING_CACHE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0,slots); - for(i=0;i<slots;i++) - { - int size=attr_size[i]; - OUT_RING_CACHE(NV_VERTEX_ATTRIBUTE_TYPE_FLOAT|(size*0x10)); - } - // FIXME this is probably not needed - BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0,1); - OUT_RING(0); - BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0,1); - OUT_RING(0); - BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0,1); - OUT_RING(0); - } -} - - -static void nv10ChooseVertexState( GLcontext *ctx ) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - DECLARE_RENDERINPUTS(index); - - RENDERINPUTS_COPY(index, tnl->render_inputs_bitset); - if (!RENDERINPUTS_EQUAL(index, nmesa->render_inputs_bitset)) - { - RENDERINPUTS_COPY(nmesa->render_inputs_bitset, index); - nv10OutputVertexFormat(nmesa); - } - - if (nmesa->screen->card->type == NV_30) { - nouveauShader *fp; - - if (ctx->FragmentProgram.Enabled) { - fp = (nouveauShader *) ctx->FragmentProgram.Current; - nvsUpdateShader(ctx, fp); - } else - nvsUpdateShader(ctx, nmesa->passthrough_fp); - } - - if (nmesa->screen->card->type >= NV_40) { - /* Ensure passthrough shader is being used, and mvp matrix - * is up to date - */ - nvsUpdateShader(ctx, nmesa->passthrough_vp); - - /* Update texenv shader / user fragprog */ - nvsUpdateShader(ctx, (nouveauShader*)ctx->FragmentProgram._Current); - } -} - - -/**********************************************************************/ -/* High level hooks for t_vb_render.c */ -/**********************************************************************/ - - -static void nv10RenderStart(GLcontext *ctx) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - - if (nmesa->new_state) { - nmesa->new_render_state |= nmesa->new_state; - } - - if (nmesa->new_render_state) { - nv10ChooseVertexState(ctx); - nv10ChooseRenderState(ctx); - nmesa->new_render_state = 0; - } -} - -static void nv10RenderFinish(GLcontext *ctx) -{ -} - - -/* System to flush dma and emit state changes based on the rasterized - * primitive. - */ -void nv10RasterPrimitive(GLcontext *ctx, - GLenum glprim, - GLuint hwprim) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - - assert (!nmesa->new_state); - - if (hwprim != nmesa->current_primitive) - { - nmesa->current_primitive=hwprim; - - } -} - -static const GLuint hw_prim[GL_POLYGON+1] = { - GL_POINTS+1, - GL_LINES+1, - GL_LINE_STRIP+1, - GL_LINE_LOOP+1, - GL_TRIANGLES+1, - GL_TRIANGLE_STRIP+1, - GL_TRIANGLE_FAN+1, - GL_QUADS+1, - GL_QUAD_STRIP+1, - GL_POLYGON+1 -}; - -/* Callback for mesa: - */ -static void nv10RenderPrimitive( GLcontext *ctx, GLuint prim ) -{ - nv10RasterPrimitive( ctx, prim, hw_prim[prim] ); -} - -static void nv10ResetLineStipple( GLcontext *ctx ) -{ - /* FIXME do something here */ - WARN_ONCE("Unimplemented nv10ResetLineStipple\n"); -} - - -/**********************************************************************/ -/* Initialization. */ -/**********************************************************************/ - -void nv10TriInitFunctions(GLcontext *ctx) -{ - struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - - tnl->Driver.RunPipeline = nouveauRunPipeline; - tnl->Driver.Render.Start = nv10RenderStart; - tnl->Driver.Render.Finish = nv10RenderFinish; - tnl->Driver.Render.PrimitiveNotify = nv10RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = nv10ResetLineStipple; - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, - 64 * sizeof(GLfloat) ); - - nmesa->verts = (GLubyte *)tnl->clipspace.vertex_buf; -} - - diff --git a/src/mesa/drivers/dri/nouveau/nv10_swtcl.h b/src/mesa/drivers/dri/nouveau/nv10_swtcl.h deleted file mode 100644 index 7c854addd2d..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv10_swtcl.h +++ /dev/null @@ -1,40 +0,0 @@ -/************************************************************************** - -Copyright 2006 Stephane Marchesin -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - - - -#ifndef __NV10_SWTCL_H__ -#define __NV10_SWTCL_H__ - -#include "mtypes.h" - -extern void nv10Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ); -extern void nv10FinishPrimitive(struct nouveau_context *nmesa); -extern void nv10TriInitFunctions(GLcontext *ctx); -#define FALLBACK( nmesa, bit, mode ) nouveauFallback( nmesa->glCtx, bit, mode ) - -#endif /* __NV10_SWTCL_H__ */ - diff --git a/src/mesa/drivers/dri/nouveau/nv20_shader.h b/src/mesa/drivers/dri/nouveau/nv20_shader.h deleted file mode 100644 index 7d2e29db668..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv20_shader.h +++ /dev/null @@ -1,121 +0,0 @@ -/* NV20_TCL_PRIMITIVE_3D_0x0B00 */ -#define NV20_VP_INST_0B00 0x00000000 /* always 0? */ -#define NV20_VP_INST0_KNOWN 0 - -/* NV20_TCL_PRIMITIVE_3D_0x0B04 */ -#define NV20_VP_INST_SCA_OPCODE_SHIFT 25 -#define NV20_VP_INST_SCA_OPCODE_MASK (0x0F << 25) -#define NV20_VP_INST_OPCODE_RCP 0x2 -#define NV20_VP_INST_OPCODE_RCC 0x3 -#define NV20_VP_INST_OPCODE_RSQ 0x4 -#define NV20_VP_INST_OPCODE_EXP 0x5 -#define NV20_VP_INST_OPCODE_LOG 0x6 -#define NV20_VP_INST_OPCODE_LIT 0x7 -#define NV20_VP_INST_VEC_OPCODE_SHIFT 21 -#define NV20_VP_INST_VEC_OPCODE_MASK (0x0F << 21) -#define NV20_VP_INST_OPCODE_NOP 0x0 /* guess */ -#define NV20_VP_INST_OPCODE_MOV 0x1 -#define NV20_VP_INST_OPCODE_MUL 0x2 -#define NV20_VP_INST_OPCODE_ADD 0x3 -#define NV20_VP_INST_OPCODE_MAD 0x4 -#define NV20_VP_INST_OPCODE_DP3 0x5 -#define NV20_VP_INST_OPCODE_DPH 0x6 -#define NV20_VP_INST_OPCODE_DP4 0x7 -#define NV20_VP_INST_OPCODE_DST 0x8 -#define NV20_VP_INST_OPCODE_MIN 0x9 -#define NV20_VP_INST_OPCODE_MAX 0xA -#define NV20_VP_INST_OPCODE_SLT 0xB -#define NV20_VP_INST_OPCODE_SGE 0xC -#define NV20_VP_INST_OPCODE_ARL 0xD -#define NV20_VP_INST_CONST_SRC_SHIFT 13 -#define NV20_VP_INST_CONST_SRC_MASK (0xFF << 13) -#define NV20_VP_INST_INPUT_SRC_SHIFT 9 -#define NV20_VP_INST_INPUT_SRC_MASK (0xF << 9) /* guess */ -#define NV20_VP_INST_INPUT_SRC_POS 0 -#define NV20_VP_INST_INPUT_SRC_COL0 3 -#define NV20_VP_INST_INPUT_SRC_COL1 4 -#define NV20_VP_INST_INPUT_SRC_TC(n) (9+n) -#define NV20_VP_INST_SRC0H_SHIFT 0 -#define NV20_VP_INST_SRC0H_MASK (0x1FF << 0) -#define NV20_VP_INST1_KNOWN ( \ - NV20_VP_INST_OPCODE_MASK | \ - NV20_VP_INST_CONST_SRC_MASK | \ - NV20_VP_INST_INPUT_SRC_MASK | \ - NV20_VP_INST_SRC0H_MASK \ - ) - -/* NV20_TCL_PRIMITIVE_3D_0x0B08 */ -#define NV20_VP_INST_SRC0L_SHIFT 26 -#define NV20_VP_INST_SRC0L_MASK (0x3F <<26) -#define NV20_VP_INST_SRC1_SHIFT 11 -#define NV20_VP_INST_SRC1_MASK (0x7FFF<<11) -#define NV20_VP_INST_SRC2H_SHIFT 0 -#define NV20_VP_INST_SRC2H_MASK (0x7FF << 0) - -/* NV20_TCL_PRIMITIVE_3D_0x0B0C */ -#define NV20_VP_INST_SRC2L_SHIFT 28 -#define NV20_VP_INST_SRC2L_MASK (0x0F <<28) -#define NV20_VP_INST_VTEMP_WRITEMASK_SHIFT 24 -#define NV20_VP_INST_VTEMP_WRITEMASK_MASK (0x0F <<24) -# define NV20_VP_INST_TEMP_WRITEMASK_X (1<<27) -# define NV20_VP_INST_TEMP_WRITEMASK_Y (1<<26) -# define NV20_VP_INST_TEMP_WRITEMASK_Z (1<<25) -# define NV20_VP_INST_TEMP_WRITEMASK_W (1<<24) -#define NV20_VP_INST_DEST_TEMP_ID_SHIFT 20 -#define NV20_VP_INST_DEST_TEMP_ID_MASK (0x0F <<20) -#define NV20_VP_INST_STEMP_WRITEMASK_SHIFT 16 -#define NV20_VP_INST_STEMP_WRITEMASK_MASK (0x0F <<16) -# define NV20_VP_INST_STEMP_WRITEMASK_X (1<<19) -# define NV20_VP_INST_STEMP_WRITEMASK_Y (1<<18) -# define NV20_VP_INST_STEMP_WRITEMASK_Z (1<<17) -# define NV20_VP_INST_STEMP_WRITEMASK_W (1<<16) -#define NV20_VP_INST_DEST_WRITEMASK_SHIFT 12 -#define NV20_VP_INST_DEST_WRITEMASK_MASK (0x0F <<12) -# define NV20_VP_INST_DEST_WRITEMASK_X (1<<15) -# define NV20_VP_INST_DEST_WRITEMASK_Y (1<<14) -# define NV20_VP_INST_DEST_WRITEMASK_Z (1<<13) -# define NV20_VP_INST_DEST_WRITEMASK_W (1<<12) -#define NV20_VP_INST_DEST_SHIFT 3 -#define NV20_VP_INST_DEST_MASK (0xF << 3) /* guess */ -#define NV20_VP_INST_DEST_POS 0 -#define NV20_VP_INST_DEST_COL0 3 -#define NV20_VP_INST_DEST_COL1 4 -#define NV20_VP_INST_DEST_TC(n) (9+n) -#define NV20_VP_INST_INDEX_CONST (1<<1) -#define NV20_VP_INST3_KNOWN ( \ - NV20_VP_INST_SRC2L_MASK | \ - NV20_VP_INST_TEMP_WRITEMASK_MASK | \ - NV20_VP_INST_DEST_TEMP_ID_MASK | \ - NV20_VP_INST_STEMP_WRITEMASK_MASK | \ - NV20_VP_INST_DEST_WRITEMASK_MASK | \ - NV20_VP_INST_DEST_MASK | \ - NV20_VP_INST_INDEX_CONST \ - ) - -/* Useful to split the source selection regs into their pieces */ -#define NV20_VP_SRC0_HIGH_SHIFT 6 -#define NV20_VP_SRC0_HIGH_MASK 0x00007FC0 -#define NV20_VP_SRC0_LOW_MASK 0x0000003F -#define NV20_VP_SRC2_HIGH_SHIFT 4 -#define NV20_VP_SRC2_HIGH_MASK 0x00007FF0 -#define NV20_VP_SRC2_LOW_MASK 0x0000000F - -#define NV20_VP_SRC_REG_NEGATE (1<<14) -#define NV20_VP_SRC_REG_SWZ_X_SHIFT 12 -#define NV20_VP_SRC_REG_SWZ_X_MASK (0x03 <<12) -#define NV20_VP_SRC_REG_SWZ_Y_SHIFT 10 -#define NV20_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10) -#define NV20_VP_SRC_REG_SWZ_Z_SHIFT 8 -#define NV20_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8) -#define NV20_VP_SRC_REG_SWZ_W_SHIFT 6 -#define NV20_VP_SRC_REG_SWZ_W_MASK (0x03 << 6) -#define NV20_VP_SRC_REG_SWZ_ALL_SHIFT 6 -#define NV20_VP_SRC_REG_SWZ_ALL_MASK (0xFF << 6) -#define NV20_VP_SRC_REG_TEMP_ID_SHIFT 2 -#define NV20_VP_SRC_REG_TEMP_ID_MASK (0x0F << 0) -#define NV20_VP_SRC_REG_TYPE_SHIFT 0 -#define NV20_VP_SRC_REG_TYPE_MASK (0x03 << 0) -#define NV20_VP_SRC_REG_TYPE_TEMP 1 -#define NV20_VP_SRC_REG_TYPE_INPUT 2 -#define NV20_VP_SRC_REG_TYPE_CONST 3 /* guess */ - diff --git a/src/mesa/drivers/dri/nouveau/nv20_state.c b/src/mesa/drivers/dri/nouveau/nv20_state.c deleted file mode 100644 index 6b583980a49..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv20_state.c +++ /dev/null @@ -1,824 +0,0 @@ -/************************************************************************** - -Copyright 2006 Nouveau -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" - -#include "tnl/t_pipeline.h" - -#include "mtypes.h" -#include "colormac.h" - -static void nv20AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte ubRef; - CLAMPED_FLOAT_TO_UBYTE(ubRef, ref); - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC, 2); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ubRef); -} - -static void nv20BlendColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte cf[4]; - - CLAMPED_FLOAT_TO_UBYTE(cf[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(cf[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(cf[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(cf[3], color[3]); - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_COLOR, 1); - OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0])); -} - -static void nv20BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION, 1); - OUT_RING_CACHE((modeA<<16) | modeRGB); -} - - -static void nv20BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC, 2); - OUT_RING_CACHE((sfactorA<<16) | sfactorRGB); - OUT_RING_CACHE((dfactorA<<16) | dfactorRGB); -} - -static void nv20Clear(GLcontext *ctx, GLbitfield mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLuint hw_bufs = 0; - - if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT)) - hw_bufs |= 0xf0; - if (mask & (BUFFER_BIT_DEPTH)) - hw_bufs |= 0x03; - - if (hw_bufs) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS, 1); - OUT_RING_CACHE(hw_bufs); - } -} - -static void nv20ClearColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte c[4]; - UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,color); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB, 1); - OUT_RING_CACHE(PACK_COLOR_8888(c[3],c[0],c[1],c[2])); -} - -static void nv20ClearDepth(GLcontext *ctx, GLclampd d) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nmesa->clear_value=((nmesa->clear_value&0x000000FF)|(((uint32_t)(d*0xFFFFFF))<<8)); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1); - OUT_RING_CACHE(nmesa->clear_value); -} - -/* we're don't support indexed buffers - void (*ClearIndex)(GLcontext *ctx, GLuint index) - */ - -static void nv20ClearStencil(GLcontext *ctx, GLint s) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nmesa->clear_value=((nmesa->clear_value&0xFFFFFF00)|(s&0x000000FF)); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1); - OUT_RING_CACHE(nmesa->clear_value); -} - -static void nv20ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_A(plane), 4); - OUT_RING_CACHEf(equation[0]); - OUT_RING_CACHEf(equation[1]); - OUT_RING_CACHEf(equation[2]); - OUT_RING_CACHEf(equation[3]); -} - -static void nv20ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask, - GLboolean bmask, GLboolean amask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_COLOR_MASK, 1); - OUT_RING_CACHE(((amask && 0x01) << 24) | ((rmask && 0x01) << 16) | ((gmask && 0x01)<< 8) | ((bmask && 0x01) << 0)); -} - -static void nv20ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode) -{ - // TODO I need love -} - -static void nv20CullFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CULL_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv20FrontFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_FRONT_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv20DepthFunc(GLcontext *ctx, GLenum func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1); - OUT_RING_CACHE(func); -} - -static void nv20DepthMask(GLcontext *ctx, GLboolean flag) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1); - OUT_RING_CACHE(flag); -} - -static void nv20DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2); - OUT_RING_CACHEf(nearval); - OUT_RING_CACHEf(farval); -} - -/** Specify the current buffer for writing */ -//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer ); -/** Specify the buffers for writing for fragment programs*/ -//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers ); - -static void nv20Enable(GLcontext *ctx, GLenum cap, GLboolean state) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - switch(cap) - { - case GL_ALPHA_TEST: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_AUTO_NORMAL: - case GL_BLEND: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_CLIP_PLANE0: - case GL_CLIP_PLANE1: - case GL_CLIP_PLANE2: - case GL_CLIP_PLANE3: - case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(cap-GL_CLIP_PLANE0), 1); - OUT_RING_CACHE(state); - break; - case GL_COLOR_LOGIC_OP: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_COLOR_MATERIAL: -// case GL_COLOR_SUM_EXT: -// case GL_COLOR_TABLE: -// case GL_CONVOLUTION_1D: -// case GL_CONVOLUTION_2D: - case GL_CULL_FACE: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DEPTH_TEST: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DITHER: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DITHER_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_FOG: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_FOG_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_HISTOGRAM: -// case GL_INDEX_LOGIC_OP: - case GL_LIGHT0: - case GL_LIGHT1: - case GL_LIGHT2: - case GL_LIGHT3: - case GL_LIGHT4: - case GL_LIGHT5: - case GL_LIGHT6: - case GL_LIGHT7: - { - uint32_t mask=0x11<<(2*(cap-GL_LIGHT0)); - nmesa->enabled_lights=((nmesa->enabled_lights&mask)|(mask*state)); - if (nmesa->lighting_enabled) - { - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1); - OUT_RING_CACHE(nmesa->enabled_lights); - } - break; - } - case GL_LIGHTING: - nmesa->lighting_enabled=state; - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1); - if (nmesa->lighting_enabled) - OUT_RING_CACHE(nmesa->enabled_lights); - else - OUT_RING_CACHE(0x0); - break; - case GL_LINE_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_LINE_STIPPLE: -// case GL_MAP1_COLOR_4: -// case GL_MAP1_INDEX: -// case GL_MAP1_NORMAL: -// case GL_MAP1_TEXTURE_COORD_1: -// case GL_MAP1_TEXTURE_COORD_2: -// case GL_MAP1_TEXTURE_COORD_3: -// case GL_MAP1_TEXTURE_COORD_4: -// case GL_MAP1_VERTEX_3: -// case GL_MAP1_VERTEX_4: -// case GL_MAP2_COLOR_4: -// case GL_MAP2_INDEX: -// case GL_MAP2_NORMAL: -// case GL_MAP2_TEXTURE_COORD_1: -// case GL_MAP2_TEXTURE_COORD_2: -// case GL_MAP2_TEXTURE_COORD_3: -// case GL_MAP2_TEXTURE_COORD_4: -// case GL_MAP2_VERTEX_3: -// case GL_MAP2_VERTEX_4: -// case GL_MINMAX: - case GL_NORMALIZE: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_POINT_SMOOTH: - case GL_POLYGON_OFFSET_POINT: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_LINE: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_FILL: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_STIPPLE: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_POST_COLOR_MATRIX_COLOR_TABLE: -// case GL_POST_CONVOLUTION_COLOR_TABLE: -// case GL_RESCALE_NORMAL: - case GL_SCISSOR_TEST: - /* No enable bit, nv20Scissor will adjust to max range */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - break; -// case GL_SEPARABLE_2D: - case GL_STENCIL_TEST: - // TODO BACK and FRONT ? - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_TEXTURE_GEN_Q: -// case GL_TEXTURE_GEN_R: -// case GL_TEXTURE_GEN_S: -// case GL_TEXTURE_GEN_T: -// case GL_TEXTURE_1D: -// case GL_TEXTURE_2D: -// case GL_TEXTURE_3D: - } -} - -static void nv20Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - switch(pname) - { - case GL_FOG_MODE: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_FOG_MODE, 1); - //OUT_RING_CACHE (params); - break; - /* TODO: unsure about the rest.*/ - default: - break; - } - -} - -static void nv20Hint(GLcontext *ctx, GLenum target, GLenum mode) -{ - // TODO I need love (fog and line_smooth hints) -} - -// void (*IndexMask)(GLcontext *ctx, GLuint mask); - -enum { - SPOTLIGHT_NO_UPDATE, - SPOTLIGHT_UPDATE_EXPONENT, - SPOTLIGHT_UPDATE_DIRECTION, - SPOTLIGHT_UPDATE_ALL -}; - -static void nv20Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLint p = light - GL_LIGHT0; - struct gl_light *l = &ctx->Light.Light[p]; - int spotlight_update = SPOTLIGHT_NO_UPDATE; - - /* not sure where the fourth param value goes...*/ - switch(pname) - { - case GL_AMBIENT: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_DIFFUSE: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_SPECULAR: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_POSITION: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_SPOT_DIRECTION: - spotlight_update = SPOTLIGHT_UPDATE_DIRECTION; - break; - case GL_SPOT_EXPONENT: - spotlight_update = SPOTLIGHT_UPDATE_EXPONENT; - break; - case GL_SPOT_CUTOFF: - spotlight_update = SPOTLIGHT_UPDATE_ALL; - break; - case GL_CONSTANT_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - case GL_LINEAR_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - case GL_QUADRATIC_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - default: - break; - } - - switch(spotlight_update) { - case SPOTLIGHT_UPDATE_DIRECTION: - { - GLfloat x,y,z; - GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0); - x = spot_light_coef_a * l->_NormDirection[0]; - y = spot_light_coef_a * l->_NormDirection[1]; - z = spot_light_coef_a * l->_NormDirection[2]; - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(p), 3); - OUT_RING_CACHEf(x); - OUT_RING_CACHEf(y); - OUT_RING_CACHEf(z); - } - break; - case SPOTLIGHT_UPDATE_EXPONENT: - { - GLfloat cc,lc,qc; - cc = 1.0; /* FIXME: These need to be correctly computed */ - lc = 0.0; - qc = 2.0; - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 3); - OUT_RING_CACHEf(cc); - OUT_RING_CACHEf(lc); - OUT_RING_CACHEf(qc); - } - break; - case SPOTLIGHT_UPDATE_ALL: - { - GLfloat cc,lc,qc, x,y,z, c; - GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0); - cc = 1.0; /* FIXME: These need to be correctly computed */ - lc = 0.0; - qc = 2.0; - x = spot_light_coef_a * l->_NormDirection[0]; - y = spot_light_coef_a * l->_NormDirection[1]; - z = spot_light_coef_a * l->_NormDirection[2]; - c = spot_light_coef_a + 1.0; - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 7); - OUT_RING_CACHEf(cc); - OUT_RING_CACHEf(lc); - OUT_RING_CACHEf(qc); - OUT_RING_CACHEf(x); - OUT_RING_CACHEf(y); - OUT_RING_CACHEf(z); - OUT_RING_CACHEf(c); - } - break; - default: - break; - } -} - -/** Set the lighting model parameters */ -static void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params); - - -static void nv20LineStipple(GLcontext *ctx, GLint factor, GLushort pattern ) -{ -/* nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN, 1); - OUT_RING_CACHE((pattern << 16) | factor);*/ -} - -static void nv20LineWidth(GLcontext *ctx, GLfloat width) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LINE_WIDTH, 1); - OUT_RING_CACHEf(width); -} - -static void nv20LogicOpcode(GLcontext *ctx, GLenum opcode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP, 1); - OUT_RING_CACHE(opcode); -} - -static void nv20PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - /*TODO: not sure what goes here. */ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -} - -/** Specify the diameter of rasterized points */ -static void nv20PointSize(GLcontext *ctx, GLfloat size) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POINT_SIZE, 1); - OUT_RING_CACHEf(size); -} - -/** Select a polygon rasterization mode */ -static void nv20PolygonMode(GLcontext *ctx, GLenum face, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1); - OUT_RING_CACHE(mode); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1); - OUT_RING_CACHE(mode); - } -} - -/** Set the scale and units used to calculate depth values */ -static void nv20PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 2); - OUT_RING_CACHEf(factor); - OUT_RING_CACHEf(units); -} - -/** Set the polygon stippling pattern */ -static void nv20PolygonStipple(GLcontext *ctx, const GLubyte *mask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(0), 32); - OUT_RING_CACHEp(mask, 32); -} - -/* Specifies the current buffer for reading */ -void (*ReadBuffer)( GLcontext *ctx, GLenum buffer ); -/** Set rasterization mode */ -void (*RenderMode)(GLcontext *ctx, GLenum mode ); - -/** Define the scissor box */ -static void nv20Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* There's no scissor enable bit, so adjust the scissor to cover the - * maximum draw buffer bounds - */ - if (!ctx->Scissor.Enabled) { - x = y = 0; - w = h = 4095; - } else { - x += nmesa->drawX; - y += nmesa->drawY; - } - - /*BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1, 1); - OUT_RING_CACHE((w << 16) | x ); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1, 1); - OUT_RING_CACHE((h << 16) | y );*/ - -} - -/** Select flat or smooth shading */ -static void nv20ShadeModel(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SHADE_MODEL, 1); - OUT_RING_CACHE(mode); -} - -/** OpenGL 2.0 two-sided StencilFunc */ -static void nv20StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, - GLint ref, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC, 3); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ref); - OUT_RING_CACHE(mask); -} - -/** OpenGL 2.0 two-sided StencilMask */ -static void nv20StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_MASK, 1); - OUT_RING_CACHE(mask); -} - -/** OpenGL 2.0 two-sided StencilOp */ -static void nv20StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, - GLenum zfail, GLenum zpass) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL, 1); - OUT_RING_CACHE(fail); - OUT_RING_CACHE(zfail); - OUT_RING_CACHE(zpass); -} - -/** Control the generation of texture coordinates */ -void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname, - const GLfloat *params); -/** Set texture environment parameters */ -void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname, - const GLfloat *param); -/** Set texture parameters */ -void (*TexParameter)(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat *params); - -static void nv20TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_TX_MATRIX(unit, 0), 16); - /*XXX: This SHOULD work.*/ - OUT_RING_CACHEp(mat->m, 16); -} - -/* Update anything that depends on the window position/size */ -static void nv20WindowMoved(nouveauContextPtr nmesa) -{ - GLcontext *ctx = nmesa->glCtx; - GLfloat *v = nmesa->viewport.m; - GLuint w = ctx->Viewport.Width; - GLuint h = ctx->Viewport.Height; - GLuint x = ctx->Viewport.X + nmesa->drawX; - GLuint y = ctx->Viewport.Y + nmesa->drawY; - int i; - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 2); - OUT_RING_CACHE((w << 16) | x); - OUT_RING_CACHE((h << 16) | y); - - BEGIN_RING_SIZE(NvSub3D, 0x02b4, 1); - OUT_RING(0); - - BEGIN_RING_CACHE(NvSub3D, - NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 1); - OUT_RING_CACHE((4095 << 16) | 0); - BEGIN_RING_CACHE(NvSub3D, - NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(0), 1); - OUT_RING_CACHE((4095 << 16) | 0); - for (i=1; i<8; i++) { - BEGIN_RING_CACHE(NvSub3D, - NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(i), 1); - OUT_RING_CACHE(0); - BEGIN_RING_CACHE(NvSub3D, - NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(i), 1); - OUT_RING_CACHE(0); - } - - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - - /* TODO: recalc viewport scale coefs */ -} - -/* Initialise any card-specific non-GL related state */ -static GLboolean nv20InitCard(nouveauContextPtr nmesa) -{ - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); - - BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT1, 2); - OUT_RING(NvDmaFB); /* 184 dma_object1 */ - OUT_RING(NvDmaFB); /* 188 dma_object2 */ - BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT3, 2); - OUT_RING(NvDmaFB); /* 194 dma_object3 */ - OUT_RING(NvDmaFB); /* 198 dma_object4 */ - BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT8, 1); - OUT_RING(NvDmaFB); /* 1a8 dma_object8 */ - - BEGIN_RING_SIZE(NvSub3D, 0x17e0, 3); - OUT_RINGf(0.0); - OUT_RINGf(0.0); - OUT_RINGf(1.0); - - BEGIN_RING_SIZE(NvSub3D, 0x1e6c, 1); - OUT_RING(0x0db6); - BEGIN_RING_SIZE(NvSub3D, 0x0290, 1); - OUT_RING(0x00100001); - BEGIN_RING_SIZE(NvSub3D, 0x09fc, 1); - OUT_RING(0); - BEGIN_RING_SIZE(NvSub3D, 0x1d80, 1); - OUT_RING(1); - BEGIN_RING_SIZE(NvSub3D, 0x09f8, 1); - OUT_RING(4); - - BEGIN_RING_SIZE(NvSub3D, 0x17ec, 3); - OUT_RINGf(0.0); - OUT_RINGf(1.0); - OUT_RINGf(0.0); - - BEGIN_RING_SIZE(NvSub3D, 0x1d88, 1); - OUT_RING(3); - - /* FIXME: More dma objects to setup ? */ - - BEGIN_RING_SIZE(NvSub3D, 0x1e98, 1); - OUT_RING(0); - - BEGIN_RING_SIZE(NvSub3D, 0x120, 3); - OUT_RING(0); - OUT_RING(1); - OUT_RING(2); - - return GL_TRUE; -} - -/* Update buffer offset/pitch/format */ -static GLboolean nv20BindBuffers(nouveauContextPtr nmesa, int num_color, - nouveau_renderbuffer_t **color, - nouveau_renderbuffer_t *depth) -{ - GLuint x, y, w, h; - GLuint pitch, format, depth_pitch; - - w = color[0]->mesa.Width; - h = color[0]->mesa.Height; - x = nmesa->drawX; - y = nmesa->drawY; - - if (num_color != 1) - return GL_FALSE; - - BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 6); - OUT_RING_CACHE((w << 16) | x); - OUT_RING_CACHE((h << 16) | y); - depth_pitch = (depth ? depth->pitch : color[0]->pitch); - pitch = (depth_pitch<<16) | color[0]->pitch; - format = 0x128; - if (color[0]->mesa._ActualFormat != GL_RGBA8) { - format = 0x123; /* R5G6B5 color buffer */ - } - OUT_RING_CACHE(format); - OUT_RING_CACHE(pitch); - OUT_RING_CACHE(color[0]->offset); - OUT_RING_CACHE(depth ? depth->offset : color[0]->offset); - - if (depth) { - BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH, 2); - /* TODO: use a different buffer */ - OUT_RING(depth->pitch); - OUT_RING(depth->offset); - } - - /* Always set to bottom left of buffer */ - /*BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_X, 4); - OUT_RING_CACHEf (0.0); - OUT_RING_CACHEf ((GLfloat) h); - OUT_RING_CACHEf (0.0); - OUT_RING_CACHEf (0.0);*/ - - return GL_TRUE; -} - -void nv20InitStateFuncs(GLcontext *ctx, struct dd_function_table *func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - func->AlphaFunc = nv20AlphaFunc; - func->BlendColor = nv20BlendColor; - func->BlendEquationSeparate = nv20BlendEquationSeparate; - func->BlendFuncSeparate = nv20BlendFuncSeparate; - func->Clear = nv20Clear; - func->ClearColor = nv20ClearColor; - func->ClearDepth = nv20ClearDepth; - func->ClearStencil = nv20ClearStencil; - func->ClipPlane = nv20ClipPlane; - func->ColorMask = nv20ColorMask; - func->ColorMaterial = nv20ColorMaterial; - func->CullFace = nv20CullFace; - func->FrontFace = nv20FrontFace; - func->DepthFunc = nv20DepthFunc; - func->DepthMask = nv20DepthMask; - func->DepthRange = nv20DepthRange; - func->Enable = nv20Enable; - func->Fogfv = nv20Fogfv; - func->Hint = nv20Hint; - func->Lightfv = nv20Lightfv; -/* func->LightModelfv = nv20LightModelfv; */ - func->LineStipple = nv20LineStipple; - func->LineWidth = nv20LineWidth; - func->LogicOpcode = nv20LogicOpcode; - func->PointParameterfv = nv20PointParameterfv; - func->PointSize = nv20PointSize; - func->PolygonMode = nv20PolygonMode; - func->PolygonOffset = nv20PolygonOffset; - func->PolygonStipple = nv20PolygonStipple; -/* func->ReadBuffer = nv20ReadBuffer;*/ -/* func->RenderMode = nv20RenderMode;*/ - func->Scissor = nv20Scissor; - func->ShadeModel = nv20ShadeModel; - func->StencilFuncSeparate = nv20StencilFuncSeparate; - func->StencilMaskSeparate = nv20StencilMaskSeparate; - func->StencilOpSeparate = nv20StencilOpSeparate; -/* func->TexGen = nv20TexGen;*/ -/* func->TexParameter = nv20TexParameter;*/ - func->TextureMatrix = nv20TextureMatrix; - - nmesa->hw_func.InitCard = nv20InitCard; - nmesa->hw_func.BindBuffers = nv20BindBuffers; - nmesa->hw_func.WindowMoved = nv20WindowMoved; -} - diff --git a/src/mesa/drivers/dri/nouveau/nv20_vertprog.c b/src/mesa/drivers/dri/nouveau/nv20_vertprog.c deleted file mode 100644 index 60cfcd70561..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv20_vertprog.c +++ /dev/null @@ -1,447 +0,0 @@ -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" - -#include "nouveau_shader.h" -#include "nv20_shader.h" - -unsigned int NVVP_TX_VOP_COUNT = 16; -unsigned int NVVP_TX_NVS_OP_COUNT = 16; -struct _op_xlat NVVP_TX_VOP[32]; -struct _op_xlat NVVP_TX_SOP[32]; - -nvsSwzComp NV20VP_TX_SWIZZLE[4] = { NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W }; - -/***************************************************************************** - * Support routines - */ -static void -NV20VPUploadToHW(GLcontext *ctx, nouveauShader *nvs) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - int i; - - /* XXX: missing a way to say what insn we're uploading from, and possible - * the program start position (if NV20 has one) */ - for (i=0; i<nvs->program_size; i+=4) { - BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0, 4); - OUT_RING(nvs->program[i + 0]); - OUT_RING(nvs->program[i + 1]); - OUT_RING(nvs->program[i + 2]); - OUT_RING(nvs->program[i + 3]); - } -} - -static void -NV20VPUpdateConst(GLcontext *ctx, nouveauShader *nvs, int id) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* Worth checking if the value *actually* changed? Mesa doesn't tell us this - * as far as I know.. - */ - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID, 1); - OUT_RING (id); - BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_X, 4); - OUT_RINGf(nvs->params[id].source_val[0]); - OUT_RINGf(nvs->params[id].source_val[1]); - OUT_RINGf(nvs->params[id].source_val[2]); - OUT_RINGf(nvs->params[id].source_val[3]); -} - -/***************************************************************************** - * Assembly routines - */ - -/***************************************************************************** - * Disassembly routines - */ -void -NV20VPTXSwizzle(int hwswz, nvsSwzComp *swz) -{ - swz[NVS_SWZ_X] = NV20VP_TX_SWIZZLE[(hwswz & 0xC0) >> 6]; - swz[NVS_SWZ_Y] = NV20VP_TX_SWIZZLE[(hwswz & 0x30) >> 4]; - swz[NVS_SWZ_Z] = NV20VP_TX_SWIZZLE[(hwswz & 0x0C) >> 2]; - swz[NVS_SWZ_W] = NV20VP_TX_SWIZZLE[(hwswz & 0x03) >> 0]; -} - -static int -NV20VPHasMergedInst(nvsFunc * shader) -{ - if (shader->GetOpcodeHW(shader, 0) != NV20_VP_INST_OPCODE_NOP && - shader->GetOpcodeHW(shader, 1) != NV20_VP_INST_OPCODE_NOP) - printf - ("\n\n*****both opcode fields have values - PLEASE REPORT*****\n"); - return 0; -} - -static int -NV20VPIsLastInst(nvsFunc * shader) -{ - return ((shader->inst[3] & (1 << 0)) ? 1 : 0); -} - -static int -NV20VPGetOffsetNext(nvsFunc * shader) -{ - return 4; -} - -static struct _op_xlat * -NV20VPGetOPTXRec(nvsFunc * shader, int merged) -{ - struct _op_xlat *opr; - int op; - - if (shader->GetOpcodeSlot(shader, merged)) { - opr = NVVP_TX_SOP; - op = shader->GetOpcodeHW(shader, 1); - if (op >= NVVP_TX_NVS_OP_COUNT) - return NULL; - } - else { - opr = NVVP_TX_VOP; - op = shader->GetOpcodeHW(shader, 0); - if (op >= NVVP_TX_VOP_COUNT) - return NULL; - } - - if (opr[op].SOP == NVS_OP_UNKNOWN) - return NULL; - return &opr[op]; -} - -static struct _op_xlat * -NV20VPGetOPTXFromSOP(nvsOpcode sop, int *id) -{ - int i; - - for (i=0;i<NVVP_TX_VOP_COUNT;i++) { - if (NVVP_TX_VOP[i].SOP == sop) { - if (id) *id = 0; - return &NVVP_TX_VOP[i]; - } - } - - for (i=0;i<NVVP_TX_NVS_OP_COUNT;i++) { - if (NVVP_TX_SOP[i].SOP == sop) { - if (id) *id = 1; - return &NVVP_TX_SOP[i]; - } - } - - return NULL; -} - -static int -NV20VPGetOpcodeSlot(nvsFunc * shader, int merged) -{ - if (shader->HasMergedInst(shader)) - return merged; - if (shader->GetOpcodeHW(shader, 0) == NV20_VP_INST_OPCODE_NOP) - return 1; - return 0; -} - -static nvsOpcode -NV20VPGetOpcode(nvsFunc * shader, int merged) -{ - struct _op_xlat *opr; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr) - return NVS_OP_UNKNOWN; - - return opr->SOP; -} - -static nvsOpcode -NV20VPGetOpcodeHW(nvsFunc * shader, int slot) -{ - if (slot) - return (shader->inst[1] & NV20_VP_INST_SCA_OPCODE_MASK) - >> NV20_VP_INST_SCA_OPCODE_SHIFT; - return (shader->inst[1] & NV20_VP_INST_VEC_OPCODE_MASK) - >> NV20_VP_INST_VEC_OPCODE_SHIFT; -} - -static nvsRegFile -NV20VPGetDestFile(nvsFunc * shader, int merged) -{ - switch (shader->GetOpcode(shader, merged)) { - case NVS_OP_ARL: - return NVS_FILE_ADDRESS; - default: - /*FIXME: This probably isn't correct.. */ - if ((shader->inst[3] & NV20_VP_INST_DEST_WRITEMASK_MASK) == 0) - return NVS_FILE_TEMP; - return NVS_FILE_RESULT; - } -} - -static unsigned int -NV20VPGetDestID(nvsFunc * shader, int merged) -{ - int id; - - switch (shader->GetDestFile(shader, merged)) { - case NVS_FILE_RESULT: - id = ((shader->inst[3] & NV20_VP_INST_DEST_MASK) - >> NV20_VP_INST_DEST_SHIFT); - switch (id) { - case NV20_VP_INST_DEST_POS : return NVS_FR_POSITION; - case NV20_VP_INST_DEST_COL0 : return NVS_FR_COL0; - case NV20_VP_INST_DEST_COL1 : return NVS_FR_COL1; - case NV20_VP_INST_DEST_TC(0): return NVS_FR_TEXCOORD0; - case NV20_VP_INST_DEST_TC(1): return NVS_FR_TEXCOORD1; - case NV20_VP_INST_DEST_TC(2): return NVS_FR_TEXCOORD2; - case NV20_VP_INST_DEST_TC(3): return NVS_FR_TEXCOORD3; - default: - return -1; - } - case NVS_FILE_ADDRESS: - return 0; - case NVS_FILE_TEMP: - id = ((shader->inst[3] & NV20_VP_INST_DEST_TEMP_ID_MASK) - >> NV20_VP_INST_DEST_TEMP_ID_SHIFT); - return id; - default: - return -1; - } -} - -static unsigned int -NV20VPGetDestMask(nvsFunc * shader, int merged) -{ - int hwmask, mask = 0; - - /* Special handling for ARL - hardware only supports a - * 1-component address reg - */ - if (shader->GetOpcode(shader, merged) == NVS_OP_ARL) - return SMASK_X; - - if (shader->GetDestFile(shader, merged) == NVS_FILE_RESULT) - hwmask = (shader->inst[3] & NV20_VP_INST_DEST_WRITEMASK_MASK) - >> NV20_VP_INST_DEST_WRITEMASK_SHIFT; - else if (shader->GetOpcodeSlot(shader, merged)) - hwmask = (shader->inst[3] & NV20_VP_INST_STEMP_WRITEMASK_MASK) - >> NV20_VP_INST_STEMP_WRITEMASK_SHIFT; - else - hwmask = (shader->inst[3] & NV20_VP_INST_VTEMP_WRITEMASK_MASK) - >> NV20_VP_INST_VTEMP_WRITEMASK_SHIFT; - - if (hwmask & (1 << 3)) mask |= SMASK_X; - if (hwmask & (1 << 2)) mask |= SMASK_Y; - if (hwmask & (1 << 1)) mask |= SMASK_Z; - if (hwmask & (1 << 0)) mask |= SMASK_W; - - return mask; -} - -static unsigned int -NV20VPGetSourceHW(nvsFunc * shader, int merged, int pos) -{ - struct _op_xlat *opr; - unsigned int src; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr) - return -1; - - switch (opr->srcpos[pos]) { - case 0: - src = ((shader->inst[1] & NV20_VP_INST_SRC0H_MASK) - >> NV20_VP_INST_SRC0H_SHIFT) - << NV20_VP_SRC0_HIGH_SHIFT; - src |= ((shader->inst[2] & NV20_VP_INST_SRC0L_MASK) - >> NV20_VP_INST_SRC0L_SHIFT); - break; - case 1: - src = ((shader->inst[2] & NV20_VP_INST_SRC1_MASK) - >> NV20_VP_INST_SRC1_SHIFT); - break; - case 2: - src = ((shader->inst[2] & NV20_VP_INST_SRC2H_MASK) - >> NV20_VP_INST_SRC2H_SHIFT) - << NV20_VP_SRC2_HIGH_SHIFT; - src |= ((shader->inst[3] & NV20_VP_INST_SRC2L_MASK) - >> NV20_VP_INST_SRC2L_SHIFT); - break; - default: - src = -1; - } - - return src; -} - -static nvsRegFile -NV20VPGetSourceFile(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - struct _op_xlat *opr; - int file; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr || opr->srcpos[pos] == -1) - return -1; - - switch (opr->srcpos[pos]) { - case SPOS_ADDRESS: - return NVS_FILE_ADDRESS; - default: - src = NV20VPGetSourceHW(shader, merged, pos); - file = (src & NV20_VP_SRC_REG_TYPE_MASK) >> NV20_VP_SRC_REG_TYPE_SHIFT; - - switch (file) { - case NV20_VP_SRC_REG_TYPE_TEMP : return NVS_FILE_TEMP; - case NV20_VP_SRC_REG_TYPE_INPUT: return NVS_FILE_ATTRIB; - case NV20_VP_SRC_REG_TYPE_CONST: return NVS_FILE_CONST; - default: - return NVS_FILE_UNKNOWN; - } - } -} - -static int -NV20VPGetSourceID(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_TEMP: - src = shader->GetSourceHW(shader, merged, pos); - return ((src & NV20_VP_SRC_REG_TEMP_ID_MASK) >> - NV20_VP_SRC_REG_TEMP_ID_SHIFT); - case NVS_FILE_CONST: - return ((shader->inst[1] & NV20_VP_INST_CONST_SRC_MASK) - >> NV20_VP_INST_CONST_SRC_SHIFT); - case NVS_FILE_ATTRIB: - src = ((shader->inst[1] & NV20_VP_INST_INPUT_SRC_MASK) - >> NV20_VP_INST_INPUT_SRC_SHIFT); - switch (src) { - case NV20_VP_INST_INPUT_SRC_POS : return NVS_FR_POSITION; - case NV20_VP_INST_INPUT_SRC_COL0 : return NVS_FR_COL0; - case NV20_VP_INST_INPUT_SRC_COL1 : return NVS_FR_COL1; - case NV20_VP_INST_INPUT_SRC_TC(0): return NVS_FR_TEXCOORD0; - case NV20_VP_INST_INPUT_SRC_TC(1): return NVS_FR_TEXCOORD1; - case NV20_VP_INST_INPUT_SRC_TC(2): return NVS_FR_TEXCOORD2; - case NV20_VP_INST_INPUT_SRC_TC(3): return NVS_FR_TEXCOORD3; - default: - return NVS_FR_UNKNOWN; - } - default: - return -1; - } -} - -static int -NV20VPGetSourceNegate(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - - src = shader->GetSourceHW(shader, merged, pos); - - return ((src & NV20_VP_SRC_REG_NEGATE) ? 1 : 0); -} - -static int -NV20VPGetSourceAbs(nvsFunc * shader, int merged, int pos) -{ - /* NV20 can't do ABS on sources? Appears to be emulated with - * MAX reg, reg, -reg - */ - return 0; -} - -static void -NV20VPGetSourceSwizzle(nvsFunc * shader, int merged, int pos, nvsSwzComp *swz) -{ - unsigned int src; - int swzbits; - - src = shader->GetSourceHW(shader, merged, pos); - swzbits = - (src & NV20_VP_SRC_REG_SWZ_ALL_MASK) >> NV20_VP_SRC_REG_SWZ_ALL_SHIFT; - return NV20VPTXSwizzle(swzbits, swz); -} - -static int -NV20VPGetSourceIndexed(nvsFunc * shader, int merged, int pos) -{ - /* I don't think NV20 can index into attribs, at least no GL - * extension is exposed that will allow it. - */ - if (shader->GetSourceFile(shader, merged, pos) != NVS_FILE_CONST) - return 0; - if (shader->inst[3] & NV20_VP_INST_INDEX_CONST) - return 1; - return 0; -} - -static int -NV20VPGetAddressRegID(nvsFunc * shader) -{ - /* Only 1 address reg */ - return 0; -} - -static nvsSwzComp -NV20VPGetAddressRegSwizzle(nvsFunc * shader) -{ - /* Only A0.x available */ - return NVS_SWZ_X; -} - -void -NV20VPInitShaderFuncs(nvsFunc * shader) -{ - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_NOP, NVS_OP_NOP, -1, -1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MOV, NVS_OP_MOV, 0, -1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MUL, NVS_OP_MUL, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_ADD, NVS_OP_ADD, 0, 2, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MAD, NVS_OP_MAD, 0, 1, 2); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DP3, NVS_OP_DP3, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DPH, NVS_OP_DPH, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DP4, NVS_OP_DP4, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DST, NVS_OP_DST, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MIN, NVS_OP_MIN, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MAX, NVS_OP_MAX, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_SLT, NVS_OP_SLT, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_SGE, NVS_OP_SGE, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_ARL, NVS_OP_ARL, 0, -1, -1); - - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_NOP, NVS_OP_NOP, -1, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_RCP, NVS_OP_RCP, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_RCC, NVS_OP_RCC, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_RSQ, NVS_OP_RSQ, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_EXP, NVS_OP_EXP, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_LOG, NVS_OP_LOG, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_LIT, NVS_OP_LIT, 2, -1, -1); - - shader->UploadToHW = NV20VPUploadToHW; - shader->UpdateConst = NV20VPUpdateConst; - - shader->GetOPTXRec = NV20VPGetOPTXRec; - shader->GetOPTXFromSOP = NV20VPGetOPTXFromSOP; - - shader->HasMergedInst = NV20VPHasMergedInst; - shader->IsLastInst = NV20VPIsLastInst; - shader->GetOffsetNext = NV20VPGetOffsetNext; - shader->GetOpcodeSlot = NV20VPGetOpcodeSlot; - shader->GetOpcode = NV20VPGetOpcode; - shader->GetOpcodeHW = NV20VPGetOpcodeHW; - shader->GetDestFile = NV20VPGetDestFile; - shader->GetDestID = NV20VPGetDestID; - shader->GetDestMask = NV20VPGetDestMask; - shader->GetSourceHW = NV20VPGetSourceHW; - shader->GetSourceFile = NV20VPGetSourceFile; - shader->GetSourceID = NV20VPGetSourceID; - shader->GetSourceNegate = NV20VPGetSourceNegate; - shader->GetSourceAbs = NV20VPGetSourceAbs; - shader->GetSourceSwizzle = NV20VPGetSourceSwizzle; - shader->GetSourceIndexed = NV20VPGetSourceIndexed; - shader->GetRelAddressRegID = NV20VPGetAddressRegID; - shader->GetRelAddressSwizzle = NV20VPGetAddressRegSwizzle; -} diff --git a/src/mesa/drivers/dri/nouveau/nv30_fragprog.c b/src/mesa/drivers/dri/nouveau/nv30_fragprog.c deleted file mode 100644 index 5f61f76a0ab..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv30_fragprog.c +++ /dev/null @@ -1,742 +0,0 @@ -#include <stdint.h> - -#include "glheader.h" -#include "macros.h" - -#include "nouveau_context.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" -#include "nouveau_drm.h" -#include "nouveau_shader.h" -#include "nouveau_object.h" -#include "nouveau_msg.h" -#include "nouveau_bufferobj.h" -#include "nv30_shader.h" - -unsigned int NVFP_TX_AOP_COUNT = 64; -struct _op_xlat NVFP_TX_AOP[64]; - -/******************************************************************************* - * Support routines - */ - -static void -NV30FPUploadToHW(GLcontext *ctx, nouveauShader *nvs) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nvsCardPriv *priv = &nvs->card_priv; - uint32_t offset; - - if (!nvs->program_buffer) - nvs->program_buffer = ctx->Driver.NewBufferObject(ctx, 0, - GL_ARRAY_BUFFER_ARB); - - /* Should use STATIC_DRAW_ARB if shader doesn't use changable params */ - nouveau_bo_init_storage(ctx, NOUVEAU_BO_VRAM_OK, - nvs->program_size * sizeof(uint32_t), - (const GLvoid *)nvs->program, - GL_DYNAMIC_DRAW_ARB, - nvs->program_buffer, 1); - - offset = nouveau_bo_gpu_ref(ctx, nvs->program_buffer); - - /* Not using state cache here, updated programs at the same address don't - * seem to take effect unless the ACTIVE_PROGRAM method is called again. - * HW caches the program somewhere? - */ - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FP_ACTIVE_PROGRAM, 1); - OUT_RING (offset | 1); - if (nmesa->screen->card->type == NV_30) { - BEGIN_RING_SIZE(NvSub3D, - 0x1d60 /*NV30_TCL_PRIMITIVE_3D_FP_CONTROL*/, 1); - OUT_RING ((priv->NV30FP.uses_kil << 7)); - BEGIN_RING_SIZE(NvSub3D, 0x1450, 1); - OUT_RING (priv->NV30FP.num_regs << 16); - } else { - BEGIN_RING_SIZE(NvSub3D, - 0x1d60 /*NV30_TCL_PRIMITIVE_3D_FP_CONTROL*/, 1); - OUT_RING ((priv->NV30FP.uses_kil << 7) | - (priv->NV30FP.num_regs << 24)); - } -} - -static void -NV30FPUpdateConst(GLcontext *ctx, nouveauShader *nvs, int id) -{ - uint32_t *new = nvs->params[id].source_val ? - (uint32_t*)nvs->params[id].source_val : (uint32_t*)nvs->params[id].val; - uint32_t *current; - int i; - - for (i=0; i<nvs->params[id].hw_index_cnt; i++) { - current = nvs->program + nvs->params[id].hw_index[i]; - COPY_4V(current, new); - } - nvs->on_hardware = 0; -} - -/******************************************************************************* - * Assembly helpers - */ -static struct _op_xlat * -NV30FPGetOPTXFromSOP(nvsOpcode op, int *id) -{ - int i; - - for (i=0; i<NVFP_TX_AOP_COUNT; i++) { - if (NVFP_TX_AOP[i].SOP == op) { - if (id) *id = 0; - return &NVFP_TX_AOP[i]; - } - } - - return NULL; -} - -static int -NV30FPSupportsOpcode(nvsFunc *shader, nvsOpcode op) -{ - if (shader->GetOPTXFromSOP(op, NULL)) - return 1; - return 0; -} - -static void -NV30FPSetOpcode(nvsFunc *shader, unsigned int opcode, int slot) -{ - if (opcode == NV30_FP_OP_OPCODE_KIL) - shader->card_priv->NV30FP.uses_kil = GL_TRUE; - shader->inst[0] &= ~NV30_FP_OP_OPCODE_MASK; - shader->inst[0] |= (opcode << NV30_FP_OP_OPCODE_SHIFT); -} - -static void -NV30FPSetCCUpdate(nvsFunc *shader) -{ - shader->inst[0] |= NV30_FP_OP_COND_WRITE_ENABLE; -} - -static void -NV30FPSetCondition(nvsFunc *shader, int on, nvsCond cond, int reg, - nvsSwzComp *swz) -{ - nvsSwzComp default_swz[4] = { NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W }; - unsigned int hwcond; - - /* cond masking is always enabled */ - if (!on) { - cond = NVS_COND_TR; - reg = 0; - swz = default_swz; - } - - switch (cond) { - case NVS_COND_TR: hwcond = NV30_FP_OP_COND_TR; break; - case NVS_COND_FL: hwcond = NV30_FP_OP_COND_FL; break; - case NVS_COND_LT: hwcond = NV30_FP_OP_COND_LT; break; - case NVS_COND_GT: hwcond = NV30_FP_OP_COND_GT; break; - case NVS_COND_LE: hwcond = NV30_FP_OP_COND_LE; break; - case NVS_COND_GE: hwcond = NV30_FP_OP_COND_GE; break; - case NVS_COND_EQ: hwcond = NV30_FP_OP_COND_EQ; break; - case NVS_COND_NE: hwcond = NV30_FP_OP_COND_NE; break; - default: - WARN_ONCE("unknown fp condmask=%d\n", cond); - hwcond = NV30_FP_OP_COND_TR; - break; - } - - shader->inst[1] &= ~NV30_FP_OP_COND_MASK; - shader->inst[1] |= (hwcond << NV30_FP_OP_COND_SHIFT); - - shader->inst[1] &= ~NV30_FP_OP_COND_SWZ_ALL_MASK; - shader->inst[1] |= (swz[NVS_SWZ_X] << NV30_FP_OP_COND_SWZ_X_SHIFT); - shader->inst[1] |= (swz[NVS_SWZ_Y] << NV30_FP_OP_COND_SWZ_Y_SHIFT); - shader->inst[1] |= (swz[NVS_SWZ_Z] << NV30_FP_OP_COND_SWZ_Z_SHIFT); - shader->inst[1] |= (swz[NVS_SWZ_W] << NV30_FP_OP_COND_SWZ_W_SHIFT); -} - -static void -NV30FPSetHighReg(nvsFunc *shader, int id) -{ - if (shader->card_priv->NV30FP.num_regs < (id+1)) { - if (id == 0) - id = 1; /* necessary? */ - shader->card_priv->NV30FP.num_regs = (id+1); - } -} - -static void -NV30FPSetResult(nvsFunc *shader, nvsRegister *reg, unsigned int mask, int slot) -{ - unsigned int hwreg; - - if (mask & SMASK_X) shader->inst[0] |= NV30_FP_OP_OUT_X; - if (mask & SMASK_Y) shader->inst[0] |= NV30_FP_OP_OUT_Y; - if (mask & SMASK_Z) shader->inst[0] |= NV30_FP_OP_OUT_Z; - if (mask & SMASK_W) shader->inst[0] |= NV30_FP_OP_OUT_W; - - if (reg->file == NVS_FILE_RESULT) { - hwreg = 0; /* FIXME: this is only fragment.color */ - /* This is *not* correct, I have no idea what it is either */ - shader->inst[0] |= NV30_FP_OP_UNK0_7; - } else { - shader->inst[0] &= ~NV30_FP_OP_UNK0_7; - hwreg = reg->index; - } - NV30FPSetHighReg(shader, hwreg); - shader->inst[0] &= ~NV30_FP_OP_OUT_REG_SHIFT; - shader->inst[0] |= (hwreg << NV30_FP_OP_OUT_REG_SHIFT); -} - -static void -NV30FPSetSource(nvsFunc *shader, nvsRegister *reg, int pos) -{ - unsigned int hwsrc = 0; - - switch (reg->file) { - case NVS_FILE_TEMP: - hwsrc |= (NV30_FP_REG_TYPE_TEMP << NV30_FP_REG_TYPE_SHIFT); - hwsrc |= (reg->index << NV30_FP_REG_SRC_SHIFT); - NV30FPSetHighReg(shader, reg->index); - break; - case NVS_FILE_ATTRIB: - { - unsigned int hwin; - - switch (reg->index) { - case NVS_FR_POSITION : hwin = NV30_FP_OP_INPUT_SRC_POSITION; break; - case NVS_FR_COL0 : hwin = NV30_FP_OP_INPUT_SRC_COL0; break; - case NVS_FR_COL1 : hwin = NV30_FP_OP_INPUT_SRC_COL1; break; - case NVS_FR_FOGCOORD : hwin = NV30_FP_OP_INPUT_SRC_FOGC; break; - case NVS_FR_TEXCOORD0: hwin = NV30_FP_OP_INPUT_SRC_TC(0); break; - case NVS_FR_TEXCOORD1: hwin = NV30_FP_OP_INPUT_SRC_TC(1); break; - case NVS_FR_TEXCOORD2: hwin = NV30_FP_OP_INPUT_SRC_TC(2); break; - case NVS_FR_TEXCOORD3: hwin = NV30_FP_OP_INPUT_SRC_TC(3); break; - case NVS_FR_TEXCOORD4: hwin = NV30_FP_OP_INPUT_SRC_TC(4); break; - case NVS_FR_TEXCOORD5: hwin = NV30_FP_OP_INPUT_SRC_TC(5); break; - case NVS_FR_TEXCOORD6: hwin = NV30_FP_OP_INPUT_SRC_TC(6); break; - case NVS_FR_TEXCOORD7: hwin = NV30_FP_OP_INPUT_SRC_TC(7); break; - default: - WARN_ONCE("unknown fp input %d\n", reg->index); - hwin = NV30_FP_OP_INPUT_SRC_COL0; - break; - } - shader->inst[0] &= ~NV30_FP_OP_INPUT_SRC_MASK; - shader->inst[0] |= (hwin << NV30_FP_OP_INPUT_SRC_SHIFT); - hwsrc |= (hwin << NV30_FP_REG_SRC_SHIFT); - } - hwsrc |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT); - break; - case NVS_FILE_CONST: - /* consts are inlined after the inst */ - hwsrc |= (NV30_FP_REG_TYPE_CONST << NV30_FP_REG_TYPE_SHIFT); - break; - default: - assert(0); - break; - } - - if (reg->negate) - hwsrc |= NV30_FP_REG_NEGATE; - if (reg->abs) - shader->inst[1] |= (1 << (29+pos)); - hwsrc |= (reg->swizzle[NVS_SWZ_X] << NV30_FP_REG_SWZ_X_SHIFT); - hwsrc |= (reg->swizzle[NVS_SWZ_Y] << NV30_FP_REG_SWZ_Y_SHIFT); - hwsrc |= (reg->swizzle[NVS_SWZ_Z] << NV30_FP_REG_SWZ_Z_SHIFT); - hwsrc |= (reg->swizzle[NVS_SWZ_W] << NV30_FP_REG_SWZ_W_SHIFT); - - shader->inst[pos+1] &= ~NV30_FP_REG_ALL_MASK; - shader->inst[pos+1] |= hwsrc; -} - -static void -NV30FPSetTexImageUnit(nvsFunc *shader, int unit) -{ - shader->inst[0] &= ~NV30_FP_OP_TEX_UNIT_SHIFT; - shader->inst[0] |= (unit << NV30_FP_OP_TEX_UNIT_SHIFT); -} - -static void -NV30FPSetSaturate(nvsFunc *shader) -{ - shader->inst[0] |= NV30_FP_OP_OUT_SAT; -} - -static void -NV30FPInitInstruction(nvsFunc *shader) -{ - unsigned int hwsrc; - - shader->inst[0] = 0; - - hwsrc = (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT) | - (NVS_SWZ_X << NV30_FP_REG_SWZ_X_SHIFT) | - (NVS_SWZ_Y << NV30_FP_REG_SWZ_Y_SHIFT) | - (NVS_SWZ_Z << NV30_FP_REG_SWZ_Z_SHIFT) | - (NVS_SWZ_W << NV30_FP_REG_SWZ_W_SHIFT); - shader->inst[1] = hwsrc; - shader->inst[2] = hwsrc; - shader->inst[3] = hwsrc; -} - -static void -NV30FPSetLastInst(nvsFunc *shader) -{ - shader->inst[0] |= 1; -} - -/******************************************************************************* - * Disassembly helpers - */ -static struct _op_xlat * -NV30FPGetOPTXRec(nvsFunc * shader, int merged) -{ - int op; - - op = shader->GetOpcodeHW(shader, 0); - if (op > NVFP_TX_AOP_COUNT) - return NULL; - if (NVFP_TX_AOP[op].SOP == NVS_OP_UNKNOWN) - return NULL; - return &NVFP_TX_AOP[op]; -} - -static int -NV30FPHasMergedInst(nvsFunc * shader) -{ - return 0; -} - -static int -NV30FPIsLastInst(nvsFunc * shader) -{ - return ((shader->inst[0] & NV30_FP_OP_PROGRAM_END) ? 1 : 0); -} - -static int -NV30FPGetOffsetNext(nvsFunc * shader) -{ - int i; - - for (i = 0; i < 3; i++) - if (shader->GetSourceFile(shader, 0, i) == NVS_FILE_CONST) - return 8; - return 4; -} - -static nvsOpcode -NV30FPGetOpcode(nvsFunc * shader, int merged) -{ - struct _op_xlat *opr; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr) - return NVS_OP_UNKNOWN; - - return opr->SOP; -} - -static unsigned int -NV30FPGetOpcodeHW(nvsFunc * shader, int slot) -{ - int op; - - op = (shader->inst[0] & NV30_FP_OP_OPCODE_MASK) >> NV30_FP_OP_OPCODE_SHIFT; - - return op; -} - -static nvsRegFile -NV30FPGetDestFile(nvsFunc * shader, int merged) -{ - /* Result regs overlap temporary regs */ - return NVS_FILE_TEMP; -} - -static unsigned int -NV30FPGetDestID(nvsFunc * shader, int merged) -{ - int id; - - switch (shader->GetDestFile(shader, merged)) { - case NVS_FILE_TEMP: - id = ((shader->inst[0] & NV30_FP_OP_OUT_REG_MASK) - >> NV30_FP_OP_OUT_REG_SHIFT); - return id; - default: - return -1; - } -} - -static unsigned int -NV30FPGetDestMask(nvsFunc * shader, int merged) -{ - unsigned int mask = 0; - - if (shader->inst[0] & NV30_FP_OP_OUT_X) mask |= SMASK_X; - if (shader->inst[0] & NV30_FP_OP_OUT_Y) mask |= SMASK_Y; - if (shader->inst[0] & NV30_FP_OP_OUT_Z) mask |= SMASK_Z; - if (shader->inst[0] & NV30_FP_OP_OUT_W) mask |= SMASK_W; - - return mask; -} - -static unsigned int -NV30FPGetSourceHW(nvsFunc * shader, int merged, int pos) -{ - struct _op_xlat *opr; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr || opr->srcpos[pos] == -1) - return -1; - - return shader->inst[opr->srcpos[pos] + 1]; -} - -static nvsRegFile -NV30FPGetSourceFile(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - struct _op_xlat *opr; - int file; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr || opr->srcpos[pos] == -1) - return NVS_FILE_UNKNOWN; - - switch (opr->srcpos[pos]) { - case SPOS_ADDRESS: return NVS_FILE_ADDRESS; - default: - src = shader->GetSourceHW(shader, merged, pos); - file = (src & NV30_FP_REG_TYPE_MASK) >> NV30_FP_REG_TYPE_SHIFT; - - switch (file) { - case NV30_FP_REG_TYPE_TEMP : return NVS_FILE_TEMP; - case NV30_FP_REG_TYPE_INPUT: return NVS_FILE_ATTRIB; - case NV30_FP_REG_TYPE_CONST: return NVS_FILE_CONST; - default: - return NVS_FILE_UNKNOWN; - } - } -} - -static int -NV30FPGetSourceID(nvsFunc * shader, int merged, int pos) -{ - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_ATTRIB: - switch ((shader->inst[0] & NV30_FP_OP_INPUT_SRC_MASK) - >> NV30_FP_OP_INPUT_SRC_SHIFT) { - case NV30_FP_OP_INPUT_SRC_POSITION: return NVS_FR_POSITION; - case NV30_FP_OP_INPUT_SRC_COL0 : return NVS_FR_COL0; - case NV30_FP_OP_INPUT_SRC_COL1 : return NVS_FR_COL1; - case NV30_FP_OP_INPUT_SRC_FOGC : return NVS_FR_FOGCOORD; - case NV30_FP_OP_INPUT_SRC_TC(0) : return NVS_FR_TEXCOORD0; - case NV30_FP_OP_INPUT_SRC_TC(1) : return NVS_FR_TEXCOORD1; - case NV30_FP_OP_INPUT_SRC_TC(2) : return NVS_FR_TEXCOORD2; - case NV30_FP_OP_INPUT_SRC_TC(3) : return NVS_FR_TEXCOORD3; - case NV30_FP_OP_INPUT_SRC_TC(4) : return NVS_FR_TEXCOORD4; - case NV30_FP_OP_INPUT_SRC_TC(5) : return NVS_FR_TEXCOORD5; - case NV30_FP_OP_INPUT_SRC_TC(6) : return NVS_FR_TEXCOORD6; - case NV30_FP_OP_INPUT_SRC_TC(7) : return NVS_FR_TEXCOORD7; - default: - return -1; - } - break; - case NVS_FILE_TEMP: - { - unsigned int src; - - src = shader->GetSourceHW(shader, merged, pos); - return ((src & NV30_FP_REG_SRC_MASK) >> NV30_FP_REG_SRC_SHIFT); - } - case NVS_FILE_CONST: /* inlined into fragprog */ - default: - return -1; - } -} - -static int -NV30FPGetTexImageUnit(nvsFunc *shader) -{ - return ((shader->inst[0] & NV30_FP_OP_TEX_UNIT_MASK) - >> NV30_FP_OP_TEX_UNIT_SHIFT); -} - -static int -NV30FPGetSourceNegate(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - - src = shader->GetSourceHW(shader, merged, pos); - - if (src == -1) - return -1; - return ((src & NV30_FP_REG_NEGATE) ? 1 : 0); -} - -static int -NV30FPGetSourceAbs(nvsFunc * shader, int merged, int pos) -{ - struct _op_xlat *opr; - static unsigned int abspos[3] = { - NV30_FP_OP_OUT_ABS, - (1 << 30), /* guess */ - (1 << 31) /* guess */ - }; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr || opr->srcpos[pos] == -1) - return -1; - - return ((shader->inst[1] & abspos[opr->srcpos[pos]]) ? 1 : 0); -} - -nvsSwzComp NV30FP_TX_SWIZZLE[4] = {NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W }; - -static void -NV30FPTXSwizzle(int hwswz, nvsSwzComp *swz) -{ - swz[NVS_SWZ_W] = NV30FP_TX_SWIZZLE[(hwswz & 0xC0) >> 6]; - swz[NVS_SWZ_Z] = NV30FP_TX_SWIZZLE[(hwswz & 0x30) >> 4]; - swz[NVS_SWZ_Y] = NV30FP_TX_SWIZZLE[(hwswz & 0x0C) >> 2]; - swz[NVS_SWZ_X] = NV30FP_TX_SWIZZLE[(hwswz & 0x03) >> 0]; -} - -static void -NV30FPGetSourceSwizzle(nvsFunc * shader, int merged, int pos, nvsSwzComp *swz) -{ - unsigned int src; - int swzbits; - - src = shader->GetSourceHW(shader, merged, pos); - swzbits = (src & NV30_FP_REG_SWZ_ALL_MASK) >> NV30_FP_REG_SWZ_ALL_SHIFT; - NV30FPTXSwizzle(swzbits, swz); -} - -static int -NV30FPGetSourceIndexed(nvsFunc * shader, int merged, int pos) -{ - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_ATTRIB: - return ((shader->inst[3] & NV30_FP_OP_INDEX_INPUT) ? 1 : 0); - default: - return 0; - } -} - -static void -NV30FPGetSourceConstVal(nvsFunc * shader, int merged, int pos, float *val) -{ - val[0] = *(float *) &(shader->inst[4]); - val[1] = *(float *) &(shader->inst[5]); - val[2] = *(float *) &(shader->inst[6]); - val[3] = *(float *) &(shader->inst[7]); -} - -static int -NV30FPGetSourceScale(nvsFunc * shader, int merged, int pos) -{ -/*FIXME: is this per-source, only for a specific source, or all sources??*/ - return (1 << ((shader->inst[2] & NV30_FP_OP_SRC_SCALE_MASK) - >> NV30_FP_OP_SRC_SCALE_SHIFT)); -} - -static int -NV30FPGetAddressRegID(nvsFunc * shader) -{ - return 0; -} - -static nvsSwzComp -NV30FPGetAddressRegSwizzle(nvsFunc * shader) -{ - return NVS_SWZ_X; -} - -static int -NV30FPSupportsConditional(nvsFunc * shader) -{ - /*FIXME: Is this true of all ops? */ - return 1; -} - -static int -NV30FPGetConditionUpdate(nvsFunc * shader) -{ - return ((shader->inst[0] & NV30_FP_OP_COND_WRITE_ENABLE) ? 1 : 0); -} - -static int -NV30FPGetConditionTest(nvsFunc * shader) -{ - /*FIXME: always? */ - return 1; -} - -static nvsCond -NV30FPGetCondition(nvsFunc * shader) -{ - int cond; - - cond = ((shader->inst[1] & NV30_FP_OP_COND_MASK) - >> NV30_FP_OP_COND_SHIFT); - - switch (cond) { - case NV30_FP_OP_COND_FL: return NVS_COND_FL; - case NV30_FP_OP_COND_LT: return NVS_COND_LT; - case NV30_FP_OP_COND_EQ: return NVS_COND_EQ; - case NV30_FP_OP_COND_LE: return NVS_COND_LE; - case NV30_FP_OP_COND_GT: return NVS_COND_GT; - case NV30_FP_OP_COND_NE: return NVS_COND_NE; - case NV30_FP_OP_COND_GE: return NVS_COND_GE; - case NV30_FP_OP_COND_TR: return NVS_COND_TR; - default: - return NVS_COND_UNKNOWN; - } -} - -static void -NV30FPGetCondRegSwizzle(nvsFunc * shader, nvsSwzComp *swz) -{ - int swzbits; - - swzbits = (shader->inst[1] & NV30_FP_OP_COND_SWZ_ALL_MASK) - >> NV30_FP_OP_COND_SWZ_ALL_SHIFT; - NV30FPTXSwizzle(swzbits, swz); -} - -static int -NV30FPGetCondRegID(nvsFunc * shader) -{ - return 0; -} - -static nvsPrecision -NV30FPGetPrecision(nvsFunc * shader) -{ - int p; - - p = (shader->inst[0] & NV30_FP_OP_PRECISION_MASK) - >> NV30_FP_OP_PRECISION_SHIFT; - - switch (p) { - case NV30_FP_PRECISION_FP32: return NVS_PREC_FLOAT32; - case NV30_FP_PRECISION_FP16: return NVS_PREC_FLOAT16; - case NV30_FP_PRECISION_FX12: return NVS_PREC_FIXED12; - default: - return NVS_PREC_UNKNOWN; - } -} - -static int -NV30FPGetSaturate(nvsFunc * shader) -{ - return ((shader->inst[0] & NV30_FP_OP_OUT_SAT) ? 1 : 0); -} - -/******************************************************************************* - * Init - */ -void -NV30FPInitShaderFuncs(nvsFunc * shader) -{ - /* These are probably bogus, I made them up... */ - shader->MaxInst = 1024; - shader->MaxAttrib = 16; - shader->MaxTemp = 32; - shader->MaxAddress = 1; - shader->MaxConst = 256; - shader->caps = SCAP_SRC_ABS; - - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MOV, NVS_OP_MOV, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MUL, NVS_OP_MUL, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_ADD, NVS_OP_ADD, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MAD, NVS_OP_MAD, 0, 1, 2); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DP3, NVS_OP_DP3, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DP4, NVS_OP_DP4, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DST, NVS_OP_DST, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MIN, NVS_OP_MIN, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MAX, NVS_OP_MAX, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SLT, NVS_OP_SLT, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SGE, NVS_OP_SGE, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_FRC, NVS_OP_FRC, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_FLR, NVS_OP_FLR, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TEX, NVS_OP_TEX, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TXD, NVS_OP_TXD, 0, 1, 2); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TXP, NVS_OP_TXP, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TXB, NVS_OP_TXB, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SEQ, NVS_OP_SEQ, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SGT, NVS_OP_SGT, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SLE, NVS_OP_SLE, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SNE, NVS_OP_SNE, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_RCP, NVS_OP_RCP, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_LG2, NVS_OP_LG2, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_EX2, NVS_OP_EX2, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_COS, NVS_OP_COS, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SIN, NVS_OP_SIN, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_NOP, NVS_OP_NOP, -1, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DDX, NVS_OP_DDX, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DDY, NVS_OP_DDY, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_KIL, NVS_OP_KIL, -1, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK4B, NVS_OP_PK4B, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP4B, NVS_OP_UP4B, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK2H, NVS_OP_PK2H, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP2H, NVS_OP_UP2H, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK4UB, NVS_OP_PK4UB, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP4UB, NVS_OP_UP4UB, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK2US, NVS_OP_PK2US, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP2US, NVS_OP_UP2US, 0, -1, -1); - /*FIXME: Haven't confirmed the source positions for the below opcodes */ - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_LIT, NVS_OP_LIT, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_LRP, NVS_OP_LRP, 0, 1, 2); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_POW, NVS_OP_POW, 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_RSQ, NVS_OP_RSQ, 0, -1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_RFL, NVS_OP_RFL, 0, 1, -1); - - shader->GetOPTXRec = NV30FPGetOPTXRec; - shader->GetOPTXFromSOP = NV30FPGetOPTXFromSOP; - - shader->UploadToHW = NV30FPUploadToHW; - shader->UpdateConst = NV30FPUpdateConst; - - shader->InitInstruction = NV30FPInitInstruction; - shader->SupportsOpcode = NV30FPSupportsOpcode; - shader->SetOpcode = NV30FPSetOpcode; - shader->SetCCUpdate = NV30FPSetCCUpdate; - shader->SetCondition = NV30FPSetCondition; - shader->SetResult = NV30FPSetResult; - shader->SetSource = NV30FPSetSource; - shader->SetTexImageUnit = NV30FPSetTexImageUnit; - shader->SetSaturate = NV30FPSetSaturate; - shader->SetLastInst = NV30FPSetLastInst; - - shader->HasMergedInst = NV30FPHasMergedInst; - shader->IsLastInst = NV30FPIsLastInst; - shader->GetOffsetNext = NV30FPGetOffsetNext; - shader->GetOpcode = NV30FPGetOpcode; - shader->GetOpcodeHW = NV30FPGetOpcodeHW; - shader->GetDestFile = NV30FPGetDestFile; - shader->GetDestID = NV30FPGetDestID; - shader->GetDestMask = NV30FPGetDestMask; - shader->GetSourceHW = NV30FPGetSourceHW; - shader->GetSourceFile = NV30FPGetSourceFile; - shader->GetSourceID = NV30FPGetSourceID; - shader->GetTexImageUnit = NV30FPGetTexImageUnit; - shader->GetSourceNegate = NV30FPGetSourceNegate; - shader->GetSourceAbs = NV30FPGetSourceAbs; - shader->GetSourceSwizzle = NV30FPGetSourceSwizzle; - shader->GetSourceIndexed = NV30FPGetSourceIndexed; - shader->GetSourceConstVal = NV30FPGetSourceConstVal; - shader->GetSourceScale = NV30FPGetSourceScale; - shader->GetRelAddressRegID = NV30FPGetAddressRegID; - shader->GetRelAddressSwizzle = NV30FPGetAddressRegSwizzle; - shader->GetPrecision = NV30FPGetPrecision; - shader->GetSaturate = NV30FPGetSaturate; - shader->SupportsConditional = NV30FPSupportsConditional; - shader->GetConditionUpdate = NV30FPGetConditionUpdate; - shader->GetConditionTest = NV30FPGetConditionTest; - shader->GetCondition = NV30FPGetCondition; - shader->GetCondRegSwizzle = NV30FPGetCondRegSwizzle; - shader->GetCondRegID = NV30FPGetCondRegID; -} diff --git a/src/mesa/drivers/dri/nouveau/nv30_shader.h b/src/mesa/drivers/dri/nouveau/nv30_shader.h deleted file mode 100644 index 7a027dd4273..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv30_shader.h +++ /dev/null @@ -1,379 +0,0 @@ -#ifndef __NV30_SHADER_H__ -#define __NV30_SHADER_H__ - -/* Vertex programs instruction set - * - * 128bit opcodes, split into 4 32-bit ones for ease of use. - * - * Non-native instructions - * ABS - MOV + NV40_VP_INST0_DEST_ABS - * POW - EX2 + MUL + LG2 - * SUB - ADD, second source negated - * SWZ - MOV - * XPD - - * - * Register access - * - Only one INPUT can be accessed per-instruction (move extras into TEMPs) - * - Only one CONST can be accessed per-instruction (move extras into TEMPs) - * - * Relative Addressing - * According to the value returned for MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB - * there are only two address registers available. The destination in the ARL - * instruction is set to TEMP <n> (The temp isn't actually written). - * - * When using vanilla ARB_v_p, the proprietary driver will squish both the available - * ADDRESS regs into the first hardware reg in the X and Y components. - * - * To use an address reg as an index into consts, the CONST_SRC is set to - * (const_base + offset) and INDEX_CONST is set. - * - * To access the second address reg use ADDR_REG_SELECT_1. A particular component - * of the address regs is selected with ADDR_SWZ. - * - * Only one address register can be accessed per instruction. - * - * Conditional execution (see NV_vertex_program{2,3} for details) - * Conditional execution of an instruction is enabled by setting COND_TEST_ENABLE, and - * selecting the condition which will allow the test to pass with COND_{FL,LT,...}. - * It is possible to swizzle the values in the condition register, which allows for - * testing against an individual component. - * - * Branching - * The BRA/CAL instructions seem to follow a slightly different opcode layout. The - * destination instruction ID (IADDR) overlaps a source field. Instruction ID's seem to - * be numbered based on the UPLOAD_FROM_ID FIFO command, and is incremented automatically - * on each UPLOAD_INST FIFO command. - * - * Conditional branching is achieved by using the condition tests described above. - * There doesn't appear to be dedicated looping instructions, but this can be done - * using a temp reg + conditional branching. - * - * Subroutines may be uploaded before the main program itself, but the first executed - * instruction is determined by the PROGRAM_START_ID FIFO command. - * - */ - -/* DWORD 0 */ -#define NV30_VP_INST_ADDR_REG_SELECT_1 (1 << 24) -#define NV30_VP_INST_SRC2_ABS (1 << 23) /* guess */ -#define NV30_VP_INST_SRC1_ABS (1 << 22) /* guess */ -#define NV30_VP_INST_SRC0_ABS (1 << 21) /* guess */ -#define NV30_VP_INST_OUT_RESULT (1 << 20) -#define NV30_VP_INST_DEST_TEMP_ID_SHIFT 16 -#define NV30_VP_INST_DEST_TEMP_ID_MASK (0x0F << 16) -#define NV30_VP_INST_COND_UPDATE_ENABLE (1<<15) -#define NV30_VP_INST_COND_TEST_ENABLE (1<<14) -#define NV30_VP_INST_COND_SHIFT 11 -#define NV30_VP_INST_COND_MASK (0x07 << 11) -# define NV30_VP_INST_COND_FL 0 /* guess */ -# define NV30_VP_INST_COND_LT 1 -# define NV30_VP_INST_COND_EQ 2 -# define NV30_VP_INST_COND_LE 3 -# define NV30_VP_INST_COND_GT 4 -# define NV30_VP_INST_COND_NE 5 -# define NV30_VP_INST_COND_GE 6 -# define NV30_VP_INST_COND_TR 7 /* guess */ -#define NV30_VP_INST_COND_SWZ_X_SHIFT 9 -#define NV30_VP_INST_COND_SWZ_X_MASK (0x03 << 9) -#define NV30_VP_INST_COND_SWZ_Y_SHIFT 7 -#define NV30_VP_INST_COND_SWZ_Y_MASK (0x03 << 7) -#define NV30_VP_INST_COND_SWZ_Z_SHIFT 5 -#define NV30_VP_INST_COND_SWZ_Z_MASK (0x03 << 5) -#define NV30_VP_INST_COND_SWZ_W_SHIFT 3 -#define NV30_VP_INST_COND_SWZ_W_MASK (0x03 << 3) -#define NV30_VP_INST_COND_SWZ_ALL_SHIFT 3 -#define NV30_VP_INST_COND_SWZ_ALL_MASK (0xFF << 3) -#define NV30_VP_INST_ADDR_SWZ_SHIFT 1 -#define NV30_VP_INST_ADDR_SWZ_MASK (0x03 << 1) -#define NV30_VP_INST_SCA_OPCODEH_SHIFT 0 -#define NV30_VP_INST_SCA_OPCODEH_MASK (0x01 << 0) - -/* DWORD 1 */ -#define NV30_VP_INST_SCA_OPCODEL_SHIFT 28 -#define NV30_VP_INST_SCA_OPCODEL_MASK (0x0F << 28) -# define NV30_VP_INST_OP_NOP 0x00 -# define NV30_VP_INST_OP_RCP 0x02 -# define NV30_VP_INST_OP_RCC 0x03 -# define NV30_VP_INST_OP_RSQ 0x04 -# define NV30_VP_INST_OP_EXP 0x05 -# define NV30_VP_INST_OP_LOG 0x06 -# define NV30_VP_INST_OP_LIT 0x07 -# define NV30_VP_INST_OP_BRA 0x09 -# define NV30_VP_INST_OP_CAL 0x0B -# define NV30_VP_INST_OP_RET 0x0C -# define NV30_VP_INST_OP_LG2 0x0D -# define NV30_VP_INST_OP_EX2 0x0E -# define NV30_VP_INST_OP_SIN 0x0F -# define NV30_VP_INST_OP_COS 0x10 -#define NV30_VP_INST_VEC_OPCODE_SHIFT 23 -#define NV30_VP_INST_VEC_OPCODE_MASK (0x1F << 23) -# define NV30_VP_INST_OP_NOPV 0x00 -# define NV30_VP_INST_OP_MOV 0x01 -# define NV30_VP_INST_OP_MUL 0x02 -# define NV30_VP_INST_OP_ADD 0x03 -# define NV30_VP_INST_OP_MAD 0x04 -# define NV30_VP_INST_OP_DP3 0x05 -# define NV30_VP_INST_OP_DP4 0x07 -# define NV30_VP_INST_OP_DPH 0x06 -# define NV30_VP_INST_OP_DST 0x08 -# define NV30_VP_INST_OP_MIN 0x09 -# define NV30_VP_INST_OP_MAX 0x0A -# define NV30_VP_INST_OP_SLT 0x0B -# define NV30_VP_INST_OP_SGE 0x0C -# define NV30_VP_INST_OP_ARL 0x0D -# define NV30_VP_INST_OP_FRC 0x0E -# define NV30_VP_INST_OP_FLR 0x0F -# define NV30_VP_INST_OP_SEQ 0x10 -# define NV30_VP_INST_OP_SFL 0x11 -# define NV30_VP_INST_OP_SGT 0x12 -# define NV30_VP_INST_OP_SLE 0x13 -# define NV30_VP_INST_OP_SNE 0x14 -# define NV30_VP_INST_OP_STR 0x15 -# define NV30_VP_INST_OP_SSG 0x16 -# define NV30_VP_INST_OP_ARR 0x17 -# define NV30_VP_INST_OP_ARA 0x18 -#define NV30_VP_INST_CONST_SRC_SHIFT 14 -#define NV30_VP_INST_CONST_SRC_MASK (0xFF << 14) -#define NV30_VP_INST_INPUT_SRC_SHIFT 9 /*NV20*/ -#define NV30_VP_INST_INPUT_SRC_MASK (0x0F << 9) /*NV20*/ -# define NV30_VP_INST_IN_POS 0 /* These seem to match the bindings specified in */ -# define NV30_VP_INST_IN_WEIGHT 1 /* the ARB_v_p spec (2.14.3.1) */ -# define NV30_VP_INST_IN_NORMAL 2 -# define NV30_VP_INST_IN_COL0 3 /* Should probably confirm them all though */ -# define NV30_VP_INST_IN_COL1 4 -# define NV30_VP_INST_IN_FOGC 5 -# define NV30_VP_INST_IN_TC0 8 -# define NV30_VP_INST_IN_TC(n) (8+n) -#define NV30_VP_INST_SRC0H_SHIFT 0 /*NV20*/ -#define NV30_VP_INST_SRC0H_MASK (0x1FF << 0) /*NV20*/ - -/* DWORD 2 */ -#define NV30_VP_INST_SRC0L_SHIFT 26 /*NV20*/ -#define NV30_VP_INST_SRC0L_MASK (0x3F <<26) /*NV20*/ -#define NV30_VP_INST_SRC1_SHIFT 11 /*NV20*/ -#define NV30_VP_INST_SRC1_MASK (0x7FFF<<11) /*NV20*/ -#define NV30_VP_INST_SRC2H_SHIFT 0 /*NV20*/ -#define NV30_VP_INST_SRC2H_MASK (0x7FF << 0) /*NV20*/ -#define NV30_VP_INST_IADDR_SHIFT 2 -#define NV30_VP_INST_IADDR_MASK (0xFF << 2) /* guess */ - -/* DWORD 3 */ -#define NV30_VP_INST_SRC2L_SHIFT 28 /*NV20*/ -#define NV30_VP_INST_SRC2L_MASK (0x0F <<28) /*NV20*/ -#define NV30_VP_INST_STEMP_WRITEMASK_SHIFT 24 -#define NV30_VP_INST_STEMP_WRITEMASK_MASK (0x0F << 24) -#define NV30_VP_INST_VTEMP_WRITEMASK_SHIFT 20 -#define NV30_VP_INST_VTEMP_WRITEMASK_MASK (0x0F << 20) -#define NV30_VP_INST_SDEST_WRITEMASK_SHIFT 16 -#define NV30_VP_INST_SDEST_WRITEMASK_MASK (0x0F << 16) -#define NV30_VP_INST_VDEST_WRITEMASK_SHIFT 12 /*NV20*/ -#define NV30_VP_INST_VDEST_WRITEMASK_MASK (0x0F << 12) /*NV20*/ -#define NV30_VP_INST_DEST_ID_SHIFT 2 -#define NV30_VP_INST_DEST_ID_MASK (0x0F << 2) -# define NV30_VP_INST_DEST_POS 0 -# define NV30_VP_INST_DEST_COL0 3 -# define NV30_VP_INST_DEST_COL1 4 -# define NV30_VP_INST_DEST_TC(n) (8+n) - -/* Source-register definition - matches NV20 exactly */ -#define NV30_VP_SRC_REG_NEGATE (1<<14) -#define NV30_VP_SRC_REG_SWZ_X_SHIFT 12 -#define NV30_VP_SRC_REG_SWZ_X_MASK (0x03 <<12) -#define NV30_VP_SRC_REG_SWZ_Y_SHIFT 10 -#define NV30_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10) -#define NV30_VP_SRC_REG_SWZ_Z_SHIFT 8 -#define NV30_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8) -#define NV30_VP_SRC_REG_SWZ_W_SHIFT 6 -#define NV30_VP_SRC_REG_SWZ_W_MASK (0x03 << 6) -#define NV30_VP_SRC_REG_SWZ_ALL_SHIFT 6 -#define NV30_VP_SRC_REG_SWZ_ALL_MASK (0xFF << 6) -#define NV30_VP_SRC_REG_TEMP_ID_SHIFT 2 -#define NV30_VP_SRC_REG_TEMP_ID_MASK (0x0F << 0) -#define NV30_VP_SRC_REG_TYPE_SHIFT 0 -#define NV30_VP_SRC_REG_TYPE_MASK (0x03 << 0) -#define NV30_VP_SRC_REG_TYPE_TEMP 1 -#define NV30_VP_SRC_REG_TYPE_INPUT 2 -#define NV30_VP_SRC_REG_TYPE_CONST 3 /* guess */ - -/* - * Each fragment program opcode appears to be comprised of 4 32-bit values. - * - * 0 - Opcode, output reg/mask, ATTRIB source - * 1 - Source 0 - * 2 - Source 1 - * 3 - Source 2 - * - * There appears to be no special difference between result regs and temp regs. - * result.color == R0.xyzw - * result.depth == R1.z - * When the fragprog contains instructions to write depth, NV30_TCL_PRIMITIVE_3D_UNK1D78=0 - * otherwise it is set to 1. - * - * Constants are inserted directly after the instruction that uses them. - * - * It appears that it's not possible to use two input registers in one - * instruction as the input sourcing is done in the instruction dword - * and not the source selection dwords. As such instructions such as: - * - * ADD result.color, fragment.color, fragment.texcoord[0]; - * - * must be split into two MOV's and then an ADD (nvidia does this) but - * I'm not sure why it's not just one MOV and then source the second input - * in the ADD instruction.. - * - * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary - * negation requires multiplication with a const. - * - * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO/SWIZZLE_ONE - * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as SWIZZLE_ZERO - * is implemented simply by not writing to the relevant components of the destination. - * - * Conditional execution - * TODO - * - * Non-native instructions: - * LIT - * LRP - MAD+MAD - * SUB - ADD, negate second source - * RSQ - LG2 + EX2 - * POW - LG2 + MUL + EX2 - * SCS - COS + SIN - * XPD - */ - -//== Opcode / Destination selection == -#define NV30_FP_OP_PROGRAM_END (1 << 0) -#define NV30_FP_OP_OUT_REG_SHIFT 1 -#define NV30_FP_OP_OUT_REG_MASK (31 << 1) /* uncertain */ -/* Needs to be set when writing outputs to get expected result.. */ -#define NV30_FP_OP_UNK0_7 (1 << 7) -#define NV30_FP_OP_COND_WRITE_ENABLE (1 << 8) -#define NV30_FP_OP_OUTMASK_SHIFT 9 -#define NV30_FP_OP_OUTMASK_MASK (0xF << 9) -# define NV30_FP_OP_OUT_X (1<<9) -# define NV30_FP_OP_OUT_Y (1<<10) -# define NV30_FP_OP_OUT_Z (1<<11) -# define NV30_FP_OP_OUT_W (1<<12) -/* Uncertain about these, especially the input_src values.. it's possible that - * they can be dynamically changed. - */ -#define NV30_FP_OP_INPUT_SRC_SHIFT 13 -#define NV30_FP_OP_INPUT_SRC_MASK (15 << 13) -# define NV30_FP_OP_INPUT_SRC_POSITION 0x0 -# define NV30_FP_OP_INPUT_SRC_COL0 0x1 -# define NV30_FP_OP_INPUT_SRC_COL1 0x2 -# define NV30_FP_OP_INPUT_SRC_FOGC 0x3 -# define NV30_FP_OP_INPUT_SRC_TC0 0x4 -# define NV30_FP_OP_INPUT_SRC_TC(n) (0x4 + n) -#define NV30_FP_OP_TEX_UNIT_SHIFT 17 -#define NV30_FP_OP_TEX_UNIT_MASK (0xF << 17) /* guess */ -#define NV30_FP_OP_PRECISION_SHIFT 22 -#define NV30_FP_OP_PRECISION_MASK (3 << 22) -# define NV30_FP_PRECISION_FP32 0 -# define NV30_FP_PRECISION_FP16 1 -# define NV30_FP_PRECISION_FX12 2 -#define NV30_FP_OP_OPCODE_SHIFT 24 -#define NV30_FP_OP_OPCODE_MASK (0x3F << 24) -# define NV30_FP_OP_OPCODE_NOP 0x00 -# define NV30_FP_OP_OPCODE_MOV 0x01 -# define NV30_FP_OP_OPCODE_MUL 0x02 -# define NV30_FP_OP_OPCODE_ADD 0x03 -# define NV30_FP_OP_OPCODE_MAD 0x04 -# define NV30_FP_OP_OPCODE_DP3 0x05 -# define NV30_FP_OP_OPCODE_DP4 0x06 -# define NV30_FP_OP_OPCODE_DST 0x07 -# define NV30_FP_OP_OPCODE_MIN 0x08 -# define NV30_FP_OP_OPCODE_MAX 0x09 -# define NV30_FP_OP_OPCODE_SLT 0x0A -# define NV30_FP_OP_OPCODE_SGE 0x0B -# define NV30_FP_OP_OPCODE_SLE 0x0C -# define NV30_FP_OP_OPCODE_SGT 0x0D -# define NV30_FP_OP_OPCODE_SNE 0x0E -# define NV30_FP_OP_OPCODE_SEQ 0x0F -# define NV30_FP_OP_OPCODE_FRC 0x10 -# define NV30_FP_OP_OPCODE_FLR 0x11 -# define NV30_FP_OP_OPCODE_KIL 0x12 -# define NV30_FP_OP_OPCODE_PK4B 0x13 -# define NV30_FP_OP_OPCODE_UP4B 0x14 -# define NV30_FP_OP_OPCODE_DDX 0x15 /* can only write XY */ -# define NV30_FP_OP_OPCODE_DDY 0x16 /* can only write XY */ -# define NV30_FP_OP_OPCODE_TEX 0x17 -# define NV30_FP_OP_OPCODE_TXP 0x18 -# define NV30_FP_OP_OPCODE_TXD 0x19 -# define NV30_FP_OP_OPCODE_RCP 0x1A -# define NV30_FP_OP_OPCODE_RSQ 0x1B -# define NV30_FP_OP_OPCODE_EX2 0x1C -# define NV30_FP_OP_OPCODE_LG2 0x1D -# define NV30_FP_OP_OPCODE_LIT 0x1E -# define NV30_FP_OP_OPCODE_LRP 0x1F -# define NV30_FP_OP_OPCODE_COS 0x22 -# define NV30_FP_OP_OPCODE_SIN 0x23 -# define NV30_FP_OP_OPCODE_PK2H 0x24 -# define NV30_FP_OP_OPCODE_UP2H 0x25 -# define NV30_FP_OP_OPCODE_POW 0x26 -# define NV30_FP_OP_OPCODE_PK4UB 0x27 -# define NV30_FP_OP_OPCODE_UP4UB 0x28 -# define NV30_FP_OP_OPCODE_PK2US 0x29 -# define NV30_FP_OP_OPCODE_UP2US 0x2A -# define NV30_FP_OP_OPCODE_DP2A 0x2E -# define NV30_FP_OP_OPCODE_TXB 0x31 -# define NV30_FP_OP_OPCODE_RFL 0x36 -#define NV30_FP_OP_OUT_SAT (1 << 31) - -/* high order bits of SRC0 */ -#define NV30_FP_OP_OUT_ABS (1 << 29) -#define NV30_FP_OP_COND_SWZ_W_SHIFT 27 -#define NV30_FP_OP_COND_SWZ_W_MASK (3 << 27) -#define NV30_FP_OP_COND_SWZ_Z_SHIFT 25 -#define NV30_FP_OP_COND_SWZ_Z_MASK (3 << 25) -#define NV30_FP_OP_COND_SWZ_Y_SHIFT 23 -#define NV30_FP_OP_COND_SWZ_Y_MASK (3 << 23) -#define NV30_FP_OP_COND_SWZ_X_SHIFT 21 -#define NV30_FP_OP_COND_SWZ_X_MASK (3 << 21) -#define NV30_FP_OP_COND_SWZ_ALL_SHIFT 21 -#define NV30_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21) -#define NV30_FP_OP_COND_SHIFT 18 -#define NV30_FP_OP_COND_MASK (0x07 << 18) -# define NV30_FP_OP_COND_FL 0 -# define NV30_FP_OP_COND_LT 1 -# define NV30_FP_OP_COND_EQ 2 -# define NV30_FP_OP_COND_LE 3 -# define NV30_FP_OP_COND_GT 4 -# define NV30_FP_OP_COND_NE 5 -# define NV30_FP_OP_COND_GE 6 -# define NV30_FP_OP_COND_TR 7 - -/* high order bits of SRC1 */ -#define NV30_FP_OP_SRC_SCALE_SHIFT 28 -#define NV30_FP_OP_SRC_SCALE_MASK (3 << 28) - -/* high order bits of SRC2 */ -#define NV30_FP_OP_INDEX_INPUT (1 << 30) - -//== Register selection == -#define NV30_FP_REG_ALL_MASK (0x1FFFF<<0) -#define NV30_FP_REG_TYPE_SHIFT 0 -#define NV30_FP_REG_TYPE_MASK (3 << 0) -# define NV30_FP_REG_TYPE_TEMP 0 -# define NV30_FP_REG_TYPE_INPUT 1 -# define NV30_FP_REG_TYPE_CONST 2 -#define NV30_FP_REG_SRC_SHIFT 2 /* uncertain */ -#define NV30_FP_REG_SRC_MASK (31 << 2) -#define NV30_FP_REG_UNK_0 (1 << 8) -#define NV30_FP_REG_SWZ_ALL_SHIFT 9 -#define NV30_FP_REG_SWZ_ALL_MASK (255 << 9) -#define NV30_FP_REG_SWZ_X_SHIFT 9 -#define NV30_FP_REG_SWZ_X_MASK (3 << 9) -#define NV30_FP_REG_SWZ_Y_SHIFT 11 -#define NV30_FP_REG_SWZ_Y_MASK (3 << 11) -#define NV30_FP_REG_SWZ_Z_SHIFT 13 -#define NV30_FP_REG_SWZ_Z_MASK (3 << 13) -#define NV30_FP_REG_SWZ_W_SHIFT 15 -#define NV30_FP_REG_SWZ_W_MASK (3 << 15) -# define NV30_FP_SWIZZLE_X 0 -# define NV30_FP_SWIZZLE_Y 1 -# define NV30_FP_SWIZZLE_Z 2 -# define NV30_FP_SWIZZLE_W 3 -#define NV30_FP_REG_NEGATE (1 << 17) - -#endif diff --git a/src/mesa/drivers/dri/nouveau/nv30_state.c b/src/mesa/drivers/dri/nouveau/nv30_state.c deleted file mode 100644 index cd3ee986880..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv30_state.c +++ /dev/null @@ -1,1002 +0,0 @@ -/************************************************************************** - -Copyright 2006 Nouveau -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" -#include "nouveau_state.h" - -#include "tnl/t_pipeline.h" - -#include "mtypes.h" -#include "colormac.h" - -#define NOUVEAU_CARD_USING_SHADERS (nmesa->screen->card->type >= NV_40) - -static void nv30AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte ubRef; - CLAMPED_FLOAT_TO_UBYTE(ubRef, ref); - - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC, 2); - OUT_RING_CACHE(func); /* NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC */ - OUT_RING_CACHE(ubRef); /* NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF */ -} - -static void nv30BlendColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte cf[4]; - - CLAMPED_FLOAT_TO_UBYTE(cf[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(cf[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(cf[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(cf[3], color[3]); - - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_COLOR, 1); - OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0])); -} - -static void nv30BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_EQUATION, 1); - OUT_RING_CACHE((modeA<<16) | modeRGB); -} - - -static void nv30BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC, 2); - OUT_RING_CACHE((sfactorA<<16) | sfactorRGB); - OUT_RING_CACHE((dfactorA<<16) | dfactorRGB); -} - -static void nv30Clear(GLcontext *ctx, GLbitfield mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLuint hw_bufs = 0; - - if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT)) - hw_bufs |= 0xf0; - if (mask & (BUFFER_BIT_DEPTH)) - hw_bufs |= 0x03; - - if (hw_bufs) { - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS, 1); - OUT_RING(hw_bufs); - } -} - -static void nv30ClearColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte c[4]; - UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,color); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB, 1); - OUT_RING_CACHE(PACK_COLOR_8888(c[3],c[0],c[1],c[2])); -} - -static void nv30ClearDepth(GLcontext *ctx, GLclampd d) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nmesa->clear_value=((nmesa->clear_value&0x000000FF)|(((uint32_t)(d*0xFFFFFF))<<8)); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1); - OUT_RING_CACHE(nmesa->clear_value); -} - -/* we're don't support indexed buffers - void (*ClearIndex)(GLcontext *ctx, GLuint index) - */ - -static void nv30ClearStencil(GLcontext *ctx, GLint s) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - nmesa->clear_value=((nmesa->clear_value&0xFFFFFF00)|(s&0x000000FF)); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1); - OUT_RING_CACHE(nmesa->clear_value); -} - -static void nv30ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (NOUVEAU_CARD_USING_SHADERS) - return; - - plane -= GL_CLIP_PLANE0; - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_A(plane), 4); - OUT_RING_CACHEf(equation[0]); - OUT_RING_CACHEf(equation[1]); - OUT_RING_CACHEf(equation[2]); - OUT_RING_CACHEf(equation[3]); -} - -static void nv30ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask, - GLboolean bmask, GLboolean amask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_COLOR_MASK, 1); - OUT_RING_CACHE(((amask && 0x01) << 24) | ((rmask && 0x01) << 16) | ((gmask && 0x01)<< 8) | ((bmask && 0x01) << 0)); -} - -static void nv30ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode) -{ - // TODO I need love -} - -static void nv30CullFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CULL_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv30FrontFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FRONT_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv30DepthFunc(GLcontext *ctx, GLenum func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1); - OUT_RING_CACHE(func); -} - -static void nv30DepthMask(GLcontext *ctx, GLboolean flag) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1); - OUT_RING_CACHE(flag); -} - -static void nv30DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2); - OUT_RING_CACHEf(nearval); - OUT_RING_CACHEf(farval); -} - -/** Specify the current buffer for writing */ -//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer ); -/** Specify the buffers for writing for fragment programs*/ -//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers ); - -static void nv30Enable(GLcontext *ctx, GLenum cap, GLboolean state) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - switch(cap) - { - case GL_ALPHA_TEST: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_AUTO_NORMAL: - case GL_BLEND: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_CLIP_PLANE0: - case GL_CLIP_PLANE1: - case GL_CLIP_PLANE2: - case GL_CLIP_PLANE3: - case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: - if (NOUVEAU_CARD_USING_SHADERS) { - nouveauShader *nvs = (nouveauShader *)ctx->VertexProgram._Current; - if (nvs) - nvs->translated = GL_FALSE; - } else { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(cap-GL_CLIP_PLANE0), 1); - OUT_RING_CACHE(state); - } - break; - case GL_COLOR_LOGIC_OP: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_COLOR_MATERIAL: -// case GL_COLOR_SUM_EXT: -// case GL_COLOR_TABLE: -// case GL_CONVOLUTION_1D: -// case GL_CONVOLUTION_2D: - case GL_CULL_FACE: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DEPTH_TEST: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DITHER: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DITHER_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_FOG: - if (NOUVEAU_CARD_USING_SHADERS) - break; - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_HISTOGRAM: -// case GL_INDEX_LOGIC_OP: - case GL_LIGHT0: - case GL_LIGHT1: - case GL_LIGHT2: - case GL_LIGHT3: - case GL_LIGHT4: - case GL_LIGHT5: - case GL_LIGHT6: - case GL_LIGHT7: - { - uint32_t mask=0x11<<(2*(cap-GL_LIGHT0)); - - if (NOUVEAU_CARD_USING_SHADERS) - break; - - nmesa->enabled_lights=((nmesa->enabled_lights&mask)|(mask*state)); - if (nmesa->lighting_enabled) - { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1); - OUT_RING_CACHE(nmesa->enabled_lights); - } - break; - } - case GL_LIGHTING: - if (NOUVEAU_CARD_USING_SHADERS) - break; - - nmesa->lighting_enabled=state; - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1); - if (nmesa->lighting_enabled) - OUT_RING_CACHE(nmesa->enabled_lights); - else - OUT_RING_CACHE(0x0); - break; -// case GL_LINE_SMOOTH: -// case GL_LINE_STIPPLE: -// case GL_MAP1_COLOR_4: -// case GL_MAP1_INDEX: -// case GL_MAP1_NORMAL: -// case GL_MAP1_TEXTURE_COORD_1: -// case GL_MAP1_TEXTURE_COORD_2: -// case GL_MAP1_TEXTURE_COORD_3: -// case GL_MAP1_TEXTURE_COORD_4: -// case GL_MAP1_VERTEX_3: -// case GL_MAP1_VERTEX_4: -// case GL_MAP2_COLOR_4: -// case GL_MAP2_INDEX: -// case GL_MAP2_NORMAL: -// case GL_MAP2_TEXTURE_COORD_1: -// case GL_MAP2_TEXTURE_COORD_2: -// case GL_MAP2_TEXTURE_COORD_3: -// case GL_MAP2_TEXTURE_COORD_4: -// case GL_MAP2_VERTEX_3: -// case GL_MAP2_VERTEX_4: -// case GL_MINMAX: - case GL_NORMALIZE: - if (nmesa->screen->card->type != NV_44) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1); - OUT_RING_CACHE(state); - } - break; -// case GL_POINT_SMOOTH: - case GL_POLYGON_OFFSET_POINT: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_LINE: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_FILL: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_STIPPLE: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_POST_COLOR_MATRIX_COLOR_TABLE: -// case GL_POST_CONVOLUTION_COLOR_TABLE: -// case GL_RESCALE_NORMAL: - case GL_SCISSOR_TEST: - /* No enable bit, nv30Scissor will adjust to max range */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - break; -// case GL_SEPARABLE_2D: - case GL_STENCIL_TEST: - // TODO BACK and FRONT ? - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE, 1); - OUT_RING_CACHE(state); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_TEXTURE_GEN_Q: -// case GL_TEXTURE_GEN_R: -// case GL_TEXTURE_GEN_S: -// case GL_TEXTURE_GEN_T: -// case GL_TEXTURE_1D: -// case GL_TEXTURE_2D: -// case GL_TEXTURE_3D: - } -} - -static void nv30Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (NOUVEAU_CARD_USING_SHADERS) - return; - - switch(pname) - { - case GL_FOG_MODE: - { - int mode = 0; - /* The modes are different in GL and the card. */ - switch(ctx->Fog.Mode) - { - case GL_LINEAR: - mode = 0x804; - break; - case GL_EXP: - mode = 0x802; - break; - case GL_EXP2: - mode = 0x803; - break; - } - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_MODE, 1); - OUT_RING_CACHE (mode); - break; - } - case GL_FOG_COLOR: - { - GLubyte c[4]; - UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,params); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_COLOR, 1); - /* nvidia ignores the alpha channel */ - OUT_RING_CACHE(PACK_COLOR_8888_REV(c[0],c[1],c[2],c[3])); - break; - } - case GL_FOG_DENSITY: - case GL_FOG_START: - case GL_FOG_END: - { - GLfloat f=0., c=0.; - switch(ctx->Fog.Mode) - { - case GL_LINEAR: - f = -1.0/(ctx->Fog.End - ctx->Fog.Start); - c = ctx->Fog.Start/(ctx->Fog.End - ctx->Fog.Start) + 2.001953; - break; - case GL_EXP: - f = -0.090168*ctx->Fog.Density; - c = 1.5; - case GL_EXP2: - f = -0.212330*ctx->Fog.Density; - c = 1.5; - } - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR, 1); - OUT_RING_CACHE(f); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT, 1); - OUT_RING_CACHE(c); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC, 1); - OUT_RING_CACHE(0); /* Is this always the same? */ - break; - } -// case GL_FOG_COORD_SRC: - default: - break; - } -} - -static void nv30Hint(GLcontext *ctx, GLenum target, GLenum mode) -{ - // TODO I need love (fog and line_smooth hints) -} - -// void (*IndexMask)(GLcontext *ctx, GLuint mask); - -enum { - SPOTLIGHT_NO_UPDATE, - SPOTLIGHT_UPDATE_EXPONENT, - SPOTLIGHT_UPDATE_DIRECTION, - SPOTLIGHT_UPDATE_ALL -}; - -static void nv30Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLint p = light - GL_LIGHT0; - struct gl_light *l = &ctx->Light.Light[p]; - int spotlight_update = SPOTLIGHT_NO_UPDATE; - - if (NOUVEAU_CARD_USING_SHADERS) - return; - - /* not sure where the fourth param value goes...*/ - switch(pname) - { - case GL_AMBIENT: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_DIFFUSE: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_SPECULAR: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_POSITION: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(p), 3); - OUT_RING_CACHEf(params[0]); - OUT_RING_CACHEf(params[1]); - OUT_RING_CACHEf(params[2]); - break; - case GL_SPOT_DIRECTION: - spotlight_update = SPOTLIGHT_UPDATE_DIRECTION; - break; - case GL_SPOT_EXPONENT: - spotlight_update = SPOTLIGHT_UPDATE_EXPONENT; - break; - case GL_SPOT_CUTOFF: - spotlight_update = SPOTLIGHT_UPDATE_ALL; - break; - case GL_CONSTANT_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - case GL_LINEAR_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - case GL_QUADRATIC_ATTENUATION: - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(p), 1); - OUT_RING_CACHEf(*params); - break; - default: - break; - } - - switch(spotlight_update) { - case SPOTLIGHT_UPDATE_DIRECTION: - { - GLfloat x,y,z; - GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0); - x = spot_light_coef_a * l->_NormDirection[0]; - y = spot_light_coef_a * l->_NormDirection[1]; - z = spot_light_coef_a * l->_NormDirection[2]; - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(p), 3); - OUT_RING_CACHEf(x); - OUT_RING_CACHEf(y); - OUT_RING_CACHEf(z); - } - break; - case SPOTLIGHT_UPDATE_EXPONENT: - { - GLfloat cc,lc,qc; - cc = 1.0; /* FIXME: These need to be correctly computed */ - lc = 0.0; - qc = 2.0; - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 3); - OUT_RING_CACHEf(cc); - OUT_RING_CACHEf(lc); - OUT_RING_CACHEf(qc); - } - break; - case SPOTLIGHT_UPDATE_ALL: - { - GLfloat cc,lc,qc, x,y,z, c; - GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0); - cc = 1.0; /* FIXME: These need to be correctly computed */ - lc = 0.0; - qc = 2.0; - x = spot_light_coef_a * l->_NormDirection[0]; - y = spot_light_coef_a * l->_NormDirection[1]; - z = spot_light_coef_a * l->_NormDirection[2]; - c = spot_light_coef_a + 1.0; - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 7); - OUT_RING_CACHEf(cc); - OUT_RING_CACHEf(lc); - OUT_RING_CACHEf(qc); - OUT_RING_CACHEf(x); - OUT_RING_CACHEf(y); - OUT_RING_CACHEf(z); - OUT_RING_CACHEf(c); - } - break; - default: - break; - } -} - -/** Set the lighting model parameters */ -void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params); - - -static void nv30LineStipple(GLcontext *ctx, GLint factor, GLushort pattern ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN, 1); - OUT_RING_CACHE((pattern << 16) | factor); -} - -static void nv30LineWidth(GLcontext *ctx, GLfloat width) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte ubWidth; - - ubWidth = (GLubyte)(width * 8.0) & 0xFF; - - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LINE_WIDTH_SMOOTH, 1); - OUT_RING_CACHE(ubWidth); -} - -static void nv30LogicOpcode(GLcontext *ctx, GLenum opcode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP, 1); - OUT_RING_CACHE(opcode); -} - -static void nv30PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - /*TODO: not sure what goes here. */ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -} - -/** Specify the diameter of rasterized points */ -static void nv30PointSize(GLcontext *ctx, GLfloat size) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POINT_SIZE, 1); - OUT_RING_CACHEf(size); -} - -/** Select a polygon rasterization mode */ -static void nv30PolygonMode(GLcontext *ctx, GLenum face, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1); - OUT_RING_CACHE(mode); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1); - OUT_RING_CACHE(mode); - } -} - -/** Set the scale and units used to calculate depth values */ -static void nv30PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 2); - OUT_RING_CACHEf(factor); - - /* Looks like we always multiply units by 2.0... according to the dumps.*/ - OUT_RING_CACHEf(units * 2.0); -} - -/** Set the polygon stippling pattern */ -static void nv30PolygonStipple(GLcontext *ctx, const GLubyte *mask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(0), 32); - OUT_RING_CACHEp(mask, 32); -} - -/* Specifies the current buffer for reading */ -void (*ReadBuffer)( GLcontext *ctx, GLenum buffer ); -/** Set rasterization mode */ -void (*RenderMode)(GLcontext *ctx, GLenum mode ); - -/* Translate GL coords to window coords, clamping w/h to the - * dimensions of the window. - */ -static void nv30WindowCoords(nouveauContextPtr nmesa, - GLuint x, GLuint y, GLuint w, GLuint h, - GLuint *wX, GLuint *wY, GLuint *wW, GLuint *wH) -{ - if ((x+w) > nmesa->drawW) - w = nmesa->drawW - x; - (*wX) = x + nmesa->drawX; - (*wW) = w; - - if ((y+h) > nmesa->drawH) - h = nmesa->drawH - y; - (*wY) = (nmesa->drawH - y) - h + nmesa->drawY; - (*wH) = h; -} - -/** Define the scissor box */ -static void nv30Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLuint wX, wY, wW, wH; - - /* There's no scissor enable bit, so adjust the scissor to cover the - * maximum draw buffer bounds - */ - if (!ctx->Scissor.Enabled) { - wX = nmesa->drawX; - wY = nmesa->drawY; - wW = nmesa->drawW; - wH = nmesa->drawH; - } else { - nv30WindowCoords(nmesa, x, y, w, h, &wX, &wY, &wW, &wH); - } - - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS, 2); - OUT_RING_CACHE ((wW << 16) | wX); - OUT_RING_CACHE ((wH << 16) | wY); -} - -/** Select flat or smooth shading */ -static void nv30ShadeModel(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SHADE_MODEL, 1); - OUT_RING_CACHE(mode); -} - -/** OpenGL 2.0 two-sided StencilFunc */ -static void nv30StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, - GLint ref, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC, 3); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ref); - OUT_RING_CACHE(mask); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC, 3); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ref); - OUT_RING_CACHE(mask); - } -} - -/** OpenGL 2.0 two-sided StencilMask */ -static void nv30StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK, 1); - OUT_RING_CACHE(mask); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK, 1); - OUT_RING_CACHE(mask); - } -} - -/** OpenGL 2.0 two-sided StencilOp */ -static void nv30StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, - GLenum zfail, GLenum zpass) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL, 3); - OUT_RING_CACHE(fail); - OUT_RING_CACHE(zfail); - OUT_RING_CACHE(zpass); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL, 3); - OUT_RING_CACHE(fail); - OUT_RING_CACHE(zfail); - OUT_RING_CACHE(zpass); - } -} - -/** Control the generation of texture coordinates */ -void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname, - const GLfloat *params); -/** Set texture environment parameters */ -void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname, - const GLfloat *param); -/** Set texture parameters */ -void (*TexParameter)(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat *params); - -static void nv30TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (!NOUVEAU_CARD_USING_SHADERS) { - BEGIN_RING_CACHE(NvSub3D, - NV30_TCL_PRIMITIVE_3D_TX_MATRIX(unit, 0), 16); - /*XXX: This SHOULD work.*/ - OUT_RING_CACHEp(mat->m, 16); - } -} - -static void nv30WindowMoved(nouveauContextPtr nmesa) -{ - GLcontext *ctx = nmesa->glCtx; - GLfloat *v = nmesa->viewport.m; - GLuint wX, wY, wW, wH; - - nv30WindowCoords(nmesa, ctx->Viewport.X, ctx->Viewport.Y, - ctx->Viewport.Width, ctx->Viewport.Height, - &wX, &wY, &wW, &wH); - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0, 2); - OUT_RING_CACHE ((wW << 16) | wX); - OUT_RING_CACHE ((wH << 16) | wY); - - /* something to do with clears, possibly doesn't belong here */ - BEGIN_RING_CACHE(NvSub3D, - NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0, 2); - OUT_RING_CACHE(((nmesa->drawX + nmesa->drawW) << 16) | nmesa->drawX); - OUT_RING_CACHE(((nmesa->drawY + nmesa->drawH) << 16) | nmesa->drawY); - - /* viewport transform */ - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_OX, 8); - OUT_RING_CACHEf (v[MAT_TX]); - OUT_RING_CACHEf (v[MAT_TY]); - OUT_RING_CACHEf (v[MAT_TZ]); - OUT_RING_CACHEf (0.0); - OUT_RING_CACHEf (v[MAT_SX]); - OUT_RING_CACHEf (v[MAT_SY]); - OUT_RING_CACHEf (v[MAT_SZ]); - OUT_RING_CACHEf (0.0); - - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); -} - -static GLboolean nv30InitCard(nouveauContextPtr nmesa) -{ - int i; - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); - - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT1, 3); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaTT); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT8, 1); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT4, 2); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, 0x1b0, 1); /* SET_OBJECT8B*/ - OUT_RING(NvDmaFB); - - for(i = 0x2c8; i <= 0x2fc; i += 4) - { - BEGIN_RING_SIZE(NvSub3D, i, 1); - OUT_RING(0x0); - } - - BEGIN_RING_SIZE(NvSub3D, 0x0220, 1); - OUT_RING(1); - - BEGIN_RING_SIZE(NvSub3D, 0x03b0, 1); - OUT_RING(0x00100000); - BEGIN_RING_SIZE(NvSub3D, 0x1454, 1); - OUT_RING(0); - BEGIN_RING_SIZE(NvSub3D, 0x1d80, 1); - OUT_RING(3); - - /* NEW */ - BEGIN_RING_SIZE(NvSub3D, 0x1e98, 1); - OUT_RING(0); - BEGIN_RING_SIZE(NvSub3D, 0x17e0, 3); - OUT_RING(0); - OUT_RING(0); - OUT_RING(0x3f800000); - BEGIN_RING_SIZE(NvSub3D, 0x1f80, 16); - OUT_RING(0); OUT_RING(0); OUT_RING(0); OUT_RING(0); - OUT_RING(0); OUT_RING(0); OUT_RING(0); OUT_RING(0); - OUT_RING(0x0000ffff); - OUT_RING(0); OUT_RING(0); OUT_RING(0); OUT_RING(0); - OUT_RING(0); OUT_RING(0); OUT_RING(0); -/* - BEGIN_RING_SIZE(NvSub3D, 0x100, 2); - OUT_RING(0); - OUT_RING(0); -*/ - BEGIN_RING_SIZE(NvSub3D, 0x120, 3); - OUT_RING(0); - OUT_RING(1); - OUT_RING(2); - - BEGIN_RING_SIZE(NvSub3D, 0x1d88, 1); - OUT_RING(0x00001200); - - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_RC_ENABLE, 1); - OUT_RING (0); - - return GL_TRUE; -} - -static GLboolean nv40InitCard(nouveauContextPtr nmesa) -{ - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); - - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT1, 2); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT8, 1); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT4, 2); - OUT_RING(NvDmaFB); - OUT_RING(NvDmaFB); - BEGIN_RING_SIZE(NvSub3D, 0x0220, 1); - OUT_RING(1); - - BEGIN_RING_SIZE(NvSub3D, 0x1ea4, 3); - OUT_RING(0x00000010); - OUT_RING(0x01000100); - OUT_RING(0xff800006); - BEGIN_RING_SIZE(NvSub3D, 0x1fc4, 1); - OUT_RING(0x06144321); - BEGIN_RING_SIZE(NvSub3D, 0x1fc8, 2); - OUT_RING(0xedcba987); - OUT_RING(0x00000021); - BEGIN_RING_SIZE(NvSub3D, 0x1fd0, 1); - OUT_RING(0x00171615); - BEGIN_RING_SIZE(NvSub3D, 0x1fd4, 1); - OUT_RING(0x001b1a19); - - BEGIN_RING_SIZE(NvSub3D, 0x1ef8, 1); - OUT_RING(0x0020ffff); - BEGIN_RING_SIZE(NvSub3D, 0x1d64, 1); - OUT_RING(0x00d30000); - BEGIN_RING_SIZE(NvSub3D, 0x1e94, 1); - OUT_RING(0x00000001); - - return GL_TRUE; -} - -static GLboolean -nv30BindBuffers(nouveauContextPtr nmesa, int num_color, - nouveau_renderbuffer_t **color, nouveau_renderbuffer_t *depth) -{ - GLuint x, y, w, h; - - w = color[0]->mesa.Width; - h = color[0]->mesa.Height; - x = nmesa->drawX; - y = nmesa->drawY; - - if (num_color != 1) - return GL_FALSE; - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0, 5); - OUT_RING (((w+x)<<16)|x); - OUT_RING (((h+y)<<16)|y); - if (color[0]->mesa._ActualFormat == GL_RGBA8) - OUT_RING (0x148); - else - OUT_RING (0x143); - if (nmesa->screen->card->type >= NV_40) - OUT_RING (color[0]->pitch); - else - OUT_RING (color[0]->pitch | (depth ? (depth->pitch << 16): 0)); - OUT_RING (color[0]->offset); - - if (depth) { - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_OFFSET, 1); - OUT_RING (depth->offset); - if (nmesa->screen->card->type >= NV_40) { - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH, 1); - OUT_RING (depth->pitch); - } - } - - return GL_TRUE; -} - -void nv30InitStateFuncs(GLcontext *ctx, struct dd_function_table *func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - func->AlphaFunc = nv30AlphaFunc; - func->BlendColor = nv30BlendColor; - func->BlendEquationSeparate = nv30BlendEquationSeparate; - func->BlendFuncSeparate = nv30BlendFuncSeparate; - func->Clear = nv30Clear; - func->ClearColor = nv30ClearColor; - func->ClearDepth = nv30ClearDepth; - func->ClearStencil = nv30ClearStencil; - func->ClipPlane = nv30ClipPlane; - func->ColorMask = nv30ColorMask; - func->ColorMaterial = nv30ColorMaterial; - func->CullFace = nv30CullFace; - func->FrontFace = nv30FrontFace; - func->DepthFunc = nv30DepthFunc; - func->DepthMask = nv30DepthMask; - func->DepthRange = nv30DepthRange; - func->Enable = nv30Enable; - func->Fogfv = nv30Fogfv; - func->Hint = nv30Hint; - func->Lightfv = nv30Lightfv; -/* func->LightModelfv = nv30LightModelfv; */ - func->LineStipple = nv30LineStipple; - func->LineWidth = nv30LineWidth; - func->LogicOpcode = nv30LogicOpcode; - func->PointParameterfv = nv30PointParameterfv; - func->PointSize = nv30PointSize; - func->PolygonMode = nv30PolygonMode; - func->PolygonOffset = nv30PolygonOffset; - func->PolygonStipple = nv30PolygonStipple; -#if 0 - func->ReadBuffer = nv30ReadBuffer; - func->RenderMode = nv30RenderMode; -#endif - func->Scissor = nv30Scissor; - func->ShadeModel = nv30ShadeModel; - func->StencilFuncSeparate = nv30StencilFuncSeparate; - func->StencilMaskSeparate = nv30StencilMaskSeparate; - func->StencilOpSeparate = nv30StencilOpSeparate; -#if 0 - func->TexGen = nv30TexGen; - func->TexParameter = nv30TexParameter; -#endif - func->TextureMatrix = nv30TextureMatrix; - - - if (nmesa->screen->card->type >= NV_40) - nmesa->hw_func.InitCard = nv40InitCard; - else - nmesa->hw_func.InitCard = nv30InitCard; - nmesa->hw_func.BindBuffers = nv30BindBuffers; - nmesa->hw_func.WindowMoved = nv30WindowMoved; -} - diff --git a/src/mesa/drivers/dri/nouveau/nv30_vertprog.c b/src/mesa/drivers/dri/nouveau/nv30_vertprog.c deleted file mode 100644 index d023e8439e3..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv30_vertprog.c +++ /dev/null @@ -1,367 +0,0 @@ -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" - -#include "nouveau_shader.h" -#include "nv30_shader.h" - -/***************************************************************************** - * Support routines - */ -static void -NV30VPUploadToHW(GLcontext *ctx, nouveauShader *nvs) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - int i; - - /* We can do better here and keep more than one VP on the hardware, and - * switch between them with PROGRAM_START_ID.. - */ - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_FROM_ID, 1); - OUT_RING(0); - for (i=0; i<nvs->program_size; i+=4) { - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0, 4); - OUT_RING(nvs->program[i + 0]); - OUT_RING(nvs->program[i + 1]); - OUT_RING(nvs->program[i + 2]); - OUT_RING(nvs->program[i + 3]); - } - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_PROGRAM_START_ID, 1); - OUT_RING(0); - - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_IN_REG, 2); - OUT_RING(nvs->card_priv.NV30VP.vp_in_reg); - OUT_RING(nvs->card_priv.NV30VP.vp_out_reg); - - BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_CLIPPING_PLANES, 1); - OUT_RING_CACHE (nvs->card_priv.NV30VP.clip_enables); -} - -static void -NV30VPUpdateConst(GLcontext *ctx, nouveauShader *nvs, int id) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLfloat *val; - - val = nvs->params[id].source_val ? - nvs->params[id].source_val : nvs->params[id].val; - - BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID, 5); - OUT_RING (id); - OUT_RINGp(val, 4); -} - -/***************************************************************************** - * Assembly routines - */ -static void -NV30VPSetBranchTarget(nvsFunc *shader, int addr) -{ - shader->inst[2] &= ~NV30_VP_INST_IADDR_MASK; - shader->inst[2] |= (addr << NV30_VP_INST_IADDR_SHIFT); -} - -/***************************************************************************** - * Disassembly routines - */ -static unsigned int -NV30VPGetOpcodeHW(nvsFunc * shader, int slot) -{ - int op; - - if (slot) { - op = (shader->inst[1] & NV30_VP_INST_SCA_OPCODEL_MASK) - >> NV30_VP_INST_SCA_OPCODEL_SHIFT; - op |= ((shader->inst[0] & NV30_VP_INST_SCA_OPCODEH_MASK) - >> NV30_VP_INST_SCA_OPCODEH_SHIFT) << 4; - } - else { - op = (shader->inst[1] & NV30_VP_INST_VEC_OPCODE_MASK) - >> NV30_VP_INST_VEC_OPCODE_SHIFT; - } - - return op; -} - -static nvsRegFile -NV30VPGetDestFile(nvsFunc * shader, int merged) -{ - switch (shader->GetOpcode(shader, merged)) { - case NVS_OP_ARL: - case NVS_OP_ARR: - case NVS_OP_ARA: - return NVS_FILE_ADDRESS; - default: - /*FIXME: This probably isn't correct.. */ - if ((shader->inst[3] & NV30_VP_INST_VDEST_WRITEMASK_MASK) != 0) - return NVS_FILE_RESULT; - if ((shader->inst[3] & NV30_VP_INST_SDEST_WRITEMASK_MASK) != 0) - return NVS_FILE_RESULT; - return NVS_FILE_TEMP; - } -} - -static unsigned int -NV30VPGetDestID(nvsFunc * shader, int merged) -{ - int id; - - switch (shader->GetDestFile(shader, merged)) { - case NVS_FILE_RESULT: - id = ((shader->inst[3] & NV30_VP_INST_DEST_ID_MASK) - >> NV30_VP_INST_DEST_ID_SHIFT); - switch (id) { - case NV30_VP_INST_DEST_POS : return NVS_FR_POSITION; - case NV30_VP_INST_DEST_COL0 : return NVS_FR_COL0; - case NV30_VP_INST_DEST_COL1 : return NVS_FR_COL1; - case NV30_VP_INST_DEST_TC(0): return NVS_FR_TEXCOORD0; - case NV30_VP_INST_DEST_TC(1): return NVS_FR_TEXCOORD1; - case NV30_VP_INST_DEST_TC(2): return NVS_FR_TEXCOORD2; - case NV30_VP_INST_DEST_TC(3): return NVS_FR_TEXCOORD3; - case NV30_VP_INST_DEST_TC(4): return NVS_FR_TEXCOORD4; - case NV30_VP_INST_DEST_TC(5): return NVS_FR_TEXCOORD5; - case NV30_VP_INST_DEST_TC(6): return NVS_FR_TEXCOORD6; - case NV30_VP_INST_DEST_TC(7): return NVS_FR_TEXCOORD7; - default: - return -1; - } - case NVS_FILE_ADDRESS: - case NVS_FILE_TEMP: - return (shader->inst[0] & NV30_VP_INST_DEST_TEMP_ID_MASK) - >> NV30_VP_INST_DEST_TEMP_ID_SHIFT; - default: - return -1; - } -} - -static unsigned int -NV30VPGetDestMask(nvsFunc * shader, int merged) -{ - int hwmask, mask = 0; - - if (shader->GetDestFile(shader, merged) == NVS_FILE_RESULT) - if (shader->GetOpcodeSlot(shader, merged)) - hwmask = (shader->inst[3] & NV30_VP_INST_SDEST_WRITEMASK_MASK) - >> NV30_VP_INST_SDEST_WRITEMASK_SHIFT; - else - hwmask = (shader->inst[3] & NV30_VP_INST_VDEST_WRITEMASK_MASK) - >> NV30_VP_INST_VDEST_WRITEMASK_SHIFT; - else if (shader->GetOpcodeSlot(shader, merged)) - hwmask = (shader->inst[3] & NV30_VP_INST_STEMP_WRITEMASK_MASK) - >> NV30_VP_INST_STEMP_WRITEMASK_SHIFT; - else - hwmask = (shader->inst[3] & NV30_VP_INST_VTEMP_WRITEMASK_MASK) - >> NV30_VP_INST_VTEMP_WRITEMASK_SHIFT; - - if (hwmask & (1 << 3)) mask |= SMASK_X; - if (hwmask & (1 << 2)) mask |= SMASK_Y; - if (hwmask & (1 << 1)) mask |= SMASK_Z; - if (hwmask & (1 << 0)) mask |= SMASK_W; - - return mask; -} - -static int -NV30VPGetSourceID(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_TEMP: - src = shader->GetSourceHW(shader, merged, pos); - return ((src & NV30_VP_SRC_REG_TEMP_ID_MASK) >> - NV30_VP_SRC_REG_TEMP_ID_SHIFT); - case NVS_FILE_CONST: - return ((shader->inst[1] & NV30_VP_INST_CONST_SRC_MASK) - >> NV30_VP_INST_CONST_SRC_SHIFT); - case NVS_FILE_ATTRIB: - src = ((shader->inst[1] & NV30_VP_INST_INPUT_SRC_MASK) - >> NV30_VP_INST_INPUT_SRC_SHIFT); - switch (src) { - case NV30_VP_INST_IN_POS : return NVS_FR_POSITION; - case NV30_VP_INST_IN_COL0 : return NVS_FR_COL0; - case NV30_VP_INST_IN_COL1 : return NVS_FR_COL1; - case NV30_VP_INST_IN_TC(0): return NVS_FR_TEXCOORD0; - case NV30_VP_INST_IN_TC(1): return NVS_FR_TEXCOORD1; - case NV30_VP_INST_IN_TC(2): return NVS_FR_TEXCOORD2; - case NV30_VP_INST_IN_TC(3): return NVS_FR_TEXCOORD3; - case NV30_VP_INST_IN_TC(4): return NVS_FR_TEXCOORD4; - case NV30_VP_INST_IN_TC(5): return NVS_FR_TEXCOORD5; - case NV30_VP_INST_IN_TC(6): return NVS_FR_TEXCOORD6; - case NV30_VP_INST_IN_TC(7): return NVS_FR_TEXCOORD7; - default: - return NVS_FR_UNKNOWN; - } - default: - return -1; - } -} - -static int -NV30VPGetSourceAbs(nvsFunc * shader, int merged, int pos) -{ - struct _op_xlat *opr; - static unsigned int abspos[3] = { - NV30_VP_INST_SRC0_ABS, - NV30_VP_INST_SRC1_ABS, - NV30_VP_INST_SRC2_ABS, - }; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr || opr->srcpos[pos] == -1 || opr->srcpos[pos] > 2) - return 0; - - return ((shader->inst[0] & abspos[opr->srcpos[pos]]) ? 1 : 0); -} - -static int -NV30VPGetRelAddressRegID(nvsFunc * shader) -{ - return ((shader->inst[0] & NV30_VP_INST_ADDR_REG_SELECT_1) ? 1 : 0); -} - -static nvsSwzComp -NV30VPGetRelAddressSwizzle(nvsFunc * shader) -{ - nvsSwzComp swz; - - swz = NV20VP_TX_SWIZZLE[(shader->inst[0] & NV30_VP_INST_ADDR_SWZ_MASK) - >> NV30_VP_INST_ADDR_SWZ_SHIFT]; - return swz; -} - -static int -NV30VPSupportsConditional(nvsFunc * shader) -{ - /*FIXME: Is this true of all ops? */ - return 1; -} - -static int -NV30VPGetConditionUpdate(nvsFunc * shader) -{ - return ((shader->inst[0] & NV30_VP_INST_COND_UPDATE_ENABLE) ? 1 : 0); -} - -static int -NV30VPGetConditionTest(nvsFunc * shader) -{ - int op; - - /* The condition test is unconditionally enabled on some - * instructions. ie: the condition test bit does *NOT* have - * to be set. - * - * FIXME: check other relevant ops for this situation. - */ - op = shader->GetOpcodeHW(shader, 1); - switch (op) { - case NV30_VP_INST_OP_BRA: - return 1; - default: - return ((shader->inst[0] & NV30_VP_INST_COND_TEST_ENABLE) ? 1 : 0); - } -} - -static nvsCond -NV30VPGetCondition(nvsFunc * shader) -{ - int cond; - - cond = ((shader->inst[0] & NV30_VP_INST_COND_MASK) - >> NV30_VP_INST_COND_SHIFT); - - switch (cond) { - case NV30_VP_INST_COND_FL: return NVS_COND_FL; - case NV30_VP_INST_COND_LT: return NVS_COND_LT; - case NV30_VP_INST_COND_EQ: return NVS_COND_EQ; - case NV30_VP_INST_COND_LE: return NVS_COND_LE; - case NV30_VP_INST_COND_GT: return NVS_COND_GT; - case NV30_VP_INST_COND_NE: return NVS_COND_NE; - case NV30_VP_INST_COND_GE: return NVS_COND_GE; - case NV30_VP_INST_COND_TR: return NVS_COND_TR; - default: - return NVS_COND_UNKNOWN; - } -} - -static void -NV30VPGetCondRegSwizzle(nvsFunc * shader, nvsSwzComp *swz) -{ - int swzbits; - - swzbits = (shader->inst[0] & NV30_VP_INST_COND_SWZ_ALL_MASK) - >> NV30_VP_INST_COND_SWZ_ALL_SHIFT; - NV20VPTXSwizzle(swzbits, swz); -} - -static int -NV30VPGetCondRegID(nvsFunc * shader) -{ - return 0; -} - - -static int -NV30VPGetBranch(nvsFunc * shader) -{ - return ((shader->inst[2] & NV30_VP_INST_IADDR_MASK) - >> NV30_VP_INST_IADDR_SHIFT); -} - -void -NV30VPInitShaderFuncs(nvsFunc * shader) -{ - /* Inherit NV20 code, a lot of it is the same */ - NV20VPInitShaderFuncs(shader); - - /* Increase max valid opcode ID, and add new instructions */ - NVVP_TX_VOP_COUNT = NVVP_TX_NVS_OP_COUNT = 32; - - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_FRC, NVS_OP_FRC, 0, -1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_FLR, NVS_OP_FLR, 0, -1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SEQ, NVS_OP_SEQ, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SFL, NVS_OP_SFL, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SGT, NVS_OP_SGT, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SLE, NVS_OP_SLE, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SNE, NVS_OP_SNE, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_STR, NVS_OP_STR, 0, 1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SSG, NVS_OP_SSG, 0, -1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_ARR, NVS_OP_ARR, 0, -1, -1); - MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_ARA, NVS_OP_ARA, 3, -1, -1); - - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_BRA, NVS_OP_BRA, -1, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_CAL, NVS_OP_CAL, -1, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_RET, NVS_OP_RET, -1, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_LG2, NVS_OP_LG2, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_EX2, NVS_OP_EX2, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_SIN, NVS_OP_SIN, 2, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_COS, NVS_OP_COS, 2, -1, -1); - - shader->UploadToHW = NV30VPUploadToHW; - shader->UpdateConst = NV30VPUpdateConst; - - shader->GetOpcodeHW = NV30VPGetOpcodeHW; - - shader->GetDestFile = NV30VPGetDestFile; - shader->GetDestID = NV30VPGetDestID; - shader->GetDestMask = NV30VPGetDestMask; - - shader->GetSourceID = NV30VPGetSourceID; - shader->GetSourceAbs = NV30VPGetSourceAbs; - - shader->GetRelAddressRegID = NV30VPGetRelAddressRegID; - shader->GetRelAddressSwizzle = NV30VPGetRelAddressSwizzle; - - shader->SupportsConditional = NV30VPSupportsConditional; - shader->GetConditionUpdate = NV30VPGetConditionUpdate; - shader->GetConditionTest = NV30VPGetConditionTest; - shader->GetCondition = NV30VPGetCondition; - shader->GetCondRegSwizzle = NV30VPGetCondRegSwizzle; - shader->GetCondRegID = NV30VPGetCondRegID; - - shader->GetBranch = NV30VPGetBranch; - shader->SetBranchTarget = NV30VPSetBranchTarget; -} - diff --git a/src/mesa/drivers/dri/nouveau/nv40_fragprog.c b/src/mesa/drivers/dri/nouveau/nv40_fragprog.c deleted file mode 100644 index 3e4ae0496e4..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv40_fragprog.c +++ /dev/null @@ -1,224 +0,0 @@ -#include "nouveau_shader.h" -#include "nv40_shader.h" - -/* branching ops */ -unsigned int NVFP_TX_BOP_COUNT = 5; -struct _op_xlat NVFP_TX_BOP[64]; - - -/***************************************************************************** - * Assembly routines - * - These extend the NV30 routines, which are almost identical. NV40 - * just has branching hacked into the instruction set. - */ -static int -NV40FPSupportsResultScale(nvsFunc *shader, nvsScale scale) -{ - switch (scale) { - case NVS_SCALE_1X: - case NVS_SCALE_2X: - case NVS_SCALE_4X: - case NVS_SCALE_8X: - case NVS_SCALE_INV_2X: - case NVS_SCALE_INV_4X: - case NVS_SCALE_INV_8X: - return 1; - default: - return 0; - } -} - -static void -NV40FPSetResultScale(nvsFunc *shader, nvsScale scale) -{ - shader->inst[2] &= ~NV40_FP_OP_DST_SCALE_MASK; - shader->inst[2] |= ((unsigned int)scale << NV40_FP_OP_DST_SCALE_SHIFT); -} - -static void -NV40FPSetBranchTarget(nvsFunc *shader, int addr) -{ - shader->inst[2] &= ~NV40_FP_OP_IADDR_MASK; - shader->inst[2] |= (addr << NV40_FP_OP_IADDR_SHIFT); -} - -static void -NV40FPSetBranchElse(nvsFunc *shader, int addr) -{ - shader->inst[2] &= ~NV40_FP_OP_ELSE_ID_MASK; - shader->inst[2] |= (addr << NV40_FP_OP_ELSE_ID_SHIFT); -} - -static void -NV40FPSetBranchEnd(nvsFunc *shader, int addr) -{ - shader->inst[3] &= ~NV40_FP_OP_END_ID_MASK; - shader->inst[3] |= (addr << NV40_FP_OP_END_ID_SHIFT); -} - -static void -NV40FPSetLoopParams(nvsFunc *shader, int count, int initial, int increment) -{ - shader->inst[2] &= ~(NV40_FP_OP_LOOP_COUNT_MASK | - NV40_FP_OP_LOOP_INDEX_MASK | - NV40_FP_OP_LOOP_INCR_MASK); - shader->inst[2] |= ((count << NV40_FP_OP_LOOP_COUNT_SHIFT) | - (initial << NV40_FP_OP_LOOP_INDEX_SHIFT) | - (increment << NV40_FP_OP_LOOP_INCR_SHIFT)); -} - -/***************************************************************************** - * Disassembly routines - */ -static struct _op_xlat * -NV40FPGetOPTXRec(nvsFunc * shader, int merged) -{ - struct _op_xlat *opr; - int op; - - op = shader->GetOpcodeHW(shader, 0); - if (shader->inst[2] & NV40_FP_OP_OPCODE_IS_BRANCH) { - opr = NVFP_TX_BOP; - op &= ~NV40_FP_OP_OPCODE_IS_BRANCH; - if (op > NVFP_TX_BOP_COUNT) - return NULL; - } - else { - opr = NVFP_TX_AOP; - if (op > NVFP_TX_AOP_COUNT) - return NULL; - } - - if (opr[op].SOP == NVS_OP_UNKNOWN) - return NULL; - return &opr[op]; -} - -static int -NV40FPGetSourceID(nvsFunc * shader, int merged, int pos) -{ - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_ATTRIB: - switch ((shader->inst[0] & NV40_FP_OP_INPUT_SRC_MASK) - >> NV40_FP_OP_INPUT_SRC_SHIFT) { - case NV40_FP_OP_INPUT_SRC_POSITION: return NVS_FR_POSITION; - case NV40_FP_OP_INPUT_SRC_COL0 : return NVS_FR_COL0; - case NV40_FP_OP_INPUT_SRC_COL1 : return NVS_FR_COL1; - case NV40_FP_OP_INPUT_SRC_FOGC : return NVS_FR_FOGCOORD; - case NV40_FP_OP_INPUT_SRC_TC(0) : return NVS_FR_TEXCOORD0; - case NV40_FP_OP_INPUT_SRC_TC(1) : return NVS_FR_TEXCOORD1; - case NV40_FP_OP_INPUT_SRC_TC(2) : return NVS_FR_TEXCOORD2; - case NV40_FP_OP_INPUT_SRC_TC(3) : return NVS_FR_TEXCOORD3; - case NV40_FP_OP_INPUT_SRC_TC(4) : return NVS_FR_TEXCOORD4; - case NV40_FP_OP_INPUT_SRC_TC(5) : return NVS_FR_TEXCOORD5; - case NV40_FP_OP_INPUT_SRC_TC(6) : return NVS_FR_TEXCOORD6; - case NV40_FP_OP_INPUT_SRC_TC(7) : return NVS_FR_TEXCOORD7; - case NV40_FP_OP_INPUT_SRC_FACING : return NVS_FR_FACING; - default: - return -1; - } - break; - case NVS_FILE_TEMP: - { - unsigned int src; - - src = shader->GetSourceHW(shader, merged, pos); - return ((src & NV40_FP_REG_SRC_MASK) >> NV40_FP_REG_SRC_SHIFT); - } - case NVS_FILE_CONST: /* inlined into fragprog */ - default: - return -1; - } -} - -static int -NV40FPGetBranch(nvsFunc * shader) -{ - return ((shader->inst[2] & NV40_FP_OP_IADDR_MASK) - >> NV40_FP_OP_IADDR_SHIFT);; -} - -static int -NV40FPGetBranchElse(nvsFunc * shader) -{ - return ((shader->inst[2] & NV40_FP_OP_ELSE_ID_MASK) - >> NV40_FP_OP_ELSE_ID_SHIFT); -} - -static int -NV40FPGetBranchEnd(nvsFunc * shader) -{ - return ((shader->inst[3] & NV40_FP_OP_END_ID_MASK) - >> NV40_FP_OP_END_ID_SHIFT); -} - -static int -NV40FPGetLoopCount(nvsFunc * shader) -{ - return ((shader->inst[2] & NV40_FP_OP_LOOP_COUNT_MASK) - >> NV40_FP_OP_LOOP_COUNT_SHIFT); -} - -static int -NV40FPGetLoopInitial(nvsFunc * shader) -{ - return ((shader->inst[2] & NV40_FP_OP_LOOP_INDEX_MASK) - >> NV40_FP_OP_LOOP_INDEX_SHIFT); -} - -static int -NV40FPGetLoopIncrement(nvsFunc * shader) -{ - return ((shader->inst[2] & NV40_FP_OP_LOOP_INCR_MASK) - >> NV40_FP_OP_LOOP_INCR_SHIFT); -} - -void -NV40FPInitShaderFuncs(nvsFunc * shader) -{ - /* Inherit NV30 FP code, it's mostly the same */ - NV30FPInitShaderFuncs(shader); - - /* Kill off opcodes seen on NV30, but not seen on NV40 - need to find - * out if these actually work or not. - * - * update: either LIT/RSQ don't work on nv40, or I generate bad code for - * them. haven't tested the others yet - */ - MOD_OPCODE(NVFP_TX_AOP, 0x1B, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 RSQ */ - MOD_OPCODE(NVFP_TX_AOP, 0x1E, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 LIT */ - MOD_OPCODE(NVFP_TX_AOP, 0x1F, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 LRP */ - MOD_OPCODE(NVFP_TX_AOP, 0x26, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 POW */ - MOD_OPCODE(NVFP_TX_AOP, 0x36, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 RFL */ - - /* Extra opcodes supported on NV40 */ - MOD_OPCODE(NVFP_TX_AOP, NV40_FP_OP_OPCODE_DIV , NVS_OP_DIV , 0, 1, -1); - MOD_OPCODE(NVFP_TX_AOP, NV40_FP_OP_OPCODE_DP2A , NVS_OP_DP2A, 0, 1, 2); - MOD_OPCODE(NVFP_TX_AOP, NV40_FP_OP_OPCODE_TXL , NVS_OP_TXL , 0, -1, -1); - - MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_BRK , NVS_OP_BRK , -1, -1, -1); - MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_CAL , NVS_OP_CAL , -1, -1, -1); - MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_IF , NVS_OP_IF , -1, -1, -1); - MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_LOOP, NVS_OP_LOOP, -1, -1, -1); - MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_REP , NVS_OP_REP , -1, -1, -1); - MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_RET , NVS_OP_RET , -1, -1, -1); - - shader->SupportsResultScale = NV40FPSupportsResultScale; - shader->SetResultScale = NV40FPSetResultScale; - - /* fragment.facing */ - shader->GetSourceID = NV40FPGetSourceID; - - /* branching */ - shader->GetOPTXRec = NV40FPGetOPTXRec; - shader->GetBranch = NV40FPGetBranch; - shader->GetBranchElse = NV40FPGetBranchElse; - shader->GetBranchEnd = NV40FPGetBranchEnd; - shader->GetLoopCount = NV40FPGetLoopCount; - shader->GetLoopInitial = NV40FPGetLoopInitial; - shader->GetLoopIncrement = NV40FPGetLoopIncrement; - shader->SetBranchTarget = NV40FPSetBranchTarget; - shader->SetBranchElse = NV40FPSetBranchElse; - shader->SetBranchEnd = NV40FPSetBranchEnd; - shader->SetLoopParams = NV40FPSetLoopParams; -} diff --git a/src/mesa/drivers/dri/nouveau/nv40_shader.h b/src/mesa/drivers/dri/nouveau/nv40_shader.h deleted file mode 100644 index 584f4c23e08..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv40_shader.h +++ /dev/null @@ -1,467 +0,0 @@ -#ifndef __NV40_SHADER_H__ -#define __NV40_SHADER_H__ - -/* Vertex programs instruction set - * - * The NV40 instruction set is very similar to NV30. Most fields are in - * a slightly different position in the instruction however. - * - * Merged instructions - * In some cases it is possible to put two instructions into one opcode - * slot. The rules for when this is OK is not entirely clear to me yet. - * - * There are separate writemasks and dest temp register fields for each - * grouping of instructions. There is however only one field with the - * ID of a result register. Writing to temp/result regs is selected by - * setting VEC_RESULT/SCA_RESULT. - * - * Temporary registers - * The source/dest temp register fields have been extended by 1 bit, to - * give a total of 32 temporary registers. - * - * Relative Addressing - * NV40 can use an address register to index into vertex attribute regs. - * This is done by putting the offset value into INPUT_SRC and setting - * the INDEX_INPUT flag. - * - * Conditional execution (see NV_vertex_program{2,3} for details) - * There is a second condition code register on NV40, it's use is enabled - * by setting the COND_REG_SELECT_1 flag. - * - * Texture lookup - * TODO - */ - -/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */ -#define NV40_VP_INST_VEC_RESULT (1 << 30) -/* uncertain.. */ -#define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29) -/* use address reg as index into attribs */ -#define NV40_VP_INST_INDEX_INPUT (1 << 27) -#define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25) -#define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24) -#define NV40_VP_INST_SRC2_ABS (1 << 23) -#define NV40_VP_INST_SRC1_ABS (1 << 22) -#define NV40_VP_INST_SRC0_ABS (1 << 21) -#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15 -#define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 15) -#define NV40_VP_INST_COND_TEST_ENABLE (1 << 13) -#define NV40_VP_INST_COND_SHIFT 10 -#define NV40_VP_INST_COND_MASK (0x7 << 10) -# define NV40_VP_INST_COND_FL 0 -# define NV40_VP_INST_COND_LT 1 -# define NV40_VP_INST_COND_EQ 2 -# define NV40_VP_INST_COND_LE 3 -# define NV40_VP_INST_COND_GT 4 -# define NV40_VP_INST_COND_NE 5 -# define NV40_VP_INST_COND_GE 6 -# define NV40_VP_INST_COND_TR 7 -#define NV40_VP_INST_COND_SWZ_X_SHIFT 8 -#define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8) -#define NV40_VP_INST_COND_SWZ_Y_SHIFT 6 -#define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6) -#define NV40_VP_INST_COND_SWZ_Z_SHIFT 4 -#define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4) -#define NV40_VP_INST_COND_SWZ_W_SHIFT 2 -#define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2) -#define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2 -#define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2) -#define NV40_VP_INST_ADDR_SWZ_SHIFT 0 -#define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0) -#define NV40_VP_INST0_KNOWN ( \ - NV40_VP_INST_INDEX_INPUT | \ - NV40_VP_INST_COND_REG_SELECT_1 | \ - NV40_VP_INST_ADDR_REG_SELECT_1 | \ - NV40_VP_INST_SRC2_ABS | \ - NV40_VP_INST_SRC1_ABS | \ - NV40_VP_INST_SRC0_ABS | \ - NV40_VP_INST_VEC_DEST_TEMP_MASK | \ - NV40_VP_INST_COND_TEST_ENABLE | \ - NV40_VP_INST_COND_MASK | \ - NV40_VP_INST_COND_SWZ_ALL_MASK | \ - NV40_VP_INST_ADDR_SWZ_MASK) - -/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */ -#define NV40_VP_INST_VEC_OPCODE_SHIFT 22 -#define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22) -# define NV40_VP_INST_OP_NOP 0x00 -# define NV40_VP_INST_OP_MOV 0x01 -# define NV40_VP_INST_OP_MUL 0x02 -# define NV40_VP_INST_OP_ADD 0x03 -# define NV40_VP_INST_OP_MAD 0x04 -# define NV40_VP_INST_OP_DP3 0x05 -# define NV40_VP_INST_OP_DP4 0x07 -# define NV40_VP_INST_OP_DPH 0x06 -# define NV40_VP_INST_OP_DST 0x08 -# define NV40_VP_INST_OP_MIN 0x09 -# define NV40_VP_INST_OP_MAX 0x0A -# define NV40_VP_INST_OP_SLT 0x0B -# define NV40_VP_INST_OP_SGE 0x0C -# define NV40_VP_INST_OP_ARL 0x0D -# define NV40_VP_INST_OP_FRC 0x0E -# define NV40_VP_INST_OP_FLR 0x0F -# define NV40_VP_INST_OP_SEQ 0x10 -# define NV40_VP_INST_OP_SFL 0x11 -# define NV40_VP_INST_OP_SGT 0x12 -# define NV40_VP_INST_OP_SLE 0x13 -# define NV40_VP_INST_OP_SNE 0x14 -# define NV40_VP_INST_OP_STR 0x15 -# define NV40_VP_INST_OP_SSG 0x16 -# define NV40_VP_INST_OP_ARR 0x17 -# define NV40_VP_INST_OP_ARA 0x18 -# define NV40_VP_INST_OP_TXWHAT 0x19 -#define NV40_VP_INST_SCA_OPCODE_SHIFT 27 -#define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27) -# define NV40_VP_INST_OP_RCP 0x02 -# define NV40_VP_INST_OP_RCC 0x03 -# define NV40_VP_INST_OP_RSQ 0x04 -# define NV40_VP_INST_OP_EXP 0x05 -# define NV40_VP_INST_OP_LOG 0x06 -# define NV40_VP_INST_OP_LIT 0x07 -# define NV40_VP_INST_OP_BRA 0x09 -# define NV40_VP_INST_OP_CAL 0x0B -# define NV40_VP_INST_OP_RET 0x0C -# define NV40_VP_INST_OP_LG2 0x0D -# define NV40_VP_INST_OP_EX2 0x0E -# define NV40_VP_INST_OP_SIN 0x0F -# define NV40_VP_INST_OP_COS 0x10 -# define NV40_VP_INST_OP_PUSHA 0x13 -# define NV40_VP_INST_OP_POPA 0x14 -#define NV40_VP_INST_CONST_SRC_SHIFT 12 -#define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12) -#define NV40_VP_INST_INPUT_SRC_SHIFT 8 -#define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8) -# define NV40_VP_INST_IN_POS 0 -# define NV40_VP_INST_IN_WEIGHT 1 -# define NV40_VP_INST_IN_NORMAL 2 -# define NV40_VP_INST_IN_COL0 3 -# define NV40_VP_INST_IN_COL1 4 -# define NV40_VP_INST_IN_FOGC 5 -# define NV40_VP_INST_IN_TC0 8 -# define NV40_VP_INST_IN_TC(n) (8+n) -#define NV40_VP_INST_SRC0H_SHIFT 0 -#define NV40_VP_INST_SRC0H_MASK (0xFF << 0) -#define NV40_VP_INST1_KNOWN ( \ - NV40_VP_INST_VEC_OPCODE_MASK | \ - NV40_VP_INST_SCA_OPCODE_MASK | \ - NV40_VP_INST_CONST_SRC_MASK | \ - NV40_VP_INST_INPUT_SRC_MASK | \ - NV40_VP_INST_SRC0H_MASK \ - ) - -/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */ -#define NV40_VP_INST_SRC0L_SHIFT 23 -#define NV40_VP_INST_SRC0L_MASK (0x1FF << 23) -#define NV40_VP_INST_SRC1_SHIFT 6 -#define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6) -#define NV40_VP_INST_SRC2H_SHIFT 0 -#define NV40_VP_INST_SRC2H_MASK (0x3F << 0) -#define NV40_VP_INST_IADDRH_SHIFT 0 -#define NV40_VP_INST_IADDRH_MASK (0x1F << 0) - -/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */ -#define NV40_VP_INST_IADDRL_SHIFT 29 -#define NV40_VP_INST_IADDRL_MASK (7 << 29) -#define NV40_VP_INST_SRC2L_SHIFT 21 -#define NV40_VP_INST_SRC2L_MASK (0x7FF << 21) -#define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17 -#define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17) -# define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20) -# define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19) -# define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18) -# define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17) -#define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13 -#define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13) -# define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16) -# define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15) -# define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14) -# define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13) -#define NV40_VP_INST_SCA_RESULT (1 << 12) -#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7 -#define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7) -#define NV40_VP_INST_DEST_SHIFT 2 -#define NV40_VP_INST_DEST_MASK (31 << 2) -# define NV40_VP_INST_DEST_POS 0 -# define NV40_VP_INST_DEST_COL0 1 -# define NV40_VP_INST_DEST_COL1 2 -# define NV40_VP_INST_DEST_BFC0 3 -# define NV40_VP_INST_DEST_BFC1 4 -# define NV40_VP_INST_DEST_FOGC 5 -# define NV40_VP_INST_DEST_PSZ 6 -# define NV40_VP_INST_DEST_TC0 7 -# define NV40_VP_INST_DEST_TC(n) (7+n) -# define NV40_VP_INST_DEST_TEMP 0x1F -#define NV40_VP_INST_INDEX_CONST (1 << 1) -#define NV40_VP_INST_LAST (1 << 0) -#define NV40_VP_INST3_KNOWN ( \ - NV40_VP_INST_SRC2L_MASK |\ - NV40_VP_INST_SCA_WRITEMASK_MASK |\ - NV40_VP_INST_VEC_WRITEMASK_MASK |\ - NV40_VP_INST_SCA_DEST_TEMP_MASK |\ - NV40_VP_INST_DEST_MASK |\ - NV40_VP_INST_INDEX_CONST) - -/* Useful to split the source selection regs into their pieces */ -#define NV40_VP_SRC0_HIGH_SHIFT 9 -#define NV40_VP_SRC0_HIGH_MASK 0x0001FE00 -#define NV40_VP_SRC0_LOW_MASK 0x000001FF -#define NV40_VP_SRC2_HIGH_SHIFT 11 -#define NV40_VP_SRC2_HIGH_MASK 0x0001F800 -#define NV40_VP_SRC2_LOW_MASK 0x000007FF - -/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */ -#define NV40_VP_SRC_NEGATE (1 << 16) -#define NV40_VP_SRC_SWZ_X_SHIFT 14 -#define NV40_VP_SRC_SWZ_X_MASK (3 << 14) -#define NV40_VP_SRC_SWZ_Y_SHIFT 12 -#define NV40_VP_SRC_SWZ_Y_MASK (3 << 12) -#define NV40_VP_SRC_SWZ_Z_SHIFT 10 -#define NV40_VP_SRC_SWZ_Z_MASK (3 << 10) -#define NV40_VP_SRC_SWZ_W_SHIFT 8 -#define NV40_VP_SRC_SWZ_W_MASK (3 << 8) -#define NV40_VP_SRC_SWZ_ALL_SHIFT 8 -#define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8) -#define NV40_VP_SRC_TEMP_SRC_SHIFT 2 -#define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2) -#define NV40_VP_SRC_REG_TYPE_SHIFT 0 -#define NV40_VP_SRC_REG_TYPE_MASK (3 << 0) -# define NV40_VP_SRC_REG_TYPE_UNK0 0 -# define NV40_VP_SRC_REG_TYPE_TEMP 1 -# define NV40_VP_SRC_REG_TYPE_INPUT 2 -# define NV40_VP_SRC_REG_TYPE_CONST 3 - - -/* - * Each fragment program opcode appears to be comprised of 4 32-bit values. - * - * 0 - Opcode, output reg/mask, ATTRIB source - * 1 - Source 0 - * 2 - Source 1 - * 3 - Source 2 - * - * There appears to be no special difference between result regs and temp regs. - * result.color == R0.xyzw - * result.depth == R1.z - * When the fragprog contains instructions to write depth, - * NV30_TCL_PRIMITIVE_3D_UNK1D78=0 otherwise it is set to 1. - * - * Constants are inserted directly after the instruction that uses them. - * - * It appears that it's not possible to use two input registers in one - * instruction as the input sourcing is done in the instruction dword - * and not the source selection dwords. As such instructions such as: - * - * ADD result.color, fragment.color, fragment.texcoord[0]; - * - * must be split into two MOV's and then an ADD (nvidia does this) but - * I'm not sure why it's not just one MOV and then source the second input - * in the ADD instruction.. - * - * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary - * negation requires multiplication with a const. - * - * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO and - * SWIZZLE_ONE. - * - * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as - * SWIZZLE_ZERO is implemented simply by not writing to the relevant components - * of the destination. - * - * Looping - * Loops appear to be fairly expensive on NV40 at least, the proprietary - * driver goes to a lot of effort to avoid using the native looping - * instructions. If the total number of *executed* instructions between - * REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop. - * The maximum loop count is 255. - * - * Conditional execution - * TODO - * - * Non-native instructions: - * LIT - * LRP - MAD+MAD - * SUB - ADD, negate second source - * RSQ - LG2 + EX2 - * POW - LG2 + MUL + EX2 - * SCS - COS + SIN - * XPD - * DP2 - MUL + ADD - * NRM - */ - -//== Opcode / Destination selection == -#define NV40_FP_OP_PROGRAM_END (1 << 0) -#define NV40_FP_OP_OUT_REG_SHIFT 1 -#define NV40_FP_OP_OUT_REG_MASK (31 << 1) -/* Needs to be set when writing outputs to get expected result.. */ -#define NV40_FP_OP_UNK0_7 (1 << 7) -#define NV40_FP_OP_COND_WRITE_ENABLE (1 << 8) -#define NV40_FP_OP_OUTMASK_SHIFT 9 -#define NV40_FP_OP_OUTMASK_MASK (0xF << 9) -# define NV40_FP_OP_OUT_X (1 << 9) -# define NV40_FP_OP_OUT_Y (1 <<10) -# define NV40_FP_OP_OUT_Z (1 <<11) -# define NV40_FP_OP_OUT_W (1 <<12) -/* Uncertain about these, especially the input_src values.. it's possible that - * they can be dynamically changed. - */ -#define NV40_FP_OP_INPUT_SRC_SHIFT 13 -#define NV40_FP_OP_INPUT_SRC_MASK (15 << 13) -# define NV40_FP_OP_INPUT_SRC_POSITION 0x0 -# define NV40_FP_OP_INPUT_SRC_COL0 0x1 -# define NV40_FP_OP_INPUT_SRC_COL1 0x2 -# define NV40_FP_OP_INPUT_SRC_FOGC 0x3 -# define NV40_FP_OP_INPUT_SRC_TC0 0x4 -# define NV40_FP_OP_INPUT_SRC_TC(n) (0x4 + n) -# define NV40_FP_OP_INPUT_SRC_FACING 0xE -#define NV40_FP_OP_TEX_UNIT_SHIFT 17 -#define NV40_FP_OP_TEX_UNIT_MASK (0xF << 17) -#define NV40_FP_OP_PRECISION_SHIFT 22 -#define NV40_FP_OP_PRECISION_MASK (3 << 22) -# define NV40_FP_PRECISION_FP32 0 -# define NV40_FP_PRECISION_FP16 1 -# define NV40_FP_PRECISION_FX12 2 -#define NV40_FP_OP_OPCODE_SHIFT 24 -#define NV40_FP_OP_OPCODE_MASK (0x3F << 24) -# define NV40_FP_OP_OPCODE_NOP 0x00 -# define NV40_FP_OP_OPCODE_MOV 0x01 -# define NV40_FP_OP_OPCODE_MUL 0x02 -# define NV40_FP_OP_OPCODE_ADD 0x03 -# define NV40_FP_OP_OPCODE_MAD 0x04 -# define NV40_FP_OP_OPCODE_DP3 0x05 -# define NV40_FP_OP_OPCODE_DP4 0x06 -# define NV40_FP_OP_OPCODE_DST 0x07 -# define NV40_FP_OP_OPCODE_MIN 0x08 -# define NV40_FP_OP_OPCODE_MAX 0x09 -# define NV40_FP_OP_OPCODE_SLT 0x0A -# define NV40_FP_OP_OPCODE_SGE 0x0B -# define NV40_FP_OP_OPCODE_SLE 0x0C -# define NV40_FP_OP_OPCODE_SGT 0x0D -# define NV40_FP_OP_OPCODE_SNE 0x0E -# define NV40_FP_OP_OPCODE_SEQ 0x0F -# define NV40_FP_OP_OPCODE_FRC 0x10 -# define NV40_FP_OP_OPCODE_FLR 0x11 -# define NV40_FP_OP_OPCODE_KIL 0x12 -# define NV40_FP_OP_OPCODE_PK4B 0x13 -# define NV40_FP_OP_OPCODE_UP4B 0x14 -/* DDX/DDY can only write to XY */ -# define NV40_FP_OP_OPCODE_DDX 0x15 -# define NV40_FP_OP_OPCODE_DDY 0x16 -# define NV40_FP_OP_OPCODE_TEX 0x17 -# define NV40_FP_OP_OPCODE_TXP 0x18 -# define NV40_FP_OP_OPCODE_TXD 0x19 -# define NV40_FP_OP_OPCODE_RCP 0x1A -# define NV40_FP_OP_OPCODE_EX2 0x1C -# define NV40_FP_OP_OPCODE_LG2 0x1D -# define NV40_FP_OP_OPCODE_COS 0x22 -# define NV40_FP_OP_OPCODE_SIN 0x23 -# define NV40_FP_OP_OPCODE_PK2H 0x24 -# define NV40_FP_OP_OPCODE_UP2H 0x25 -# define NV40_FP_OP_OPCODE_PK4UB 0x27 -# define NV40_FP_OP_OPCODE_UP4UB 0x28 -# define NV40_FP_OP_OPCODE_PK2US 0x29 -# define NV40_FP_OP_OPCODE_UP2US 0x2A -# define NV40_FP_OP_OPCODE_DP2A 0x2E -# define NV40_FP_OP_OPCODE_TXL 0x2F -# define NV40_FP_OP_OPCODE_TXB 0x31 -# define NV40_FP_OP_OPCODE_DIV 0x3A -/* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/ -# define NV40_FP_OP_BRA_OPCODE_BRK 0x0 -# define NV40_FP_OP_BRA_OPCODE_CAL 0x1 -# define NV40_FP_OP_BRA_OPCODE_IF 0x2 -# define NV40_FP_OP_BRA_OPCODE_LOOP 0x3 -# define NV40_FP_OP_BRA_OPCODE_REP 0x4 -# define NV40_FP_OP_BRA_OPCODE_RET 0x5 -#define NV40_FP_OP_OUT_SAT (1 << 31) - -/* high order bits of SRC0 */ -#define NV40_FP_OP_OUT_ABS (1 << 29) -#define NV40_FP_OP_COND_SWZ_W_SHIFT 27 -#define NV40_FP_OP_COND_SWZ_W_MASK (3 << 27) -#define NV40_FP_OP_COND_SWZ_Z_SHIFT 25 -#define NV40_FP_OP_COND_SWZ_Z_MASK (3 << 25) -#define NV40_FP_OP_COND_SWZ_Y_SHIFT 23 -#define NV40_FP_OP_COND_SWZ_Y_MASK (3 << 23) -#define NV40_FP_OP_COND_SWZ_X_SHIFT 21 -#define NV40_FP_OP_COND_SWZ_X_MASK (3 << 21) -#define NV40_FP_OP_COND_SWZ_ALL_SHIFT 21 -#define NV40_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21) -#define NV40_FP_OP_COND_SHIFT 18 -#define NV40_FP_OP_COND_MASK (0x07 << 18) -# define NV40_FP_OP_COND_FL 0 -# define NV40_FP_OP_COND_LT 1 -# define NV40_FP_OP_COND_EQ 2 -# define NV40_FP_OP_COND_LE 3 -# define NV40_FP_OP_COND_GT 4 -# define NV40_FP_OP_COND_NE 5 -# define NV40_FP_OP_COND_GE 6 -# define NV40_FP_OP_COND_TR 7 - -/* high order bits of SRC1 */ -#define NV40_FP_OP_OPCODE_IS_BRANCH (1<<31) -#define NV40_FP_OP_DST_SCALE_SHIFT 28 -#define NV40_FP_OP_DST_SCALE_MASK (3 << 28) - -/* SRC1 LOOP */ -#define NV40_FP_OP_LOOP_INCR_SHIFT 19 -#define NV40_FP_OP_LOOP_INCR_MASK (0xFF << 19) -#define NV40_FP_OP_LOOP_INDEX_SHIFT 10 -#define NV40_FP_OP_LOOP_INDEX_MASK (0xFF << 10) -#define NV40_FP_OP_LOOP_COUNT_SHIFT 2 -#define NV40_FP_OP_LOOP_COUNT_MASK (0xFF << 2) - -/* SRC1 IF */ -#define NV40_FP_OP_ELSE_ID_SHIFT 2 -#define NV40_FP_OP_ELSE_ID_MASK (0xFF << 2) - -/* SRC1 CAL */ -#define NV40_FP_OP_IADDR_SHIFT 2 -#define NV40_FP_OP_IADDR_MASK (0xFF << 2) - -/* SRC1 REP - * I have no idea why there are 3 count values here.. but they - * have always been filled with the same value in my tests so - * far.. - */ -#define NV40_FP_OP_REP_COUNT1_SHIFT 2 -#define NV40_FP_OP_REP_COUNT1_MASK (0xFF << 2) -#define NV40_FP_OP_REP_COUNT2_SHIFT 10 -#define NV40_FP_OP_REP_COUNT2_MASK (0xFF << 10) -#define NV40_FP_OP_REP_COUNT3_SHIFT 19 -#define NV40_FP_OP_REP_COUNT3_MASK (0xFF << 19) - -/* SRC2 REP/IF */ -#define NV40_FP_OP_END_ID_SHIFT 2 -#define NV40_FP_OP_END_ID_MASK (0xFF << 2) - -// SRC2 high-order -#define NV40_FP_OP_INDEX_INPUT (1 << 30) -#define NV40_FP_OP_ADDR_INDEX_SHIFT 19 -#define NV40_FP_OP_ADDR_INDEX_MASK (0xF << 19) - -//== Register selection == -#define NV40_FP_REG_TYPE_SHIFT 0 -#define NV40_FP_REG_TYPE_MASK (3 << 0) -# define NV40_FP_REG_TYPE_TEMP 0 -# define NV40_FP_REG_TYPE_INPUT 1 -# define NV40_FP_REG_TYPE_CONST 2 -#define NV40_FP_REG_SRC_SHIFT 2 -#define NV40_FP_REG_SRC_MASK (31 << 2) -#define NV40_FP_REG_UNK_0 (1 << 8) -#define NV40_FP_REG_SWZ_ALL_SHIFT 9 -#define NV40_FP_REG_SWZ_ALL_MASK (255 << 9) -#define NV40_FP_REG_SWZ_X_SHIFT 9 -#define NV40_FP_REG_SWZ_X_MASK (3 << 9) -#define NV40_FP_REG_SWZ_Y_SHIFT 11 -#define NV40_FP_REG_SWZ_Y_MASK (3 << 11) -#define NV40_FP_REG_SWZ_Z_SHIFT 13 -#define NV40_FP_REG_SWZ_Z_MASK (3 << 13) -#define NV40_FP_REG_SWZ_W_SHIFT 15 -#define NV40_FP_REG_SWZ_W_MASK (3 << 15) -# define NV40_FP_SWIZZLE_X 0 -# define NV40_FP_SWIZZLE_Y 1 -# define NV40_FP_SWIZZLE_Z 2 -# define NV40_FP_SWIZZLE_W 3 -#define NV40_FP_REG_NEGATE (1 << 17) - -#endif diff --git a/src/mesa/drivers/dri/nouveau/nv40_vertprog.c b/src/mesa/drivers/dri/nouveau/nv40_vertprog.c deleted file mode 100644 index d054140bcd0..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv40_vertprog.c +++ /dev/null @@ -1,778 +0,0 @@ -#include "nouveau_shader.h" -#include "nouveau_msg.h" -#include "nv40_shader.h" - -/***************************************************************************** - * Assembly routines - */ -static int -NV40VPSupportsOpcode(nvsFunc * shader, nvsOpcode op) -{ - if (shader->GetOPTXFromSOP(op, NULL)) - return 1; - return 0; -} - -static void -NV40VPSetOpcode(nvsFunc *shader, unsigned int opcode, int slot) -{ - if (slot) { - shader->inst[1] &= ~NV40_VP_INST_SCA_OPCODE_MASK; - shader->inst[1] |= (opcode << NV40_VP_INST_SCA_OPCODE_SHIFT); - } else { - shader->inst[1] &= ~NV40_VP_INST_VEC_OPCODE_MASK; - shader->inst[1] |= (opcode << NV40_VP_INST_VEC_OPCODE_SHIFT); - } -} - -static void -NV40VPSetCCUpdate(nvsFunc *shader) -{ - shader->inst[0] |= NV40_VP_INST_COND_UPDATE_ENABLE; -} - -static void -NV40VPSetCondition(nvsFunc *shader, int on, nvsCond cond, int reg, - nvsSwzComp *swizzle) -{ - unsigned int hwcond; - - if (on ) shader->inst[0] |= NV40_VP_INST_COND_TEST_ENABLE; - else shader->inst[0] &= ~NV40_VP_INST_COND_TEST_ENABLE; - if (reg) shader->inst[0] |= NV40_VP_INST_COND_REG_SELECT_1; - else shader->inst[0] &= ~NV40_VP_INST_COND_REG_SELECT_1; - - switch (cond) { - case NVS_COND_TR: hwcond = NV40_VP_INST_COND_TR; break; - case NVS_COND_FL: hwcond = NV40_VP_INST_COND_FL; break; - case NVS_COND_LT: hwcond = NV40_VP_INST_COND_LT; break; - case NVS_COND_GT: hwcond = NV40_VP_INST_COND_GT; break; - case NVS_COND_NE: hwcond = NV40_VP_INST_COND_NE; break; - case NVS_COND_EQ: hwcond = NV40_VP_INST_COND_EQ; break; - case NVS_COND_GE: hwcond = NV40_VP_INST_COND_GE; break; - case NVS_COND_LE: hwcond = NV40_VP_INST_COND_LE; break; - default: - WARN_ONCE("unknown vp cond %d\n", cond); - hwcond = NV40_VP_INST_COND_TR; - break; - } - shader->inst[0] &= ~NV40_VP_INST_COND_MASK; - shader->inst[0] |= (hwcond << NV40_VP_INST_COND_SHIFT); - - shader->inst[0] &= ~NV40_VP_INST_COND_SWZ_ALL_MASK; - shader->inst[0] |= (swizzle[NVS_SWZ_X] << NV40_VP_INST_COND_SWZ_X_SHIFT); - shader->inst[0] |= (swizzle[NVS_SWZ_Y] << NV40_VP_INST_COND_SWZ_Y_SHIFT); - shader->inst[0] |= (swizzle[NVS_SWZ_Z] << NV40_VP_INST_COND_SWZ_Z_SHIFT); - shader->inst[0] |= (swizzle[NVS_SWZ_W] << NV40_VP_INST_COND_SWZ_W_SHIFT); -} - -/* these just exist here until nouveau_reg.h has them. */ -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL0 (1<<0) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1 (1<<1) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0 (1<<2) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1 (1<<3) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC (1<<4) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ (1<<5) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0 (1<<6) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1 (1<<7) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2 (1<<8) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3 (1<<9) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4 (1<<10) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5 (1<<11) -#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0 (1<<14) - -static unsigned int -NV40VPTranslateResultReg(nvsFunc *shader, nvsFixedReg result, - unsigned int *mask_ret) -{ - unsigned int *out_reg = &shader->card_priv->NV30VP.vp_out_reg; - unsigned int *clip_en = &shader->card_priv->NV30VP.clip_enables; - - *mask_ret = 0xf; - - switch (result) { - case NVS_FR_POSITION: - /* out_reg POS implied */ - return NV40_VP_INST_DEST_POS; - case NVS_FR_COL0: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL0; - return NV40_VP_INST_DEST_COL0; - case NVS_FR_COL1: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1; - return NV40_VP_INST_DEST_COL1; - case NVS_FR_BFC0: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0; - return NV40_VP_INST_DEST_BFC0; - case NVS_FR_BFC1: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1; - return NV40_VP_INST_DEST_BFC1; - case NVS_FR_FOGCOORD: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC; - *mask_ret = 0x8; - return NV40_VP_INST_DEST_FOGC; - case NVS_FR_CLIP0: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0; - (*clip_en) |= 0x00000002; - *mask_ret = 0x4; - return NV40_VP_INST_DEST_FOGC; - case NVS_FR_CLIP1: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1; - (*clip_en) |= 0x00000020; - *mask_ret = 0x2; - return NV40_VP_INST_DEST_FOGC; - case NVS_FR_CLIP2: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2; - (*clip_en) |= 0x00000200; - *mask_ret = 0x1; - return NV40_VP_INST_DEST_FOGC; - case NVS_FR_POINTSZ: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ; - *mask_ret = 0x8; - return NV40_VP_INST_DEST_PSZ; - case NVS_FR_CLIP3: - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3; - (*clip_en) |= 0x00002000; - *mask_ret = 0x4; - return NV40_VP_INST_DEST_PSZ; - case NVS_FR_CLIP4: - (*clip_en) |= 0x00020000; - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4; - *mask_ret = 0x2; - return NV40_VP_INST_DEST_PSZ; - case NVS_FR_CLIP5: - (*clip_en) |= 0x00200000; - (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5; - *mask_ret = 0x1; - return NV40_VP_INST_DEST_PSZ; - case NVS_FR_TEXCOORD0: - case NVS_FR_TEXCOORD1: - case NVS_FR_TEXCOORD2: - case NVS_FR_TEXCOORD3: - case NVS_FR_TEXCOORD4: - case NVS_FR_TEXCOORD5: - case NVS_FR_TEXCOORD6: - case NVS_FR_TEXCOORD7: - { - int unit = result - NVS_FR_TEXCOORD0; - (*out_reg) |= (NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0 << unit); - return NV40_VP_INST_DEST_TC(unit); - } - default: - WARN_ONCE("unknown vp output %d\n", result); - return NV40_VP_INST_DEST_POS; - } -} - -static void -NV40VPSetResult(nvsFunc *shader, nvsRegister * dest, unsigned int mask, - int slot) -{ - unsigned int hwmask = 0; - - if (mask & SMASK_X) hwmask |= (1 << 3); - if (mask & SMASK_Y) hwmask |= (1 << 2); - if (mask & SMASK_Z) hwmask |= (1 << 1); - if (mask & SMASK_W) hwmask |= (1 << 0); - - if (dest->file == NVS_FILE_RESULT) { - unsigned int valid_mask; - int hwidx; - - hwidx = NV40VPTranslateResultReg(shader, dest->index, &valid_mask); - if (hwmask & ~valid_mask) - WARN_ONCE("writing invalid components of result reg\n"); - hwmask &= valid_mask; - - shader->inst[3] &= ~NV40_VP_INST_DEST_MASK; - shader->inst[3] |= (hwidx << NV40_VP_INST_DEST_SHIFT); - - if (slot) shader->inst[3] |= NV40_VP_INST_SCA_RESULT; - else shader->inst[0] |= NV40_VP_INST_VEC_RESULT; - } else { - /* NVS_FILE_TEMP || NVS_FILE_ADDRESS */ - if (slot) { - shader->inst[3] &= ~NV40_VP_INST_SCA_RESULT; - shader->inst[3] &= ~NV40_VP_INST_SCA_DEST_TEMP_MASK; - shader->inst[3] |= (dest->index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT); - } else { - shader->inst[0] &= ~NV40_VP_INST_VEC_RESULT; - shader->inst[0] &= ~(NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20)); - shader->inst[0] |= (dest->index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT); - } - } - - if (slot) { - shader->inst[3] &= ~NV40_VP_INST_SCA_WRITEMASK_MASK; - shader->inst[3] |= (hwmask << NV40_VP_INST_SCA_WRITEMASK_SHIFT); - } else { - shader->inst[3] &= ~NV40_VP_INST_VEC_WRITEMASK_MASK; - shader->inst[3] |= (hwmask << NV40_VP_INST_VEC_WRITEMASK_SHIFT); - } -} - -static void -NV40VPInsertSource(nvsFunc *shader, unsigned int hw, int pos) -{ - switch (pos) { - case 0: - shader->inst[1] &= ~NV40_VP_INST_SRC0H_MASK; - shader->inst[2] &= ~NV40_VP_INST_SRC0L_MASK; - shader->inst[1] |= ((hw & NV40_VP_SRC0_HIGH_MASK) >> - NV40_VP_SRC0_HIGH_SHIFT) - << NV40_VP_INST_SRC0H_SHIFT; - shader->inst[2] |= (hw & NV40_VP_SRC0_LOW_MASK) - << NV40_VP_INST_SRC0L_SHIFT; - break; - case 1: - shader->inst[2] &= ~NV40_VP_INST_SRC1_MASK; - shader->inst[2] |= hw - << NV40_VP_INST_SRC1_SHIFT; - break; - case 2: - shader->inst[2] &= ~NV40_VP_INST_SRC2H_MASK; - shader->inst[3] &= ~NV40_VP_INST_SRC2L_MASK; - shader->inst[2] |= ((hw & NV40_VP_SRC2_HIGH_MASK) >> - NV40_VP_SRC2_HIGH_SHIFT) - << NV40_VP_INST_SRC2H_SHIFT; - shader->inst[3] |= (hw & NV40_VP_SRC2_LOW_MASK) - << NV40_VP_INST_SRC2L_SHIFT; - break; - default: - assert(0); - break; - } -} - -static void -NV40VPSetSource(nvsFunc *shader, nvsRegister * src, int pos) -{ - unsigned int hw = 0; - - switch (src->file) { - case NVS_FILE_ADDRESS: - break; - case NVS_FILE_ATTRIB: - hw |= (NV40_VP_SRC_REG_TYPE_INPUT << NV40_VP_SRC_REG_TYPE_SHIFT); - - shader->inst[1] &= ~NV40_VP_INST_INPUT_SRC_MASK; - shader->inst[1] |= (src->index << NV40_VP_INST_INPUT_SRC_SHIFT); - shader->card_priv->NV30VP.vp_in_reg |= (1 << src->index); - if (src->indexed) { - shader->inst[0] |= NV40_VP_INST_INDEX_INPUT; - if (src->addr_reg) - shader->inst[0] |= NV40_VP_INST_ADDR_REG_SELECT_1; - else - shader->inst[0] &= ~NV40_VP_INST_ADDR_REG_SELECT_1; - shader->inst[0] &= ~NV40_VP_INST_ADDR_SWZ_SHIFT; - shader->inst[0] |= (src->addr_comp << NV40_VP_INST_ADDR_SWZ_SHIFT); - } else - shader->inst[0] &= ~NV40_VP_INST_INDEX_INPUT; - break; - case NVS_FILE_CONST: - hw |= (NV40_VP_SRC_REG_TYPE_CONST << NV40_VP_SRC_REG_TYPE_SHIFT); - - shader->inst[1] &= ~NV40_VP_INST_CONST_SRC_MASK; - shader->inst[1] |= (src->index << NV40_VP_INST_CONST_SRC_SHIFT); - if (src->indexed) { - shader->inst[3] |= NV40_VP_INST_INDEX_CONST; - if (src->addr_reg) - shader->inst[0] |= NV40_VP_INST_ADDR_REG_SELECT_1; - else - shader->inst[0] &= ~NV40_VP_INST_ADDR_REG_SELECT_1; - shader->inst[0] &= ~NV40_VP_INST_ADDR_SWZ_MASK; - shader->inst[0] |= (src->addr_comp << NV40_VP_INST_ADDR_SWZ_SHIFT); - } else - shader->inst[3] &= ~NV40_VP_INST_INDEX_CONST; - break; - case NVS_FILE_TEMP: - hw |= (NV40_VP_SRC_REG_TYPE_TEMP << NV40_VP_SRC_REG_TYPE_SHIFT); - hw |= (src->index << NV40_VP_SRC_TEMP_SRC_SHIFT); - break; - default: - fprintf(stderr, "unknown source file %d\n", src->file); - assert(0); - break; - } - - if (src->file != NVS_FILE_ADDRESS) { - if (src->negate) - hw |= NV40_VP_SRC_NEGATE; - if (src->abs) - shader->inst[0] |= (1 << (21 + pos)); - else - shader->inst[0] &= ~(1 << (21 + pos)); - hw |= (src->swizzle[0] << NV40_VP_SRC_SWZ_X_SHIFT); - hw |= (src->swizzle[1] << NV40_VP_SRC_SWZ_Y_SHIFT); - hw |= (src->swizzle[2] << NV40_VP_SRC_SWZ_Z_SHIFT); - hw |= (src->swizzle[3] << NV40_VP_SRC_SWZ_W_SHIFT); - - NV40VPInsertSource(shader, hw, pos); - } -} - -static void -NV40VPSetBranchTarget(nvsFunc *shader, int addr) -{ - shader->inst[2] &= ~NV40_VP_INST_IADDRH_MASK; - shader->inst[2] |= ((addr & 0xf8) >> 3) << NV40_VP_INST_IADDRH_SHIFT; - shader->inst[3] &= ~NV40_VP_INST_IADDRL_MASK; - shader->inst[3] |= ((addr & 0x07) << NV40_VP_INST_IADDRL_SHIFT); -} - -static void -NV40VPInitInstruction(nvsFunc *shader) -{ - unsigned int hwsrc = 0; - - shader->inst[0] = /*NV40_VP_INST_VEC_RESULT | */ - NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20); - shader->inst[1] = 0; - shader->inst[2] = 0; - shader->inst[3] = NV40_VP_INST_SCA_RESULT | - NV40_VP_INST_SCA_DEST_TEMP_MASK | - NV40_VP_INST_DEST_MASK; - - hwsrc = (NV40_VP_SRC_REG_TYPE_INPUT << NV40_VP_SRC_REG_TYPE_SHIFT) | - (NVS_SWZ_X << NV40_VP_SRC_SWZ_X_SHIFT) | - (NVS_SWZ_Y << NV40_VP_SRC_SWZ_Y_SHIFT) | - (NVS_SWZ_Z << NV40_VP_SRC_SWZ_Z_SHIFT) | - (NVS_SWZ_W << NV40_VP_SRC_SWZ_W_SHIFT); - NV40VPInsertSource(shader, hwsrc, 0); - NV40VPInsertSource(shader, hwsrc, 1); - NV40VPInsertSource(shader, hwsrc, 2); -} - -static void -NV40VPSetLastInst(nvsFunc *shader) -{ - shader->inst[3] |= 1; -} - -/***************************************************************************** - * Disassembly routines - */ -static int -NV40VPHasMergedInst(nvsFunc * shader) -{ - if (shader->GetOpcodeHW(shader, 0) != NV40_VP_INST_OP_NOP && - shader->GetOpcodeHW(shader, 1) != NV40_VP_INST_OP_NOP) - return 1; - return 0; -} - -static unsigned int -NV40VPGetOpcodeHW(nvsFunc * shader, int slot) -{ - int op; - - if (slot) - op = (shader->inst[1] & NV40_VP_INST_SCA_OPCODE_MASK) - >> NV40_VP_INST_SCA_OPCODE_SHIFT; - else - op = (shader->inst[1] & NV40_VP_INST_VEC_OPCODE_MASK) - >> NV40_VP_INST_VEC_OPCODE_SHIFT; - - return op; -} - -static nvsRegFile -NV40VPGetDestFile(nvsFunc * shader, int merged) -{ - nvsOpcode op; - - op = shader->GetOpcode(shader, merged); - switch (op) { - case NVS_OP_ARL: - case NVS_OP_ARR: - case NVS_OP_ARA: - case NVS_OP_POPA: - return NVS_FILE_ADDRESS; - default: - if (shader->GetOpcodeSlot(shader, merged)) { - if (shader->inst[3] & NV40_VP_INST_SCA_RESULT) - return NVS_FILE_RESULT; - } - else { - if (shader->inst[0] & NV40_VP_INST_VEC_RESULT) - return NVS_FILE_RESULT; - } - return NVS_FILE_TEMP; - } - -} - -static unsigned int -NV40VPGetDestID(nvsFunc * shader, int merged) -{ - int id; - - switch (shader->GetDestFile(shader, merged)) { - case NVS_FILE_RESULT: - id = ((shader->inst[3] & NV40_VP_INST_DEST_MASK) - >> NV40_VP_INST_DEST_SHIFT); - switch (id) { - case NV40_VP_INST_DEST_POS : return NVS_FR_POSITION; - case NV40_VP_INST_DEST_COL0: return NVS_FR_COL0; - case NV40_VP_INST_DEST_COL1: return NVS_FR_COL1; - case NV40_VP_INST_DEST_BFC0: return NVS_FR_BFC0; - case NV40_VP_INST_DEST_BFC1: return NVS_FR_BFC1; - case NV40_VP_INST_DEST_FOGC: { - int mask = shader->GetDestMask(shader, merged); - switch (mask) { - case SMASK_X: return NVS_FR_FOGCOORD; - case SMASK_Y: return NVS_FR_CLIP0; - case SMASK_Z: return NVS_FR_CLIP1; - case SMASK_W: return NVS_FR_CLIP2; - default: - printf("more than 1 mask component set in FOGC writemask!\n"); - return NVS_FR_UNKNOWN; - } - } - case NV40_VP_INST_DEST_PSZ: - { - int mask = shader->GetDestMask(shader, merged); - switch (mask) { - case SMASK_X: return NVS_FR_POINTSZ; - case SMASK_Y: return NVS_FR_CLIP3; - case SMASK_Z: return NVS_FR_CLIP4; - case SMASK_W: return NVS_FR_CLIP5; - default: - printf("more than 1 mask component set in PSZ writemask!\n"); - return NVS_FR_UNKNOWN; - } - } - case NV40_VP_INST_DEST_TC(0): return NVS_FR_TEXCOORD0; - case NV40_VP_INST_DEST_TC(1): return NVS_FR_TEXCOORD1; - case NV40_VP_INST_DEST_TC(2): return NVS_FR_TEXCOORD2; - case NV40_VP_INST_DEST_TC(3): return NVS_FR_TEXCOORD3; - case NV40_VP_INST_DEST_TC(4): return NVS_FR_TEXCOORD4; - case NV40_VP_INST_DEST_TC(5): return NVS_FR_TEXCOORD5; - case NV40_VP_INST_DEST_TC(6): return NVS_FR_TEXCOORD6; - case NV40_VP_INST_DEST_TC(7): return NVS_FR_TEXCOORD7; - default: - return -1; - } - case NVS_FILE_ADDRESS: - /* Instructions that write address regs are encoded as if - * they would write temps. - */ - case NVS_FILE_TEMP: - if (shader->GetOpcodeSlot(shader, merged)) - id = ((shader->inst[3] & NV40_VP_INST_SCA_DEST_TEMP_MASK) - >> NV40_VP_INST_SCA_DEST_TEMP_SHIFT); - else - id = ((shader->inst[0] & NV40_VP_INST_VEC_DEST_TEMP_MASK) - >> NV40_VP_INST_VEC_DEST_TEMP_SHIFT); - return id; - default: - return -1; - } -} - -static unsigned int -NV40VPGetDestMask(nvsFunc * shader, int merged) -{ - unsigned int mask = 0; - - if (shader->GetOpcodeSlot(shader, merged)) { - if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_X) mask |= SMASK_X; - if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_Y) mask |= SMASK_Y; - if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_Z) mask |= SMASK_Z; - if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_W) mask |= SMASK_W; - } else { - if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_X) mask |= SMASK_X; - if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_Y) mask |= SMASK_Y; - if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_Z) mask |= SMASK_Z; - if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_W) mask |= SMASK_W; - } - - return mask; -} - -static unsigned int -NV40VPGetSourceHW(nvsFunc * shader, int merged, int pos) -{ - struct _op_xlat *opr; - unsigned int src; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr) - return -1; - - switch (opr->srcpos[pos]) { - case 0: - src = ((shader->inst[1] & NV40_VP_INST_SRC0H_MASK) - >> NV40_VP_INST_SRC0H_SHIFT) - << NV40_VP_SRC0_HIGH_SHIFT; - src |= ((shader->inst[2] & NV40_VP_INST_SRC0L_MASK) - >> NV40_VP_INST_SRC0L_SHIFT); - break; - case 1: - src = ((shader->inst[2] & NV40_VP_INST_SRC1_MASK) - >> NV40_VP_INST_SRC1_SHIFT); - break; - case 2: - src = ((shader->inst[2] & NV40_VP_INST_SRC2H_MASK) - >> NV40_VP_INST_SRC2H_SHIFT) - << NV40_VP_SRC2_HIGH_SHIFT; - src |= ((shader->inst[3] & NV40_VP_INST_SRC2L_MASK) - >> NV40_VP_INST_SRC2L_SHIFT); - break; - default: - src = -1; - } - - return src; -} - -static nvsRegFile -NV40VPGetSourceFile(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - struct _op_xlat *opr; - int file; - - opr = shader->GetOPTXRec(shader, merged); - if (!opr || opr->srcpos[pos] == -1) - return -1; - - switch (opr->srcpos[pos]) { - case SPOS_ADDRESS: return NVS_FILE_ADDRESS; - default: - src = shader->GetSourceHW(shader, merged, pos); - file = (src & NV40_VP_SRC_REG_TYPE_MASK) >> NV40_VP_SRC_REG_TYPE_SHIFT; - - switch (file) { - case NV40_VP_SRC_REG_TYPE_TEMP : return NVS_FILE_TEMP; - case NV40_VP_SRC_REG_TYPE_INPUT: return NVS_FILE_ATTRIB; - case NV40_VP_SRC_REG_TYPE_CONST: return NVS_FILE_CONST; - default: - return NVS_FILE_UNKNOWN; - } - } -} - -static int -NV40VPGetSourceID(nvsFunc * shader, int merged, int pos) -{ - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_ATTRIB: - switch ((shader->inst[1] & NV40_VP_INST_INPUT_SRC_MASK) - >> NV40_VP_INST_INPUT_SRC_SHIFT) { - case NV40_VP_INST_IN_POS: return NVS_FR_POSITION; - case NV40_VP_INST_IN_WEIGHT: return NVS_FR_WEIGHT; - case NV40_VP_INST_IN_NORMAL: return NVS_FR_NORMAL; - case NV40_VP_INST_IN_COL0: return NVS_FR_COL0; - case NV40_VP_INST_IN_COL1: return NVS_FR_COL1; - case NV40_VP_INST_IN_FOGC: return NVS_FR_FOGCOORD; - case NV40_VP_INST_IN_TC(0): return NVS_FR_TEXCOORD0; - case NV40_VP_INST_IN_TC(1): return NVS_FR_TEXCOORD1; - case NV40_VP_INST_IN_TC(2): return NVS_FR_TEXCOORD2; - case NV40_VP_INST_IN_TC(3): return NVS_FR_TEXCOORD3; - case NV40_VP_INST_IN_TC(4): return NVS_FR_TEXCOORD4; - case NV40_VP_INST_IN_TC(5): return NVS_FR_TEXCOORD5; - case NV40_VP_INST_IN_TC(6): return NVS_FR_TEXCOORD6; - case NV40_VP_INST_IN_TC(7): return NVS_FR_TEXCOORD7; - default: - return -1; - } - break; - case NVS_FILE_CONST: - return ((shader->inst[1] & NV40_VP_INST_CONST_SRC_MASK) - >> NV40_VP_INST_CONST_SRC_SHIFT); - case NVS_FILE_TEMP: - { - unsigned int src; - - src = shader->GetSourceHW(shader, merged, pos); - return ((src & NV40_VP_SRC_TEMP_SRC_MASK) >> - NV40_VP_SRC_TEMP_SRC_SHIFT); - } - default: - return -1; - } -} - -static int -NV40VPGetSourceNegate(nvsFunc * shader, int merged, int pos) -{ - unsigned int src; - - src = shader->GetSourceHW(shader, merged, pos); - - if (src == -1) - return -1; - return ((src & NV40_VP_SRC_NEGATE) ? 1 : 0); -} - -static void -NV40VPGetSourceSwizzle(nvsFunc * shader, int merged, int pos, nvsSwzComp *swz) -{ - unsigned int src; - int swzbits; - - src = shader->GetSourceHW(shader, merged, pos); - swzbits = (src & NV40_VP_SRC_SWZ_ALL_MASK) >> NV40_VP_SRC_SWZ_ALL_SHIFT; - NV20VPTXSwizzle(swzbits, swz); -} - -static int -NV40VPGetSourceIndexed(nvsFunc * shader, int merged, int pos) -{ - switch (shader->GetSourceFile(shader, merged, pos)) { - case NVS_FILE_ATTRIB: - return ((shader->inst[0] & NV40_VP_INST_INDEX_INPUT) ? 1 : 0); - case NVS_FILE_CONST: - return ((shader->inst[3] & NV40_VP_INST_INDEX_CONST) ? 1 : 0); - default: - return 0; - } -} - -static nvsSwzComp -NV40VPGetAddressRegSwizzle(nvsFunc * shader) -{ - nvsSwzComp swz; - - swz = NV20VP_TX_SWIZZLE[(shader->inst[0] & NV40_VP_INST_ADDR_SWZ_MASK) - >> NV40_VP_INST_ADDR_SWZ_SHIFT]; - return swz; -} - -static int -NV40VPSupportsConditional(nvsFunc * shader) -{ - /*FIXME: Is this true of all ops? */ - return 1; -} - -static int -NV40VPGetConditionUpdate(nvsFunc * shader) -{ - return ((shader->inst[0] & NV40_VP_INST_COND_UPDATE_ENABLE) ? 1 : 0); -} - -static int -NV40VPGetConditionTest(nvsFunc * shader) -{ - int op; - - /* The condition test is unconditionally enabled on some - * instructions. ie: the condition test bit does *NOT* have - * to be set. - * - * FIXME: check other relevant ops for this situation. - */ - op = shader->GetOpcodeHW(shader, 1); - switch (op) { - case NV40_VP_INST_OP_BRA: - return 1; - default: - return ((shader->inst[0] & NV40_VP_INST_COND_TEST_ENABLE) ? 1 : 0); - } -} - -static nvsCond -NV40VPGetCondition(nvsFunc * shader) -{ - int cond; - - cond = ((shader->inst[0] & NV40_VP_INST_COND_MASK) - >> NV40_VP_INST_COND_SHIFT); - - switch (cond) { - case NV40_VP_INST_COND_FL: return NVS_COND_FL; - case NV40_VP_INST_COND_LT: return NVS_COND_LT; - case NV40_VP_INST_COND_EQ: return NVS_COND_EQ; - case NV40_VP_INST_COND_LE: return NVS_COND_LE; - case NV40_VP_INST_COND_GT: return NVS_COND_GT; - case NV40_VP_INST_COND_NE: return NVS_COND_NE; - case NV40_VP_INST_COND_GE: return NVS_COND_GE; - case NV40_VP_INST_COND_TR: return NVS_COND_TR; - default: - return NVS_COND_UNKNOWN; - } -} - -static void -NV40VPGetCondRegSwizzle(nvsFunc * shader, nvsSwzComp *swz) -{ - int swzbits; - - swzbits = (shader->inst[0] & NV40_VP_INST_COND_SWZ_ALL_MASK) - >> NV40_VP_INST_COND_SWZ_ALL_SHIFT; - NV20VPTXSwizzle(swzbits, swz); -} - -static int -NV40VPGetCondRegID(nvsFunc * shader) -{ - return ((shader->inst[0] & NV40_VP_INST_COND_REG_SELECT_1) ? 1 : 0); -} - -static int -NV40VPGetBranch(nvsFunc * shader) -{ - int addr; - - addr = ((shader->inst[2] & NV40_VP_INST_IADDRH_MASK) - >> NV40_VP_INST_IADDRH_SHIFT) << 3; - addr |= ((shader->inst[3] & NV40_VP_INST_IADDRL_MASK) - >> NV40_VP_INST_IADDRL_SHIFT); - return addr; -} - -void -NV40VPInitShaderFuncs(nvsFunc * shader) -{ - /* Inherit NV30 VP code, we share some of it */ - NV30VPInitShaderFuncs(shader); - - /* Limits */ - shader->MaxInst = 4096; - shader->MaxAttrib = 16; - shader->MaxTemp = 32; - shader->MaxAddress = 2; - shader->MaxConst = 256; - shader->caps = SCAP_SRC_ABS; - - /* Add extra opcodes for NV40+ */ -// MOD_OPCODE(NVVP_TX_VOP, NV40_VP_INST_OP_TXWHAT, NVS_OP_TEX , 0, 4, -1); - MOD_OPCODE(NVVP_TX_SOP, NV40_VP_INST_OP_PUSHA, NVS_OP_PUSHA, 3, -1, -1); - MOD_OPCODE(NVVP_TX_SOP, NV40_VP_INST_OP_POPA , NVS_OP_POPA , -1, -1, -1); - - shader->InitInstruction = NV40VPInitInstruction; - shader->SupportsOpcode = NV40VPSupportsOpcode; - shader->SetOpcode = NV40VPSetOpcode; - shader->SetCCUpdate = NV40VPSetCCUpdate; - shader->SetCondition = NV40VPSetCondition; - shader->SetResult = NV40VPSetResult; - shader->SetSource = NV40VPSetSource; - shader->SetLastInst = NV40VPSetLastInst; - shader->SetBranchTarget = NV40VPSetBranchTarget; - - shader->HasMergedInst = NV40VPHasMergedInst; - shader->GetOpcodeHW = NV40VPGetOpcodeHW; - - shader->GetDestFile = NV40VPGetDestFile; - shader->GetDestID = NV40VPGetDestID; - shader->GetDestMask = NV40VPGetDestMask; - - shader->GetSourceHW = NV40VPGetSourceHW; - shader->GetSourceFile = NV40VPGetSourceFile; - shader->GetSourceID = NV40VPGetSourceID; - shader->GetSourceNegate = NV40VPGetSourceNegate; - shader->GetSourceSwizzle = NV40VPGetSourceSwizzle; - shader->GetSourceIndexed = NV40VPGetSourceIndexed; - - shader->GetRelAddressSwizzle = NV40VPGetAddressRegSwizzle; - - shader->SupportsConditional = NV40VPSupportsConditional; - shader->GetConditionUpdate = NV40VPGetConditionUpdate; - shader->GetConditionTest = NV40VPGetConditionTest; - shader->GetCondition = NV40VPGetCondition; - shader->GetCondRegSwizzle = NV40VPGetCondRegSwizzle; - shader->GetCondRegID = NV40VPGetCondRegID; - - shader->GetBranch = NV40VPGetBranch; -} diff --git a/src/mesa/drivers/dri/nouveau/nv50_state.c b/src/mesa/drivers/dri/nouveau/nv50_state.c deleted file mode 100644 index a9236f093c3..00000000000 --- a/src/mesa/drivers/dri/nouveau/nv50_state.c +++ /dev/null @@ -1,641 +0,0 @@ -/************************************************************************** - -Copyright 2006 Nouveau -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -#include "nouveau_context.h" -#include "nouveau_object.h" -#include "nouveau_fifo.h" -#include "nouveau_reg.h" -#include "nouveau_state.h" - -#include "tnl/t_pipeline.h" - -#include "mtypes.h" -#include "colormac.h" - -static void nv50AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte ubRef; - CLAMPED_FLOAT_TO_UBYTE(ubRef, ref); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF, 2); - OUT_RING_CACHE(ubRef); - OUT_RING_CACHE(func); -} - -static void nv50BlendColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_R, 4); - OUT_RING_CACHEf(color[0]); - OUT_RING_CACHEf(color[1]); - OUT_RING_CACHEf(color[2]); - OUT_RING_CACHEf(color[3]); -} - -static void nv50BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB, 1); - OUT_RING_CACHE(modeRGB); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA, 1); - OUT_RING_CACHE(modeA); -} - - -static void nv50BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB, 2); - OUT_RING_CACHE(sfactorRGB); /* FIXME, sometimes has |0x4000 */ - OUT_RING_CACHE(dfactorRGB); /* FIXME, sometimes has |0x4000 */ - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA, 2); - OUT_RING_CACHE(sfactorA); /* FIXME, sometimes has |0x4000 */ - OUT_RING_CACHE(dfactorA); /* FIXME, sometimes has |0x4000 */ -} - -static void nv50Clear(GLcontext *ctx, GLbitfield mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLuint hw_bufs = 0; - - if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT)) - hw_bufs |= 0x3c; - if (mask & (BUFFER_BIT_STENCIL)) - hw_bufs |= 0x02; - if (mask & (BUFFER_BIT_DEPTH)) - hw_bufs |= 0x01; - - if (hw_bufs) { - BEGIN_RING_SIZE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS, 1); - OUT_RING(hw_bufs); - } -} - -static void nv50ClearColor(GLcontext *ctx, const GLfloat color[4]) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_R, 4); - OUT_RING_CACHEf(color[0]); - OUT_RING_CACHEf(color[1]); - OUT_RING_CACHEf(color[2]); - OUT_RING_CACHEf(color[3]); -} - -static void nv50ClearDepth(GLcontext *ctx, GLclampd d) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_DEPTH, 1); - OUT_RING_CACHEf(d); -} - -/* we're don't support indexed buffers - void (*ClearIndex)(GLcontext *ctx, GLuint index) - */ - -static void nv50ClearStencil(GLcontext *ctx, GLint s) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_STENCIL, 1); - OUT_RING_CACHE(s); -} - -static void nv50ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation) -{ - /* Only using shaders */ -} - -static void nv50ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask, - GLboolean bmask, GLboolean amask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - int i; - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_COLOR_MASK(0), 8); - for (i=0; i<8; i++) { - OUT_RING_CACHE(((amask && 0x01) << 12) | ((bmask && 0x01) << 8) | ((gmask && 0x01)<< 4) | ((rmask && 0x01) << 0)); - } -} - -static void nv50ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode) -{ - // TODO I need love -} - -static void nv50CullFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CULL_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv50FrontFace(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_FRONT_FACE, 1); - OUT_RING_CACHE(mode); -} - -static void nv50DepthFunc(GLcontext *ctx, GLenum func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1); - OUT_RING_CACHE(func); -} - -static void nv50DepthMask(GLcontext *ctx, GLboolean flag) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1); - OUT_RING_CACHE(flag); -} - -static void nv50DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2); - OUT_RING_CACHEf(nearval); - OUT_RING_CACHEf(farval); -} - -/** Specify the current buffer for writing */ -//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer ); -/** Specify the buffers for writing for fragment programs*/ -//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers ); - -static void nv50Enable(GLcontext *ctx, GLenum cap, GLboolean state) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - switch(cap) - { - case GL_ALPHA_TEST: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_AUTO_NORMAL: -// case GL_BLEND: -// case GL_CLIP_PLANE0: -// case GL_CLIP_PLANE1: -// case GL_CLIP_PLANE2: -// case GL_CLIP_PLANE3: -// case GL_CLIP_PLANE4: -// case GL_CLIP_PLANE5: - case GL_COLOR_LOGIC_OP: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LOGIC_OP_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_COLOR_MATERIAL: -// case GL_COLOR_SUM_EXT: -// case GL_COLOR_TABLE: -// case GL_CONVOLUTION_1D: -// case GL_CONVOLUTION_2D: - case GL_CULL_FACE: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_DEPTH_TEST: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_DITHER: -// case GL_FOG: -// case GL_HISTOGRAM: -// case GL_INDEX_LOGIC_OP: -// case GL_LIGHT0: -// case GL_LIGHT1: -// case GL_LIGHT2: -// case GL_LIGHT3: -// case GL_LIGHT4: -// case GL_LIGHT5: -// case GL_LIGHT6: -// case GL_LIGHT7: -// case GL_LIGHTING: - case GL_LINE_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_LINE_STIPPLE: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_MAP1_COLOR_4: -// case GL_MAP1_INDEX: -// case GL_MAP1_NORMAL: -// case GL_MAP1_TEXTURE_COORD_1: -// case GL_MAP1_TEXTURE_COORD_2: -// case GL_MAP1_TEXTURE_COORD_3: -// case GL_MAP1_TEXTURE_COORD_4: -// case GL_MAP1_VERTEX_3: -// case GL_MAP1_VERTEX_4: -// case GL_MAP2_COLOR_4: -// case GL_MAP2_INDEX: -// case GL_MAP2_NORMAL: -// case GL_MAP2_TEXTURE_COORD_1: -// case GL_MAP2_TEXTURE_COORD_2: -// case GL_MAP2_TEXTURE_COORD_3: -// case GL_MAP2_TEXTURE_COORD_4: -// case GL_MAP2_VERTEX_3: -// case GL_MAP2_VERTEX_4: -// case GL_MINMAX: -// case GL_NORMALIZE: -// case GL_POINT_SMOOTH: - case GL_POLYGON_OFFSET_POINT: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_LINE: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_OFFSET_FILL: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_SMOOTH: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1); - OUT_RING_CACHE(state); - break; - case GL_POLYGON_STIPPLE: - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_POST_COLOR_MATRIX_COLOR_TABLE: -// case GL_POST_CONVOLUTION_COLOR_TABLE: -// case GL_RESCALE_NORMAL: - case GL_SCISSOR_TEST: - /* No enable bit, nv50Scissor will adjust to max range */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - break; -// case GL_SEPARABLE_2D: - case GL_STENCIL_TEST: - // TODO BACK and FRONT ? - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE, 1); - OUT_RING_CACHE(state); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE, 1); - OUT_RING_CACHE(state); - break; -// case GL_TEXTURE_GEN_Q: -// case GL_TEXTURE_GEN_R: -// case GL_TEXTURE_GEN_S: -// case GL_TEXTURE_GEN_T: -// case GL_TEXTURE_1D: -// case GL_TEXTURE_2D: -// case GL_TEXTURE_3D: - } -} - -static void nv50Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - /* Only using shaders */ -} - -static void nv50Hint(GLcontext *ctx, GLenum target, GLenum mode) -{ - // TODO I need love (fog and line_smooth hints) -} - -// void (*IndexMask)(GLcontext *ctx, GLuint mask); - -static void nv50Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params ) -{ - /* Only with shaders */ -} - -/** Set the lighting model parameters */ -void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params); - - -static void nv50LineStipple(GLcontext *ctx, GLint factor, GLushort pattern ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN, 1); - OUT_RING_CACHE((pattern << 8) | factor); -} - -static void nv50LineWidth(GLcontext *ctx, GLfloat width) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_WIDTH, 1); - OUT_RING_CACHEf(width); -} - -static void nv50LogicOpcode(GLcontext *ctx, GLenum opcode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP, 1); - OUT_RING_CACHE(opcode); -} - -static void nv50PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params) -{ - /*TODO: not sure what goes here. */ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -} - -/** Specify the diameter of rasterized points */ -static void nv50PointSize(GLcontext *ctx, GLfloat size) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POINT_SIZE, 1); - OUT_RING_CACHEf(size); -} - -/** Select a polygon rasterization mode */ -static void nv50PolygonMode(GLcontext *ctx, GLenum face, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1); - OUT_RING_CACHE(mode); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1); - OUT_RING_CACHE(mode); - } -} - -/** Set the scale and units used to calculate depth values */ -static void nv50PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 1); - OUT_RING_CACHEf(factor); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS, 1); - OUT_RING_CACHEf(units); -} - -/** Set the polygon stippling pattern */ -static void nv50PolygonStipple(GLcontext *ctx, const GLubyte *mask ) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(0), 32); - OUT_RING_CACHEp(mask, 32); -} - -/* Specifies the current buffer for reading */ -void (*ReadBuffer)( GLcontext *ctx, GLenum buffer ); -/** Set rasterization mode */ -void (*RenderMode)(GLcontext *ctx, GLenum mode ); - -/** Define the scissor box */ -static void nv50Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - /* There's no scissor enable bit, so adjust the scissor to cover the - * maximum draw buffer bounds - */ - if (!ctx->Scissor.Enabled) { - x = y = 0; - w = h = 8191; - } else { - x += nmesa->drawX; - y += nmesa->drawY; - } - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS, 2); - OUT_RING_CACHE(((w) << 16) | x); - OUT_RING_CACHE(((h) << 16) | y); -} - -/** Select flat or smooth shading */ -static void nv50ShadeModel(GLcontext *ctx, GLenum mode) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SHADE_MODEL, 1); - OUT_RING_CACHE(mode); -} - -/** OpenGL 2.0 two-sided StencilFunc */ -static void nv50StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, - GLint ref, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC, 1); - OUT_RING_CACHE(func); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF, 1); - OUT_RING_CACHE(ref); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK, 1); - OUT_RING_CACHE(mask); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC, 2); - OUT_RING_CACHE(func); - OUT_RING_CACHE(ref); - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK, 1); - OUT_RING_CACHE(mask); - } -} - -/** OpenGL 2.0 two-sided StencilMask */ -static void nv50StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK, 1); - OUT_RING_CACHE(mask); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK, 1); - OUT_RING_CACHE(mask); - } -} - -/** OpenGL 2.0 two-sided StencilOp */ -static void nv50StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, - GLenum zfail, GLenum zpass) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (face == GL_FRONT || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL, 3); - OUT_RING_CACHE(fail); - OUT_RING_CACHE(zfail); - OUT_RING_CACHE(zpass); - } - if (face == GL_BACK || face == GL_FRONT_AND_BACK) { - BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL, 3); - OUT_RING_CACHE(fail); - OUT_RING_CACHE(zfail); - OUT_RING_CACHE(zpass); - } -} - -/** Control the generation of texture coordinates */ -void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname, - const GLfloat *params); -/** Set texture environment parameters */ -void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname, - const GLfloat *param); -/** Set texture parameters */ -void (*TexParameter)(GLcontext *ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat *params); - -static void nv50TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat) -{ - /* Only with shaders */ -} - -static void nv50WindowMoved(nouveauContextPtr nmesa) -{ - GLcontext *ctx = nmesa->glCtx; - GLfloat *v = nmesa->viewport.m; - GLuint w = ctx->Viewport.Width; - GLuint h = ctx->Viewport.Height; - GLuint x = ctx->Viewport.X + nmesa->drawX; - GLuint y = ctx->Viewport.Y + nmesa->drawY; - int i; - - BEGIN_RING_CACHE(NvSub3D, - NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 2); - OUT_RING_CACHE((8191 << 16) | 0); - OUT_RING_CACHE((8191 << 16) | 0); - for (i=1; i<8; i++) { - BEGIN_RING_CACHE(NvSub3D, - NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(i), 2); - OUT_RING_CACHE(0); - OUT_RING_CACHE(0); - } - - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); -} - -static GLboolean nv50InitCard(nouveauContextPtr nmesa) -{ - int i,j; - - nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D); - - BEGIN_RING_SIZE(NvSub3D, 0x1558, 1); - OUT_RING(1); - - BEGIN_RING_SIZE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SET_OBJECT_1(0), 8); - for (i=0; i<8; i++) { - OUT_RING(NvDmaFB); - } - - BEGIN_RING_SIZE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SET_OBJECT_0(0), 12); - for (i=0; i<12; i++) { - OUT_RING(NvDmaFB); - } - - BEGIN_RING_SIZE(NvSub3D, 0x121c, 1); - OUT_RING(1); - - for (i=0; i<8; i++) { - BEGIN_RING_SIZE(NvSub3D, 0x0200 + (i*0x20), 5); - for (j=0; j<5; j++) { - OUT_RING(0); - } - } - - BEGIN_RING_SIZE(NvSub3D, 0x0fe0, 5); - OUT_RING(0); - OUT_RING(0); - OUT_RING(0x16); - OUT_RING(0); - OUT_RING(0); - - return GL_FALSE; -} - -static GLboolean -nv50BindBuffers(nouveauContextPtr nmesa, int num_color, - nouveau_renderbuffer_t **color, nouveau_renderbuffer_t *depth) -{ - return GL_FALSE; -} - -void nv50InitStateFuncs(GLcontext *ctx, struct dd_function_table *func) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - func->AlphaFunc = nv50AlphaFunc; - func->BlendColor = nv50BlendColor; - func->BlendEquationSeparate = nv50BlendEquationSeparate; - func->BlendFuncSeparate = nv50BlendFuncSeparate; - func->Clear = nv50Clear; - func->ClearColor = nv50ClearColor; - func->ClearDepth = nv50ClearDepth; - func->ClearStencil = nv50ClearStencil; - func->ClipPlane = nv50ClipPlane; - func->ColorMask = nv50ColorMask; - func->ColorMaterial = nv50ColorMaterial; - func->CullFace = nv50CullFace; - func->FrontFace = nv50FrontFace; - func->DepthFunc = nv50DepthFunc; - func->DepthMask = nv50DepthMask; - func->DepthRange = nv50DepthRange; - func->Enable = nv50Enable; - func->Fogfv = nv50Fogfv; - func->Hint = nv50Hint; - func->Lightfv = nv50Lightfv; -/* func->LightModelfv = nv50LightModelfv; */ - func->LineStipple = nv50LineStipple; - func->LineWidth = nv50LineWidth; - func->LogicOpcode = nv50LogicOpcode; - func->PointParameterfv = nv50PointParameterfv; - func->PointSize = nv50PointSize; - func->PolygonMode = nv50PolygonMode; - func->PolygonOffset = nv50PolygonOffset; - func->PolygonStipple = nv50PolygonStipple; -/* func->ReadBuffer = nv50ReadBuffer; */ -/* func->RenderMode = nv50RenderMode; */ - func->Scissor = nv50Scissor; - func->ShadeModel = nv50ShadeModel; - func->StencilFuncSeparate = nv50StencilFuncSeparate; - func->StencilMaskSeparate = nv50StencilMaskSeparate; - func->StencilOpSeparate = nv50StencilOpSeparate; -/* func->TexGen = nv50TexGen; */ -/* func->TexParameter = nv50TexParameter; */ - func->TextureMatrix = nv50TextureMatrix; - - nmesa->hw_func.InitCard = nv50InitCard; - nmesa->hw_func.BindBuffers = nv50BindBuffers; - nmesa->hw_func.WindowMoved = nv50WindowMoved; -} diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index d52b2b4c36d..6ca934204f3 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -38,8 +38,11 @@ DRIVER_SOURCES = \ r300_texstate.c \ radeon_program.c \ radeon_program_alu.c \ + radeon_program_pair.c \ + radeon_nqssadce.c \ r300_vertprog.c \ r300_fragprog.c \ + r300_fragprog_swizzle.c \ r300_fragprog_emit.c \ r500_fragprog.c \ r500_fragprog_emit.c \ diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index d378045b983..4dc31614492 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -405,7 +405,7 @@ void r300InitCmdBuf(r300ContextPtr r300) ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0); r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R500_RS_IP_0, 16); for (i = 0; i < 8; i++) { - r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = + r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | @@ -470,8 +470,13 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2); ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0); r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(RB3D_COLOR_CHANNEL_MASK, 1); - ALLOC_STATE(blend_color, always, 4, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 3); + if (is_r500) { + ALLOC_STATE(blend_color, always, 3, 0); + r300->hw.blend_color.cmd[0] = cmdpacket0(R500_RB3D_CONSTANT_COLOR_AR, 2); + } else { + ALLOC_STATE(blend_color, always, 2, 0); + r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 1); + } ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0); r300->hw.cb.cmd[R300_CB_CMD_0] = cmdpacket0(R300_RB3D_COLOROFFSET0, 1); r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 063d4e575ef..a9c581b236e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -79,6 +79,7 @@ int hw_tcl_on = 1; #define need_GL_EXT_stencil_two_side #define need_GL_ARB_multisample +#define need_GL_ARB_point_parameters #define need_GL_ARB_texture_compression #define need_GL_ARB_vertex_buffer_object #define need_GL_ARB_vertex_program @@ -98,6 +99,7 @@ const struct dri_extension card_extensions[] = { {"GL_ARB_fragment_program", NULL}, {"GL_ARB_multisample", GL_ARB_multisample_functions}, {"GL_ARB_multitexture", NULL}, + {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions}, {"GL_ARB_shadow", NULL}, {"GL_ARB_texture_border_clamp", NULL}, {"GL_ARB_texture_compression", GL_ARB_texture_compression_functions}, @@ -279,6 +281,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, MIN2(ctx->Const.MaxTextureImageUnits, ctx->Const.MaxTextureCoordUnits); ctx->Const.MaxTextureMaxAnisotropy = 16.0; + ctx->Const.MaxTextureLodBias = 16.0; if (screen->chip_family >= CHIP_FAMILY_RV515) { ctx->Const.MaxTextureLevels = 13; diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 285b2ad6fd6..98af6d8f10a 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -683,16 +683,25 @@ struct r300_fragment_program_external_state { }; +struct r300_fragment_program_node { + int tex_offset; /**< first tex instruction */ + int tex_end; /**< last tex instruction, relative to tex_offset */ + int alu_offset; /**< first ALU instruction */ + int alu_end; /**< last ALU instruction, relative to alu_offset */ + int flags; +}; + /** * Stores an R300 fragment program in its compiled-to-hardware form. */ struct r300_fragment_program_code { struct { - int length; + int length; /**< total # of texture instructions used */ GLuint inst[PFS_MAX_TEX_INST]; } tex; struct { + int length; /**< total # of ALU instructions used */ struct { GLuint inst0; GLuint inst1; @@ -701,29 +710,15 @@ struct r300_fragment_program_code { } inst[PFS_MAX_ALU_INST]; } alu; - struct { - int tex_offset; - int tex_end; - int alu_offset; - int alu_end; - int flags; - } node[4]; + struct r300_fragment_program_node node[4]; int cur_node; int first_node_has_tex; - int alu_offset; - int alu_end; - int tex_offset; - int tex_end; - - /* Hardware constants. - * Contains a pointer to the value. The destination of the pointer - * is supposed to be updated when GL state changes. - * Typically, this is either a pointer into - * gl_program_parameter_list::ParameterValues, or a pointer to a - * global constant (e.g. for sin/cos-approximation) + /** + * Remember which program register a given hardware constant + * belongs to. */ - const GLfloat *constant[PFS_NUM_CONST_REGS]; + struct prog_src_register constant[PFS_NUM_CONST_REGS]; int const_nr; int max_temp_idx; @@ -780,21 +775,15 @@ struct r500_fragment_program_code { GLuint inst4; GLuint inst5; } inst[512]; - /* TODO: This is magic! */ - - int temp_reg_offset; int inst_offset; int inst_end; - /* Hardware constants. - * Contains a pointer to the value. The destination of the pointer - * is supposed to be updated when GL state changes. - * Typically, this is either a pointer into - * gl_program_parameter_list::ParameterValues, or a pointer to a - * global constant (e.g. for sin/cos-approximation) - */ - const GLfloat *constant[PFS_NUM_CONST_REGS]; + /** + * Remember which program register a given hardware constant + * belongs to. + */ + struct prog_src_register constant[PFS_NUM_CONST_REGS]; int const_nr; int max_temp_idx; @@ -806,10 +795,10 @@ struct r500_fragment_program { GLcontext *ctx; GLboolean translated; GLboolean error; - + struct r500_fragment_program_external_state state; struct r500_fragment_program_code code; - + GLboolean writes_depth; GLuint optimization; @@ -925,7 +914,6 @@ struct r300_context { driTextureObject swapped; int texture_depth; float initialMaxAnisotropy; - float LODBias; /* Clientdata textures; */ diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index 6d24d266fec..d390de54b8a 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -29,10 +29,8 @@ * \file * * Fragment program compiler. Perform transformations on the intermediate - * \ref radeon_program representation (which is essentially the Mesa - * program representation plus the notion of clauses) until the program - * is in a form where we can translate it more or less directly into - * machine-readable form. + * representation until the program is in a form where we can translate + * it more or less directly into machine-readable form. * * \author Ben Skeggs <[email protected]> * \author Jerome Glisse <[email protected]> @@ -47,8 +45,10 @@ #include "r300_context.h" #include "r300_fragprog.h" +#include "r300_fragprog_swizzle.h" #include "r300_state.h" +#include "radeon_nqssadce.h" #include "radeon_program_alu.h" @@ -68,7 +68,7 @@ static void reset_srcreg(struct prog_src_register* reg) * be reused. */ static GLboolean transform_TEX( - struct radeon_program_transform_context* context, + struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data) { struct r300_fragment_program_compiler *compiler = @@ -84,12 +84,11 @@ static GLboolean transform_TEX( return GL_FALSE; if (inst.Opcode != OPCODE_KIL && - compiler->fp->mesa_program.Base.ShadowSamplers & (1 << inst.TexSrcUnit)) { + t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) { GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func; if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) { - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); tgt->Opcode = OPCODE_MOV; tgt->DstReg = inst.DstReg; @@ -99,7 +98,7 @@ static GLboolean transform_TEX( } inst.DstReg.File = PROGRAM_TEMPORARY; - inst.DstReg.Index = radeonCompilerAllocateTemporary(context->compiler); + inst.DstReg.Index = radeonFindFreeTemporary(t); inst.DstReg.WriteMask = WRITEMASK_XYZW; } @@ -114,16 +113,13 @@ static GLboolean transform_TEX( 0 }; - int tempreg = radeonCompilerAllocateTemporary(context->compiler); + int tempreg = radeonFindFreeTemporary(t); int factor_index; tokens[2] = inst.TexSrcUnit; - factor_index = - _mesa_add_state_reference( - compiler->fp->mesa_program.Base.Parameters, tokens); + factor_index = _mesa_add_state_reference(t->Program->Parameters, tokens); - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); tgt->Opcode = OPCODE_MUL; tgt->DstReg.File = PROGRAM_TEMPORARY; @@ -137,30 +133,10 @@ static GLboolean transform_TEX( inst.SrcReg[0].Index = tempreg; } - /* Texture operations do not support swizzles etc. in hardware, - * so emit an additional arithmetic operation if necessary. - */ - if (inst.SrcReg[0].Swizzle != SWIZZLE_NOOP || - inst.SrcReg[0].Abs || inst.SrcReg[0].NegateBase || inst.SrcReg[0].NegateAbs) { - int tempreg = radeonCompilerAllocateTemporary(context->compiler); - - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); - - tgt->Opcode = OPCODE_MOV; - tgt->DstReg.File = PROGRAM_TEMPORARY; - tgt->DstReg.Index = tempreg; - tgt->SrcReg[0] = inst.SrcReg[0]; - - reset_srcreg(&inst.SrcReg[0]); - inst.SrcReg[0].File = PROGRAM_TEMPORARY; - inst.SrcReg[0].Index = tempreg; - } - if (inst.Opcode != OPCODE_KIL) { if (inst.DstReg.File != PROGRAM_TEMPORARY || inst.DstReg.WriteMask != WRITEMASK_XYZW) { - int tempreg = radeonCompilerAllocateTemporary(context->compiler); + int tempreg = radeonFindFreeTemporary(t); inst.DstReg.File = PROGRAM_TEMPORARY; inst.DstReg.Index = tempreg; @@ -169,55 +145,63 @@ static GLboolean transform_TEX( } } - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); _mesa_copy_instructions(tgt, &inst, 1); if (inst.Opcode != OPCODE_KIL && - compiler->fp->mesa_program.Base.ShadowSamplers & (1 << inst.TexSrcUnit)) { + t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) { GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func; GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode; - - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 2); - - tgt[0].Opcode = OPCODE_ADD; - tgt[0].DstReg = inst.DstReg; - tgt[0].DstReg.WriteMask = orig_inst->DstReg.WriteMask; - tgt[0].SrcReg[0].File = PROGRAM_TEMPORARY; - tgt[0].SrcReg[0].Index = inst.DstReg.Index; + int rcptemp = radeonFindFreeTemporary(t); + + tgt = radeonAppendInstructions(t->Program, 3); + + tgt[0].Opcode = OPCODE_RCP; + tgt[0].DstReg.File = PROGRAM_TEMPORARY; + tgt[0].DstReg.Index = rcptemp; + tgt[0].DstReg.WriteMask = WRITEMASK_W; + tgt[0].SrcReg[0] = inst.SrcReg[0]; + tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW; + + tgt[1].Opcode = OPCODE_MAD; + tgt[1].DstReg = inst.DstReg; + tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask; + tgt[1].SrcReg[0] = inst.SrcReg[0]; + tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ; + tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY; + tgt[1].SrcReg[1].Index = rcptemp; + tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW; + tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY; + tgt[1].SrcReg[2].Index = inst.DstReg.Index; if (depthmode == 0) /* GL_LUMINANCE */ - tgt[0].SrcReg[0].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z); + tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z); else if (depthmode == 2) /* GL_ALPHA */ - tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW; - tgt[0].SrcReg[1] = inst.SrcReg[0]; - tgt[0].SrcReg[1].Swizzle = SWIZZLE_ZZZZ; + tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW; /* Recall that SrcReg[0] is tex, SrcReg[2] is r and: * r < tex <=> -tex+r < 0 * r >= tex <=> not (-tex+r < 0 */ if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL) - tgt[0].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW; + tgt[1].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW; else - tgt[0].SrcReg[1].NegateBase = tgt[0].SrcReg[1].NegateBase ^ NEGATE_XYZW; + tgt[1].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW; - tgt[1].Opcode = OPCODE_CMP; - tgt[1].DstReg = orig_inst->DstReg; - tgt[1].SrcReg[0].File = PROGRAM_TEMPORARY; - tgt[1].SrcReg[0].Index = tgt[0].DstReg.Index; - tgt[1].SrcReg[1].File = PROGRAM_BUILTIN; - tgt[1].SrcReg[2].File = PROGRAM_BUILTIN; + tgt[2].Opcode = OPCODE_CMP; + tgt[2].DstReg = orig_inst->DstReg; + tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY; + tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index; + tgt[2].SrcReg[1].File = PROGRAM_BUILTIN; + tgt[2].SrcReg[2].File = PROGRAM_BUILTIN; if (comparefunc == GL_LESS || comparefunc == GL_GREATER) { - tgt[1].SrcReg[1].Swizzle = SWIZZLE_1111; - tgt[1].SrcReg[2].Swizzle = SWIZZLE_0000; + tgt[2].SrcReg[1].Swizzle = SWIZZLE_1111; + tgt[2].SrcReg[2].Swizzle = SWIZZLE_0000; } else { - tgt[1].SrcReg[1].Swizzle = SWIZZLE_0000; - tgt[1].SrcReg[2].Swizzle = SWIZZLE_1111; + tgt[2].SrcReg[1].Swizzle = SWIZZLE_0000; + tgt[2].SrcReg[2].Swizzle = SWIZZLE_1111; } } else if (destredirect) { - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); tgt->Opcode = OPCODE_MOV; tgt->DstReg = orig_inst->DstReg; @@ -263,9 +247,10 @@ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) struct prog_instruction *fpi; GLuint window_index; int i = 0; - GLuint tempregi = radeonCompilerAllocateTemporary(&compiler->compiler); + GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY); - fpi = radeonClauseInsertInstructions(&compiler->compiler, &compiler->compiler.Clauses[0], 0, 3); + _mesa_insert_instructions(compiler->program, 0, 3); + fpi = compiler->program->Instructions; /* perspective divide */ fpi[i].Opcode = OPCODE_RCP; @@ -297,7 +282,7 @@ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) i++; /* viewport transformation */ - window_index = _mesa_add_state_reference(compiler->fp->mesa_program.Base.Parameters, tokens); + window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens); fpi[i].Opcode = OPCODE_MAD; @@ -322,7 +307,7 @@ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); i++; - for (; i < compiler->compiler.Clauses[0].NumInstructions; ++i) { + for (; i < compiler->program->NumInstructions; ++i) { int reg; for (reg = 0; reg < 3; reg++) { if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT && @@ -335,6 +320,13 @@ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) } +static void nqssadce_init(struct nqssadce_state* s) +{ + s->Outputs[FRAG_RESULT_COLR].Sourced = WRITEMASK_XYZW; + s->Outputs[FRAG_RESULT_DEPR].Sourced = WRITEMASK_W; +} + + static GLuint build_dtm(GLuint depthmode) { switch(depthmode) { @@ -393,28 +385,52 @@ void r300TranslateFragmentShader(r300ContextPtr r300, compiler.r300 = r300; compiler.fp = fp; compiler.code = &fp->code; + compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base); - radeonCompilerInit(&compiler.compiler, r300->radeon.glCtx, &fp->mesa_program.Base); + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Fragment Program: Initial program:\n"); + _mesa_print_program(compiler.program); + } insert_WPOS_trailer(&compiler); struct radeon_program_transformation transformations[] = { { &transform_TEX, &compiler }, - { &radeonTransformALU, 0 } + { &radeonTransformALU, 0 }, + { &radeonTransformTrigSimple, 0 } }; - radeonClauseLocalTransform(&compiler.compiler, - &compiler.compiler.Clauses[0], - 2, transformations); + radeonLocalTransform( + r300->radeon.glCtx, + compiler.program, + 3, transformations); if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler state after transformations:\n"); - radeonCompilerDump(&compiler.compiler); + _mesa_printf("Fragment Program: After native rewrite:\n"); + _mesa_print_program(compiler.program); + } + + struct radeon_nqssadce_descr nqssadce = { + .Init = &nqssadce_init, + .IsNativeSwizzle = &r300FPIsNativeSwizzle, + .BuildSwizzle = &r300FPBuildSwizzle, + .RewriteDepthOut = GL_TRUE + }; + radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce); + + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Compiler: after NqSSA-DCE:\n"); + _mesa_print_program(compiler.program); } if (!r300FragmentProgramEmit(&compiler)) fp->error = GL_TRUE; - radeonCompilerCleanup(&compiler.compiler); + /* Subtle: Rescue any parameters that have been added during transformations */ + _mesa_free_parameter_list(fp->mesa_program.Base.Parameters); + fp->mesa_program.Base.Parameters = compiler.program->Parameters; + compiler.program->Parameters = 0; + + _mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL); if (!fp->error) fp->translated = GL_TRUE; @@ -436,22 +452,18 @@ void r300FragmentProgramDump( fprintf(stderr, "pc=%d*************************************\n", pc++); - fprintf(stderr, "Mesa program:\n"); - fprintf(stderr, "-------------\n"); - _mesa_print_program(&fp->mesa_program.Base); - fflush(stdout); - fprintf(stderr, "Hardware program\n"); fprintf(stderr, "----------------\n"); for (n = 0; n < (code->cur_node + 1); n++) { fprintf(stderr, "NODE %d: alu_offset: %d, tex_offset: %d, " - "alu_end: %d, tex_end: %d\n", n, + "alu_end: %d, tex_end: %d, flags: %08x\n", n, code->node[n].alu_offset, code->node[n].tex_offset, - code->node[n].alu_end, code->node[n].tex_end); + code->node[n].alu_end, code->node[n].tex_end, + code->node[n].flags); - if (code->tex.length) { + if (n > 0 || code->first_node_has_tex) { fprintf(stderr, " TEX:\n"); for (i = code->node[n].tex_offset; i <= code->node[n].tex_offset + code->node[n].tex_end; diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.h b/src/mesa/drivers/dri/r300/r300_fragprog.h index 7c1e210b044..b3a3cd2e04c 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog.h @@ -42,33 +42,6 @@ #include "r300_context.h" #include "radeon_program.h" -/* supported hw opcodes */ -#define PFS_OP_MAD 0 -#define PFS_OP_DP3 1 -#define PFS_OP_DP4 2 -#define PFS_OP_MIN 3 -#define PFS_OP_MAX 4 -#define PFS_OP_CMP 5 -#define PFS_OP_FRC 6 -#define PFS_OP_EX2 7 -#define PFS_OP_LG2 8 -#define PFS_OP_RCP 9 -#define PFS_OP_RSQ 10 -#define PFS_OP_REPL_ALPHA 11 -#define PFS_OP_CMPH 12 -#define MAX_PFS_OP 12 - -#define PFS_FLAG_SAT (1 << 0) -#define PFS_FLAG_ABS (1 << 1) - -#define ARG_NEG (1 << 5) -#define ARG_ABS (1 << 6) -#define ARG_MASK (127 << 0) -#define ARG_STRIDE 7 -#define SRC_CONST (1 << 5) -#define SRC_MASK (63 << 0) -#define SRC_STRIDE 6 - #define DRI_CONF_FP_OPTIMIZATION_SPEED 0 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 @@ -146,10 +119,9 @@ struct r300_fragment_program_compiler { r300ContextPtr r300; struct r300_fragment_program *fp; struct r300_fragment_program_code *code; - struct radeon_compiler compiler; + struct gl_program *program; }; -extern void r300FPTransformTextures(struct r300_fragment_program_compiler *compiler); extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c index d72b92832c9..9f0b7e35349 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog_emit.c @@ -36,2022 +36,308 @@ * \author Jerome Glisse <[email protected]> * * \todo FogOption - * - * \todo Verify results of opcodes for accuracy, I've only checked them in - * specific cases. */ -#include "glheader.h" -#include "macros.h" -#include "enums.h" -#include "shader/prog_instruction.h" -#include "shader/prog_parameter.h" -#include "shader/prog_print.h" - -#include "r300_context.h" #include "r300_fragprog.h" -#include "r300_reg.h" -#include "r300_state.h" - -/* Mapping Mesa registers to R300 temporaries */ -struct reg_acc { - int reg; /* Assigned hw temp */ - unsigned int refcount; /* Number of uses by mesa program */ -}; - -/** - * Describe the current lifetime information for an R300 temporary - */ -struct reg_lifetime { - /* Index of the first slot where this register is free in the sense - that it can be used as a new destination register. - This is -1 if the register has been assigned to a Mesa register - and the last access to the register has not yet been emitted */ - int free; - - /* Index of the first slot where this register is currently reserved. - This is used to stop e.g. a scalar operation from being moved - before the allocation time of a register that was first allocated - for a vector operation. */ - int reserved; - - /* Index of the first slot in which the register can be used as a - source without losing the value that is written by the last - emitted instruction that writes to the register */ - int vector_valid; - int scalar_valid; - - /* Index to the slot where the register was last read. - This is also the first slot in which the register may be written again */ - int vector_lastread; - int scalar_lastread; -}; - -/** - * Store usage information about an ALU instruction slot during the - * compilation of a fragment program. - */ -#define SLOT_SRC_VECTOR (1<<0) -#define SLOT_SRC_SCALAR (1<<3) -#define SLOT_SRC_BOTH (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR) -#define SLOT_OP_VECTOR (1<<16) -#define SLOT_OP_SCALAR (1<<17) -#define SLOT_OP_BOTH (SLOT_OP_VECTOR | SLOT_OP_SCALAR) - -struct r300_pfs_compile_slot { - /* Bitmask indicating which parts of the slot are used, using SLOT_ constants - defined above */ - unsigned int used; - - /* Selected sources */ - int vsrc[3]; - int ssrc[3]; -}; - -/** - * Store information during compilation of fragment programs. - */ -struct r300_pfs_compile_state { - struct r300_fragment_program_compiler *compiler; - - int nrslots; /* number of ALU slots used so far */ - - /* Track which (parts of) slots are already filled with instructions */ - struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST]; - - /* Track the validity of R300 temporaries */ - struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS]; - /* Used to map Mesa's inputs/temps onto hardware temps */ - int temp_in_use; - struct reg_acc temps[PFS_NUM_TEMP_REGS]; - struct reg_acc inputs[32]; /* don't actually need 32... */ +#include "radeon_program_pair.h" +#include "r300_fragprog_swizzle.h" +#include "r300_reg.h" - /* Track usage of hardware temps, for register allocation, - * indirection detection, etc. */ - GLuint used_in_node; - GLuint dest_in_node; -}; +#define PROG_CODE \ + struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \ + struct r300_fragment_program_code *code = c->code -/* - * Usefull macros and values - */ -#define ERROR(fmt, args...) do { \ +#define error(fmt, args...) do { \ fprintf(stderr, "%s::%s(): " fmt "\n", \ __FILE__, __FUNCTION__, ##args); \ - fp->error = GL_TRUE; \ } while(0) -#define PFS_INVAL 0xFFFFFFFF -#define COMPILE_STATE \ - struct r300_fragment_program *fp = cs->compiler->fp; \ - struct r300_fragment_program_code *code = cs->compiler->code; \ - (void)code; (void)fp - -#define SWIZZLE_XYZ 0 -#define SWIZZLE_XXX 1 -#define SWIZZLE_YYY 2 -#define SWIZZLE_ZZZ 3 -#define SWIZZLE_WWW 4 -#define SWIZZLE_YZX 5 -#define SWIZZLE_ZXY 6 -#define SWIZZLE_WZY 7 -#define SWIZZLE_111 8 -#define SWIZZLE_000 9 -#define SWIZZLE_HHH 10 - -#define swizzle(r, x, y, z, w) do_swizzle(cs, r, \ - ((SWIZZLE_##x<<0)| \ - (SWIZZLE_##y<<3)| \ - (SWIZZLE_##z<<6)| \ - (SWIZZLE_##w<<9)), \ - 0) - -#define REG_TYPE_INPUT 0 -#define REG_TYPE_OUTPUT 1 -#define REG_TYPE_TEMP 2 -#define REG_TYPE_CONST 3 - -#define REG_TYPE_SHIFT 0 -#define REG_INDEX_SHIFT 2 -#define REG_VSWZ_SHIFT 8 -#define REG_SSWZ_SHIFT 13 -#define REG_NEGV_SHIFT 18 -#define REG_NEGS_SHIFT 19 -#define REG_ABS_SHIFT 20 -#define REG_NO_USE_SHIFT 21 // Hack for refcounting -#define REG_VALID_SHIFT 22 // Does the register contain a defined value? -#define REG_BUILTIN_SHIFT 23 // Is it a builtin (like all zero/all one)? - -#define REG_TYPE_MASK (0x03 << REG_TYPE_SHIFT) -#define REG_INDEX_MASK (0x3F << REG_INDEX_SHIFT) -#define REG_VSWZ_MASK (0x1F << REG_VSWZ_SHIFT) -#define REG_SSWZ_MASK (0x1F << REG_SSWZ_SHIFT) -#define REG_NEGV_MASK (0x01 << REG_NEGV_SHIFT) -#define REG_NEGS_MASK (0x01 << REG_NEGS_SHIFT) -#define REG_ABS_MASK (0x01 << REG_ABS_SHIFT) -#define REG_NO_USE_MASK (0x01 << REG_NO_USE_SHIFT) -#define REG_VALID_MASK (0x01 << REG_VALID_SHIFT) -#define REG_BUILTIN_MASK (0x01 << REG_BUILTIN_SHIFT) - -#define REG(type, index, vswz, sswz, nouse, valid, builtin) \ - (((type << REG_TYPE_SHIFT) & REG_TYPE_MASK) | \ - ((index << REG_INDEX_SHIFT) & REG_INDEX_MASK) | \ - ((nouse << REG_NO_USE_SHIFT) & REG_NO_USE_MASK) | \ - ((valid << REG_VALID_SHIFT) & REG_VALID_MASK) | \ - ((builtin << REG_BUILTIN_SHIFT) & REG_BUILTIN_MASK) | \ - ((vswz << REG_VSWZ_SHIFT) & REG_VSWZ_MASK) | \ - ((sswz << REG_SSWZ_SHIFT) & REG_SSWZ_MASK)) -#define REG_GET_TYPE(reg) \ - ((reg & REG_TYPE_MASK) >> REG_TYPE_SHIFT) -#define REG_GET_INDEX(reg) \ - ((reg & REG_INDEX_MASK) >> REG_INDEX_SHIFT) -#define REG_GET_VSWZ(reg) \ - ((reg & REG_VSWZ_MASK) >> REG_VSWZ_SHIFT) -#define REG_GET_SSWZ(reg) \ - ((reg & REG_SSWZ_MASK) >> REG_SSWZ_SHIFT) -#define REG_GET_NO_USE(reg) \ - ((reg & REG_NO_USE_MASK) >> REG_NO_USE_SHIFT) -#define REG_GET_VALID(reg) \ - ((reg & REG_VALID_MASK) >> REG_VALID_SHIFT) -#define REG_GET_BUILTIN(reg) \ - ((reg & REG_BUILTIN_MASK) >> REG_BUILTIN_SHIFT) -#define REG_SET_TYPE(reg, type) \ - reg = ((reg & ~REG_TYPE_MASK) | \ - ((type << REG_TYPE_SHIFT) & REG_TYPE_MASK)) -#define REG_SET_INDEX(reg, index) \ - reg = ((reg & ~REG_INDEX_MASK) | \ - ((index << REG_INDEX_SHIFT) & REG_INDEX_MASK)) -#define REG_SET_VSWZ(reg, vswz) \ - reg = ((reg & ~REG_VSWZ_MASK) | \ - ((vswz << REG_VSWZ_SHIFT) & REG_VSWZ_MASK)) -#define REG_SET_SSWZ(reg, sswz) \ - reg = ((reg & ~REG_SSWZ_MASK) | \ - ((sswz << REG_SSWZ_SHIFT) & REG_SSWZ_MASK)) -#define REG_SET_NO_USE(reg, nouse) \ - reg = ((reg & ~REG_NO_USE_MASK) | \ - ((nouse << REG_NO_USE_SHIFT) & REG_NO_USE_MASK)) -#define REG_SET_VALID(reg, valid) \ - reg = ((reg & ~REG_VALID_MASK) | \ - ((valid << REG_VALID_SHIFT) & REG_VALID_MASK)) -#define REG_SET_BUILTIN(reg, builtin) \ - reg = ((reg & ~REG_BUILTIN_MASK) | \ - ((builtin << REG_BUILTIN_SHIFT) & REG_BUILTIN_MASK)) -#define REG_ABS(reg) \ - reg = (reg | REG_ABS_MASK) -#define REG_NEGV(reg) \ - reg = (reg | REG_NEGV_MASK) -#define REG_NEGS(reg) \ - reg = (reg | REG_NEGS_MASK) - -#define NOP_INST0 ( \ - (R300_ALU_OUTC_MAD) | \ - (R300_ALU_ARGC_ZERO << R300_ALU_ARG0C_SHIFT) | \ - (R300_ALU_ARGC_ZERO << R300_ALU_ARG1C_SHIFT) | \ - (R300_ALU_ARGC_ZERO << R300_ALU_ARG2C_SHIFT)) -#define NOP_INST1 ( \ - ((0 | SRC_CONST) << R300_ALU_SRC0C_SHIFT) | \ - ((0 | SRC_CONST) << R300_ALU_SRC1C_SHIFT) | \ - ((0 | SRC_CONST) << R300_ALU_SRC2C_SHIFT)) -#define NOP_INST2 ( \ - (R300_ALU_OUTA_MAD) | \ - (R300_ALU_ARGA_ZERO << R300_ALU_ARG0A_SHIFT) | \ - (R300_ALU_ARGA_ZERO << R300_ALU_ARG1A_SHIFT) | \ - (R300_ALU_ARGA_ZERO << R300_ALU_ARG2A_SHIFT)) -#define NOP_INST3 ( \ - ((0 | SRC_CONST) << R300_ALU_SRC0A_SHIFT) | \ - ((0 | SRC_CONST) << R300_ALU_SRC1A_SHIFT) | \ - ((0 | SRC_CONST) << R300_ALU_SRC2A_SHIFT)) - - -/* - * Datas structures for fragment program generation - */ - -/* description of r300 native hw instructions */ -static const struct { - const char *name; - int argc; - int v_op; - int s_op; -} r300_fpop[] = { - /* *INDENT-OFF* */ - {"MAD", 3, R300_ALU_OUTC_MAD, R300_ALU_OUTA_MAD}, - {"DP3", 2, R300_ALU_OUTC_DP3, R300_ALU_OUTA_DP4}, - {"DP4", 2, R300_ALU_OUTC_DP4, R300_ALU_OUTA_DP4}, - {"MIN", 2, R300_ALU_OUTC_MIN, R300_ALU_OUTA_MIN}, - {"MAX", 2, R300_ALU_OUTC_MAX, R300_ALU_OUTA_MAX}, - {"CMP", 3, R300_ALU_OUTC_CMP, R300_ALU_OUTA_CMP}, - {"FRC", 1, R300_ALU_OUTC_FRC, R300_ALU_OUTA_FRC}, - {"EX2", 1, R300_ALU_OUTC_REPL_ALPHA, R300_ALU_OUTA_EX2}, - {"LG2", 1, R300_ALU_OUTC_REPL_ALPHA, R300_ALU_OUTA_LG2}, - {"RCP", 1, R300_ALU_OUTC_REPL_ALPHA, R300_ALU_OUTA_RCP}, - {"RSQ", 1, R300_ALU_OUTC_REPL_ALPHA, R300_ALU_OUTA_RSQ}, - {"REPL_ALPHA", 1, R300_ALU_OUTC_REPL_ALPHA, PFS_INVAL}, - {"CMPH", 3, R300_ALU_OUTC_CMPH, PFS_INVAL}, - /* *INDENT-ON* */ -}; - -/* vector swizzles r300 can support natively, with a couple of - * cases we handle specially - * - * REG_VSWZ/REG_SSWZ is an index into this table - */ - -/* mapping from SWIZZLE_* to r300 native values for scalar insns */ -#define SWIZZLE_HALF 6 - -#define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, \ - SWIZZLE_##y, \ - SWIZZLE_##z, \ - SWIZZLE_ZERO)) -/* native swizzles */ -static const struct r300_pfs_swizzle { - GLuint hash; /* swizzle value this matches */ - GLuint base; /* base value for hw swizzle */ - GLuint stride; /* difference in base between arg0/1/2 */ - GLuint flags; -} v_swiz[] = { - /* *INDENT-OFF* */ - {MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4, SLOT_SRC_VECTOR}, - {MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4, SLOT_SRC_VECTOR}, - {MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4, SLOT_SRC_VECTOR}, - {MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4, SLOT_SRC_VECTOR}, - {MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1, SLOT_SRC_SCALAR}, - {MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1, SLOT_SRC_VECTOR}, - {MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1, SLOT_SRC_VECTOR}, - {MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1, SLOT_SRC_BOTH}, - {MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0, 0}, - {MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0, 0}, - {MAKE_SWZ3(HALF, HALF, HALF), R300_ALU_ARGC_HALF, 0, 0}, - {PFS_INVAL, 0, 0, 0}, - /* *INDENT-ON* */ -}; - -/* used during matching of non-native swizzles */ -#define SWZ_X_MASK (7 << 0) -#define SWZ_Y_MASK (7 << 3) -#define SWZ_Z_MASK (7 << 6) -#define SWZ_W_MASK (7 << 9) -static const struct { - GLuint hash; /* used to mask matching swizzle components */ - int mask; /* actual outmask */ - int count; /* count of components matched */ -} s_mask[] = { - /* *INDENT-OFF* */ - {SWZ_X_MASK | SWZ_Y_MASK | SWZ_Z_MASK, 1 | 2 | 4, 3}, - {SWZ_X_MASK | SWZ_Y_MASK, 1 | 2, 2}, - {SWZ_X_MASK | SWZ_Z_MASK, 1 | 4, 2}, - {SWZ_Y_MASK | SWZ_Z_MASK, 2 | 4, 2}, - {SWZ_X_MASK, 1, 1}, - {SWZ_Y_MASK, 2, 1}, - {SWZ_Z_MASK, 4, 1}, - {PFS_INVAL, PFS_INVAL, PFS_INVAL} - /* *INDENT-ON* */ -}; - -static const struct { - int base; /* hw value of swizzle */ - int stride; /* difference between SRC0/1/2 */ - GLuint flags; -} s_swiz[] = { - /* *INDENT-OFF* */ - {R300_ALU_ARGA_SRC0C_X, 3, SLOT_SRC_VECTOR}, - {R300_ALU_ARGA_SRC0C_Y, 3, SLOT_SRC_VECTOR}, - {R300_ALU_ARGA_SRC0C_Z, 3, SLOT_SRC_VECTOR}, - {R300_ALU_ARGA_SRC0A, 1, SLOT_SRC_SCALAR}, - {R300_ALU_ARGA_ZERO, 0, 0}, - {R300_ALU_ARGA_ONE, 0, 0}, - {R300_ALU_ARGA_HALF, 0, 0} - /* *INDENT-ON* */ -}; - -/* boiler-plate reg, for convenience */ -static const GLuint undef = REG(REG_TYPE_TEMP, - 0, - SWIZZLE_XYZ, - SWIZZLE_W, - GL_FALSE, - GL_FALSE, - GL_FALSE); - -/* constant one source */ -static const GLuint pfs_one = REG(REG_TYPE_CONST, - 0, - SWIZZLE_111, - SWIZZLE_ONE, - GL_FALSE, - GL_TRUE, - GL_TRUE); - -/* constant half source */ -static const GLuint pfs_half = REG(REG_TYPE_CONST, - 0, - SWIZZLE_HHH, - SWIZZLE_HALF, - GL_FALSE, - GL_TRUE, - GL_TRUE); - -/* constant zero source */ -static const GLuint pfs_zero = REG(REG_TYPE_CONST, - 0, - SWIZZLE_000, - SWIZZLE_ZERO, - GL_FALSE, - GL_TRUE, - GL_TRUE); - -/* - * Common functions prototypes - */ -static void emit_arith(struct r300_pfs_compile_state *cs, int op, - GLuint dest, int mask, - GLuint src0, GLuint src1, GLuint src2, int flags); - -/** - * Get an R300 temporary that can be written to in the given slot. - */ -static int get_hw_temp(struct r300_pfs_compile_state *cs, int slot) -{ - COMPILE_STATE; - int r; - - for (r = 0; r < PFS_NUM_TEMP_REGS; ++r) { - if (cs->hwtemps[r].free >= 0 && cs->hwtemps[r].free <= slot) - break; - } - - if (r >= PFS_NUM_TEMP_REGS) { - ERROR("Out of hardware temps\n"); - return 0; - } - // Reserved is used to avoid the following scenario: - // R300 temporary X is first assigned to Mesa temporary Y during vector ops - // R300 temporary X is then assigned to Mesa temporary Z for further vector ops - // Then scalar ops on Mesa temporary Z are emitted and move back in time - // to overwrite the value of temporary Y. - // End scenario. - cs->hwtemps[r].reserved = cs->hwtemps[r].free; - cs->hwtemps[r].free = -1; - - // Reset to some value that won't mess things up when the user - // tries to read from a temporary that hasn't been assigned a value yet. - // In the normal case, vector_valid and scalar_valid should be set to - // a sane value by the first emit that writes to this temporary. - cs->hwtemps[r].vector_valid = 0; - cs->hwtemps[r].scalar_valid = 0; - - if (r > code->max_temp_idx) - code->max_temp_idx = r; - - return r; -} - -/** - * Get an R300 temporary that will act as a TEX destination register. - */ -static int get_hw_temp_tex(struct r300_pfs_compile_state *cs) -{ - COMPILE_STATE; - int r; - - for (r = 0; r < PFS_NUM_TEMP_REGS; ++r) { - if (cs->used_in_node & (1 << r)) - continue; - - // Note: Be very careful here - if (cs->hwtemps[r].free >= 0 && cs->hwtemps[r].free <= 0) - break; - } - - if (r >= PFS_NUM_TEMP_REGS) - return get_hw_temp(cs, 0); /* Will cause an indirection */ - - cs->hwtemps[r].reserved = cs->hwtemps[r].free; - cs->hwtemps[r].free = -1; - - // Reset to some value that won't mess things up when the user - // tries to read from a temporary that hasn't been assigned a value yet. - // In the normal case, vector_valid and scalar_valid should be set to - // a sane value by the first emit that writes to this temporary. - cs->hwtemps[r].vector_valid = cs->nrslots; - cs->hwtemps[r].scalar_valid = cs->nrslots; - - if (r > code->max_temp_idx) - code->max_temp_idx = r; - - return r; -} - -/** - * Mark the given hardware register as free. - */ -static void free_hw_temp(struct r300_pfs_compile_state *cs, int idx) -{ - // Be very careful here. Consider sequences like - // MAD r0, r1,r2,r3 - // TEX r4, ... - // The TEX instruction may be moved in front of the MAD instruction - // due to the way nodes work. We don't want to alias r1 and r4 in - // this case. - // I'm certain the register allocation could be further sanitized, - // but it's tricky because of stuff that can happen inside emit_tex - // and emit_arith. - cs->hwtemps[idx].free = cs->nrslots + 1; -} - -/** - * Create a new Mesa temporary register. - */ -static GLuint get_temp_reg(struct r300_pfs_compile_state *cs) -{ - COMPILE_STATE; - GLuint r = undef; - GLuint index; - - index = ffs(~cs->temp_in_use); - if (!index) { - ERROR("Out of program temps\n"); - return r; - } - - cs->temp_in_use |= (1 << --index); - cs->temps[index].refcount = 0xFFFFFFFF; - cs->temps[index].reg = -1; - - REG_SET_TYPE(r, REG_TYPE_TEMP); - REG_SET_INDEX(r, index); - REG_SET_VALID(r, GL_TRUE); - return r; -} - -/** - * Free a Mesa temporary and the associated R300 temporary. - */ -static void free_temp(struct r300_pfs_compile_state *cs, GLuint r) -{ - GLuint index = REG_GET_INDEX(r); - - if (!(cs->temp_in_use & (1 << index))) - return; - - if (REG_GET_TYPE(r) == REG_TYPE_TEMP) { - free_hw_temp(cs, cs->temps[index].reg); - cs->temps[index].reg = -1; - cs->temp_in_use &= ~(1 << index); - } else if (REG_GET_TYPE(r) == REG_TYPE_INPUT) { - free_hw_temp(cs, cs->inputs[index].reg); - cs->inputs[index].reg = -1; - } -} -/** - * Emit a hardware constant/parameter. - * - * \p cp Stable pointer to an array of 4 floats. - * The pointer must be stable in the sense that it remains to be valid - * and hold the contents of the constant/parameter throughout the lifetime - * of the fragment program (actually, up until the next time the fragment - * program is translated). - */ -static GLuint emit_const4fv(struct r300_pfs_compile_state *cs, - const GLfloat * cp) +static GLboolean emit_const(void* data, GLuint file, GLuint index, GLuint *hwindex) { - COMPILE_STATE; - GLuint reg = undef; - int index; + PROG_CODE; - for (index = 0; index < code->const_nr; ++index) { - if (code->constant[index] == cp) + for (*hwindex = 0; *hwindex < code->const_nr; ++*hwindex) { + if (code->constant[*hwindex].File == file && + code->constant[*hwindex].Index == index) break; } - if (index >= code->const_nr) { - if (index >= PFS_NUM_CONST_REGS) { - ERROR("Out of hw constants!\n"); - return reg; + if (*hwindex >= code->const_nr) { + if (*hwindex >= PFS_NUM_CONST_REGS) { + error("Out of hw constants!\n"); + return GL_FALSE; } code->const_nr++; - code->constant[index] = cp; + code->constant[*hwindex].File = file; + code->constant[*hwindex].Index = index; } - REG_SET_TYPE(reg, REG_TYPE_CONST); - REG_SET_INDEX(reg, index); - REG_SET_VALID(reg, GL_TRUE); - return reg; + return GL_TRUE; } -static INLINE GLuint negate(GLuint r) -{ - REG_NEGS(r); - REG_NEGV(r); - return r; -} -/* Hack, to prevent clobbering sources used multiple times when - * emulating non-native instructions +/** + * Mark a temporary register as used. */ -static INLINE GLuint keep(GLuint r) -{ - REG_SET_NO_USE(r, GL_TRUE); - return r; -} - -static INLINE GLuint absolute(GLuint r) -{ - REG_ABS(r); - return r; -} - -static int swz_native(struct r300_pfs_compile_state *cs, - GLuint src, GLuint * r, GLuint arbneg) -{ - COMPILE_STATE; - - /* Native swizzle, handle negation */ - src = (src & ~REG_NEGS_MASK) | (((arbneg >> 3) & 1) << REG_NEGS_SHIFT); - - if ((arbneg & 0x7) == 0x0) { - src = src & ~REG_NEGV_MASK; - *r = src; - } else if ((arbneg & 0x7) == 0x7) { - src |= REG_NEGV_MASK; - *r = src; - } else { - if (!REG_GET_VALID(*r)) - *r = get_temp_reg(cs); - src |= REG_NEGV_MASK; - emit_arith(cs, - PFS_OP_MAD, - *r, arbneg & 0x7, keep(src), pfs_one, pfs_zero, 0); - src = src & ~REG_NEGV_MASK; - emit_arith(cs, - PFS_OP_MAD, - *r, - (arbneg ^ 0x7) | WRITEMASK_W, - src, pfs_one, pfs_zero, 0); - } - - return 3; -} - -static int swz_emit_partial(struct r300_pfs_compile_state *cs, - GLuint src, - GLuint * r, int mask, int mc, GLuint arbneg) -{ - COMPILE_STATE; - GLuint tmp; - GLuint wmask = 0; - - if (!REG_GET_VALID(*r)) - *r = get_temp_reg(cs); - - /* A partial match, VSWZ/mask define what parts of the - * desired swizzle we match - */ - if (mc + s_mask[mask].count == 3) { - wmask = WRITEMASK_W; - src |= ((arbneg >> 3) & 1) << REG_NEGS_SHIFT; - } - - tmp = arbneg & s_mask[mask].mask; - if (tmp) { - tmp = tmp ^ s_mask[mask].mask; - if (tmp) { - emit_arith(cs, - PFS_OP_MAD, - *r, - arbneg & s_mask[mask].mask, - keep(src) | REG_NEGV_MASK, - pfs_one, pfs_zero, 0); - if (!wmask) { - REG_SET_NO_USE(src, GL_TRUE); - } else { - REG_SET_NO_USE(src, GL_FALSE); - } - emit_arith(cs, - PFS_OP_MAD, - *r, tmp | wmask, src, pfs_one, pfs_zero, 0); - } else { - if (!wmask) { - REG_SET_NO_USE(src, GL_TRUE); - } else { - REG_SET_NO_USE(src, GL_FALSE); - } - emit_arith(cs, - PFS_OP_MAD, - *r, - (arbneg & s_mask[mask].mask) | wmask, - src | REG_NEGV_MASK, pfs_one, pfs_zero, 0); - } - } else { - if (!wmask) { - REG_SET_NO_USE(src, GL_TRUE); - } else { - REG_SET_NO_USE(src, GL_FALSE); - } - emit_arith(cs, PFS_OP_MAD, - *r, - s_mask[mask].mask | wmask, - src, pfs_one, pfs_zero, 0); - } - - return s_mask[mask].count; -} - -static GLuint do_swizzle(struct r300_pfs_compile_state *cs, - GLuint src, GLuint arbswz, GLuint arbneg) +static void use_temporary(struct r300_fragment_program_code *code, GLuint index) { - COMPILE_STATE; - GLuint r = undef; - GLuint vswz; - int c_mask = 0; - int v_match = 0; - - /* If swizzling from something without an XYZW native swizzle, - * emit result to a temp, and do new swizzle from the temp. - */ -#if 0 - if (REG_GET_VSWZ(src) != SWIZZLE_XYZ || REG_GET_SSWZ(src) != SWIZZLE_W) { - GLuint temp = get_temp_reg(fp); - emit_arith(fp, - PFS_OP_MAD, - temp, WRITEMASK_XYZW, src, pfs_one, pfs_zero, 0); - src = temp; - } -#endif - - if (REG_GET_VSWZ(src) != SWIZZLE_XYZ || REG_GET_SSWZ(src) != SWIZZLE_W) { - GLuint vsrcswz = - (v_swiz[REG_GET_VSWZ(src)]. - hash & (SWZ_X_MASK | SWZ_Y_MASK | SWZ_Z_MASK)) | - REG_GET_SSWZ(src) << 9; - GLint i; - - GLuint newswz = 0; - GLuint offset; - for (i = 0; i < 4; ++i) { - offset = GET_SWZ(arbswz, i); - - newswz |= - (offset <= 3) ? GET_SWZ(vsrcswz, - offset) << i * - 3 : offset << i * 3; - } - - arbswz = newswz & (SWZ_X_MASK | SWZ_Y_MASK | SWZ_Z_MASK); - REG_SET_SSWZ(src, GET_SWZ(newswz, 3)); - } else { - /* set scalar swizzling */ - REG_SET_SSWZ(src, GET_SWZ(arbswz, 3)); - - } - do { - vswz = REG_GET_VSWZ(src); - do { - int chash; - - REG_SET_VSWZ(src, vswz); - chash = v_swiz[REG_GET_VSWZ(src)].hash & - s_mask[c_mask].hash; - - if (chash == (arbswz & s_mask[c_mask].hash)) { - if (s_mask[c_mask].count == 3) { - v_match += swz_native(cs, - src, &r, arbneg); - } else { - v_match += swz_emit_partial(cs, - src, - &r, - c_mask, - v_match, - arbneg); - } - - if (v_match == 3) - return r; - - /* Fill with something invalid.. all 0's was - * wrong before, matched SWIZZLE_X. So all - * 1's will be okay for now - */ - arbswz |= (PFS_INVAL & s_mask[c_mask].hash); - } - } while (v_swiz[++vswz].hash != PFS_INVAL); - REG_SET_VSWZ(src, SWIZZLE_XYZ); - } while (s_mask[++c_mask].hash != PFS_INVAL); - - ERROR("should NEVER get here\n"); - return r; + if (index > code->max_temp_idx) + code->max_temp_idx = index; } -static GLuint t_src(struct r300_pfs_compile_state *cs, - struct prog_src_register fpsrc) -{ - COMPILE_STATE; - GLuint r = undef; - - switch (fpsrc.File) { - case PROGRAM_TEMPORARY: - REG_SET_INDEX(r, fpsrc.Index); - REG_SET_VALID(r, GL_TRUE); - REG_SET_TYPE(r, REG_TYPE_TEMP); - break; - case PROGRAM_INPUT: - REG_SET_INDEX(r, fpsrc.Index); - REG_SET_VALID(r, GL_TRUE); - REG_SET_TYPE(r, REG_TYPE_INPUT); - break; - case PROGRAM_LOCAL_PARAM: - r = emit_const4fv(cs, - fp->mesa_program.Base.LocalParams[fpsrc. - Index]); - break; - case PROGRAM_ENV_PARAM: - r = emit_const4fv(cs, - cs->compiler->r300->radeon.glCtx->FragmentProgram.Parameters[fpsrc.Index]); - break; - case PROGRAM_STATE_VAR: - case PROGRAM_NAMED_PARAM: - case PROGRAM_CONSTANT: - r = emit_const4fv(cs, - fp->mesa_program.Base.Parameters-> - ParameterValues[fpsrc.Index]); - break; - case PROGRAM_BUILTIN: - switch(fpsrc.Swizzle) { - case SWIZZLE_1111: r = pfs_one; break; - case SWIZZLE_0000: r = pfs_zero; break; - default: - ERROR("bad PROGRAM_BUILTIN swizzle %u\n", fpsrc.Swizzle); - break; - } - break; - default: - ERROR("unknown SrcReg->File %x\n", fpsrc.File); - return r; - } - - /* no point swizzling ONE/ZERO/HALF constants... */ - if (REG_GET_VSWZ(r) < SWIZZLE_111 || REG_GET_SSWZ(r) < SWIZZLE_ZERO) - r = do_swizzle(cs, r, fpsrc.Swizzle, fpsrc.NegateBase); - if (fpsrc.Abs) - r = absolute(r); - if (fpsrc.NegateAbs) - r = negate(r); - return r; -} -static GLuint t_scalar_src(struct r300_pfs_compile_state *cs, - struct prog_src_register fpsrc) +static GLuint translate_rgb_opcode(GLuint opcode) { - struct prog_src_register src = fpsrc; - int sc = GET_SWZ(fpsrc.Swizzle, 0); /* X */ - - src.Swizzle = ((sc << 0) | (sc << 3) | (sc << 6) | (sc << 9)); - - return t_src(cs, src); -} - -static GLuint t_dst(struct r300_pfs_compile_state *cs, - struct prog_dst_register dest) -{ - COMPILE_STATE; - GLuint r = undef; - - switch (dest.File) { - case PROGRAM_TEMPORARY: - REG_SET_INDEX(r, dest.Index); - REG_SET_VALID(r, GL_TRUE); - REG_SET_TYPE(r, REG_TYPE_TEMP); - return r; - case PROGRAM_OUTPUT: - REG_SET_TYPE(r, REG_TYPE_OUTPUT); - switch (dest.Index) { - case FRAG_RESULT_COLR: - case FRAG_RESULT_DEPR: - REG_SET_INDEX(r, dest.Index); - REG_SET_VALID(r, GL_TRUE); - return r; - default: - ERROR("Bad DstReg->Index 0x%x\n", dest.Index); - return r; - } + switch(opcode) { + case OPCODE_CMP: return R300_ALU_OUTC_CMP; + case OPCODE_DP3: return R300_ALU_OUTC_DP3; + case OPCODE_DP4: return R300_ALU_OUTC_DP4; + case OPCODE_FRC: return R300_ALU_OUTC_FRC; default: - ERROR("Bad DstReg->File 0x%x\n", dest.File); - return r; + error("translate_rgb_opcode(%i): Unknown opcode", opcode); + /* fall through */ + case OPCODE_NOP: + /* fall through */ + case OPCODE_MAD: return R300_ALU_OUTC_MAD; + case OPCODE_MAX: return R300_ALU_OUTC_MAX; + case OPCODE_MIN: return R300_ALU_OUTC_MIN; + case OPCODE_REPL_ALPHA: return R300_ALU_OUTC_REPL_ALPHA; } } -static int t_hw_src(struct r300_pfs_compile_state *cs, GLuint src, GLboolean tex) +static GLuint translate_alpha_opcode(GLuint opcode) { - COMPILE_STATE; - int idx; - int index = REG_GET_INDEX(src); - - switch (REG_GET_TYPE(src)) { - case REG_TYPE_TEMP: - /* NOTE: if reg==-1 here, a source is being read that - * hasn't been written to. Undefined results. - */ - if (cs->temps[index].reg == -1) - cs->temps[index].reg = get_hw_temp(cs, cs->nrslots); - - idx = cs->temps[index].reg; - - if (!REG_GET_NO_USE(src) && (--cs->temps[index].refcount == 0)) - free_temp(cs, src); - break; - case REG_TYPE_INPUT: - idx = cs->inputs[index].reg; - - if (!REG_GET_NO_USE(src) && (--cs->inputs[index].refcount == 0)) - free_hw_temp(cs, cs->inputs[index].reg); - break; - case REG_TYPE_CONST: - return (index | SRC_CONST); - default: - ERROR("Invalid type for source reg\n"); - return (0 | SRC_CONST); - } - - if (!tex) - cs->used_in_node |= (1 << idx); - - return idx; -} - -static int t_hw_dst(struct r300_pfs_compile_state *cs, - GLuint dest, GLboolean tex, int slot) -{ - COMPILE_STATE; - int idx; - GLuint index = REG_GET_INDEX(dest); - assert(REG_GET_VALID(dest)); - - switch (REG_GET_TYPE(dest)) { - case REG_TYPE_TEMP: - if (cs->temps[REG_GET_INDEX(dest)].reg == -1) { - if (!tex) { - cs->temps[index].reg = get_hw_temp(cs, slot); - } else { - cs->temps[index].reg = get_hw_temp_tex(cs); - } - } - idx = cs->temps[index].reg; - - if (!REG_GET_NO_USE(dest) && (--cs->temps[index].refcount == 0)) - free_temp(cs, dest); - - cs->dest_in_node |= (1 << idx); - cs->used_in_node |= (1 << idx); - break; - case REG_TYPE_OUTPUT: - switch (index) { - case FRAG_RESULT_COLR: - code->node[code->cur_node].flags |= R300_RGBA_OUT; - break; - case FRAG_RESULT_DEPR: - fp->WritesDepth = GL_TRUE; - code->node[code->cur_node].flags |= R300_W_OUT; - break; - } - return index; - break; + switch(opcode) { + case OPCODE_CMP: return R300_ALU_OUTA_CMP; + case OPCODE_DP3: return R300_ALU_OUTA_DP4; + case OPCODE_DP4: return R300_ALU_OUTA_DP4; + case OPCODE_EX2: return R300_ALU_OUTA_EX2; + case OPCODE_FRC: return R300_ALU_OUTA_FRC; + case OPCODE_LG2: return R300_ALU_OUTA_LG2; default: - ERROR("invalid dest reg type %d\n", REG_GET_TYPE(dest)); - return 0; - } - - return idx; -} - -static void emit_nop(struct r300_pfs_compile_state *cs) -{ - COMPILE_STATE; - - if (cs->nrslots >= PFS_MAX_ALU_INST) { - ERROR("Out of ALU instruction slots\n"); - return; + error("translate_rgb_opcode(%i): Unknown opcode", opcode); + /* fall through */ + case OPCODE_NOP: + /* fall through */ + case OPCODE_MAD: return R300_ALU_OUTA_MAD; + case OPCODE_MAX: return R300_ALU_OUTA_MAX; + case OPCODE_MIN: return R300_ALU_OUTA_MIN; + case OPCODE_RCP: return R300_ALU_OUTA_RCP; + case OPCODE_RSQ: return R300_ALU_OUTA_RSQ; } - - code->alu.inst[cs->nrslots].inst0 = NOP_INST0; - code->alu.inst[cs->nrslots].inst1 = NOP_INST1; - code->alu.inst[cs->nrslots].inst2 = NOP_INST2; - code->alu.inst[cs->nrslots].inst3 = NOP_INST3; - cs->nrslots++; -} - -static void emit_tex(struct r300_pfs_compile_state *cs, - struct prog_instruction *fpi, int opcode) -{ - COMPILE_STATE; - GLuint coord = t_src(cs, fpi->SrcReg[0]); - GLuint dest = undef; - GLuint din, uin; - int unit = fpi->TexSrcUnit; - int hwsrc, hwdest; - - /* Ensure correct node indirection */ - uin = cs->used_in_node; - din = cs->dest_in_node; - - /* Resolve source/dest to hardware registers */ - hwsrc = t_hw_src(cs, coord, GL_TRUE); - - if (opcode != R300_TEX_OP_KIL) { - dest = t_dst(cs, fpi->DstReg); - - hwdest = - t_hw_dst(cs, dest, GL_TRUE, - code->node[code->cur_node].alu_offset); - - /* Use a temp that hasn't been used in this node, rather - * than causing an indirection - */ - if (uin & (1 << hwdest)) { - free_hw_temp(cs, hwdest); - hwdest = get_hw_temp_tex(cs); - cs->temps[REG_GET_INDEX(dest)].reg = hwdest; - } - } else { - hwdest = 0; - unit = 0; - } - - /* Indirection if source has been written in this node, or if the - * dest has been read/written in this node - */ - if ((REG_GET_TYPE(coord) != REG_TYPE_CONST && - (din & (1 << hwsrc))) || (uin & (1 << hwdest))) { - - /* Finish off current node */ - if (code->node[code->cur_node].alu_offset == cs->nrslots) - emit_nop(cs); - - code->node[code->cur_node].alu_end = - cs->nrslots - code->node[code->cur_node].alu_offset - 1; - assert(code->node[code->cur_node].alu_end >= 0); - - if (++code->cur_node >= PFS_MAX_TEX_INDIRECT) { - ERROR("too many levels of texture indirection\n"); - return; - } - - /* Start new node */ - code->node[code->cur_node].tex_offset = code->tex.length; - code->node[code->cur_node].alu_offset = cs->nrslots; - code->node[code->cur_node].tex_end = -1; - code->node[code->cur_node].alu_end = -1; - code->node[code->cur_node].flags = 0; - cs->used_in_node = 0; - cs->dest_in_node = 0; - } - - if (code->cur_node == 0) - code->first_node_has_tex = 1; - - code->tex.inst[code->tex.length++] = 0 | (hwsrc << R300_SRC_ADDR_SHIFT) - | (hwdest << R300_DST_ADDR_SHIFT) - | (unit << R300_TEX_ID_SHIFT) - | (opcode << R300_TEX_INST_SHIFT); - - cs->dest_in_node |= (1 << hwdest); - if (REG_GET_TYPE(coord) != REG_TYPE_CONST) - cs->used_in_node |= (1 << hwsrc); - - code->node[code->cur_node].tex_end++; } /** - * Returns the first slot where we could possibly allow writing to dest, - * according to register allocation. + * Emit one paired ALU instruction. */ -static int get_earliest_allowed_write(struct r300_pfs_compile_state *cs, - GLuint dest, int mask) +static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst) { - COMPILE_STATE; - int idx; - int pos; - GLuint index = REG_GET_INDEX(dest); - assert(REG_GET_VALID(dest)); + PROG_CODE; - switch (REG_GET_TYPE(dest)) { - case REG_TYPE_TEMP: - if (cs->temps[index].reg == -1) - return 0; - - idx = cs->temps[index].reg; - break; - case REG_TYPE_OUTPUT: - return 0; - default: - ERROR("invalid dest reg type %d\n", REG_GET_TYPE(dest)); - return 0; - } - - pos = cs->hwtemps[idx].reserved; - if (mask & WRITEMASK_XYZ) { - if (pos < cs->hwtemps[idx].vector_lastread) - pos = cs->hwtemps[idx].vector_lastread; - } - if (mask & WRITEMASK_W) { - if (pos < cs->hwtemps[idx].scalar_lastread) - pos = cs->hwtemps[idx].scalar_lastread; + if (code->alu.length >= PFS_MAX_ALU_INST) { + error("Too many ALU instructions"); + return GL_FALSE; } - return pos; -} - -/** - * Allocates a slot for an ALU instruction that can consist of - * a vertex part or a scalar part or both. - * - * Sources from src (src[0] to src[argc-1]) are added to the slot in the - * appropriate position (vector and/or scalar), and their positions are - * recorded in the srcpos array. - * - * This function emits instruction code for the source fetch and the - * argument selection. It does not emit instruction code for the - * opcode or the destination selection. - * - * @return the index of the slot - */ -static int find_and_prepare_slot(struct r300_pfs_compile_state *cs, - GLboolean emit_vop, - GLboolean emit_sop, - int argc, GLuint * src, GLuint dest, int mask) -{ - COMPILE_STATE; - int hwsrc[3]; - int srcpos[3]; - unsigned int used; - int tempused; - int tempvsrc[3]; - int tempssrc[3]; - int pos; - int regnr; - int i, j; + int ip = code->alu.length++; + int j; + code->node[code->cur_node].alu_end++; - // Determine instruction slots, whether sources are required on - // vector or scalar side, and the smallest slot number where - // all source registers are available - used = 0; - if (emit_vop) - used |= SLOT_OP_VECTOR; - if (emit_sop) - used |= SLOT_OP_SCALAR; + code->alu.inst[ip].inst0 = translate_rgb_opcode(inst->RGB.Opcode); + code->alu.inst[ip].inst2 = translate_alpha_opcode(inst->Alpha.Opcode); - pos = get_earliest_allowed_write(cs, dest, mask); + for(j = 0; j < 3; ++j) { + GLuint src = inst->RGB.Src[j].Index | (inst->RGB.Src[j].Constant << 5); + if (!inst->RGB.Src[j].Constant) + use_temporary(code, inst->RGB.Src[j].Index); + code->alu.inst[ip].inst1 |= src << (6*j); - if (code->node[code->cur_node].alu_offset > pos) - pos = code->node[code->cur_node].alu_offset; - for (i = 0; i < argc; ++i) { - if (!REG_GET_BUILTIN(src[i])) { - if (emit_vop) - used |= v_swiz[REG_GET_VSWZ(src[i])].flags << i; - if (emit_sop) - used |= s_swiz[REG_GET_SSWZ(src[i])].flags << i; - } + src = inst->Alpha.Src[j].Index | (inst->Alpha.Src[j].Constant << 5); + if (!inst->Alpha.Src[j].Constant) + use_temporary(code, inst->Alpha.Src[j].Index); + code->alu.inst[ip].inst3 |= src << (6*j); - hwsrc[i] = t_hw_src(cs, src[i], GL_FALSE); /* Note: sideeffects wrt refcounting! */ - regnr = hwsrc[i] & 31; + GLuint arg = r300FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle); + arg |= inst->RGB.Arg[j].Abs << 6; + arg |= inst->RGB.Arg[j].Negate << 5; + code->alu.inst[ip].inst0 |= arg << (7*j); - if (REG_GET_TYPE(src[i]) == REG_TYPE_TEMP) { - if (used & (SLOT_SRC_VECTOR << i)) { - if (cs->hwtemps[regnr].vector_valid > pos) - pos = cs->hwtemps[regnr].vector_valid; - } - if (used & (SLOT_SRC_SCALAR << i)) { - if (cs->hwtemps[regnr].scalar_valid > pos) - pos = cs->hwtemps[regnr].scalar_valid; - } - } + arg = r300FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle); + arg |= inst->Alpha.Arg[j].Abs << 6; + arg |= inst->Alpha.Arg[j].Negate << 5; + code->alu.inst[ip].inst2 |= arg << (7*j); } - // Find a slot that fits - for (;; ++pos) { - if (cs->slot[pos].used & used & SLOT_OP_BOTH) - continue; - - if (pos >= cs->nrslots) { - if (cs->nrslots >= PFS_MAX_ALU_INST) { - ERROR("Out of ALU instruction slots\n"); - return -1; - } - - code->alu.inst[pos].inst0 = NOP_INST0; - code->alu.inst[pos].inst1 = NOP_INST1; - code->alu.inst[pos].inst2 = NOP_INST2; - code->alu.inst[pos].inst3 = NOP_INST3; - - cs->nrslots++; - } - // Note: When we need both parts (vector and scalar) of a source, - // we always try to put them into the same position. This makes the - // code easier to read, and it is optimal (i.e. one doesn't gain - // anything by splitting the parts). - // It also avoids headaches with swizzles that access both parts (i.e WXY) - tempused = cs->slot[pos].used; - for (i = 0; i < 3; ++i) { - tempvsrc[i] = cs->slot[pos].vsrc[i]; - tempssrc[i] = cs->slot[pos].ssrc[i]; - } - - for (i = 0; i < argc; ++i) { - int flags = (used >> i) & SLOT_SRC_BOTH; - - if (!flags) { - srcpos[i] = 0; - continue; - } - - for (j = 0; j < 3; ++j) { - if ((tempused >> j) & flags & SLOT_SRC_VECTOR) { - if (tempvsrc[j] != hwsrc[i]) - continue; - } - - if ((tempused >> j) & flags & SLOT_SRC_SCALAR) { - if (tempssrc[j] != hwsrc[i]) - continue; - } - - break; - } + if (inst->RGB.Saturate) + code->alu.inst[ip].inst0 |= R300_ALU_OUTC_CLAMP; + if (inst->Alpha.Saturate) + code->alu.inst[ip].inst2 |= R300_ALU_OUTA_CLAMP; - if (j == 3) - break; - - srcpos[i] = j; - tempused |= flags << j; - if (flags & SLOT_SRC_VECTOR) - tempvsrc[j] = hwsrc[i]; - if (flags & SLOT_SRC_SCALAR) - tempssrc[j] = hwsrc[i]; - } - - if (i == argc) - break; + if (inst->RGB.WriteMask) { + use_temporary(code, inst->RGB.DestIndex); + code->alu.inst[ip].inst1 |= + (inst->RGB.DestIndex << R300_ALU_DSTC_SHIFT) | + (inst->RGB.WriteMask << R300_ALU_DSTC_REG_MASK_SHIFT); } - - // Found a slot, reserve it - cs->slot[pos].used = tempused | (used & SLOT_OP_BOTH); - for (i = 0; i < 3; ++i) { - cs->slot[pos].vsrc[i] = tempvsrc[i]; - cs->slot[pos].ssrc[i] = tempssrc[i]; + if (inst->RGB.OutputWriteMask) { + code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R300_ALU_DSTC_OUTPUT_MASK_SHIFT); + code->node[code->cur_node].flags |= R300_RGBA_OUT; } - for (i = 0; i < argc; ++i) { - if (REG_GET_TYPE(src[i]) == REG_TYPE_TEMP) { - int regnr = hwsrc[i] & 31; - - if (used & (SLOT_SRC_VECTOR << i)) { - if (cs->hwtemps[regnr].vector_lastread < pos) - cs->hwtemps[regnr].vector_lastread = - pos; - } - if (used & (SLOT_SRC_SCALAR << i)) { - if (cs->hwtemps[regnr].scalar_lastread < pos) - cs->hwtemps[regnr].scalar_lastread = - pos; - } - } + if (inst->Alpha.WriteMask) { + use_temporary(code, inst->Alpha.DestIndex); + code->alu.inst[ip].inst3 |= + (inst->Alpha.DestIndex << R300_ALU_DSTA_SHIFT) | + R300_ALU_DSTA_REG; } - - // Emit the source fetch code - code->alu.inst[pos].inst1 &= ~R300_ALU_SRC_MASK; - code->alu.inst[pos].inst1 |= - ((cs->slot[pos].vsrc[0] << R300_ALU_SRC0C_SHIFT) | - (cs->slot[pos].vsrc[1] << R300_ALU_SRC1C_SHIFT) | - (cs->slot[pos].vsrc[2] << R300_ALU_SRC2C_SHIFT)); - - code->alu.inst[pos].inst3 &= ~R300_ALU_SRC_MASK; - code->alu.inst[pos].inst3 |= - ((cs->slot[pos].ssrc[0] << R300_ALU_SRC0A_SHIFT) | - (cs->slot[pos].ssrc[1] << R300_ALU_SRC1A_SHIFT) | - (cs->slot[pos].ssrc[2] << R300_ALU_SRC2A_SHIFT)); - - // Emit the argument selection code - if (emit_vop) { - int swz[3]; - - for (i = 0; i < 3; ++i) { - if (i < argc) { - swz[i] = (v_swiz[REG_GET_VSWZ(src[i])].base + - (srcpos[i] * - v_swiz[REG_GET_VSWZ(src[i])]. - stride)) | ((src[i] & REG_NEGV_MASK) - ? ARG_NEG : 0) | ((src[i] - & - REG_ABS_MASK) - ? - ARG_ABS - : 0); - } else { - swz[i] = R300_ALU_ARGC_ZERO; - } - } - - code->alu.inst[pos].inst0 &= - ~(R300_ALU_ARG0C_MASK | R300_ALU_ARG1C_MASK | - R300_ALU_ARG2C_MASK); - code->alu.inst[pos].inst0 |= - (swz[0] << R300_ALU_ARG0C_SHIFT) | (swz[1] << - R300_ALU_ARG1C_SHIFT) - | (swz[2] << R300_ALU_ARG2C_SHIFT); + if (inst->Alpha.OutputWriteMask) { + code->alu.inst[ip].inst3 |= R300_ALU_DSTA_OUTPUT; + code->node[code->cur_node].flags |= R300_RGBA_OUT; } - - if (emit_sop) { - int swz[3]; - - for (i = 0; i < 3; ++i) { - if (i < argc) { - swz[i] = (s_swiz[REG_GET_SSWZ(src[i])].base + - (srcpos[i] * - s_swiz[REG_GET_SSWZ(src[i])]. - stride)) | ((src[i] & REG_NEGS_MASK) - ? ARG_NEG : 0) | ((src[i] - & - REG_ABS_MASK) - ? - ARG_ABS - : 0); - } else { - swz[i] = R300_ALU_ARGA_ZERO; - } - } - - code->alu.inst[pos].inst2 &= - ~(R300_ALU_ARG0A_MASK | R300_ALU_ARG1A_MASK | - R300_ALU_ARG2A_MASK); - code->alu.inst[pos].inst2 |= - (swz[0] << R300_ALU_ARG0A_SHIFT) | (swz[1] << - R300_ALU_ARG1A_SHIFT) - | (swz[2] << R300_ALU_ARG2A_SHIFT); + if (inst->Alpha.DepthWriteMask) { + code->alu.inst[ip].inst3 |= R300_ALU_DSTA_DEPTH; + code->node[code->cur_node].flags |= R300_W_OUT; + c->fp->WritesDepth = GL_TRUE; } - return pos; + return GL_TRUE; } + /** - * Append an ALU instruction to the instruction list. + * Finish the current node without advancing to the next one. */ -static void emit_arith(struct r300_pfs_compile_state *cs, - int op, - GLuint dest, - int mask, - GLuint src0, GLuint src1, GLuint src2, int flags) +static GLboolean finish_node(struct r300_fragment_program_compiler *c) { - COMPILE_STATE; - GLuint src[3] = { src0, src1, src2 }; - int hwdest; - GLboolean emit_vop, emit_sop; - int vop, sop, argc; - int pos; - - vop = r300_fpop[op].v_op; - sop = r300_fpop[op].s_op; - argc = r300_fpop[op].argc; + struct r300_fragment_program_code *code = c->code; + struct r300_fragment_program_node *node = &code->node[code->cur_node]; - if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT && - REG_GET_INDEX(dest) == FRAG_RESULT_DEPR) { - if (mask & WRITEMASK_Z) { - mask = WRITEMASK_W; - } else { - return; - } + if (node->alu_end < 0) { + /* Generate a single NOP for this node */ + struct radeon_pair_instruction inst; + _mesa_bzero(&inst, sizeof(inst)); + if (!emit_alu(c, &inst)) + return GL_FALSE; } - emit_vop = GL_FALSE; - emit_sop = GL_FALSE; - if ((mask & WRITEMASK_XYZ) || vop == R300_ALU_OUTC_DP3) - emit_vop = GL_TRUE; - if ((mask & WRITEMASK_W) || vop == R300_ALU_OUTC_REPL_ALPHA) - emit_sop = GL_TRUE; - - pos = - find_and_prepare_slot(cs, emit_vop, emit_sop, argc, src, dest, - mask); - if (pos < 0) - return; - - hwdest = t_hw_dst(cs, dest, GL_FALSE, pos); /* Note: Side effects wrt register allocation */ - - if (flags & PFS_FLAG_SAT) { - vop |= R300_ALU_OUTC_CLAMP; - sop |= R300_ALU_OUTA_CLAMP; - } - - /* Throw the pieces together and get ALU/1 */ - if (emit_vop) { - code->alu.inst[pos].inst0 |= vop; - - code->alu.inst[pos].inst1 |= hwdest << R300_ALU_DSTC_SHIFT; - - if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { - if (REG_GET_INDEX(dest) == FRAG_RESULT_COLR) { - code->alu.inst[pos].inst1 |= - (mask & WRITEMASK_XYZ) << - R300_ALU_DSTC_OUTPUT_MASK_SHIFT; - } else - assert(0); + if (node->tex_end < 0) { + if (code->cur_node == 0) { + node->tex_end = 0; } else { - code->alu.inst[pos].inst1 |= - (mask & WRITEMASK_XYZ) << - R300_ALU_DSTC_REG_MASK_SHIFT; - - cs->hwtemps[hwdest].vector_valid = pos + 1; - } - } - - /* And now ALU/3 */ - if (emit_sop) { - code->alu.inst[pos].inst2 |= sop; - - if (mask & WRITEMASK_W) { - if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { - if (REG_GET_INDEX(dest) == FRAG_RESULT_COLR) { - code->alu.inst[pos].inst3 |= - (hwdest << R300_ALU_DSTA_SHIFT) | - R300_ALU_DSTA_OUTPUT; - } else if (REG_GET_INDEX(dest) == - FRAG_RESULT_DEPR) { - code->alu.inst[pos].inst3 |= - R300_ALU_DSTA_DEPTH; - } else - assert(0); - } else { - code->alu.inst[pos].inst3 |= - (hwdest << R300_ALU_DSTA_SHIFT) | - R300_ALU_DSTA_REG; - - cs->hwtemps[hwdest].scalar_valid = pos + 1; - } + error("Node %i has no TEX instructions", code->cur_node); + return GL_FALSE; } + } else { + if (code->cur_node == 0) + code->first_node_has_tex = 1; } - return; + return GL_TRUE; } -static GLfloat SinCosConsts[2][4] = { - { - 1.273239545, // 4/PI - -0.405284735, // -4/(PI*PI) - 3.141592654, // PI - 0.2225 // weight - }, - { - 0.75, - 0.0, - 0.159154943, // 1/(2*PI) - 6.283185307 // 2*PI - } -}; /** - * Emit a LIT instruction. - * \p flags may be PFS_FLAG_SAT - * - * Definition of LIT (from ARB_fragment_program): - * tmp = VectorLoad(op0); - * if (tmp.x < 0) tmp.x = 0; - * if (tmp.y < 0) tmp.y = 0; - * if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon); - * else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon; - * result.x = 1.0; - * result.y = tmp.x; - * result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0; - * result.w = 1.0; - * - * The longest path of computation is the one leading to result.z, - * consisting of 5 operations. This implementation of LIT takes - * 5 slots. So unless there's some special undocumented opcode, - * this implementation is potentially optimal. Unfortunately, - * emit_arith is a bit too conservative because it doesn't understand - * partial writes to the vector component. + * Begin a block of texture instructions. + * Create the necessary indirection. */ -static const GLfloat LitConst[4] = - { 127.999999, 127.999999, 127.999999, -127.999999 }; - -static void emit_lit(struct r300_pfs_compile_state *cs, - GLuint dest, int mask, GLuint src, int flags) +static GLboolean begin_tex(void* data) { - COMPILE_STATE; - GLuint cnst; - int needTemporary; - GLuint temp; - - cnst = emit_const4fv(cs, LitConst); - - needTemporary = 0; - if ((mask & WRITEMASK_XYZW) != WRITEMASK_XYZW) { - needTemporary = 1; - } else if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { - // LIT is typically followed by DP3/DP4, so there's no point - // in creating special code for this case - needTemporary = 1; - } - - if (needTemporary) { - temp = keep(get_temp_reg(cs)); - } else { - temp = keep(dest); - } + PROG_CODE; - // Note: The order of emit_arith inside the slots is relevant, - // because emit_arith only looks at scalar vs. vector when resolving - // dependencies, and it does not consider individual vector components, - // so swizzling between the two parts can create fake dependencies. - - // First slot - emit_arith(cs, PFS_OP_MAX, temp, WRITEMASK_XY, - keep(src), pfs_zero, undef, 0); - emit_arith(cs, PFS_OP_MAX, temp, WRITEMASK_W, src, cnst, undef, 0); - - // Second slot - emit_arith(cs, PFS_OP_MIN, temp, WRITEMASK_Z, - swizzle(temp, W, W, W, W), cnst, undef, 0); - emit_arith(cs, PFS_OP_LG2, temp, WRITEMASK_W, - swizzle(temp, Y, Y, Y, Y), undef, undef, 0); - - // Third slot - // If desired, we saturate the y result here. - // This does not affect the use as a condition variable in the CMP later - emit_arith(cs, PFS_OP_MAD, temp, WRITEMASK_W, - temp, swizzle(temp, Z, Z, Z, Z), pfs_zero, 0); - emit_arith(cs, PFS_OP_MAD, temp, WRITEMASK_Y, - swizzle(temp, X, X, X, X), pfs_one, pfs_zero, flags); - - // Fourth slot - emit_arith(cs, PFS_OP_MAD, temp, WRITEMASK_X, - pfs_one, pfs_one, pfs_zero, 0); - emit_arith(cs, PFS_OP_EX2, temp, WRITEMASK_W, temp, undef, undef, 0); - - // Fifth slot - emit_arith(cs, PFS_OP_CMP, temp, WRITEMASK_Z, - pfs_zero, swizzle(temp, W, W, W, W), - negate(swizzle(temp, Y, Y, Y, Y)), flags); - emit_arith(cs, PFS_OP_MAD, temp, WRITEMASK_W, pfs_one, pfs_one, - pfs_zero, 0); - - if (needTemporary) { - emit_arith(cs, PFS_OP_MAD, dest, mask, - temp, pfs_one, pfs_zero, flags); - free_temp(cs, temp); - } else { - // Decrease refcount of the destination - t_hw_dst(cs, dest, GL_FALSE, cs->nrslots); + if (code->cur_node == 0) { + if (code->node[0].alu_end < 0 && + code->node[0].tex_end < 0) + return GL_TRUE; } -} - -static void emit_instruction(struct r300_pfs_compile_state *cs, struct prog_instruction *fpi) -{ - COMPILE_STATE; - GLuint src[3], dest, temp[2]; - int flags, mask = 0; - int const_sin[2]; - - if (fpi->SaturateMode == SATURATE_ZERO_ONE) - flags = PFS_FLAG_SAT; - else - flags = 0; - - if (fpi->Opcode != OPCODE_KIL) { - dest = t_dst(cs, fpi->DstReg); - mask = fpi->DstReg.WriteMask; - } - - switch (fpi->Opcode) { - case OPCODE_ADD: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - emit_arith(cs, PFS_OP_MAD, dest, mask, - src[0], pfs_one, src[1], flags); - break; - case OPCODE_CMP: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - src[2] = t_src(cs, fpi->SrcReg[2]); - /* ARB_f_p - if src0.c < 0.0 ? src1.c : src2.c - * r300 - if src2.c < 0.0 ? src1.c : src0.c - */ - emit_arith(cs, PFS_OP_CMP, dest, mask, - src[2], src[1], src[0], flags); - break; - case OPCODE_COS: - /* - * cos using a parabola (see SIN): - * cos(x): - * x = (x/(2*PI))+0.75 - * x = frac(x) - * x = (x*2*PI)-PI - * result = sin(x) - */ - temp[0] = get_temp_reg(cs); - const_sin[0] = emit_const4fv(cs, SinCosConsts[0]); - const_sin[1] = emit_const4fv(cs, SinCosConsts[1]); - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - - /* add 0.5*PI and do range reduction */ - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_X, - swizzle(src[0], X, X, X, X), - swizzle(const_sin[1], Z, Z, Z, Z), - swizzle(const_sin[1], X, X, X, X), 0); - - emit_arith(cs, PFS_OP_FRC, temp[0], WRITEMASK_X, - swizzle(temp[0], X, X, X, X), - undef, undef, 0); - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_Z, swizzle(temp[0], X, X, X, X), swizzle(const_sin[1], W, W, W, W), //2*PI - negate(swizzle(const_sin[0], Z, Z, Z, Z)), //-PI - 0); - - /* SIN */ - - emit_arith(cs, PFS_OP_MAD, temp[0], - WRITEMASK_X | WRITEMASK_Y, swizzle(temp[0], - Z, Z, Z, - Z), - const_sin[0], pfs_zero, 0); - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_X, - swizzle(temp[0], Y, Y, Y, Y), - absolute(swizzle(temp[0], Z, Z, Z, Z)), - swizzle(temp[0], X, X, X, X), 0); - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_Y, - swizzle(temp[0], X, X, X, X), - absolute(swizzle(temp[0], X, X, X, X)), - negate(swizzle(temp[0], X, X, X, X)), 0); - - emit_arith(cs, PFS_OP_MAD, dest, mask, - swizzle(temp[0], Y, Y, Y, Y), - swizzle(const_sin[0], W, W, W, W), - swizzle(temp[0], X, X, X, X), flags); - - free_temp(cs, temp[0]); - break; - case OPCODE_DP3: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - emit_arith(cs, PFS_OP_DP3, dest, mask, - src[0], src[1], undef, flags); - break; - case OPCODE_DP4: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - emit_arith(cs, PFS_OP_DP4, dest, mask, - src[0], src[1], undef, flags); - break; - case OPCODE_DST: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - /* dest.y = src0.y * src1.y */ - if (mask & WRITEMASK_Y) - emit_arith(cs, PFS_OP_MAD, dest, WRITEMASK_Y, - keep(src[0]), keep(src[1]), - pfs_zero, flags); - /* dest.z = src0.z */ - if (mask & WRITEMASK_Z) - emit_arith(cs, PFS_OP_MAD, dest, WRITEMASK_Z, - src[0], pfs_one, pfs_zero, flags); - /* result.x = 1.0 - * result.w = src1.w */ - if (mask & WRITEMASK_XW) { - REG_SET_VSWZ(src[1], SWIZZLE_111); /*Cheat */ - emit_arith(cs, PFS_OP_MAD, dest, - mask & WRITEMASK_XW, - src[1], pfs_one, pfs_zero, flags); - } - break; - case OPCODE_EX2: - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - emit_arith(cs, PFS_OP_EX2, dest, mask, - src[0], undef, undef, flags); - break; - case OPCODE_FRC: - src[0] = t_src(cs, fpi->SrcReg[0]); - emit_arith(cs, PFS_OP_FRC, dest, mask, - src[0], undef, undef, flags); - break; - case OPCODE_KIL: - emit_tex(cs, fpi, R300_TEX_OP_KIL); - break; - case OPCODE_LG2: - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - emit_arith(cs, PFS_OP_LG2, dest, mask, - src[0], undef, undef, flags); - break; - case OPCODE_LIT: - src[0] = t_src(cs, fpi->SrcReg[0]); - emit_lit(cs, dest, mask, src[0], flags); - break; - case OPCODE_LRP: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - src[2] = t_src(cs, fpi->SrcReg[2]); - /* result = tmp0tmp1 + (1 - tmp0)tmp2 - * = tmp0tmp1 + tmp2 + (-tmp0)tmp2 - * MAD temp, -tmp0, tmp2, tmp2 - * MAD result, tmp0, tmp1, temp - */ - temp[0] = get_temp_reg(cs); - emit_arith(cs, PFS_OP_MAD, temp[0], mask, - negate(keep(src[0])), keep(src[2]), src[2], - 0); - emit_arith(cs, PFS_OP_MAD, dest, mask, - src[0], src[1], temp[0], flags); - free_temp(cs, temp[0]); - break; - case OPCODE_MAD: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - src[2] = t_src(cs, fpi->SrcReg[2]); - emit_arith(cs, PFS_OP_MAD, dest, mask, - src[0], src[1], src[2], flags); - break; - case OPCODE_MAX: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - emit_arith(cs, PFS_OP_MAX, dest, mask, - src[0], src[1], undef, flags); - break; - case OPCODE_MIN: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - emit_arith(cs, PFS_OP_MIN, dest, mask, - src[0], src[1], undef, flags); - break; - case OPCODE_MOV: - src[0] = t_src(cs, fpi->SrcReg[0]); - emit_arith(cs, PFS_OP_MAD, dest, mask, - src[0], pfs_one, pfs_zero, flags); - break; - case OPCODE_MUL: - src[0] = t_src(cs, fpi->SrcReg[0]); - src[1] = t_src(cs, fpi->SrcReg[1]); - emit_arith(cs, PFS_OP_MAD, dest, mask, - src[0], src[1], pfs_zero, flags); - break; - case OPCODE_RCP: - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - emit_arith(cs, PFS_OP_RCP, dest, mask, - src[0], undef, undef, flags); - break; - case OPCODE_RSQ: - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - emit_arith(cs, PFS_OP_RSQ, dest, mask, - absolute(src[0]), pfs_zero, pfs_zero, flags); - break; - case OPCODE_SCS: - /* - * scs using a parabola : - * scs(x): - * result.x = sin(-abs(x)+0.5*PI) (cos) - * result.y = sin(x) (sin) - * - */ - temp[0] = get_temp_reg(cs); - temp[1] = get_temp_reg(cs); - const_sin[0] = emit_const4fv(cs, SinCosConsts[0]); - const_sin[1] = emit_const4fv(cs, SinCosConsts[1]); - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - - /* x = -abs(x)+0.5*PI */ - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_Z, swizzle(const_sin[0], Z, Z, Z, Z), //PI - pfs_half, - negate(abs - (swizzle(keep(src[0]), X, X, X, X))), - 0); - - /* C*x (sin) */ - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_W, - swizzle(const_sin[0], Y, Y, Y, Y), - swizzle(keep(src[0]), X, X, X, X), - pfs_zero, 0); - - /* B*x, C*x (cos) */ - emit_arith(cs, PFS_OP_MAD, temp[0], - WRITEMASK_X | WRITEMASK_Y, swizzle(temp[0], - Z, Z, Z, - Z), - const_sin[0], pfs_zero, 0); - - /* B*x (sin) */ - emit_arith(cs, PFS_OP_MAD, temp[1], WRITEMASK_W, - swizzle(const_sin[0], X, X, X, X), - keep(src[0]), pfs_zero, 0); - - /* y = B*x + C*x*abs(x) (sin) */ - emit_arith(cs, PFS_OP_MAD, temp[1], WRITEMASK_Z, - absolute(src[0]), - swizzle(temp[0], W, W, W, W), - swizzle(temp[1], W, W, W, W), 0); - - /* y = B*x + C*x*abs(x) (cos) */ - emit_arith(cs, PFS_OP_MAD, temp[1], WRITEMASK_W, - swizzle(temp[0], Y, Y, Y, Y), - absolute(swizzle(temp[0], Z, Z, Z, Z)), - swizzle(temp[0], X, X, X, X), 0); - - /* y*abs(y) - y (cos), y*abs(y) - y (sin) */ - emit_arith(cs, PFS_OP_MAD, temp[0], - WRITEMASK_X | WRITEMASK_Y, swizzle(temp[1], - W, Z, Y, - X), - absolute(swizzle(temp[1], W, Z, Y, X)), - negate(swizzle(temp[1], W, Z, Y, X)), 0); - - /* dest.xy = mad(temp.xy, P, temp2.wz) */ - emit_arith(cs, PFS_OP_MAD, dest, - mask & (WRITEMASK_X | WRITEMASK_Y), temp[0], - swizzle(const_sin[0], W, W, W, W), - swizzle(temp[1], W, Z, Y, X), flags); - - free_temp(cs, temp[0]); - free_temp(cs, temp[1]); - break; - case OPCODE_SIN: - /* - * using a parabola: - * sin(x) = 4/pi * x + -4/(pi*pi) * x * abs(x) - * extra precision is obtained by weighting against - * itself squared. - */ - - temp[0] = get_temp_reg(cs); - const_sin[0] = emit_const4fv(cs, SinCosConsts[0]); - const_sin[1] = emit_const4fv(cs, SinCosConsts[1]); - src[0] = t_scalar_src(cs, fpi->SrcReg[0]); - /* do range reduction */ - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_X, - swizzle(keep(src[0]), X, X, X, X), - swizzle(const_sin[1], Z, Z, Z, Z), - pfs_half, 0); - - emit_arith(cs, PFS_OP_FRC, temp[0], WRITEMASK_X, - swizzle(temp[0], X, X, X, X), - undef, undef, 0); - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_Z, swizzle(temp[0], X, X, X, X), swizzle(const_sin[1], W, W, W, W), //2*PI - negate(swizzle(const_sin[0], Z, Z, Z, Z)), //PI - 0); - - /* SIN */ - - emit_arith(cs, PFS_OP_MAD, temp[0], - WRITEMASK_X | WRITEMASK_Y, swizzle(temp[0], - Z, Z, Z, - Z), - const_sin[0], pfs_zero, 0); - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_X, - swizzle(temp[0], Y, Y, Y, Y), - absolute(swizzle(temp[0], Z, Z, Z, Z)), - swizzle(temp[0], X, X, X, X), 0); - - emit_arith(cs, PFS_OP_MAD, temp[0], WRITEMASK_Y, - swizzle(temp[0], X, X, X, X), - absolute(swizzle(temp[0], X, X, X, X)), - negate(swizzle(temp[0], X, X, X, X)), 0); - - emit_arith(cs, PFS_OP_MAD, dest, mask, - swizzle(temp[0], Y, Y, Y, Y), - swizzle(const_sin[0], W, W, W, W), - swizzle(temp[0], X, X, X, X), flags); - - free_temp(cs, temp[0]); - break; - case OPCODE_TEX: - emit_tex(cs, fpi, R300_TEX_OP_LD); - break; - case OPCODE_TXB: - emit_tex(cs, fpi, R300_TEX_OP_TXB); - break; - case OPCODE_TXP: - emit_tex(cs, fpi, R300_TEX_OP_TXP); - break; - default: - ERROR("unknown fpi->Opcode %d\n", fpi->Opcode); - break; + if (code->cur_node == 3) { + error("Too many texture indirections"); + return GL_FALSE; } -} -static GLboolean parse_program(struct r300_pfs_compile_state *cs) -{ - COMPILE_STATE; - int clauseidx; - - for (clauseidx = 0; clauseidx < cs->compiler->compiler.NumClauses; ++clauseidx) { - struct radeon_clause* clause = &cs->compiler->compiler.Clauses[clauseidx]; - int ip; - - for(ip = 0; ip < clause->NumInstructions; ++ip) { - emit_instruction(cs, clause->Instructions + ip); - - if (fp->error) - return GL_FALSE; - } - } + if (!finish_node(c)) + return GL_FALSE; + struct r300_fragment_program_node *node = &code->node[++code->cur_node]; + node->alu_offset = code->alu.length; + node->alu_end = -1; + node->tex_offset = code->tex.length; + node->tex_end = -1; return GL_TRUE; } -/* - Init structures - * - Determine what hwregs each input corresponds to - */ -static void init_program(struct r300_pfs_compile_state *cs) +static GLboolean emit_tex(void* data, struct prog_instruction* inst) { - COMPILE_STATE; - struct gl_fragment_program *mp = &fp->mesa_program; - GLuint InputsRead = mp->Base.InputsRead; - GLuint temps_used = 0; /* for fp->temps[] */ - int i, j; - - /* New compile, reset tracking data */ - fp->optimization = - driQueryOptioni(&cs->compiler->r300->radeon.optionCache, "fp_optimization"); - fp->translated = GL_FALSE; - fp->error = GL_FALSE; - fp->WritesDepth = GL_FALSE; - code->tex.length = 0; - code->cur_node = 0; - code->first_node_has_tex = 0; - code->const_nr = 0; - code->max_temp_idx = 0; - code->node[0].alu_end = -1; - code->node[0].tex_end = -1; + PROG_CODE; - for (i = 0; i < PFS_MAX_ALU_INST; i++) { - for (j = 0; j < 3; j++) { - cs->slot[i].vsrc[j] = SRC_CONST; - cs->slot[i].ssrc[j] = SRC_CONST; - } - } - - /* Work out what temps the Mesa inputs correspond to, this must match - * what setup_rs_unit does, which shouldn't be a problem as rs_unit - * configures itself based on the fragprog's InputsRead - * - * NOTE: this depends on get_hw_temp() allocating registers in order, - * starting from register 0. - */ - - /* Texcoords come first */ - for (i = 0; i < cs->compiler->r300->radeon.glCtx->Const.MaxTextureUnits; i++) { - if (InputsRead & (FRAG_BIT_TEX0 << i)) { - cs->inputs[FRAG_ATTRIB_TEX0 + i].refcount = 0; - cs->inputs[FRAG_ATTRIB_TEX0 + i].reg = - get_hw_temp(cs, 0); - } - } - InputsRead &= ~FRAG_BITS_TEX_ANY; - - /* fragment position treated as a texcoord */ - if (InputsRead & FRAG_BIT_WPOS) { - cs->inputs[FRAG_ATTRIB_WPOS].refcount = 0; - cs->inputs[FRAG_ATTRIB_WPOS].reg = get_hw_temp(cs, 0); + if (code->tex.length >= PFS_MAX_TEX_INST) { + error("Too many TEX instructions"); + return GL_FALSE; } - InputsRead &= ~FRAG_BIT_WPOS; - /* Then primary colour */ - if (InputsRead & FRAG_BIT_COL0) { - cs->inputs[FRAG_ATTRIB_COL0].refcount = 0; - cs->inputs[FRAG_ATTRIB_COL0].reg = get_hw_temp(cs, 0); - } - InputsRead &= ~FRAG_BIT_COL0; + GLuint unit = inst->TexSrcUnit; + GLuint dest = inst->DstReg.Index; + GLuint opcode; - /* Secondary color */ - if (InputsRead & FRAG_BIT_COL1) { - cs->inputs[FRAG_ATTRIB_COL1].refcount = 0; - cs->inputs[FRAG_ATTRIB_COL1].reg = get_hw_temp(cs, 0); + switch(inst->Opcode) { + case OPCODE_KIL: opcode = R300_TEX_OP_KIL; break; + case OPCODE_TEX: opcode = R300_TEX_OP_LD; break; + case OPCODE_TXB: opcode = R300_TEX_OP_TXB; break; + case OPCODE_TXP: opcode = R300_TEX_OP_TXP; break; + default: + error("Unknown texture opcode %i", inst->Opcode); + return GL_FALSE; } - InputsRead &= ~FRAG_BIT_COL1; - /* Anything else */ - if (InputsRead) { - WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead); - /* force read from hwreg 0 for now */ - for (i = 0; i < 32; i++) - if (InputsRead & (1 << i)) - cs->inputs[i].reg = 0; + if (inst->Opcode == OPCODE_KIL) { + unit = 0; + dest = 0; + } else { + use_temporary(code, dest); } - /* Pre-parse the program, grabbing refcounts on input/temp regs. - * That way, we can free up the reg when it's no longer needed - */ - for (i = 0; i < cs->compiler->compiler.Clauses[0].NumInstructions; ++i) { - struct prog_instruction *fpi = cs->compiler->compiler.Clauses[0].Instructions + i; - int idx; + use_temporary(code, inst->SrcReg[0].Index); - for (j = 0; j < 3; j++) { - idx = fpi->SrcReg[j].Index; - switch (fpi->SrcReg[j].File) { - case PROGRAM_TEMPORARY: - if (!(temps_used & (1 << idx))) { - cs->temps[idx].reg = -1; - cs->temps[idx].refcount = 1; - temps_used |= (1 << idx); - } else - cs->temps[idx].refcount++; - break; - case PROGRAM_INPUT: - cs->inputs[idx].refcount++; - break; - default: - break; - } - } - - idx = fpi->DstReg.Index; - if (fpi->DstReg.File == PROGRAM_TEMPORARY) { - if (!(temps_used & (1 << idx))) { - cs->temps[idx].reg = -1; - cs->temps[idx].refcount = 1; - temps_used |= (1 << idx); - } else - cs->temps[idx].refcount++; - } - } - cs->temp_in_use = temps_used; + code->node[code->cur_node].tex_end++; + code->tex.inst[code->tex.length++] = + (inst->SrcReg[0].Index << R300_SRC_ADDR_SHIFT) | + (dest << R300_DST_ADDR_SHIFT) | + (unit << R300_TEX_ID_SHIFT) | + (opcode << R300_TEX_INST_SHIFT); + return GL_TRUE; } +static const struct radeon_pair_handler pair_handler = { + .EmitConst = &emit_const, + .EmitPaired = &emit_alu, + .EmitTex = &emit_tex, + .BeginTexBlock = &begin_tex, + .MaxHwTemps = PFS_NUM_TEMP_REGS +}; + /** * Final compilation step: Turn the intermediate radeon_program into * machine-readable instructions. */ GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler) { - struct r300_pfs_compile_state cs; struct r300_fragment_program_code *code = compiler->code; - _mesa_memset(&cs, 0, sizeof(cs)); - cs.compiler = compiler; - init_program(&cs); + _mesa_bzero(code, sizeof(struct r300_fragment_program_code)); + code->node[0].alu_end = -1; + code->node[0].tex_end = -1; - if (!parse_program(&cs)) + if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler)) return GL_FALSE; - /* Finish off */ - code->node[code->cur_node].alu_end = - cs.nrslots - code->node[code->cur_node].alu_offset - 1; - if (code->node[code->cur_node].tex_end < 0) - code->node[code->cur_node].tex_end = 0; - code->alu_offset = 0; - code->alu_end = cs.nrslots - 1; - code->tex_offset = 0; - code->tex_end = code->tex.length ? code->tex.length - 1 : 0; - assert(code->node[code->cur_node].alu_end >= 0); - assert(code->alu_end >= 0); + if (!finish_node(compiler)) + return GL_FALSE; return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_swizzle.c b/src/mesa/drivers/dri/r300/r300_fragprog_swizzle.c new file mode 100644 index 00000000000..a86d2bd4712 --- /dev/null +++ b/src/mesa/drivers/dri/r300/r300_fragprog_swizzle.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/** + * @file + * Utilities to deal with the somewhat odd restriction on R300 fragment + * program swizzles. + */ + +#include "r300_fragprog_swizzle.h" + +#include "r300_reg.h" +#include "radeon_nqssadce.h" + +#define MAKE_SWZ3(x, y, z) (MAKE_SWIZZLE4(SWIZZLE_##x, SWIZZLE_##y, SWIZZLE_##z, SWIZZLE_ZERO)) + +struct swizzle_data { + GLuint hash; /**< swizzle value this matches */ + GLuint base; /**< base value for hw swizzle */ + GLuint stride; /**< difference in base between arg0/1/2 */ +}; + +static const struct swizzle_data native_swizzles[] = { + {MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4}, + {MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4}, + {MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4}, + {MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4}, + {MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1}, + {MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1}, + {MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1}, + {MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1}, + {MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0}, + {MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0} +}; + +static const int num_native_swizzles = sizeof(native_swizzles)/sizeof(native_swizzles[0]); + + +/** + * Find a native RGB swizzle that matches the given swizzle. + * Returns 0 if none found. + */ +static const struct swizzle_data* lookup_native_swizzle(GLuint swizzle) +{ + int i, comp; + + for(i = 0; i < num_native_swizzles; ++i) { + const struct swizzle_data* sd = &native_swizzles[i]; + for(comp = 0; comp < 3; ++comp) { + GLuint swz = GET_SWZ(swizzle, comp); + if (swz == SWIZZLE_NIL) + continue; + if (swz != GET_SWZ(sd->hash, comp)) + break; + } + if (comp == 3) + return sd; + } + + return 0; +} + + +/** + * Check whether the given instruction supports the swizzle and negate + * combinations in the given source register. + */ +GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) +{ + if (reg.Abs) + reg.NegateBase = 0; + + if (opcode == OPCODE_KIL || + opcode == OPCODE_TEX || + opcode == OPCODE_TXB || + opcode == OPCODE_TXP) { + int j; + + if (reg.Abs || reg.NegateBase != (15*reg.NegateAbs)) + return GL_FALSE; + + for(j = 0; j < 4; ++j) { + GLuint swz = GET_SWZ(reg.Swizzle, j); + if (swz == SWIZZLE_NIL) + continue; + if (swz != j) + return GL_FALSE; + } + + return GL_TRUE; + } + + GLuint relevant = 0; + int j; + + for(j = 0; j < 3; ++j) + if (GET_SWZ(reg.Swizzle, j) != SWIZZLE_NIL) + relevant |= 1 << j; + + if ((reg.NegateBase & relevant) && (reg.NegateBase & relevant) != relevant) + return GL_FALSE; + + if (!lookup_native_swizzle(reg.Swizzle)) + return GL_FALSE; + + return GL_TRUE; +} + + +/** + * Generate MOV dst, src using only native swizzles. + */ +void r300FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src) +{ + if (src.Abs) + src.NegateBase = 0; + + while(dst.WriteMask) { + const struct swizzle_data *best_swizzle = 0; + GLuint best_matchcount = 0; + GLuint best_matchmask = 0; + GLboolean rgbnegate; + int i, comp; + + for(i = 0; i < num_native_swizzles; ++i) { + const struct swizzle_data *sd = &native_swizzles[i]; + GLuint matchcount = 0; + GLuint matchmask = 0; + for(comp = 0; comp < 3; ++comp) { + if (!GET_BIT(dst.WriteMask, comp)) + continue; + GLuint swz = GET_SWZ(src.Swizzle, comp); + if (swz == SWIZZLE_NIL) + continue; + if (swz == GET_SWZ(sd->hash, comp)) { + matchcount++; + matchmask |= 1 << comp; + } + } + if (matchcount > best_matchcount) { + best_swizzle = sd; + best_matchcount = matchcount; + best_matchmask = matchmask; + if (matchmask == (dst.WriteMask & WRITEMASK_XYZ)) + break; + } + } + + if ((src.NegateBase & best_matchmask) != 0) { + best_matchmask &= src.NegateBase; + rgbnegate = !src.NegateAbs; + } else { + rgbnegate = src.NegateAbs; + } + + struct prog_instruction *inst; + + _mesa_insert_instructions(s->Program, s->IP, 1); + inst = s->Program->Instructions + s->IP++; + inst->Opcode = OPCODE_MOV; + inst->DstReg = dst; + inst->DstReg.WriteMask &= (best_matchmask | WRITEMASK_W); + inst->SrcReg[0] = src; + /* Note: We rely on NqSSA/DCE to set unused swizzle components to NIL */ + + dst.WriteMask &= ~inst->DstReg.WriteMask; + } +} + + +/** + * Translate an RGB (XYZ) swizzle into the hardware code for the given + * instruction source. + */ +GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle) +{ + const struct swizzle_data* sd = lookup_native_swizzle(swizzle); + + if (!sd) { + _mesa_printf("Not a native swizzle: %08x\n", swizzle); + return 0; + } + + return sd->base + src*sd->stride; +} + + +/** + * Translate an Alpha (W) swizzle into the hardware code for the given + * instruction source. + */ +GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle) +{ + if (swizzle < 3) + return swizzle + 3*src; + + switch(swizzle) { + case SWIZZLE_W: return R300_ALU_ARGA_SRC0A + src; + case SWIZZLE_ONE: return R300_ALU_ARGA_ONE; + case SWIZZLE_ZERO: return R300_ALU_ARGA_ZERO; + default: return R300_ALU_ARGA_ONE; + } +} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_query.h b/src/mesa/drivers/dri/r300/r300_fragprog_swizzle.h index 3ded41417e1..3da99a9dbe2 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_query.h +++ b/src/mesa/drivers/dri/r300/r300_fragprog_swizzle.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Ben Skeggs. + * Copyright (C) 2008 Nicolai Haehnle. * * All Rights Reserved. * @@ -25,14 +25,18 @@ * */ -#ifndef __NOUVEAU_QUERY_H__ -#define __NOUVEAU_QUERY_H__ +#ifndef __R300_FRAGPROG_SWIZZLE_H_ +#define __R300_FRAGPROG_SWIZZLE_H_ -typedef struct nouveau_query_object_t { - struct gl_query_object mesa; +#include "glheader.h" +#include "shader/prog_instruction.h" - int notifier_id; -} nouveau_query_object; +struct nqssadce_state; -extern void nouveauQueryInitFuncs(GLcontext *ctx); -#endif +GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg); +void r300FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src); + +GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle); +GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle); + +#endif /* __R300_FRAGPROG_SWIZZLE_H_ */ diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 71821a01ea0..bd7f060435f 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -419,13 +419,14 @@ static void r300EmitClearState(GLcontext * ctx) if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560)) + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); - else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420) + else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580)) vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); else vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index 8b00f9958cc..ec2b58377c5 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -1366,8 +1366,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_TX_WRAP_S_MASK (7 << 0) # define R300_TX_WRAP_T_SHIFT 3 # define R300_TX_WRAP_T_MASK (7 << 3) -# define R300_TX_WRAP_Q_SHIFT 6 -# define R300_TX_WRAP_Q_MASK (7 << 6) +# define R300_TX_WRAP_R_SHIFT 6 +# define R300_TX_WRAP_R_MASK (7 << 6) # define R300_TX_MAG_FILTER_4 (0 << 9) # define R300_TX_MAG_FILTER_NEAREST (1 << 9) # define R300_TX_MAG_FILTER_LINEAR (2 << 9) @@ -2705,6 +2705,7 @@ enum { # define R500_ALPHA_OP_MDV 15 # define R500_ALPHA_ADDRD(x) (x << 4) # define R500_ALPHA_ADDRD_REL (1 << 11) +# define R500_ALPHA_SEL_A_SHIFT 12 # define R500_ALPHA_SEL_A_SRC0 (0 << 12) # define R500_ALPHA_SEL_A_SRC1 (1 << 12) # define R500_ALPHA_SEL_A_SRC2 (2 << 12) @@ -2721,6 +2722,7 @@ enum { # define R500_ALPHA_MOD_A_NEG (1 << 17) # define R500_ALPHA_MOD_A_ABS (2 << 17) # define R500_ALPHA_MOD_A_NAB (3 << 17) +# define R500_ALPHA_SEL_B_SHIFT 19 # define R500_ALPHA_SEL_B_SRC0 (0 << 19) # define R500_ALPHA_SEL_B_SRC1 (1 << 19) # define R500_ALPHA_SEL_B_SRC2 (2 << 19) @@ -2777,6 +2779,7 @@ enum { # define R500_ALU_RGBA_OP_MDV (12 << 0) # define R500_ALU_RGBA_ADDRD(x) (x << 4) # define R500_ALU_RGBA_ADDRD_REL (1 << 11) +# define R500_ALU_RGBA_SEL_C_SHIFT 12 # define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) # define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) # define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) @@ -2809,6 +2812,7 @@ enum { # define R500_ALU_RGBA_MOD_C_NEG (1 << 23) # define R500_ALU_RGBA_MOD_C_ABS (2 << 23) # define R500_ALU_RGBA_MOD_C_NAB (3 << 23) +# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) # define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) # define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) @@ -2826,6 +2830,7 @@ enum { # define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) # define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) #define R500_US_ALU_RGB_INST_0 0xa000 +# define R500_ALU_RGB_SEL_A_SHIFT 0 # define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) # define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) # define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) @@ -2858,6 +2863,7 @@ enum { # define R500_ALU_RGB_MOD_A_NEG (1 << 11) # define R500_ALU_RGB_MOD_A_ABS (2 << 11) # define R500_ALU_RGB_MOD_A_NAB (3 << 11) +# define R500_ALU_RGB_SEL_B_SHIFT 13 # define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) # define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) # define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) @@ -2915,6 +2921,7 @@ enum { # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) # define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) #define R500_US_CMN_INST_0 0xb800 +# define R500_INST_TYPE_MASK (3 << 0) # define R500_INST_TYPE_ALU (0 << 0) # define R500_INST_TYPE_OUT (1 << 0) # define R500_INST_TYPE_FC (2 << 0) diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 8f74f9d785e..69ff6d573e2 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -373,7 +373,7 @@ static int r300Fallback(GLcontext * ctx) if (!r300->disable_lowimpact_fallback) { FALLBACK_IF(ctx->Polygon.StippleFlag); - FALLBACK_IF(ctx->Multisample.Enabled); + FALLBACK_IF(ctx->Multisample._Enabled); FALLBACK_IF(ctx->Line.StippleFlag); FALLBACK_IF(ctx->Line.SmoothFlag); FALLBACK_IF(ctx->Point.SmoothFlag); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index b1284647da1..6931de4421d 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -70,20 +70,28 @@ extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx); static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4]) { - GLubyte color[4]; r300ContextPtr rmesa = R300_CONTEXT(ctx); R300_STATECHANGE(rmesa, blend_color); - CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]); - CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); - CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); - CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); + if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + GLuint r = IROUND(cf[0]*1023.0f); + GLuint g = IROUND(cf[1]*1023.0f); + GLuint b = IROUND(cf[2]*1023.0f); + GLuint a = IROUND(cf[3]*1023.0f); - rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0], - color[1], color[2]); - rmesa->hw.blend_color.cmd[2] = 0; - rmesa->hw.blend_color.cmd[3] = 0; + rmesa->hw.blend_color.cmd[1] = r | (a << 16); + rmesa->hw.blend_color.cmd[2] = b | (g << 16); + } else { + GLubyte color[4]; + CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]); + CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); + CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); + CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); + + rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0], + color[1], color[2]); + } } /** @@ -827,6 +835,31 @@ static void r300PointSize(GLcontext * ctx, GLfloat size) ((int)(size * 6) << R300_POINTSIZE_Y_SHIFT); } +static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + + switch (pname) { + case GL_POINT_SIZE_MIN: + R300_STATECHANGE(r300, ga_point_minmax); + r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK; + r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 16.0); + break; + case GL_POINT_SIZE_MAX: + R300_STATECHANGE(r300, ga_point_minmax); + r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK; + r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 16.0) + << R300_GA_POINT_MINMAX_MAX_SHIFT; + break; + case GL_POINT_DISTANCE_ATTENUATION: + break; + case GL_POINT_FADE_THRESHOLD_SIZE: + break; + default: + break; + } +} + /* ============================================================= * Line state */ @@ -1256,8 +1289,8 @@ static unsigned long gen_fixed_filter(unsigned long f) (R300_TX_CLAMP << R300_TX_WRAP_T_SHIFT)) { needs_fixing |= 2; } - if ((f & ((7 - 1) << R300_TX_WRAP_Q_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_Q_SHIFT)) { + if ((f & ((7 - 1) << R300_TX_WRAP_R_SHIFT)) == + (R300_TX_CLAMP << R300_TX_WRAP_R_SHIFT)) { needs_fixing |= 4; } @@ -1297,8 +1330,8 @@ static unsigned long gen_fixed_filter(unsigned long f) f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT; } if (needs_fixing & 4) { - f &= ~((7 - 1) << R300_TX_WRAP_Q_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_Q_SHIFT; + f &= ~((7 - 1) << R300_TX_WRAP_R_SHIFT); + f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT; } return f; } @@ -1381,16 +1414,14 @@ static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) } } -static GLuint r300CalculateTexLodBias(GLfloat bias) +static GLuint translate_lod_bias(GLfloat bias) { - GLuint b; - b = (unsigned int)fabsf(ceilf(bias*31)); - if (signbit(bias)) { - b ^= 0x3ff; /* 10 bits */ - } - b <<= 3; - b &= R300_LOD_BIAS_MASK; - return b; + GLint b = (int)(bias*32); + if (b >= (1 << 9)) + b = (1 << 9)-1; + else if (b < -(1 << 9)) + b = -(1 << 9); + return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; } static void r300SetupTextures(GLcontext * ctx) @@ -1456,8 +1487,14 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + hw_tmu] = gen_fixed_filter(t->filter) | (hw_tmu << 28); - r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->filter_1 - | r300CalculateTexLodBias(r300->LODBias); + /* Note: There is a LOD bias per texture unit and a LOD bias + * per texture object. We add them here to get the correct behaviour. + * (The per-texture object LOD bias was introduced in OpenGL 1.4 + * and is not present in the EXT_texture_object extension). + */ + r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = + t->filter_1 | + translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.tObj->LodBias); r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] = t->size; r300->hw.tex.format.cmd[R300_TEX_VALUE_0 + @@ -1934,13 +1971,14 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (2 << R300_PVS_NUM_FPUS_SHIFT); else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560)) + (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || + (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (5 << R300_PVS_NUM_FPUS_SHIFT); - else if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420) + else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || + (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (6 << R300_PVS_NUM_FPUS_SHIFT); else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) || - (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) + (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580)) rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (8 << R300_PVS_NUM_FPUS_SHIFT); else rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (4 << R300_PVS_NUM_FPUS_SHIFT); @@ -2416,6 +2454,27 @@ void r300UpdateShaders(r300ContextPtr rmesa) r300UpdateStateParameters(ctx, _NEW_PROGRAM); } +static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, + struct gl_program *program, struct prog_src_register srcreg) +{ + static const GLfloat dummy[4] = { 0, 0, 0, 0 }; + + switch(srcreg.File) { + case PROGRAM_LOCAL_PARAM: + return program->LocalParams[srcreg.Index]; + case PROGRAM_ENV_PARAM: + return ctx->FragmentProgram.Parameters[srcreg.Index]; + case PROGRAM_STATE_VAR: + case PROGRAM_NAMED_PARAM: + case PROGRAM_CONSTANT: + return program->Parameters->ParameterValues[srcreg.Index]; + default: + _mesa_problem(ctx, "get_fragmentprogram_constant: Unknown\n"); + return dummy; + } +} + + static void r300SetupPixelShader(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; @@ -2438,26 +2497,17 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) r300SetupTextures(ctx); R300_STATECHANGE(rmesa, fpi[0]); - rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, code->alu_end + 1); - for (i = 0; i <= code->alu_end; i++) { - rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; - } - R300_STATECHANGE(rmesa, fpi[1]); - rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, code->alu_end + 1); - for (i = 0; i <= code->alu_end; i++) { - rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; - } - R300_STATECHANGE(rmesa, fpi[2]); - rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, code->alu_end + 1); - for (i = 0; i <= code->alu_end; i++) { - rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst2; - } - R300_STATECHANGE(rmesa, fpi[3]); - rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, code->alu_end + 1); - for (i = 0; i <= code->alu_end; i++) { + rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, code->alu.length); + rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, code->alu.length); + rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, code->alu.length); + rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, code->alu.length); + for (i = 0; i < code->alu.length; i++) { + rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; + rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; + rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst2; rmesa->hw.fpi[3].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst3; } @@ -2465,10 +2515,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) rmesa->hw.fp.cmd[R300_FP_CNTL0] = code->cur_node | (code->first_node_has_tex << 3); rmesa->hw.fp.cmd[R300_FP_CNTL1] = code->max_temp_idx; rmesa->hw.fp.cmd[R300_FP_CNTL2] = - (code->alu_offset << R300_PFS_CNTL_ALU_OFFSET_SHIFT) | - (code->alu_end << R300_PFS_CNTL_ALU_END_SHIFT) | - (code->tex_offset << R300_PFS_CNTL_TEX_OFFSET_SHIFT) | - (code->tex_end << R300_PFS_CNTL_TEX_END_SHIFT); + (0 << R300_PFS_CNTL_ALU_OFFSET_SHIFT) | + ((code->alu.length-1) << R300_PFS_CNTL_ALU_END_SHIFT) | + (0 << R300_PFS_CNTL_TEX_OFFSET_SHIFT) | + ((code->tex.length ? code->tex.length-1 : 0) << R300_PFS_CNTL_TEX_END_SHIFT); /* I just want to say, the way these nodes are stored.. weird.. */ for (i = 0, k = (4 - (code->cur_node + 1)); i < 4; i++, k++) { if (i < (code->cur_node + 1)) { @@ -2486,10 +2536,12 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) R300_STATECHANGE(rmesa, fpp); rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, code->const_nr * 4); for (i = 0; i < code->const_nr; i++) { - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(code->constant[i][0]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(code->constant[i][1]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(code->constant[i][2]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(code->constant[i][3]); + const GLfloat *constant = get_fragmentprogram_constant(ctx, + &fp->mesa_program.Base, code->constant[i]); + rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]); + rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]); + rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]); + rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]); } } @@ -2558,10 +2610,12 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) R300_STATECHANGE(rmesa, r500fp_const); for (i = 0; i < code->const_nr; i++) { - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(code->constant[i][0]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(code->constant[i][1]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(code->constant[i][2]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(code->constant[i][3]); + const GLfloat *constant = get_fragmentprogram_constant(ctx, + &fp->mesa_program.Base, code->constant[i]); + rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]); + rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]); + rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]); + rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]); } bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4); @@ -2702,6 +2756,9 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->FrontFace = r300FrontFace; functions->ShadeModel = r300ShadeModel; + /* ARB_point_parameters */ + functions->PointParameterfv = r300PointParameter; + /* Stencil related */ functions->StencilFuncSeparate = r300StencilFuncSeparate; functions->StencilMaskSeparate = r300StencilMaskSeparate; diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 5f54bcad9a3..c8f02c4ef5b 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -52,112 +52,45 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" + +static unsigned int translate_wrap_mode(GLenum wrapmode) +{ + switch(wrapmode) { + case GL_REPEAT: return R300_TX_REPEAT; + case GL_CLAMP: return R300_TX_CLAMP; + case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE; + case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER; + case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED; + case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED; + case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; + case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED; + default: + _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); + return 0; + } +} + + /** - * Set the texture wrap modes. + * Update the cached hardware registers based on the current texture wrap modes. * * \param t Texture object whose wrap modes are to be set - * \param swrap Wrap mode for the \a s texture coordinate - * \param twrap Wrap mode for the \a t texture coordinate */ - -static void r300SetTexWrap(r300TexObjPtr t, GLenum swrap, GLenum twrap, - GLenum rwrap) +static void r300UpdateTexWrap(r300TexObjPtr t) { - unsigned long hw_swrap = 0, hw_twrap = 0, hw_qwrap = 0; + struct gl_texture_object *tObj = t->base.tObj; t->filter &= - ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_Q_MASK); + ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK); - switch (swrap) { - case GL_REPEAT: - hw_swrap |= R300_TX_REPEAT; - break; - case GL_CLAMP: - hw_swrap |= R300_TX_CLAMP; - break; - case GL_CLAMP_TO_EDGE: - hw_swrap |= R300_TX_CLAMP_TO_EDGE; - break; - case GL_CLAMP_TO_BORDER: - hw_swrap |= R300_TX_CLAMP_TO_BORDER; - break; - case GL_MIRRORED_REPEAT: - hw_swrap |= R300_TX_REPEAT | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_EXT: - hw_swrap |= R300_TX_CLAMP | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - hw_swrap |= R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - hw_swrap |= R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED; - break; - default: - _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__); - } + t->filter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT; - switch (twrap) { - case GL_REPEAT: - hw_twrap |= R300_TX_REPEAT; - break; - case GL_CLAMP: - hw_twrap |= R300_TX_CLAMP; - break; - case GL_CLAMP_TO_EDGE: - hw_twrap |= R300_TX_CLAMP_TO_EDGE; - break; - case GL_CLAMP_TO_BORDER: - hw_twrap |= R300_TX_CLAMP_TO_BORDER; - break; - case GL_MIRRORED_REPEAT: - hw_twrap |= R300_TX_REPEAT | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_EXT: - hw_twrap |= R300_TX_CLAMP | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - hw_twrap |= R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - hw_twrap |= R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED; - break; - default: - _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__); - } + if (tObj->Target != GL_TEXTURE_1D) { + t->filter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT; - switch (rwrap) { - case GL_REPEAT: - hw_qwrap |= R300_TX_REPEAT; - break; - case GL_CLAMP: - hw_qwrap |= R300_TX_CLAMP; - break; - case GL_CLAMP_TO_EDGE: - hw_qwrap |= R300_TX_CLAMP_TO_EDGE; - break; - case GL_CLAMP_TO_BORDER: - hw_qwrap |= R300_TX_CLAMP_TO_BORDER; - break; - case GL_MIRRORED_REPEAT: - hw_qwrap |= R300_TX_REPEAT | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_EXT: - hw_qwrap |= R300_TX_CLAMP | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - hw_qwrap |= R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; - break; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - hw_qwrap |= R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED; - break; - default: - _mesa_problem(NULL, "bad R wrap mode in %s", __FUNCTION__); + if (tObj->Target == GL_TEXTURE_3D) + t->filter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT; } - - t->filter |= hw_swrap << R300_TX_WRAP_S_SHIFT; - t->filter |= hw_twrap << R300_TX_WRAP_T_SHIFT; - t->filter |= hw_qwrap << R300_TX_WRAP_Q_SHIFT; } static GLuint aniso_filter(GLfloat anisotropy) @@ -242,20 +175,6 @@ static void r300SetTexBorderColor(r300TexObjPtr t, GLubyte c[4]) t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); } -static void r300SetTexLodBias(r300TexObjPtr t, GLfloat bias) -{ - GLuint b; - b = (unsigned int)fabsf(ceilf(bias*31)); - if (signbit(bias)) { - b ^= 0x3ff; /* 10 bits */ - } - b <<= 3; - b &= R300_LOD_BIAS_MASK; - - t->filter_1 &= ~R300_LOD_BIAS_MASK; - t->filter_1 |= b; -} - /** * Allocate space for and load the mesa images into the texture memory block. * This will happen before drawing with a new texture, or drawing with a @@ -281,7 +200,7 @@ static r300TexObjPtr r300AllocTexObj(struct gl_texture_object *texObj) make_empty_list(&t->base); - r300SetTexWrap(t, texObj->WrapS, texObj->WrapT, texObj->WrapR); + r300UpdateTexWrap(t); r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); r300SetTexBorderColor(t, texObj->_BorderChan); } @@ -979,72 +898,6 @@ r300TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, t->dirty_images[0] |= (1 << level); } -/* This feels like a prime target for code reuse, so I'm putting it here - * instead of inlining it in TexEnv. */ -static GLenum r300TexUnitTarget(struct gl_texture_unit *unit) { - if (unit->_ReallyEnabled & (TEXTURE_RECT_BIT)) { - return GL_TEXTURE_RECTANGLE_NV; - } else if (unit->_ReallyEnabled & (TEXTURE_1D_BIT)) { - return GL_TEXTURE_1D; - } else if (unit->_ReallyEnabled & (TEXTURE_2D_BIT)) { - return GL_TEXTURE_2D; - } else if (unit->_ReallyEnabled & (TEXTURE_3D_BIT)) { - return GL_TEXTURE_3D; - } else if (unit->_ReallyEnabled & (TEXTURE_CUBE_BIT)) { - return GL_TEXTURE_CUBE_MAP; - } - if (unit->Enabled & (TEXTURE_RECT_BIT)) { - return GL_TEXTURE_RECTANGLE_NV; - } else if (unit->Enabled & (TEXTURE_1D_BIT)) { - return GL_TEXTURE_1D; - } else if (unit->Enabled & (TEXTURE_2D_BIT)) { - return GL_TEXTURE_2D; - } else if (unit->Enabled & (TEXTURE_3D_BIT)) { - return GL_TEXTURE_3D; - } else if (unit->Enabled & (TEXTURE_CUBE_BIT)) { - return GL_TEXTURE_CUBE_MAP; - } - return 0; -} - -static void r300TexEnv(GLcontext * ctx, GLenum target, - GLenum pname, const GLfloat * param) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - if (RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, "%s( %s )\n", - __FUNCTION__, _mesa_lookup_enum_by_nr(pname)); - } - - /* This is incorrect: Need to maintain this data for each of - * GL_TEXTURE_{123}D, GL_TEXTURE_RECTANGLE_NV, etc, and switch - * between them according to _ReallyEnabled. - */ - switch (pname) { - case GL_TEXTURE_LOD_BIAS_EXT: { - /* Needs to be relocated in order to make sure we got the right tmu */ - GLfloat bias, min; - - /* The R300's LOD bias is a signed 2's complement value with a - * range of -16.0 <= bias < 16.0. - * - * NOTE: Add a small bias to the bias for conform mipsel.c test. - */ - bias = *param + .01; - min = driQueryOptionb(&rmesa->radeon.optionCache, - "no_neg_lod_bias") ? 0.0 : -16.0; - bias = CLAMP(bias, min, 16.0); - - rmesa->LODBias = bias; - - break; - } - - default: - return; - } -} - /** * Changes variables and flags for a state update, which will happen at the * next UpdateTextureState @@ -1071,7 +924,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, case GL_TEXTURE_WRAP_S: case GL_TEXTURE_WRAP_T: case GL_TEXTURE_WRAP_R: - r300SetTexWrap(t, texObj->WrapS, texObj->WrapT, texObj->WrapR); + r300UpdateTexWrap(t); break; case GL_TEXTURE_BORDER_COLOR: @@ -1167,10 +1020,6 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, return NULL; obj->MaxAnisotropy = rmesa->initialMaxAnisotropy; - /* Attempt to fill LOD bias, if previously set. - * Should start at 0.0, which won't affect the HW. */ - obj->LodBias = rmesa->LODBias; - r300AllocTexObj(obj); return obj; } @@ -1192,7 +1041,6 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->DeleteTexture = r300DeleteTexture; functions->IsTextureResident = driIsTextureResident; - functions->TexEnv = r300TexEnv; functions->TexParameter = r300TexParameter; functions->CompressedTexImage2D = r300CompressedTexImage2D; diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c index 5d72ec2784f..7b18efa69d6 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog.c @@ -27,11 +27,9 @@ #include "r500_fragprog.h" -static void reset_srcreg(struct prog_src_register* reg) -{ - _mesa_bzero(reg, sizeof(*reg)); - reg->Swizzle = SWIZZLE_NOOP; -} +#include "radeon_nqssadce.h" +#include "radeon_program_alu.h" + /** * Transform TEX, TXP, TXB, and KIL instructions in the following way: @@ -41,7 +39,7 @@ static void reset_srcreg(struct prog_src_register* reg) * */ static GLboolean transform_TEX( - struct radeon_program_transform_context* context, + struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data) { struct r500_fragment_program_compiler *compiler = @@ -58,12 +56,11 @@ static GLboolean transform_TEX( /* ARB_shadow & EXT_shadow_funcs */ if (inst.Opcode != OPCODE_KIL && - compiler->fp->mesa_program.Base.ShadowSamplers & (1 << inst.TexSrcUnit)) { + t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) { GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func; if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) { - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); tgt->Opcode = OPCODE_MOV; tgt->DstReg.File = inst.DstReg.File; @@ -75,70 +72,72 @@ static GLboolean transform_TEX( } inst.DstReg.File = PROGRAM_TEMPORARY; - inst.DstReg.Index = radeonCompilerAllocateTemporary(context->compiler); + inst.DstReg.Index = radeonFindFreeTemporary(t); inst.DstReg.WriteMask = WRITEMASK_XYZW; } - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); _mesa_copy_instructions(tgt, &inst, 1); if (inst.Opcode != OPCODE_KIL && - compiler->fp->mesa_program.Base.ShadowSamplers & (1 << inst.TexSrcUnit)) { + t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) { GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func; GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode; - - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 2); - - tgt[0].Opcode = OPCODE_MAD; - tgt[0].DstReg = inst.DstReg; - tgt[0].DstReg.WriteMask = orig_inst->DstReg.WriteMask; - tgt[0].SrcReg[0].File = PROGRAM_TEMPORARY; - tgt[0].SrcReg[0].Index = inst.DstReg.Index; + int rcptemp = radeonFindFreeTemporary(t); + + tgt = radeonAppendInstructions(t->Program, 3); + + tgt[0].Opcode = OPCODE_RCP; + tgt[0].DstReg.File = PROGRAM_TEMPORARY; + tgt[0].DstReg.Index = rcptemp; + tgt[0].DstReg.WriteMask = WRITEMASK_W; + tgt[0].SrcReg[0] = inst.SrcReg[0]; + tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW; + + tgt[1].Opcode = OPCODE_MAD; + tgt[1].DstReg = inst.DstReg; + tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask; + tgt[1].SrcReg[0] = inst.SrcReg[0]; + tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ; + tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY; + tgt[1].SrcReg[1].Index = rcptemp; + tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW; + tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY; + tgt[1].SrcReg[2].Index = inst.DstReg.Index; if (depthmode == 0) /* GL_LUMINANCE */ - tgt[0].SrcReg[0].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z); + tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z); else if (depthmode == 2) /* GL_ALPHA */ - tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW; - tgt[0].SrcReg[1].File = PROGRAM_BUILTIN; - tgt[0].SrcReg[1].Swizzle = SWIZZLE_1111; - tgt[0].SrcReg[2] = inst.SrcReg[0]; - tgt[0].SrcReg[2].Swizzle = SWIZZLE_ZZZZ; + tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW; /* Recall that SrcReg[0] is tex, SrcReg[2] is r and: * r < tex <=> -tex+r < 0 * r >= tex <=> not (-tex+r < 0 */ if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL) - tgt[0].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW; + tgt[1].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW; else - tgt[0].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW; + tgt[1].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW; - tgt[1].Opcode = OPCODE_CMP; - tgt[1].DstReg = orig_inst->DstReg; - tgt[1].SrcReg[0].File = PROGRAM_TEMPORARY; - tgt[1].SrcReg[0].Index = tgt[0].DstReg.Index; - tgt[1].SrcReg[1].File = PROGRAM_BUILTIN; - tgt[1].SrcReg[2].File = PROGRAM_BUILTIN; + tgt[2].Opcode = OPCODE_CMP; + tgt[2].DstReg = orig_inst->DstReg; + tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY; + tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index; + tgt[2].SrcReg[1].File = PROGRAM_BUILTIN; + tgt[2].SrcReg[2].File = PROGRAM_BUILTIN; if (comparefunc == GL_LESS || comparefunc == GL_GREATER) { - tgt[1].SrcReg[1].Swizzle = SWIZZLE_1111; - tgt[1].SrcReg[2].Swizzle = SWIZZLE_0000; + tgt[2].SrcReg[1].Swizzle = SWIZZLE_1111; + tgt[2].SrcReg[2].Swizzle = SWIZZLE_0000; } else { - tgt[1].SrcReg[1].Swizzle = SWIZZLE_0000; - tgt[1].SrcReg[2].Swizzle = SWIZZLE_1111; + tgt[2].SrcReg[1].Swizzle = SWIZZLE_0000; + tgt[2].SrcReg[2].Swizzle = SWIZZLE_1111; } } else if (destredirect) { - tgt = radeonClauseInsertInstructions(context->compiler, context->dest, - context->dest->NumInstructions, 1); + tgt = radeonAppendInstructions(t->Program, 1); - tgt->Opcode = OPCODE_MAD; + tgt->Opcode = OPCODE_MOV; tgt->DstReg = orig_inst->DstReg; tgt->SrcReg[0].File = PROGRAM_TEMPORARY; tgt->SrcReg[0].Index = inst.DstReg.Index; - tgt->SrcReg[1].File = PROGRAM_BUILTIN; - tgt->SrcReg[1].Swizzle = SWIZZLE_1111; - tgt->SrcReg[2].File = PROGRAM_BUILTIN; - tgt->SrcReg[2].Swizzle = SWIZZLE_0000; } return GL_TRUE; @@ -179,9 +178,10 @@ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) struct prog_instruction *fpi; GLuint window_index; int i = 0; - GLuint tempregi = radeonCompilerAllocateTemporary(&compiler->compiler); + GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY); - fpi = radeonClauseInsertInstructions(&compiler->compiler, &compiler->compiler.Clauses[0], 0, 3); + _mesa_insert_instructions(compiler->program, 0, 3); + fpi = compiler->program->Instructions; /* perspective divide */ fpi[i].Opcode = OPCODE_RCP; @@ -213,7 +213,7 @@ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) i++; /* viewport transformation */ - window_index = _mesa_add_state_reference(compiler->fp->mesa_program.Base.Parameters, tokens); + window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens); fpi[i].Opcode = OPCODE_MAD; @@ -238,7 +238,7 @@ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); i++; - for (; i < compiler->compiler.Clauses[0].NumInstructions; ++i) { + for (; i < compiler->program->NumInstructions; ++i) { int reg; for (reg = 0; reg < 3; reg++) { if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT && @@ -251,6 +251,57 @@ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) } +static void nqssadce_init(struct nqssadce_state* s) +{ + s->Outputs[FRAG_RESULT_COLR].Sourced = WRITEMASK_XYZW; + s->Outputs[FRAG_RESULT_DEPR].Sourced = WRITEMASK_W; +} + +static GLboolean is_native_swizzle(GLuint opcode, struct prog_src_register reg) +{ + GLuint relevant; + int i; + + if (reg.Abs) + return GL_TRUE; + + relevant = 0; + for(i = 0; i < 3; ++i) { + GLuint swz = GET_SWZ(reg.Swizzle, i); + if (swz != SWIZZLE_NIL && swz != SWIZZLE_ZERO) + relevant |= 1 << i; + } + if ((reg.NegateBase & relevant) && ((reg.NegateBase & relevant) != relevant)) + return GL_FALSE; + + return GL_TRUE; +} + +/** + * Implement a non-native swizzle. This function assumes that + * is_native_swizzle returned true. + */ +static void nqssadce_build_swizzle(struct nqssadce_state *s, + struct prog_dst_register dst, struct prog_src_register src) +{ + struct prog_instruction *inst; + + _mesa_insert_instructions(s->Program, s->IP, 2); + inst = s->Program->Instructions + s->IP; + + inst[0].Opcode = OPCODE_MOV; + inst[0].DstReg = dst; + inst[0].DstReg.WriteMask &= src.NegateBase; + inst[0].SrcReg[0] = src; + + inst[1].Opcode = OPCODE_MOV; + inst[1].DstReg = dst; + inst[1].DstReg.WriteMask &= ~src.NegateBase; + inst[1].SrcReg[0] = src; + + s->IP += 2; +} + static GLuint build_dtm(GLuint depthmode) { switch(depthmode) { @@ -310,36 +361,57 @@ void r500TranslateFragmentShader(r300ContextPtr r300, compiler.r300 = r300; compiler.fp = fp; compiler.code = &fp->code; + compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base); - radeonCompilerInit(&compiler.compiler, r300->radeon.glCtx, &fp->mesa_program.Base); + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Compiler: Initial program:\n"); + _mesa_print_program(compiler.program); + } insert_WPOS_trailer(&compiler); - struct radeon_program_transformation transformations[1] = { - { &transform_TEX, &compiler } + struct radeon_program_transformation transformations[3] = { + { &transform_TEX, &compiler }, + { &radeonTransformALU, 0 }, + { &radeonTransformTrigScale, 0 } + }; + radeonLocalTransform(r300->radeon.glCtx, compiler.program, + 3, transformations); + + if (RADEON_DEBUG & DEBUG_PIXEL) { + _mesa_printf("Compiler: after native rewrite:\n"); + _mesa_print_program(compiler.program); + } + + struct radeon_nqssadce_descr nqssadce = { + .Init = &nqssadce_init, + .IsNativeSwizzle = &is_native_swizzle, + .BuildSwizzle = &nqssadce_build_swizzle, + .RewriteDepthOut = GL_TRUE }; - radeonClauseLocalTransform(&compiler.compiler, - &compiler.compiler.Clauses[0], - 1, transformations); + radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce); if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler state after transformations:\n"); - radeonCompilerDump(&compiler.compiler); + _mesa_printf("Compiler: after NqSSA-DCE:\n"); + _mesa_print_program(compiler.program); } fp->translated = r500FragmentProgramEmit(&compiler); - radeonCompilerCleanup(&compiler.compiler); + /* Subtle: Rescue any parameters that have been added during transformations */ + _mesa_free_parameter_list(fp->mesa_program.Base.Parameters); + fp->mesa_program.Base.Parameters = compiler.program->Parameters; + compiler.program->Parameters = 0; + + _mesa_reference_program(r300->radeon.glCtx, &compiler.program, 0); r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); if (RADEON_DEBUG & DEBUG_PIXEL) { - fprintf(stderr, "Mesa program:\n"); - fprintf(stderr, "-------------\n"); - _mesa_print_program(&fp->mesa_program.Base); - fflush(stdout); - if (fp->translated) + if (fp->translated) { + _mesa_printf("Machine-readable code:\n"); dump_program(&fp->code); + } } } @@ -458,9 +530,8 @@ static void dump_program(struct r500_fragment_program_code *code) if (code->const_nr) { fprintf(stderr, "--------\nConstants:\n"); for (n = 0; n < code->const_nr; n++) { - fprintf(stderr, "Constant %d: %f %f\n\t %f %f\n", n, - code->constant[n][0], code->constant[n][1], code->constant[n][2], - code->constant[n][3]); + fprintf(stderr, "Constant %d: %i[%i]\n", n, + code->constant[n].File, code->constant[n].Index); } fprintf(stderr, "--------\n"); } diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h index ff6a9002c14..8641ceeb8f4 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/r500_fragprog.h @@ -45,36 +45,6 @@ #include "r300_state.h" #include "radeon_program.h" -/* supported hw opcodes */ -#define PFS_OP_MAD 0 -#define PFS_OP_DP3 1 -#define PFS_OP_DP4 2 -#define PFS_OP_MIN 3 -#define PFS_OP_MAX 4 -#define PFS_OP_CMP 5 -#define PFS_OP_FRC 6 -#define PFS_OP_EX2 7 -#define PFS_OP_LG2 8 -#define PFS_OP_RCP 9 -#define PFS_OP_RSQ 10 -#define PFS_OP_REPL_ALPHA 11 -#define PFS_OP_CMPH 12 -#define MAX_PFS_OP 12 - -#define PFS_FLAG_SAT (1 << 0) -#define PFS_FLAG_ABS (1 << 1) - -#define ARG_NEG (1 << 5) -#define ARG_ABS (1 << 6) -#define ARG_MASK (127 << 0) -#define ARG_STRIDE 7 -#define SRC_CONST (1 << 5) -#define SRC_MASK (63 << 0) -#define SRC_STRIDE 6 - -#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 -#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 - struct r500_fragment_program; extern void r500TranslateFragmentShader(r300ContextPtr r300, @@ -84,7 +54,7 @@ struct r500_fragment_program_compiler { r300ContextPtr r300; struct r500_fragment_program *fp; struct r500_fragment_program_code *code; - struct radeon_compiler compiler; + struct gl_program *program; }; extern GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler); diff --git a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c index 3dc72af87ab..b6f52474e26 100644 --- a/src/mesa/drivers/dri/r300/r500_fragprog_emit.c +++ b/src/mesa/drivers/dri/r300/r500_fragprog_emit.c @@ -43,1491 +43,281 @@ * */ -#include "glheader.h" -#include "macros.h" -#include "enums.h" -#include "shader/prog_instruction.h" -#include "shader/prog_parameter.h" -#include "shader/prog_print.h" - -#include "r300_context.h" #include "r500_fragprog.h" -#include "r300_reg.h" -#include "r300_state.h" - -/* Mapping Mesa registers to R500 temporaries */ -struct reg_acc { - int reg; /* Assigned hw temp */ - unsigned int refcount; /* Number of uses by mesa program */ -}; - -/** - * Describe the current lifetime information for an R300 temporary - */ -struct reg_lifetime { - /* Index of the first slot where this register is free in the sense - that it can be used as a new destination register. - This is -1 if the register has been assigned to a Mesa register - and the last access to the register has not yet been emitted */ - int free; - - /* Index of the first slot where this register is currently reserved. - This is used to stop e.g. a scalar operation from being moved - before the allocation time of a register that was first allocated - for a vector operation. */ - int reserved; - - /* Index of the first slot in which the register can be used as a - source without losing the value that is written by the last - emitted instruction that writes to the register */ - int vector_valid; - int scalar_valid; - /* Index to the slot where the register was last read. - This is also the first slot in which the register may be written again */ - int vector_lastread; - int scalar_lastread; -}; - -/** - * Store usage information about an ALU instruction slot during the - * compilation of a fragment program. - */ -#define SLOT_SRC_VECTOR (1<<0) -#define SLOT_SRC_SCALAR (1<<3) -#define SLOT_SRC_BOTH (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR) -#define SLOT_OP_VECTOR (1<<16) -#define SLOT_OP_SCALAR (1<<17) -#define SLOT_OP_BOTH (SLOT_OP_VECTOR | SLOT_OP_SCALAR) +#include "radeon_program_pair.h" -struct r500_pfs_compile_slot { - /* Bitmask indicating which parts of the slot are used, using SLOT_ constants - defined above */ - unsigned int used; - /* Selected sources */ - int vsrc[3]; - int ssrc[3]; -}; - -/** - * Store information during compilation of fragment programs. - */ -struct r500_pfs_compile_state { - struct r500_fragment_program_compiler *compiler; +#define PROG_CODE \ + struct r500_fragment_program_compiler *c = (struct r500_fragment_program_compiler*)data; \ + struct r500_fragment_program_code *code = c->code - /* number of ALU slots used so far */ - int nrslots; - - /* Track which (parts of) slots are already filled with instructions */ - struct r500_pfs_compile_slot slot[PFS_MAX_ALU_INST]; - - /* Track the validity of R300 temporaries */ - struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS]; - - /* Used to map Mesa's inputs/temps onto hardware temps */ - int temp_in_use; - struct reg_acc temps[PFS_NUM_TEMP_REGS]; - struct reg_acc inputs[32]; /* don't actually need 32... */ - - /* Track usage of hardware temps, for register allocation, - * indirection detection, etc. */ - GLuint used_in_node; - GLuint dest_in_node; -}; - -/* - * Useful macros and values - */ -#define ERROR(fmt, args...) do { \ +#define error(fmt, args...) do { \ fprintf(stderr, "%s::%s(): " fmt "\n", \ __FILE__, __FUNCTION__, ##args); \ - cs->compiler->fp->error = GL_TRUE; \ } while(0) -#define PROG_CODE struct r500_fragment_program_code *code = cs->compiler->code - -#define R500_US_NUM_TEMP_REGS 128 -#define R500_US_NUM_CONST_REGS 256 - -/* "Register" flags */ -#define REG_CONSTANT (1 << 8) -#define REG_SRC_REL (1 << 9) -#define REG_DEST_REL (1 << 7) - -/* Swizzle tools */ -#define R500_SWIZZLE_ZERO 4 -#define R500_SWIZZLE_HALF 5 -#define R500_SWIZZLE_ONE 6 -#define R500_SWIZ_RGB_ZERO ((4 << 0) | (4 << 3) | (4 << 6)) -#define R500_SWIZ_RGB_ONE ((6 << 0) | (6 << 3) | (6 << 6)) -#define R500_SWIZ_RGB_RGB ((0 << 0) | (1 << 3) | (2 << 6)) -#define R500_SWIZ_MOD_NEG 1 -#define R500_SWIZ_MOD_ABS 2 -#define R500_SWIZ_MOD_NEG_ABS 3 -/* Swizzles for inst2 */ -#define MAKE_SWIZ_TEX_STRQ(x) (x << 8) -#define MAKE_SWIZ_TEX_RGBA(x) (x << 24) -/* Swizzles for inst3 */ -#define MAKE_SWIZ_RGB_A(x) (x << 2) -#define MAKE_SWIZ_RGB_B(x) (x << 15) -/* Swizzles for inst4 */ -#define MAKE_SWIZ_ALPHA_A(x) (x << 14) -#define MAKE_SWIZ_ALPHA_B(x) (x << 21) -/* Swizzle for inst5 */ -#define MAKE_SWIZ_RGBA_C(x) (x << 14) -#define MAKE_SWIZ_ALPHA_C(x) (x << 27) - -/* Writemasks */ -#define R500_WRITEMASK_G 0x2 -#define R500_WRITEMASK_B 0x4 -#define R500_WRITEMASK_RGB 0x7 -#define R500_WRITEMASK_A 0x8 -#define R500_WRITEMASK_AR 0x9 -#define R500_WRITEMASK_AG 0xA -#define R500_WRITEMASK_ARG 0xB -#define R500_WRITEMASK_AB 0xC -#define R500_WRITEMASK_ARGB 0xF - -/* 1/(2pi), needed for quick modulus in trig insts - * Thanks to glisse for pointing out how to do it! */ -static const GLfloat RCP_2PI[] = {0.15915494309189535, - 0.15915494309189535, - 0.15915494309189535, - 0.15915494309189535}; - -static const GLfloat LIT[] = {127.999999, - 127.999999, - 127.999999, - -127.999999}; - -static INLINE GLuint make_rgb_swizzle(struct prog_src_register src) { - GLuint swiz = 0x0; - GLuint temp; - /* This could be optimized, but it should be plenty fast already. */ - int i; - for (i = 0; i < 3; i++) { - temp = GET_SWZ(src.Swizzle, i); - /* Fix SWIZZLE_ONE */ - if (temp == 5) temp++; - swiz |= temp << i*3; - } - if (src.NegateBase) - swiz |= (R500_SWIZ_MOD_NEG << 9); - return swiz; -} - -static INLINE GLuint make_rgba_swizzle(GLuint src) { - GLuint swiz = 0x0; - GLuint temp; - int i; - for (i = 0; i < 4; i++) { - temp = GET_SWZ(src, i); - /* Fix SWIZZLE_ONE */ - if (temp == 5) temp++; - swiz |= temp << i*3; - } - return swiz; -} - -static INLINE GLuint make_alpha_swizzle(struct prog_src_register src) { - GLuint swiz = GET_SWZ(src.Swizzle, 3); - - if (swiz == 5) swiz++; - - if (src.NegateBase) - swiz |= (R500_SWIZ_MOD_NEG << 3); - - return swiz; -} - -static INLINE GLuint make_sop_swizzle(struct prog_src_register src) { - GLuint swiz = GET_SWZ(src.Swizzle, 0); - - if (swiz == 5) swiz++; - return swiz; -} - -static INLINE GLuint make_strq_swizzle(struct prog_src_register src) { - GLuint swiz = 0x0, temp = 0x0; - int i; - for (i = 0; i < 4; i++) { - temp = GET_SWZ(src.Swizzle, i) & 0x3; - swiz |= temp << i*2; - } - return swiz; -} - -static int get_temp(struct r500_pfs_compile_state *cs, int slot) { - - PROG_CODE; - - int r = code->temp_reg_offset + cs->temp_in_use + slot; - - if (r > R500_US_NUM_TEMP_REGS) { - ERROR("Too many temporary registers requested, can't compile!\n"); - } - return r; -} - -/* Borrowed verbatim from r300_fragprog since it hasn't changed. */ -static GLuint emit_const4fv(struct r500_pfs_compile_state *cs, - const GLfloat * cp) +/** + * Callback to register hardware constants. + */ +static GLboolean emit_const(void *data, GLuint file, GLuint idx, GLuint *hwindex) { PROG_CODE; - GLuint reg = 0x0; - int index; - - for (index = 0; index < code->const_nr; ++index) { - if (code->constant[index] == cp) + for (*hwindex = 0; *hwindex < code->const_nr; ++*hwindex) { + if (code->constant[*hwindex].File == file && + code->constant[*hwindex].Index == idx) break; } - if (index >= code->const_nr) { - if (index >= R500_US_NUM_CONST_REGS) { - ERROR("Out of hw constants!\n"); - return reg; + if (*hwindex >= code->const_nr) { + if (*hwindex >= PFS_NUM_CONST_REGS) { + error("Out of hw constants!\n"); + return GL_FALSE; } code->const_nr++; - code->constant[index] = cp; + code->constant[*hwindex].File = file; + code->constant[*hwindex].Index = idx; } - reg = index | REG_CONSTANT; - return reg; + return GL_TRUE; } -static GLuint make_src(struct r500_pfs_compile_state *cs, struct prog_src_register src) { - PROG_CODE; - GLuint reg; - switch (src.File) { - case PROGRAM_TEMPORARY: - reg = src.Index + code->temp_reg_offset; - break; - case PROGRAM_INPUT: - reg = cs->inputs[src.Index].reg; - break; - case PROGRAM_LOCAL_PARAM: - reg = emit_const4fv(cs, - cs->compiler->fp->mesa_program.Base.LocalParams[src.Index]); - break; - case PROGRAM_ENV_PARAM: - reg = emit_const4fv(cs, - cs->compiler->compiler.Ctx->FragmentProgram.Parameters[src.Index]); - break; - case PROGRAM_STATE_VAR: - case PROGRAM_NAMED_PARAM: - case PROGRAM_CONSTANT: - reg = emit_const4fv(cs, - cs->compiler->fp->mesa_program.Base.Parameters->ParameterValues[src.Index]); - break; - case PROGRAM_BUILTIN: - reg = 0x0; - break; +static GLuint translate_rgb_op(GLuint opcode) +{ + switch(opcode) { + case OPCODE_CMP: return R500_ALU_RGBA_OP_CMP; + case OPCODE_DP3: return R500_ALU_RGBA_OP_DP3; + case OPCODE_DP4: return R500_ALU_RGBA_OP_DP4; + case OPCODE_FRC: return R500_ALU_RGBA_OP_FRC; default: - ERROR("Can't handle src.File %x\n", src.File); - reg = 0x0; - break; + error("translate_rgb_op(%d): unknown opcode\n", opcode); + /* fall through */ + case OPCODE_NOP: + /* fall through */ + case OPCODE_MAD: return R500_ALU_RGBA_OP_MAD; + case OPCODE_MAX: return R500_ALU_RGBA_OP_MAX; + case OPCODE_MIN: return R500_ALU_RGBA_OP_MIN; + case OPCODE_REPL_ALPHA: return R500_ALU_RGBA_OP_SOP; } - return reg; } -static GLuint make_dest(struct r500_pfs_compile_state *cs, struct prog_dst_register dest) { - PROG_CODE; - GLuint reg; - switch (dest.File) { - case PROGRAM_TEMPORARY: - reg = dest.Index + code->temp_reg_offset; - break; - case PROGRAM_OUTPUT: - /* Eventually we may need to handle multiple - * rendering targets... */ - reg = dest.Index; - break; - case PROGRAM_BUILTIN: - reg = 0x0; - break; +static GLuint translate_alpha_op(GLuint opcode) +{ + switch(opcode) { + case OPCODE_CMP: return R500_ALPHA_OP_CMP; + case OPCODE_COS: return R500_ALPHA_OP_COS; + case OPCODE_DP3: return R500_ALPHA_OP_DP; + case OPCODE_DP4: return R500_ALPHA_OP_DP; + case OPCODE_EX2: return R500_ALPHA_OP_EX2; + case OPCODE_FRC: return R500_ALPHA_OP_FRC; + case OPCODE_LG2: return R500_ALPHA_OP_LN2; default: - ERROR("Can't handle dest.File %x\n", dest.File); - reg = 0x0; - break; + error("translate_alpha_op(%d): unknown opcode\n", opcode); + /* fall through */ + case OPCODE_NOP: + /* fall through */ + case OPCODE_MAD: return R500_ALPHA_OP_MAD; + case OPCODE_MAX: return R500_ALPHA_OP_MAX; + case OPCODE_MIN: return R500_ALPHA_OP_MIN; + case OPCODE_RCP: return R500_ALPHA_OP_RCP; + case OPCODE_RSQ: return R500_ALPHA_OP_RSQ; + case OPCODE_SIN: return R500_ALPHA_OP_SIN; } - return reg; } -static void emit_tex(struct r500_pfs_compile_state *cs, - struct prog_instruction *fpi, int dest, int counter) +static GLuint fix_hw_swizzle(GLuint swz) { - PROG_CODE; - int hwsrc, hwdest; - GLuint mask; - - mask = fpi->DstReg.WriteMask << 11; - hwsrc = make_src(cs, fpi->SrcReg[0]); - - if (fpi->DstReg.File == PROGRAM_OUTPUT) { - hwdest = get_temp(cs, 0); - } else { - hwdest = dest; - } - - code->inst[counter].inst0 = R500_INST_TYPE_TEX | mask - | R500_INST_TEX_SEM_WAIT; - - code->inst[counter].inst1 = R500_TEX_ID(fpi->TexSrcUnit) - | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED; - - if (fpi->TexSrcTarget == TEXTURE_RECT_INDEX) - code->inst[counter].inst1 |= R500_TEX_UNSCALED; - - switch (fpi->Opcode) { - case OPCODE_KIL: - code->inst[counter].inst1 |= R500_TEX_INST_TEXKILL; - break; - case OPCODE_TEX: - code->inst[counter].inst1 |= R500_TEX_INST_LD; - break; - case OPCODE_TXB: - code->inst[counter].inst1 |= R500_TEX_INST_LODBIAS; - break; - case OPCODE_TXP: - code->inst[counter].inst1 |= R500_TEX_INST_PROJ; - break; - default: - ERROR("emit_tex can't handle opcode %x\n", fpi->Opcode); - } - - code->inst[counter].inst2 = R500_TEX_SRC_ADDR(hwsrc) - | MAKE_SWIZ_TEX_STRQ(make_strq_swizzle(fpi->SrcReg[0])) - /* | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G - | R500_TEX_SRC_R_SWIZ_B | R500_TEX_SRC_Q_SWIZ_A */ - | R500_TEX_DST_ADDR(hwdest) - | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G - | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A; - - code->inst[counter].inst3 = 0x0; - code->inst[counter].inst4 = 0x0; - code->inst[counter].inst5 = 0x0; - - if (fpi->DstReg.File == PROGRAM_OUTPUT) { - counter++; - code->inst[counter].inst0 = R500_INST_TYPE_OUT - | R500_INST_TEX_SEM_WAIT | (mask << 4); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB) - | R500_ALU_RGB_SEL_B_SRC0 - | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_RGB) - | R500_ALU_RGB_OMOD_DISABLE; - code->inst[counter].inst4 = R500_ALPHA_OP_CMP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_ALPHA_SWIZ_A_A) - | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(R500_ALPHA_SWIZ_A_A) - | R500_ALPHA_OMOD_DISABLE; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP - | R500_ALU_RGBA_ADDRD(dest) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - } + if (swz == 5) swz = 6; + if (swz == SWIZZLE_NIL) swz = 4; + return swz; } -static void emit_alu(struct r500_pfs_compile_state *cs, int counter, struct prog_instruction *fpi) { - PROG_CODE; - /* Ideally, we shouldn't have to explicitly clear memory here! */ - code->inst[counter].inst0 = 0x0; - code->inst[counter].inst1 = 0x0; - code->inst[counter].inst2 = 0x0; - code->inst[counter].inst3 = 0x0; - code->inst[counter].inst4 = 0x0; - code->inst[counter].inst5 = 0x0; - - if (fpi->DstReg.File == PROGRAM_OUTPUT) { - code->inst[counter].inst0 = R500_INST_TYPE_OUT; - - if (fpi->DstReg.Index == FRAG_RESULT_COLR) - code->inst[counter].inst0 |= (fpi->DstReg.WriteMask << 15); +static GLuint translate_arg_rgb(struct radeon_pair_instruction *inst, int arg) +{ + GLuint t = inst->RGB.Arg[arg].Source; + int comp; + t |= inst->RGB.Arg[arg].Negate << 11; + t |= inst->RGB.Arg[arg].Abs << 12; - if (fpi->DstReg.Index == FRAG_RESULT_DEPR) { - code->inst[counter].inst4 |= R500_ALPHA_W_OMASK; - /* Notify the state emission! */ - cs->compiler->fp->writes_depth = GL_TRUE; - } - } else { - code->inst[counter].inst0 = R500_INST_TYPE_ALU - /* pixel_mask */ - | (fpi->DstReg.WriteMask << 11); - } + for(comp = 0; comp < 3; ++comp) + t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2); - code->inst[counter].inst0 |= R500_INST_TEX_SEM_WAIT; + return t; } -static void emit_mov(struct r500_pfs_compile_state *cs, int counter, struct prog_instruction *fpi, GLuint src_reg, GLuint swizzle, GLuint dest) { - PROG_CODE; - /* The r3xx shader uses MAD to implement MOV. We are using CMP, since - * it is technically more accurate and recommended by ATI/AMD. */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src_reg); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src_reg); - /* (De)mangle the swizzle from Mesa to R500. */ - swizzle = make_rgba_swizzle(swizzle); - /* 0x1FF is 9 bits, size of an RGB swizzle. */ - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A((swizzle & 0x1ff)) - | R500_ALU_RGB_SEL_B_SRC0 - | MAKE_SWIZ_RGB_B((swizzle & 0x1ff)) - | R500_ALU_RGB_OMOD_DISABLE; - code->inst[counter].inst4 |= R500_ALPHA_OP_CMP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(GET_SWZ(swizzle, 3)) - | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(GET_SWZ(swizzle, 3)) - | R500_ALPHA_OMOD_DISABLE; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP - | R500_ALU_RGBA_ADDRD(dest) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); +static GLuint translate_arg_alpha(struct radeon_pair_instruction *inst, int i) +{ + GLuint t = inst->Alpha.Arg[i].Source; + t |= fix_hw_swizzle(inst->Alpha.Arg[i].Swizzle) << 2; + t |= inst->Alpha.Arg[i].Negate << 5; + t |= inst->Alpha.Arg[i].Abs << 6; + return t; } -static void emit_mad(struct r500_pfs_compile_state *cs, int counter, struct prog_instruction *fpi, int one, int two, int three) { - PROG_CODE; - /* Note: This code was all Corbin's. Corbin is a rather hackish coder. - * If you can make it pretty or fast, please do so! */ - emit_alu(cs, counter, fpi); - /* Common MAD stuff */ - code->inst[counter].inst4 |= R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(make_dest(cs, fpi->DstReg)); - code->inst[counter].inst5 |= R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(make_dest(cs, fpi->DstReg)); - switch (one) { - case 0: - case 1: - case 2: - code->inst[counter].inst1 |= R500_RGB_ADDR0(make_src(cs, fpi->SrcReg[one])); - code->inst[counter].inst2 |= R500_ALPHA_ADDR0(make_src(cs, fpi->SrcReg[one])); - code->inst[counter].inst3 |= R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[one])); - code->inst[counter].inst4 |= R500_ALPHA_SEL_A_SRC0 - | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[one])); - break; - case R500_SWIZZLE_ZERO: - code->inst[counter].inst3 |= MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ZERO); - code->inst[counter].inst4 |= MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ZERO); - break; - case R500_SWIZZLE_ONE: - code->inst[counter].inst3 |= MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE); - code->inst[counter].inst4 |= MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE); - break; - default: - ERROR("Bad src index in emit_mad: %d\n", one); - break; - } - switch (two) { - case 0: - case 1: - case 2: - code->inst[counter].inst1 |= R500_RGB_ADDR1(make_src(cs, fpi->SrcReg[two])); - code->inst[counter].inst2 |= R500_ALPHA_ADDR1(make_src(cs, fpi->SrcReg[two])); - code->inst[counter].inst3 |= R500_ALU_RGB_SEL_B_SRC1 - | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[two])); - code->inst[counter].inst4 |= R500_ALPHA_SEL_B_SRC1 - | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[two])); - break; - case R500_SWIZZLE_ZERO: - code->inst[counter].inst3 |= MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ZERO); - code->inst[counter].inst4 |= MAKE_SWIZ_ALPHA_B(R500_SWIZZLE_ZERO); - break; - case R500_SWIZZLE_ONE: - code->inst[counter].inst3 |= MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE); - code->inst[counter].inst4 |= MAKE_SWIZ_ALPHA_B(R500_SWIZZLE_ONE); - break; - default: - ERROR("Bad src index in emit_mad: %d\n", two); - break; - } - switch (three) { - case 0: - case 1: - case 2: - code->inst[counter].inst1 |= R500_RGB_ADDR2(make_src(cs, fpi->SrcReg[three])); - code->inst[counter].inst2 |= R500_ALPHA_ADDR2(make_src(cs, fpi->SrcReg[three])); - code->inst[counter].inst5 |= R500_ALU_RGBA_SEL_C_SRC2 - | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[three])) - | R500_ALU_RGBA_ALPHA_SEL_C_SRC2 - | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[three])); - break; - case R500_SWIZZLE_ZERO: - code->inst[counter].inst5 |= MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - break; - case R500_SWIZZLE_ONE: - code->inst[counter].inst5 |= MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ONE) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ONE); - break; - default: - ERROR("Bad src index in emit_mad: %d\n", three); - break; - } +static void use_temporary(struct r500_fragment_program_code* code, GLuint index) +{ + if (index > code->max_temp_idx) + code->max_temp_idx = index; } -static void emit_sop(struct r500_pfs_compile_state *cs, int counter, struct prog_instruction *fpi, int opcode, GLuint src, GLuint swiz, GLuint dest) { - PROG_CODE; - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src); - code->inst[counter].inst4 |= R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(swiz); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP - | R500_ALU_RGBA_ADDRD(dest); - switch (opcode) { - case OPCODE_COS: - code->inst[counter].inst4 |= R500_ALPHA_OP_COS; - break; - case OPCODE_EX2: - code->inst[counter].inst4 |= R500_ALPHA_OP_EX2; - break; - case OPCODE_LG2: - code->inst[counter].inst4 |= R500_ALPHA_OP_LN2; - break; - case OPCODE_RCP: - code->inst[counter].inst4 |= R500_ALPHA_OP_RCP; - break; - case OPCODE_RSQ: - code->inst[counter].inst4 |= R500_ALPHA_OP_RSQ; - break; - case OPCODE_SIN: - code->inst[counter].inst4 |= R500_ALPHA_OP_SIN; - break; - default: - ERROR("Bad opcode in emit_sop: %d\n", opcode); - break; - } +static GLuint use_source(struct r500_fragment_program_code* code, struct radeon_pair_instruction_source src) +{ + if (!src.Constant) + use_temporary(code, src.Index); + return src.Index | src.Constant << 8; } -static int do_inst(struct r500_pfs_compile_state *cs, struct prog_instruction *fpi, int counter) { - PROG_CODE; - GLuint src[3], dest = 0; - int temp_swiz = 0; - if (fpi->Opcode != OPCODE_KIL) { - dest = make_dest(cs, fpi->DstReg); - } - - switch (fpi->Opcode) { - case OPCODE_ABS: - emit_mov(cs, counter, fpi, make_src(cs, fpi->SrcReg[0]), fpi->SrcReg[0].Swizzle, dest); - code->inst[counter].inst3 |= R500_ALU_RGB_MOD_A_ABS - | R500_ALU_RGB_MOD_B_ABS; - code->inst[counter].inst4 |= R500_ALPHA_MOD_A_ABS - | R500_ALPHA_MOD_B_ABS; - break; - case OPCODE_ADD: - /* Variation on MAD: 1*src0+src1 */ - emit_mad(cs, counter, fpi, R500_SWIZZLE_ONE, 0, 1); - break; - case OPCODE_CMP: - /* This inst's selects need to be swapped as follows: - * 0 -> C ; 1 -> B ; 2 -> A */ - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - src[2] = make_src(cs, fpi->SrcReg[2]); - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[2]) - | R500_RGB_ADDR1(src[1]) | R500_RGB_ADDR2(src[0]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[2]) - | R500_ALPHA_ADDR1(src[1]) | R500_ALPHA_ADDR2(src[0]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[2])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 |= R500_ALPHA_OP_CMP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[2])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC2 - | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGBA_ALPHA_SEL_C_SRC2 - | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[0])); - break; - case OPCODE_COS: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = emit_const4fv(cs, RCP_2PI); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_FRC - | R500_ALPHA_ADDRD(get_temp(cs, 1)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC - | R500_ALU_RGBA_ADDRD(get_temp(cs, 1)); - counter++; - emit_sop(cs, counter, fpi, OPCODE_COS, get_temp(cs, 1), make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_DP3: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 |= R500_ALPHA_OP_DP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_DP3 - | R500_ALU_RGBA_ADDRD(dest); - break; - case OPCODE_DP4: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - /* Based on DP3 */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 |= R500_ALPHA_OP_DP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4 - | R500_ALU_RGBA_ADDRD(dest); - break; - case OPCODE_DPH: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - /* Based on DP3 */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 |= R500_ALPHA_OP_DP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4 - | R500_ALU_RGBA_ADDRD(dest); - break; - case OPCODE_DST: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - /* [1, src0.y*src1.y, src0.z, src1.w] - * So basically MUL with lotsa swizzling. */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | R500_ALU_RGB_SEL_B_SRC1; - /* Select [1, y, z, 1] */ - temp_swiz = (make_rgb_swizzle(fpi->SrcReg[0]) & ~0x7) | R500_SWIZZLE_ONE; - code->inst[counter].inst3 |= MAKE_SWIZ_RGB_A(temp_swiz); - /* Select [1, y, 1, w] */ - temp_swiz = (make_rgb_swizzle(fpi->SrcReg[0]) & ~0x1c7) | R500_SWIZZLE_ONE | (R500_SWIZZLE_ONE << 6); - code->inst[counter].inst3 |= MAKE_SWIZ_RGB_B(temp_swiz); - code->inst[counter].inst4 |= R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(dest) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - break; - case OPCODE_EX2: - src[0] = make_src(cs, fpi->SrcReg[0]); - emit_sop(cs, counter, fpi, OPCODE_EX2, src[0], make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_FLR: - src[0] = make_src(cs, fpi->SrcReg[0]); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst4 |= R500_ALPHA_OP_FRC - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)); - counter++; - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(get_temp(cs, 0)); - code->inst[counter].inst3 = MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE) - | R500_ALU_RGB_SEL_B_SRC0 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SWIZ_A_A - | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC1 - | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGBA_ALPHA_SEL_C_SRC1 - | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGBA_MOD_C_NEG; - break; - case OPCODE_FRC: - src[0] = make_src(cs, fpi->SrcReg[0]); - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst4 |= R500_ALPHA_OP_FRC - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC - | R500_ALU_RGBA_ADDRD(dest); - break; - case OPCODE_LG2: - src[0] = make_src(cs, fpi->SrcReg[0]); - emit_sop(cs, counter, fpi, OPCODE_LG2, src[0], make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_LIT: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = emit_const4fv(cs, LIT); - /* First inst: MAX temp, input, [0, 0, 0, -128] - * Write: RG, A */ - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_ARG << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ZERO); - code->inst[counter].inst4 = R500_ALPHA_OP_MAX - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)); - counter++; - /* Second inst: MIN temp, temp, [x, x, x, 128] - * Write: A */ - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_A << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)) | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)) | R500_ALPHA_ADDR1(src[1]); - /* code->inst[counter].inst3; */ - code->inst[counter].inst4 = R500_ALPHA_OP_MAX - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX - | R500_ALU_RGBA_ADDRD(dest); - counter++; - /* Third-fifth insts: POW temp, temp.y, temp.w - * Write: B */ - emit_sop(cs, counter, fpi, OPCODE_LG2, get_temp(cs, 0), SWIZZLE_Y, get_temp(cs, 1)); - code->inst[counter].inst0 |= (R500_WRITEMASK_ARGB << 11); - counter++; - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 1)) - | R500_RGB_ADDR1(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 1)) - | R500_ALPHA_ADDR1(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 1)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 1)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - emit_sop(cs, counter, fpi, OPCODE_EX2, get_temp(cs, 1), SWIZZLE_W, get_temp(cs, 0)); - code->inst[counter].inst0 |= (R500_WRITEMASK_B << 11); - counter++; - /* Sixth inst: CMP dest, temp.xxxx, temp.[1, x, z, 1], temp.[1, x, 0, 1]; - * Write: ARGB - * This inst's selects need to be swapped as follows: - * 0 -> C ; 1 -> B ; 2 -> A */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | R500_ALU_RGB_R_SWIZ_A_1 - | R500_ALU_RGB_G_SWIZ_A_R - | R500_ALU_RGB_B_SWIZ_A_B - | R500_ALU_RGB_SEL_B_SRC0 - | R500_ALU_RGB_R_SWIZ_B_1 - | R500_ALU_RGB_G_SWIZ_B_R - | R500_ALU_RGB_B_SWIZ_B_0; - code->inst[counter].inst4 |= R500_ALPHA_OP_CMP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_1 - | R500_ALPHA_SEL_B_SRC0 | R500_ALPHA_SWIZ_B_1; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC0 - | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 - | R500_ALU_RGBA_R_SWIZ_R - | R500_ALU_RGBA_G_SWIZ_R - | R500_ALU_RGBA_B_SWIZ_R - | R500_ALU_RGBA_A_SWIZ_R; - break; - case OPCODE_LRP: - /* src0 * src1 + INV(src0) * src2 - * 1) MUL src0, src1, temp - * 2) PRE 1-src0; MAD srcp, src2, temp */ - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - src[2] = make_src(cs, fpi->SrcReg[2]); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | R500_INST_NOP | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[2]) - | R500_RGB_ADDR2(get_temp(cs, 0)) - | R500_RGB_SRCP_OP_1_MINUS_RGB0; - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[2]) - | R500_ALPHA_ADDR2(get_temp(cs, 0)) - | R500_ALPHA_SRCP_OP_1_MINUS_A0; - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRCP - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 |= R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRCP | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC2 | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[2])) - | R500_ALU_RGBA_ALPHA_SEL_C_SRC2 - | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[2])); - break; - case OPCODE_MAD: - emit_mad(cs, counter, fpi, 0, 1, 2); - break; - case OPCODE_MAX: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 - | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 |= R500_ALPHA_OP_MAX - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAX - | R500_ALU_RGBA_ADDRD(dest); - break; - case OPCODE_MIN: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 - | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 |= R500_ALPHA_OP_MIN - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MIN - | R500_ALU_RGBA_ADDRD(dest); - break; - case OPCODE_MOV: - emit_mov(cs, counter, fpi, make_src(cs, fpi->SrcReg[0]), fpi->SrcReg[0].Swizzle, dest); - break; - case OPCODE_MUL: - /* Variation on MAD: src0*src1+0 */ - emit_mad(cs, counter, fpi, 0, 1, R500_SWIZZLE_ZERO); - break; - case OPCODE_POW: - /* POW(a,b) = EX2(LN2(a)*b) */ - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - emit_sop(cs, counter, fpi, OPCODE_LG2, src[0], make_sop_swizzle(fpi->SrcReg[0]), get_temp(cs, 0)); - code->inst[counter].inst0 |= (R500_WRITEMASK_ARGB << 11); - counter++; - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0])) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 1)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 1)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - emit_sop(cs, counter, fpi, OPCODE_EX2, get_temp(cs, 1), make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_RCP: - src[0] = make_src(cs, fpi->SrcReg[0]); - emit_sop(cs, counter, fpi, OPCODE_RCP, src[0], make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_RSQ: - src[0] = make_src(cs, fpi->SrcReg[0]); - emit_sop(cs, counter, fpi, OPCODE_RSQ, src[0], make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_SCS: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = emit_const4fv(cs, RCP_2PI); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_FRC - | R500_ALPHA_ADDRD(get_temp(cs, 1)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC - | R500_ALU_RGBA_ADDRD(get_temp(cs, 1)); - counter++; - /* Do a cosine, then a sine, masking out the channels we want to protect. */ - /* Cosine only goes in R (x) channel. */ - fpi->DstReg.WriteMask = 0x1; - emit_sop(cs, counter, fpi, OPCODE_COS, get_temp(cs, 1), make_sop_swizzle(fpi->SrcReg[0]), dest); - counter++; - /* Sine only goes in G (y) channel. */ - fpi->DstReg.WriteMask = 0x2; - emit_sop(cs, counter, fpi, OPCODE_SIN, get_temp(cs, 1), make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_SGE: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR1(src[0]) - | R500_RGB_ADDR2(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR1(src[0]) - | R500_ALPHA_ADDR2(src[1]); - code->inst[counter].inst3 = /* 1 */ - MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | R500_ALU_RGBA_SEL_C_SRC2 - | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1])) - | R500_ALU_RGBA_MOD_C_NEG - | R500_ALU_RGBA_ALPHA_SEL_C_SRC2 - | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1])) - | R500_ALU_RGBA_ALPHA_MOD_C_NEG; - counter++; - /* This inst's selects need to be swapped as follows: - * 0 -> C ; 1 -> B ; 2 -> A */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE) - | R500_ALU_RGB_SEL_B_SRC0 - | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ZERO); - code->inst[counter].inst4 |= R500_ALPHA_OP_CMP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE) - | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(R500_SWIZZLE_ZERO); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC0 - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_RGB) - | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 - | R500_ALU_RGBA_A_SWIZ_A; - break; - case OPCODE_SIN: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = emit_const4fv(cs, RCP_2PI); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A - | R500_ALPHA_SEL_B_SRC1 | R500_ALPHA_SWIZ_B_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - code->inst[counter].inst0 = R500_INST_TYPE_ALU | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_RGB); - code->inst[counter].inst4 = R500_ALPHA_OP_FRC - | R500_ALPHA_ADDRD(get_temp(cs, 1)) - | R500_ALPHA_SEL_A_SRC0 | R500_ALPHA_SWIZ_A_A; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC - | R500_ALU_RGBA_ADDRD(get_temp(cs, 1)); - counter++; - emit_sop(cs, counter, fpi, OPCODE_SIN, get_temp(cs, 1), make_sop_swizzle(fpi->SrcReg[0]), dest); - break; - case OPCODE_SLT: - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_ARGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR1(src[0]) - | R500_RGB_ADDR2(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR1(src[0]) - | R500_ALPHA_ADDR2(src[1]); - code->inst[counter].inst3 = /* 1 */ - MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ONE) - | R500_ALU_RGB_SEL_B_SRC1 | MAKE_SWIZ_RGB_B(make_rgb_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ONE) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[0])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | R500_ALU_RGBA_SEL_C_SRC2 - | MAKE_SWIZ_RGBA_C(make_rgb_swizzle(fpi->SrcReg[1])) - | R500_ALU_RGBA_MOD_C_NEG - | R500_ALU_RGBA_ALPHA_SEL_C_SRC2 - | MAKE_SWIZ_ALPHA_C(make_alpha_swizzle(fpi->SrcReg[1])) - | R500_ALU_RGBA_ALPHA_MOD_C_NEG; - counter++; - /* This inst's selects need to be swapped as follows: - * 0 -> C ; 1 -> B ; 2 -> A */ - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(get_temp(cs, 0)); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(R500_SWIZ_RGB_ZERO) - | R500_ALU_RGB_SEL_B_SRC0 - | MAKE_SWIZ_RGB_B(R500_SWIZ_RGB_ONE); - code->inst[counter].inst4 |= R500_ALPHA_OP_CMP - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(R500_SWIZZLE_ZERO) - | R500_ALPHA_SEL_B_SRC0 | MAKE_SWIZ_ALPHA_B(R500_SWIZZLE_ONE); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_CMP - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC0 - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_RGB) - | R500_ALU_RGBA_ALPHA_SEL_C_SRC0 - | R500_ALU_RGBA_A_SWIZ_A; - break; - case OPCODE_SUB: - /* Variation on MAD: 1*src0-src1 */ - fpi->SrcReg[1].NegateBase = 0xF; /* NEG_XYZW */ - emit_mad(cs, counter, fpi, R500_SWIZZLE_ONE, 0, 1); - break; - case OPCODE_SWZ: - /* TODO: The rarer negation masks! */ - emit_mov(cs, counter, fpi, make_src(cs, fpi->SrcReg[0]), fpi->SrcReg[0].Swizzle, dest); - break; - case OPCODE_XPD: - /* src0 * src1 - src1 * src0 - * 1) MUL temp.xyz, src0.yzx, src1.zxy - * 2) MAD src0.zxy, src1.yzx, -temp.xyz */ - src[0] = make_src(cs, fpi->SrcReg[0]); - src[1] = make_src(cs, fpi->SrcReg[1]); - code->inst[counter].inst0 = R500_INST_TYPE_ALU | R500_INST_TEX_SEM_WAIT - | (R500_WRITEMASK_RGB << 11); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]); - /* Select [y, z, x] */ - temp_swiz = make_rgb_swizzle(fpi->SrcReg[0]); - temp_swiz = (GET_SWZ(temp_swiz, 1) << 0) | (GET_SWZ(temp_swiz, 2) << 3) | (GET_SWZ(temp_swiz, 0) << 6); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(temp_swiz); - /* Select [z, x, y] */ - temp_swiz = make_rgb_swizzle(fpi->SrcReg[1]); - temp_swiz = (GET_SWZ(temp_swiz, 2) << 0) | (GET_SWZ(temp_swiz, 0) << 3) | (GET_SWZ(temp_swiz, 1) << 6); - code->inst[counter].inst3 |= R500_ALU_RGB_SEL_B_SRC1 - | MAKE_SWIZ_RGB_B(temp_swiz); - code->inst[counter].inst4 = R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(get_temp(cs, 0)) - | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0])) - | R500_ALPHA_SEL_B_SRC1 | MAKE_SWIZ_ALPHA_B(make_alpha_swizzle(fpi->SrcReg[1])); - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(get_temp(cs, 0)) - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_ZERO) - | MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO); - counter++; - emit_alu(cs, counter, fpi); - code->inst[counter].inst1 = R500_RGB_ADDR0(src[0]) - | R500_RGB_ADDR1(src[1]) - | R500_RGB_ADDR2(get_temp(cs, 0)); - code->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]) - | R500_ALPHA_ADDR1(src[1]) - | R500_ALPHA_ADDR2(get_temp(cs, 0)); - /* Select [z, x, y] */ - temp_swiz = make_rgb_swizzle(fpi->SrcReg[0]); - temp_swiz = (GET_SWZ(temp_swiz, 2) << 0) | (GET_SWZ(temp_swiz, 0) << 3) | (GET_SWZ(temp_swiz, 1) << 6); - code->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0 - | MAKE_SWIZ_RGB_A(temp_swiz); - /* Select [y, z, x] */ - temp_swiz = make_rgb_swizzle(fpi->SrcReg[1]); - temp_swiz = (GET_SWZ(temp_swiz, 1) << 0) | (GET_SWZ(temp_swiz, 2) << 3) | (GET_SWZ(temp_swiz, 0) << 6); - code->inst[counter].inst3 |= R500_ALU_RGB_SEL_B_SRC1 - | MAKE_SWIZ_RGB_B(temp_swiz); - code->inst[counter].inst4 |= R500_ALPHA_OP_MAD - | R500_ALPHA_ADDRD(dest) - | R500_ALPHA_SWIZ_A_1 - | R500_ALPHA_SWIZ_B_1; - code->inst[counter].inst5 = R500_ALU_RGBA_OP_MAD - | R500_ALU_RGBA_ADDRD(dest) - | R500_ALU_RGBA_SEL_C_SRC2 - | MAKE_SWIZ_RGBA_C(R500_SWIZ_RGB_RGB) - | R500_ALU_RGBA_MOD_C_NEG - | R500_ALU_RGBA_A_SWIZ_0; - break; - case OPCODE_KIL: - case OPCODE_TEX: - case OPCODE_TXB: - case OPCODE_TXP: - emit_tex(cs, fpi, dest, counter); - if (fpi->DstReg.File == PROGRAM_OUTPUT) - counter++; - break; - default: - ERROR("unknown fpi->Opcode %s\n", _mesa_opcode_string(fpi->Opcode)); - break; - } +/** + * Emit a paired ALU instruction. + */ +static GLboolean emit_paired(void *data, struct radeon_pair_instruction *inst) +{ + PROG_CODE; - /* Finishing touches */ - if (fpi->SaturateMode == SATURATE_ZERO_ONE) { - code->inst[counter].inst0 |= R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP; + if (code->inst_end >= 511) { + error("emit_alu: Too many instructions"); + return GL_FALSE; } - counter++; + int ip = ++code->inst_end; - return counter; -} + code->inst[ip].inst5 = translate_rgb_op(inst->RGB.Opcode); + code->inst[ip].inst4 = translate_alpha_op(inst->Alpha.Opcode); -static GLboolean parse_program(struct r500_pfs_compile_state *cs) -{ - PROG_CODE; - int clauseidx, counter = 0; + if (inst->RGB.OutputWriteMask || inst->Alpha.OutputWriteMask || inst->Alpha.DepthWriteMask) + code->inst[ip].inst0 = R500_INST_TYPE_OUT; + else + code->inst[ip].inst0 = R500_INST_TYPE_ALU; + code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT; - for (clauseidx = 0; clauseidx < cs->compiler->compiler.NumClauses; clauseidx++) { - struct radeon_clause* clause = &cs->compiler->compiler.Clauses[clauseidx]; - struct prog_instruction* fpi; + code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14); + code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18); + if (inst->Alpha.DepthWriteMask) { + code->inst[ip].inst4 |= R500_ALPHA_W_OMASK; + c->fp->writes_depth = GL_TRUE; + } - int ip; + code->inst[ip].inst4 |= R500_ALPHA_ADDRD(inst->Alpha.DestIndex); + code->inst[ip].inst5 |= R500_ALU_RGBA_ADDRD(inst->RGB.DestIndex); + use_temporary(code, inst->Alpha.DestIndex); + use_temporary(code, inst->RGB.DestIndex); - for (ip = 0; ip < clause->NumInstructions; ip++) { - fpi = clause->Instructions + ip; - counter = do_inst(cs, fpi, counter); + if (inst->RGB.Saturate) + code->inst[ip].inst0 |= R500_INST_RGB_CLAMP; + if (inst->Alpha.Saturate) + code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP; - if (cs->compiler->fp->error) - return GL_FALSE; - } - } + code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0])); + code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1])); + code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2])); - /* Finish him! (If it's an ALU/OUT instruction...) */ - if ((code->inst[counter-1].inst0 & 0x3) == 1) { - code->inst[counter-1].inst0 |= R500_INST_LAST; - } else { - /* We still need to put an output inst, right? */ - WARN_ONCE("Final FP instruction is not an OUT.\n"); - } + code->inst[ip].inst2 |= R500_ALPHA_ADDR0(use_source(code, inst->Alpha.Src[0])); + code->inst[ip].inst2 |= R500_ALPHA_ADDR1(use_source(code, inst->Alpha.Src[1])); + code->inst[ip].inst2 |= R500_ALPHA_ADDR2(use_source(code, inst->Alpha.Src[2])); - cs->nrslots = counter; + code->inst[ip].inst3 |= translate_arg_rgb(inst, 0) << R500_ALU_RGB_SEL_A_SHIFT; + code->inst[ip].inst3 |= translate_arg_rgb(inst, 1) << R500_ALU_RGB_SEL_B_SHIFT; + code->inst[ip].inst5 |= translate_arg_rgb(inst, 2) << R500_ALU_RGBA_SEL_C_SHIFT; - code->max_temp_idx++; + code->inst[ip].inst4 |= translate_arg_alpha(inst, 0) << R500_ALPHA_SEL_A_SHIFT; + code->inst[ip].inst4 |= translate_arg_alpha(inst, 1) << R500_ALPHA_SEL_B_SHIFT; + code->inst[ip].inst5 |= translate_arg_alpha(inst, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT; return GL_TRUE; } -static void init_program(struct r500_pfs_compile_state *cs) +static GLuint translate_strq_swizzle(struct prog_src_register src) { - PROG_CODE; - struct gl_fragment_program *mp = &cs->compiler->fp->mesa_program; - struct prog_instruction *fpi; - GLuint InputsRead = mp->Base.InputsRead; - GLuint temps_used = 0; - int i, j; - - /* New compile, reset tracking data */ - cs->compiler->fp->optimization = - driQueryOptioni(&cs->compiler->r300->radeon.optionCache, "fp_optimization"); - cs->compiler->fp->translated = GL_FALSE; - cs->compiler->fp->error = GL_FALSE; - code->const_nr = 0; - /* Size of pixel stack, plus 1. */ - code->max_temp_idx = 1; - /* Temp register offset. */ - code->temp_reg_offset = 0; - /* Whether or not we perform any depth writing. */ - cs->compiler->fp->writes_depth = GL_FALSE; - - for (i = 0; i < PFS_MAX_ALU_INST; i++) { - for (j = 0; j < 3; j++) { - cs->slot[i].vsrc[j] = SRC_CONST; - cs->slot[i].ssrc[j] = SRC_CONST; - } - } - - /* Work out what temps the Mesa inputs correspond to, this must match - * what setup_rs_unit does, which shouldn't be a problem as rs_unit - * configures itself based on the fragprog's InputsRead - * - * NOTE: this depends on get_hw_temp() allocating registers in order, - * starting from register 0, so we're just going to do that instead. - */ - - /* Texcoords come first */ - for (i = 0; i < cs->compiler->fp->ctx->Const.MaxTextureUnits; i++) { - if (InputsRead & (FRAG_BIT_TEX0 << i)) { - cs->inputs[FRAG_ATTRIB_TEX0 + i].refcount = 0; - cs->inputs[FRAG_ATTRIB_TEX0 + i].reg = - code->temp_reg_offset; - code->temp_reg_offset++; - } - } - InputsRead &= ~FRAG_BITS_TEX_ANY; - - /* fragment position treated as a texcoord */ - if (InputsRead & FRAG_BIT_WPOS) { - cs->inputs[FRAG_ATTRIB_WPOS].refcount = 0; - cs->inputs[FRAG_ATTRIB_WPOS].reg = - code->temp_reg_offset; - code->temp_reg_offset++; - } - InputsRead &= ~FRAG_BIT_WPOS; + GLuint swiz = 0; + int i; + for (i = 0; i < 4; i++) + swiz |= (GET_SWZ(src.Swizzle, i) & 0x3) << i*2; + return swiz; +} - /* Then primary colour */ - if (InputsRead & FRAG_BIT_COL0) { - cs->inputs[FRAG_ATTRIB_COL0].refcount = 0; - cs->inputs[FRAG_ATTRIB_COL0].reg = - code->temp_reg_offset; - code->temp_reg_offset++; - } - InputsRead &= ~FRAG_BIT_COL0; +/** + * Emit a single TEX instruction + */ +static GLboolean emit_tex(void *data, struct prog_instruction *inst) +{ + PROG_CODE; - /* Secondary color */ - if (InputsRead & FRAG_BIT_COL1) { - cs->inputs[FRAG_ATTRIB_COL1].refcount = 0; - cs->inputs[FRAG_ATTRIB_COL1].reg = - code->temp_reg_offset; - code->temp_reg_offset++; + if (code->inst_end >= 511) { + error("emit_tex: Too many instructions"); + return GL_FALSE; } - InputsRead &= ~FRAG_BIT_COL1; - /* Anything else */ - if (InputsRead) { - WARN_ONCE("Don't know how to handle inputs 0x%x\n", InputsRead); - /* force read from hwreg 0 for now */ - for (i = 0; i < 32; i++) - if (InputsRead & (1 << i)) - cs->inputs[i].reg = 0; - } + int ip = ++code->inst_end; - int clauseidx; + code->inst[ip].inst0 = R500_INST_TYPE_TEX + | (inst->DstReg.WriteMask << 11) + | R500_INST_TEX_SEM_WAIT; + code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit) + | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED; - for (clauseidx = 0; clauseidx < cs->compiler->compiler.NumClauses; ++clauseidx) { - struct radeon_clause* clause = &cs->compiler->compiler.Clauses[clauseidx]; - int ip; + if (inst->TexSrcTarget == TEXTURE_RECT_INDEX) + code->inst[ip].inst1 |= R500_TEX_UNSCALED; - for (ip = 0; ip < clause->NumInstructions; ip++) { - fpi = clause->Instructions + ip; - for (i = 0; i < 3; i++) { - if (fpi->SrcReg[i].File == PROGRAM_TEMPORARY) { - if (fpi->SrcReg[i].Index >= temps_used) - temps_used = fpi->SrcReg[i].Index + 1; - } - } - } + switch (inst->Opcode) { + case OPCODE_KIL: + code->inst[ip].inst1 |= R500_TEX_INST_TEXKILL; + break; + case OPCODE_TEX: + code->inst[ip].inst1 |= R500_TEX_INST_LD; + break; + case OPCODE_TXB: + code->inst[ip].inst1 |= R500_TEX_INST_LODBIAS; + break; + case OPCODE_TXP: + code->inst[ip].inst1 |= R500_TEX_INST_PROJ; + break; + default: + error("emit_tex can't handle opcode %x\n", inst->Opcode); } + code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index) + | (translate_strq_swizzle(inst->SrcReg[0]) << 8) + | R500_TEX_DST_ADDR(inst->DstReg.Index) + | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G + | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A; - cs->temp_in_use = temps_used + 1; - - code->max_temp_idx = code->temp_reg_offset + cs->temp_in_use; - - if (RADEON_DEBUG & DEBUG_PIXEL) - fprintf(stderr, "FP temp indices: code->max_temp_idx: %d cs->temp_in_use: %d\n", code->max_temp_idx, cs->temp_in_use); + return GL_TRUE; } -static void dumb_shader(struct r500_pfs_compile_state *cs) -{ - PROG_CODE; - code->inst[0].inst0 = R500_INST_TYPE_TEX - | R500_INST_TEX_SEM_WAIT - | R500_INST_RGB_WMASK_R - | R500_INST_RGB_WMASK_G - | R500_INST_RGB_WMASK_B - | R500_INST_ALPHA_WMASK - | R500_INST_RGB_CLAMP - | R500_INST_ALPHA_CLAMP; - code->inst[0].inst1 = R500_TEX_ID(0) - | R500_TEX_INST_LD - | R500_TEX_SEM_ACQUIRE - | R500_TEX_IGNORE_UNCOVERED; - code->inst[0].inst2 = R500_TEX_SRC_ADDR(0) - | R500_TEX_SRC_S_SWIZ_R - | R500_TEX_SRC_T_SWIZ_G - | R500_TEX_DST_ADDR(0) - | R500_TEX_DST_R_SWIZ_R - | R500_TEX_DST_G_SWIZ_G - | R500_TEX_DST_B_SWIZ_B - | R500_TEX_DST_A_SWIZ_A; - code->inst[0].inst3 = R500_DX_ADDR(0) - | R500_DX_S_SWIZ_R - | R500_DX_T_SWIZ_R - | R500_DX_R_SWIZ_R - | R500_DX_Q_SWIZ_R - | R500_DY_ADDR(0) - | R500_DY_S_SWIZ_R - | R500_DY_T_SWIZ_R - | R500_DY_R_SWIZ_R - | R500_DY_Q_SWIZ_R; - code->inst[0].inst4 = 0x0; - code->inst[0].inst5 = 0x0; - - code->inst[1].inst0 = R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK; - code->inst[1].inst1 = R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST | - R500_RGB_SRCP_OP_1_MINUS_2RGB0; - code->inst[1].inst2 = R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST | - R500_ALPHA_SRCP_OP_1_MINUS_2A0; - code->inst[1].inst3 = R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_1 | - R500_ALU_RGB_B_SWIZ_B_1 | - R500_ALU_RGB_G_SWIZ_B_1; - code->inst[1].inst4 = R500_ALPHA_OP_MAD | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_1; - code->inst[1].inst5 = R500_ALU_RGBA_OP_MAD | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0; - - cs->nrslots = 2; -} +static const struct radeon_pair_handler pair_handler = { + .EmitConst = emit_const, + .EmitPaired = emit_paired, + .EmitTex = emit_tex, + .MaxHwTemps = 128 +}; GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler) { - struct r500_pfs_compile_state cs; struct r500_fragment_program_code *code = compiler->code; - _mesa_memset(&cs, 0, sizeof(cs)); - cs.compiler = compiler; - init_program(&cs); + _mesa_bzero(code, sizeof(*code)); + code->max_temp_idx = 1; + code->inst_offset = 0; + code->inst_end = -1; - if (!parse_program(&cs)) { -#if 0 - ERROR("Huh. Couldn't parse program. There should be additional errors explaining why.\nUsing dumb shader...\n"); - dumb_shader(fp); - code->inst_offset = 0; - code->inst_end = cs.nrslots - 1; -#endif + if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler)) return GL_FALSE; - } - code->inst_offset = 0; - code->inst_end = cs.nrslots - 1; + if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) { + /* This may happen when dead-code elimination is disabled or + * when most of the fragment program logic is leading to a KIL */ + if (code->inst_end >= 511) { + error("Introducing fake OUT: Too many instructions"); + return GL_FALSE; + } + + int ip = ++code->inst_end; + code->inst[ip].inst0 = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT; + } return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r300/radeon_nqssadce.c b/src/mesa/drivers/dri/r300/radeon_nqssadce.c new file mode 100644 index 00000000000..f10ba4004aa --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_nqssadce.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/** + * @file + * + * "Not-quite SSA" and Dead-Code Elimination. + * + * @note This code uses SWIZZLE_NIL in a source register to indicate that + * the corresponding component is ignored by the corresponding instruction. + */ + +#include "radeon_nqssadce.h" + + +/** + * Return the @ref register_state for the given register (or 0 for untracked + * registers, i.e. constants). + */ +static struct register_state *get_reg_state(struct nqssadce_state* s, GLuint file, GLuint index) +{ + switch(file) { + case PROGRAM_TEMPORARY: return &s->Temps[index]; + case PROGRAM_OUTPUT: return &s->Outputs[index]; + default: return 0; + } +} + + +/** + * Left multiplication of a register with a swizzle + * + * @note Works correctly only for X, Y, Z, W swizzles, not for constant swizzles. + */ +static struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg) +{ + struct prog_src_register tmp = srcreg; + int i; + tmp.Swizzle = 0; + tmp.NegateBase = 0; + for(i = 0; i < 4; ++i) { + GLuint swz = GET_SWZ(swizzle, i); + if (swz < 4) { + tmp.Swizzle |= GET_SWZ(srcreg.Swizzle, swz) << (i*3); + tmp.NegateBase |= GET_BIT(srcreg.NegateBase, swz) << i; + } else { + tmp.Swizzle |= swz << (i*3); + } + } + return tmp; +} + + +static struct prog_instruction* track_used_srcreg(struct nqssadce_state* s, + struct prog_instruction *inst, GLint src, GLuint sourced) +{ + int i; + GLuint deswz_source = 0; + + for(i = 0; i < 4; ++i) { + if (GET_BIT(sourced, i)) { + GLuint swz = GET_SWZ(inst->SrcReg[src].Swizzle, i); + deswz_source |= 1 << swz; + } else { + inst->SrcReg[src].Swizzle &= ~(7 << (3*i)); + inst->SrcReg[src].Swizzle |= SWIZZLE_NIL << (3*i); + } + } + + if (!s->Descr->IsNativeSwizzle(inst->Opcode, inst->SrcReg[src])) { + struct prog_dst_register dstreg = inst->DstReg; + dstreg.File = PROGRAM_TEMPORARY; + dstreg.Index = _mesa_find_free_register(s->Program, PROGRAM_TEMPORARY); + dstreg.WriteMask = sourced; + + s->Descr->BuildSwizzle(s, dstreg, inst->SrcReg[src]); + + inst = s->Program->Instructions + s->IP; + inst->SrcReg[src].File = PROGRAM_TEMPORARY; + inst->SrcReg[src].Index = dstreg.Index; + inst->SrcReg[src].Swizzle = 0; + inst->SrcReg[src].NegateBase = 0; + inst->SrcReg[src].Abs = 0; + inst->SrcReg[src].NegateAbs = 0; + for(i = 0; i < 4; ++i) { + if (GET_BIT(sourced, i)) + inst->SrcReg[src].Swizzle |= i << (3*i); + else + inst->SrcReg[src].Swizzle |= SWIZZLE_NIL << (3*i); + } + deswz_source = sourced; + } + + struct register_state *regstate = get_reg_state(s, inst->SrcReg[src].File, inst->SrcReg[src].Index); + if (regstate) + regstate->Sourced |= deswz_source & 0xf; + + return inst; +} + + +static void rewrite_depth_out(struct prog_instruction *inst) +{ + if (inst->DstReg.WriteMask & WRITEMASK_Z) { + inst->DstReg.WriteMask = WRITEMASK_W; + } else { + inst->DstReg.WriteMask = 0; + return; + } + + switch (inst->Opcode) { + case OPCODE_FRC: + case OPCODE_MOV: + inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]); + break; + case OPCODE_ADD: + case OPCODE_MAX: + case OPCODE_MIN: + case OPCODE_MUL: + inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]); + inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]); + break; + case OPCODE_CMP: + case OPCODE_MAD: + inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]); + inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]); + inst->SrcReg[2] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[2]); + break; + default: + // Scalar instructions needn't be reswizzled + break; + } +} + +static void unalias_srcregs(struct prog_instruction *inst, GLuint oldindex, GLuint newindex) +{ + int nsrc = _mesa_num_inst_src_regs(inst->Opcode); + int i; + for(i = 0; i < nsrc; ++i) + if (inst->SrcReg[i].File == PROGRAM_TEMPORARY && inst->SrcReg[i].Index == oldindex) + inst->SrcReg[i].Index = newindex; +} + +static void unalias_temporary(struct nqssadce_state* s, GLuint oldindex) +{ + GLuint newindex = _mesa_find_free_register(s->Program, PROGRAM_TEMPORARY); + int ip; + for(ip = 0; ip < s->IP; ++ip) { + struct prog_instruction* inst = s->Program->Instructions + ip; + if (inst->DstReg.File == PROGRAM_TEMPORARY && inst->DstReg.Index == oldindex) + inst->DstReg.Index = newindex; + unalias_srcregs(inst, oldindex, newindex); + } + unalias_srcregs(s->Program->Instructions + s->IP, oldindex, newindex); +} + + +/** + * Handle one instruction. + */ +static void process_instruction(struct nqssadce_state* s) +{ + struct prog_instruction *inst = s->Program->Instructions + s->IP; + + if (inst->Opcode == OPCODE_END) + return; + + if (inst->Opcode != OPCODE_KIL) { + if (s->Descr->RewriteDepthOut) { + if (inst->DstReg.File == PROGRAM_OUTPUT && inst->DstReg.Index == FRAG_RESULT_DEPR) + rewrite_depth_out(inst); + } + + struct register_state *regstate = get_reg_state(s, inst->DstReg.File, inst->DstReg.Index); + if (!regstate) { + _mesa_problem(s->Ctx, "NqssaDce: bad destination register (%i[%i])\n", + inst->DstReg.File, inst->DstReg.Index); + return; + } + + inst->DstReg.WriteMask &= regstate->Sourced; + regstate->Sourced &= ~inst->DstReg.WriteMask; + + if (inst->DstReg.WriteMask == 0) { + _mesa_delete_instructions(s->Program, s->IP, 1); + return; + } + + if (inst->DstReg.File == PROGRAM_TEMPORARY && !regstate->Sourced) + unalias_temporary(s, inst->DstReg.Index); + } + + /* Attention: Due to swizzle emulation code, the following + * might change the instruction stream under us, so we have + * to be careful with the inst pointer. */ + switch (inst->Opcode) { + case OPCODE_FRC: + case OPCODE_MOV: + inst = track_used_srcreg(s, inst, 0, inst->DstReg.WriteMask); + break; + case OPCODE_ADD: + case OPCODE_MAX: + case OPCODE_MIN: + case OPCODE_MUL: + inst = track_used_srcreg(s, inst, 0, inst->DstReg.WriteMask); + inst = track_used_srcreg(s, inst, 1, inst->DstReg.WriteMask); + break; + case OPCODE_CMP: + case OPCODE_MAD: + inst = track_used_srcreg(s, inst, 0, inst->DstReg.WriteMask); + inst = track_used_srcreg(s, inst, 1, inst->DstReg.WriteMask); + inst = track_used_srcreg(s, inst, 2, inst->DstReg.WriteMask); + break; + case OPCODE_COS: + case OPCODE_EX2: + case OPCODE_LG2: + case OPCODE_RCP: + case OPCODE_RSQ: + case OPCODE_SIN: + inst = track_used_srcreg(s, inst, 0, 0x1); + break; + case OPCODE_DP3: + inst = track_used_srcreg(s, inst, 0, 0x7); + inst = track_used_srcreg(s, inst, 1, 0x7); + break; + case OPCODE_DP4: + inst = track_used_srcreg(s, inst, 0, 0xf); + inst = track_used_srcreg(s, inst, 1, 0xf); + break; + case OPCODE_KIL: + case OPCODE_TEX: + case OPCODE_TXB: + case OPCODE_TXP: + inst = track_used_srcreg(s, inst, 0, 0xf); + break; + default: + _mesa_problem(s->Ctx, "NqssaDce: Unknown opcode %d\n", inst->Opcode); + return; + } +} + + +void radeonNqssaDce(GLcontext *ctx, struct gl_program *p, struct radeon_nqssadce_descr* descr) +{ + struct nqssadce_state s; + + _mesa_bzero(&s, sizeof(s)); + s.Ctx = ctx; + s.Program = p; + s.Descr = descr; + s.Descr->Init(&s); + s.IP = p->NumInstructions; + + while(s.IP > 0) { + s.IP--; + process_instruction(&s); + } +} diff --git a/src/mesa/drivers/dri/r300/radeon_nqssadce.h b/src/mesa/drivers/dri/r300/radeon_nqssadce.h new file mode 100644 index 00000000000..a4f94abcb62 --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_nqssadce.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RADEON_PROGRAM_NQSSADCE_H_ +#define __RADEON_PROGRAM_NQSSADCE_H_ + +#include "radeon_program.h" + + +struct register_state { + /** + * Bitmask indicating which components of the register are sourced + * by later instructions. + */ + GLuint Sourced : 4; +}; + +/** + * Maintain state such as which registers are used, which registers are + * read from, etc. + */ +struct nqssadce_state { + GLcontext *Ctx; + struct gl_program *Program; + struct radeon_nqssadce_descr *Descr; + + /** + * All instructions after this instruction pointer have been dealt with. + */ + int IP; + + /** + * Which registers are read by subsequent instructions? + */ + struct register_state Temps[MAX_PROGRAM_TEMPS]; + struct register_state Outputs[VERT_RESULT_MAX]; +}; + + +/** + * This structure contains a description of the hardware in-so-far as + * it is required for the NqSSA-DCE pass. + */ +struct radeon_nqssadce_descr { + /** + * Fill in which outputs + */ + void (*Init)(struct nqssadce_state *); + + /** + * Check whether the given swizzle, absolute and negate combination + * can be implemented natively by the hardware for this opcode. + */ + GLboolean (*IsNativeSwizzle)(GLuint opcode, struct prog_src_register reg); + + /** + * Emit (at the current IP) the instruction MOV dst, src; + * The transformation will work recursively on the emitted instruction(s). + */ + void (*BuildSwizzle)(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src); + + /** + * Rewrite instructions that write to DEPR.z to write to DEPR.w + * instead (rewriting is done *before* the WriteMask test). + */ + GLboolean RewriteDepthOut; + void *Data; +}; + +void radeonNqssaDce(GLcontext *ctx, struct gl_program *p, struct radeon_nqssadce_descr* descr); + +#endif /* __RADEON_PROGRAM_NQSSADCE_H_ */ diff --git a/src/mesa/drivers/dri/r300/radeon_program.c b/src/mesa/drivers/dri/r300/radeon_program.c index c8f40e81893..da5e7aefce5 100644 --- a/src/mesa/drivers/dri/r300/radeon_program.c +++ b/src/mesa/drivers/dri/r300/radeon_program.c @@ -29,201 +29,6 @@ #include "shader/prog_print.h" -/** - * Initialize a compiler structure with a single mixed clause - * containing all instructions from the source program. - */ -void radeonCompilerInit( - struct radeon_compiler *compiler, - GLcontext *ctx, - struct gl_program *source) -{ - struct radeon_clause* clause; - - _mesa_memset(compiler, 0, sizeof(*compiler)); - compiler->Source = source; - compiler->Ctx = ctx; - - compiler->NumTemporaries = source->NumTemporaries; - - clause = radeonCompilerInsertClause(compiler, 0, CLAUSE_MIXED); - clause->NumInstructions = 0; - while(source->Instructions[clause->NumInstructions].Opcode != OPCODE_END) - clause->NumInstructions++; - clause->ReservedInstructions = clause->NumInstructions; - clause->Instructions = _mesa_alloc_instructions(clause->NumInstructions); - _mesa_copy_instructions(clause->Instructions, source->Instructions, clause->NumInstructions); -} - - -/** - * Free all data that is referenced by the compiler structure. - * However, the compiler structure itself is not freed. - */ -void radeonCompilerCleanup(struct radeon_compiler *compiler) -{ - radeonCompilerEraseClauses(compiler, 0, compiler->NumClauses); -} - - -/** - * Allocate and return a unique temporary register. - */ -int radeonCompilerAllocateTemporary(struct radeon_compiler *compiler) -{ - if (compiler->NumTemporaries >= 256) { - _mesa_problem(compiler->Ctx, "radeonCompiler: Too many temporaries"); - return 0; - } - - return compiler->NumTemporaries++; -} - - -static const char* clausename(int type) -{ - switch(type) { - case CLAUSE_MIXED: return "CLAUSE_MIXED"; - case CLAUSE_ALU: return "CLAUSE_ALU"; - case CLAUSE_TEX: return "CLAUSE_TEX"; - default: return "CLAUSE_UNKNOWN"; - } -} - - -/** - * Dump the current compiler state to the console for debugging. - */ -void radeonCompilerDump(struct radeon_compiler *compiler) -{ - int i; - for(i = 0; i < compiler->NumClauses; ++i) { - struct radeon_clause *clause = &compiler->Clauses[i]; - int j; - - _mesa_printf("%2i: %s\n", i+1, clausename(clause->Type)); - - for(j = 0; j < clause->NumInstructions; ++j) { - _mesa_printf("%4i: ", j+1); - _mesa_print_instruction(&clause->Instructions[j]); - } - } -} - - -/** - * \p position index of the new clause; later clauses are moved - * \p type of the new clause; one of CLAUSE_XXX - * \return a pointer to the new clause - */ -struct radeon_clause* radeonCompilerInsertClause( - struct radeon_compiler *compiler, - int position, int type) -{ - struct radeon_clause* oldClauses = compiler->Clauses; - struct radeon_clause* clause; - - assert(position >= 0 && position <= compiler->NumClauses); - - compiler->Clauses = (struct radeon_clause *) - _mesa_malloc((compiler->NumClauses+1) * sizeof(struct radeon_clause)); - if (oldClauses) { - _mesa_memcpy(compiler->Clauses, oldClauses, - position*sizeof(struct radeon_clause)); - _mesa_memcpy(compiler->Clauses+position+1, oldClauses+position, - (compiler->NumClauses - position) * sizeof(struct radeon_clause)); - _mesa_free(oldClauses); - } - compiler->NumClauses++; - - clause = compiler->Clauses + position; - _mesa_memset(clause, 0, sizeof(*clause)); - clause->Type = type; - - return clause; -} - - -/** - * Remove clauses in the range [start, end) - */ -void radeonCompilerEraseClauses( - struct radeon_compiler *compiler, - int start, int end) -{ - struct radeon_clause* oldClauses = compiler->Clauses; - int i; - - assert(0 <= start); - assert(start <= end); - assert(end <= compiler->NumClauses); - - if (end == start) - return; - - for(i = start; i < end; ++i) { - struct radeon_clause* clause = oldClauses + i; - _mesa_free_instructions(clause->Instructions, clause->NumInstructions); - } - - if (start > 0 || end < compiler->NumClauses) { - compiler->Clauses = (struct radeon_clause*) - _mesa_malloc((compiler->NumClauses+start-end) * sizeof(struct radeon_clause)); - _mesa_memcpy(compiler->Clauses, oldClauses, - start * sizeof(struct radeon_clause)); - _mesa_memcpy(compiler->Clauses + start, oldClauses + end, - (compiler->NumClauses - end) * sizeof(struct radeon_clause)); - compiler->NumClauses -= end - start; - } else { - compiler->Clauses = 0; - compiler->NumClauses = 0; - } - - _mesa_free(oldClauses); -} - - -/** - * Insert new instructions at the given position, initialize them as NOPs - * and return a pointer to the first new instruction. - */ -struct prog_instruction* radeonClauseInsertInstructions( - struct radeon_compiler *compiler, - struct radeon_clause *clause, - int position, int count) -{ - int newNumInstructions = clause->NumInstructions + count; - - assert(position >= 0 && position <= clause->NumInstructions); - - if (newNumInstructions <= clause->ReservedInstructions) { - memmove(clause->Instructions + position + count, clause->Instructions + position, - (clause->NumInstructions - position) * sizeof(struct prog_instruction)); - } else { - struct prog_instruction *oldInstructions = clause->Instructions; - - clause->ReservedInstructions *= 2; - if (newNumInstructions > clause->ReservedInstructions) - clause->ReservedInstructions = newNumInstructions; - - clause->Instructions = (struct prog_instruction*) - _mesa_malloc(clause->ReservedInstructions * sizeof(struct prog_instruction)); - - if (oldInstructions) { - _mesa_memcpy(clause->Instructions, oldInstructions, - position * sizeof(struct prog_instruction)); - _mesa_memcpy(clause->Instructions + position + count, oldInstructions + position, - (clause->NumInstructions - position) * sizeof(struct prog_instruction)); - - _mesa_free(oldInstructions); - } - } - - clause->NumInstructions = newNumInstructions; - _mesa_init_instructions(clause->Instructions + position, count); - return clause->Instructions + position; -} - /** * Transform the given clause in the following way: @@ -240,42 +45,84 @@ struct prog_instruction* radeonClauseInsertInstructions( * \note The transform is called 'local' because it can only look at * one instruction at a time. */ -void radeonClauseLocalTransform( - struct radeon_compiler *compiler, - struct radeon_clause *clause, +void radeonLocalTransform( + GLcontext *Ctx, + struct gl_program *program, int num_transformations, struct radeon_program_transformation* transformations) { - struct radeon_program_transform_context context; - struct radeon_clause source; + struct radeon_transform_context ctx; int ip; - source = *clause; - clause->Instructions = 0; - clause->NumInstructions = 0; - clause->ReservedInstructions = 0; + ctx.Ctx = Ctx; + ctx.Program = program; + ctx.OldInstructions = program->Instructions; + ctx.OldNumInstructions = program->NumInstructions; - context.compiler = compiler; - context.dest = clause; - context.src = &source; + program->Instructions = 0; + program->NumInstructions = 0; - for(ip = 0; ip < source.NumInstructions; ++ip) { - struct prog_instruction *instr = source.Instructions + ip; + for(ip = 0; ip < ctx.OldNumInstructions; ++ip) { + struct prog_instruction *instr = ctx.OldInstructions + ip; int i; for(i = 0; i < num_transformations; ++i) { struct radeon_program_transformation* t = transformations + i; - if (t->function(&context, instr, t->userData)) + if (t->function(&ctx, instr, t->userData)) break; } if (i >= num_transformations) { - struct prog_instruction *tgt = - radeonClauseInsertInstructions(compiler, clause, clause->NumInstructions, 1); - _mesa_copy_instructions(tgt, instr, 1); + struct prog_instruction* dest = radeonAppendInstructions(program, 1); + _mesa_copy_instructions(dest, instr, 1); + } + } + + _mesa_free_instructions(ctx.OldInstructions, ctx.OldNumInstructions); +} + + +static void scan_instructions(GLboolean* used, const struct prog_instruction* insts, GLuint count) +{ + GLuint i; + for (i = 0; i < count; i++) { + const struct prog_instruction *inst = insts + i; + const GLuint n = _mesa_num_inst_src_regs(inst->Opcode); + GLuint k; + + for (k = 0; k < n; k++) { + if (inst->SrcReg[k].File == PROGRAM_TEMPORARY) + used[inst->SrcReg[k].Index] = GL_TRUE; } } +} - _mesa_free_instructions(source.Instructions, source.NumInstructions); +GLint radeonFindFreeTemporary(struct radeon_transform_context *t) +{ + GLboolean used[MAX_PROGRAM_TEMPS]; + GLuint i; + + _mesa_memset(used, 0, sizeof(used)); + scan_instructions(used, t->Program->Instructions, t->Program->NumInstructions); + scan_instructions(used, t->OldInstructions, t->OldNumInstructions); + + for (i = 0; i < MAX_PROGRAM_TEMPS; i++) { + if (!used[i]) + return i; + } + + return -1; +} + + +/** + * Append the given number of instructions to the program and return a + * pointer to the first new instruction. + */ +struct prog_instruction *radeonAppendInstructions(struct gl_program *program, int count) +{ + int oldnum = program->NumInstructions; + _mesa_insert_instructions(program, oldnum, count); + return program->Instructions + oldnum; } diff --git a/src/mesa/drivers/dri/r300/radeon_program.h b/src/mesa/drivers/dri/r300/radeon_program.h index 25e70505b16..2e01dd496b3 100644 --- a/src/mesa/drivers/dri/r300/radeon_program.h +++ b/src/mesa/drivers/dri/r300/radeon_program.h @@ -45,100 +45,28 @@ enum { PROGRAM_BUILTIN = PROGRAM_FILE_MAX /**< not a real register, but a special swizzle constant */ }; -#define SWIZZLE_0000 MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO) -#define SWIZZLE_1111 MAKE_SWIZZLE4(SWIZZLE_ONE, SWIZZLE_ONE, SWIZZLE_ONE, SWIZZLE_ONE) - -/** - * A clause is simply a sequence of instructions that are executed - * in order. - */ -struct radeon_clause { - /** - * Type of this clause, one of CLAUSE_XXX. - */ - int Type : 2; - - /** - * Pointer to an array of instructions. - * The array is terminated by an OPCODE_END instruction. - */ - struct prog_instruction *Instructions; - - /** - * Number of instructions in this clause. - */ - int NumInstructions; - - /** - * Space reserved for instructions in this clause. - */ - int ReservedInstructions; -}; - -/** - * A compile object, holding the current intermediate state during compilation. - */ -struct radeon_compiler { - struct gl_program *Source; - GLcontext* Ctx; - - /** - * Number of clauses in this program. - */ - int NumClauses; - - /** - * Pointer to an array of NumClauses clauses. - */ - struct radeon_clause *Clauses; - - /** - * Number of registers in the PROGRAM_TEMPORARIES file. - */ - int NumTemporaries; +enum { + OPCODE_REPL_ALPHA = MAX_OPCODE /**< used in paired instructions */ }; -void radeonCompilerInit( - struct radeon_compiler *compiler, - GLcontext *ctx, - struct gl_program *source); -void radeonCompilerCleanup(struct radeon_compiler *compiler); -int radeonCompilerAllocateTemporary(struct radeon_compiler *compiler); -void radeonCompilerDump(struct radeon_compiler *compiler); - -struct radeon_clause *radeonCompilerInsertClause( - struct radeon_compiler *compiler, - int position, - int type); -void radeonCompilerEraseClauses( - struct radeon_compiler *compiler, - int start, - int end); - -struct prog_instruction* radeonClauseInsertInstructions( - struct radeon_compiler *compiler, - struct radeon_clause *clause, - int position, int count); +#define SWIZZLE_0000 MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO) +#define SWIZZLE_1111 MAKE_SWIZZLE4(SWIZZLE_ONE, SWIZZLE_ONE, SWIZZLE_ONE, SWIZZLE_ONE) /** + * Transformation context that is passed to local transformations. * + * Care must be taken with some operations during transformation, + * e.g. finding new temporary registers must use @ref radeonFindFreeTemporary */ -struct radeon_program_transform_context { - struct radeon_compiler *compiler; - - /** - * Destination clause where new instructions must be written. - */ - struct radeon_clause *dest; - - /** - * Original clause that is currently being transformed. - */ - struct radeon_clause *src; +struct radeon_transform_context { + GLcontext *Ctx; + struct gl_program *Program; + struct prog_instruction *OldInstructions; + GLuint OldNumInstructions; }; /** - * A transformation that can be passed to \ref radeonClauseLinearTransform. + * A transformation that can be passed to \ref radeonLocalTransform. * * The function will be called once for each instruction. * It has to either emit the appropriate transformed code for the instruction @@ -149,16 +77,23 @@ struct radeon_program_transform_context { */ struct radeon_program_transformation { GLboolean (*function)( - struct radeon_program_transform_context*, + struct radeon_transform_context*, struct prog_instruction*, void*); void *userData; }; -void radeonClauseLocalTransform( - struct radeon_compiler *compiler, - struct radeon_clause *clause, +void radeonLocalTransform( + GLcontext* ctx, + struct gl_program *program, int num_transformations, struct radeon_program_transformation* transformations); +/** + * Find a usable free temporary register during program transformation + */ +GLint radeonFindFreeTemporary(struct radeon_transform_context *ctx); + +struct prog_instruction *radeonAppendInstructions(struct gl_program *program, int count); + #endif diff --git a/src/mesa/drivers/dri/r300/radeon_program_alu.c b/src/mesa/drivers/dri/r300/radeon_program_alu.c index 7fe940a7d7f..e0a2bd0e934 100644 --- a/src/mesa/drivers/dri/r300/radeon_program_alu.c +++ b/src/mesa/drivers/dri/r300/radeon_program_alu.c @@ -35,46 +35,45 @@ #include "radeon_program_alu.h" +#include "shader/prog_parameter.h" -static struct prog_instruction *emit1(struct radeon_program_transform_context* ctx, - gl_inst_opcode Opcode, struct prog_dst_register DstReg, + +static struct prog_instruction *emit1(struct gl_program* p, + gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg, struct prog_src_register SrcReg) { - struct prog_instruction *fpi = - radeonClauseInsertInstructions(ctx->compiler, ctx->dest, - ctx->dest->NumInstructions, 1); + struct prog_instruction *fpi = radeonAppendInstructions(p, 1); fpi->Opcode = Opcode; + fpi->SaturateMode = Saturate; fpi->DstReg = DstReg; fpi->SrcReg[0] = SrcReg; return fpi; } -static struct prog_instruction *emit2(struct radeon_program_transform_context* ctx, - gl_inst_opcode Opcode, struct prog_dst_register DstReg, +static struct prog_instruction *emit2(struct gl_program* p, + gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg, struct prog_src_register SrcReg0, struct prog_src_register SrcReg1) { - struct prog_instruction *fpi = - radeonClauseInsertInstructions(ctx->compiler, ctx->dest, - ctx->dest->NumInstructions, 1); + struct prog_instruction *fpi = radeonAppendInstructions(p, 1); fpi->Opcode = Opcode; + fpi->SaturateMode = Saturate; fpi->DstReg = DstReg; fpi->SrcReg[0] = SrcReg0; fpi->SrcReg[1] = SrcReg1; return fpi; } -static struct prog_instruction *emit3(struct radeon_program_transform_context* ctx, - gl_inst_opcode Opcode, struct prog_dst_register DstReg, +static struct prog_instruction *emit3(struct gl_program* p, + gl_inst_opcode Opcode, GLuint Saturate, struct prog_dst_register DstReg, struct prog_src_register SrcReg0, struct prog_src_register SrcReg1, struct prog_src_register SrcReg2) { - struct prog_instruction *fpi = - radeonClauseInsertInstructions(ctx->compiler, ctx->dest, - ctx->dest->NumInstructions, 1); + struct prog_instruction *fpi = radeonAppendInstructions(p, 1); fpi->Opcode = Opcode; + fpi->SaturateMode = Saturate; fpi->DstReg = DstReg; fpi->SrcReg[0] = SrcReg0; fpi->SrcReg[1] = SrcReg1; @@ -107,6 +106,19 @@ static struct prog_dst_register dstreg(int file, int index) return dst; } +static struct prog_dst_register dstregtmpmask(int index, int mask) +{ + struct prog_dst_register dst; + dst.File = PROGRAM_TEMPORARY; + dst.Index = index; + dst.WriteMask = mask; + dst.CondMask = COND_TR; + dst.CondSwizzle = SWIZZLE_NOOP; + dst.CondSrc = 0; + dst.pad = 0; + return dst; +} + static const struct prog_src_register builtin_zero = { .File = PROGRAM_BUILTIN, .Index = 0, @@ -131,6 +143,24 @@ static struct prog_src_register srcreg(int file, int index) return src; } +static struct prog_src_register srcregswz(int file, int index, int swz) +{ + struct prog_src_register src = srcreg_undefined; + src.File = file; + src.Index = index; + src.Swizzle = swz; + return src; +} + +static struct prog_src_register absolute(struct prog_src_register reg) +{ + struct prog_src_register newreg = reg; + newreg.Abs = 1; + newreg.NegateBase = 0; + newreg.NegateAbs = 0; + return newreg; +} + static struct prog_src_register negate(struct prog_src_register reg) { struct prog_src_register newreg = reg; @@ -142,10 +172,10 @@ static struct prog_src_register swizzle(struct prog_src_register reg, GLuint x, { struct prog_src_register swizzled = reg; swizzled.Swizzle = MAKE_SWIZZLE4( - GET_SWZ(reg.Swizzle, x), - GET_SWZ(reg.Swizzle, y), - GET_SWZ(reg.Swizzle, z), - GET_SWZ(reg.Swizzle, w)); + x >= 4 ? x : GET_SWZ(reg.Swizzle, x), + y >= 4 ? y : GET_SWZ(reg.Swizzle, y), + z >= 4 ? z : GET_SWZ(reg.Swizzle, z), + w >= 4 ? w : GET_SWZ(reg.Swizzle, w)); return swizzled; } @@ -154,24 +184,24 @@ static struct prog_src_register scalar(struct prog_src_register reg) return swizzle(reg, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X); } -static void transform_ABS(struct radeon_program_transform_context* ctx, +static void transform_ABS(struct radeon_transform_context* t, struct prog_instruction* inst) { struct prog_src_register src = inst->SrcReg[0]; src.Abs = 1; src.NegateBase = 0; src.NegateAbs = 0; - emit1(ctx, OPCODE_MOV, inst->DstReg, src); + emit1(t->Program, OPCODE_MOV, inst->SaturateMode, inst->DstReg, src); } -static void transform_DPH(struct radeon_program_transform_context* ctx, +static void transform_DPH(struct radeon_transform_context* t, struct prog_instruction* inst) { struct prog_src_register src0 = inst->SrcReg[0]; if (src0.NegateAbs) { if (src0.Abs) { - int tempreg = radeonCompilerAllocateTemporary(ctx->compiler); - emit1(ctx, OPCODE_MOV, dstreg(PROGRAM_TEMPORARY, tempreg), src0); + int tempreg = radeonFindFreeTemporary(t); + emit1(t->Program, OPCODE_MOV, 0, dstreg(PROGRAM_TEMPORARY, tempreg), src0); src0 = srcreg(src0.File, src0.Index); } else { src0.NegateAbs = 0; @@ -180,70 +210,191 @@ static void transform_DPH(struct radeon_program_transform_context* ctx, } set_swizzle(&src0, 3, SWIZZLE_ONE); set_negate_base(&src0, 3, 0); - emit2(ctx, OPCODE_DP4, inst->DstReg, src0, inst->SrcReg[1]); + emit2(t->Program, OPCODE_DP4, inst->SaturateMode, inst->DstReg, src0, inst->SrcReg[1]); } -static void transform_FLR(struct radeon_program_transform_context* ctx, +/** + * [1, src0.y*src1.y, src0.z, src1.w] + * So basically MUL with lotsa swizzling. + */ +static void transform_DST(struct radeon_transform_context* t, + struct prog_instruction* inst) +{ + emit2(t->Program, OPCODE_MUL, inst->SaturateMode, inst->DstReg, + swizzle(inst->SrcReg[0], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE), + swizzle(inst->SrcReg[1], SWIZZLE_ONE, SWIZZLE_Y, SWIZZLE_ONE, SWIZZLE_W)); +} + +static void transform_FLR(struct radeon_transform_context* t, + struct prog_instruction* inst) +{ + int tempreg = radeonFindFreeTemporary(t); + emit1(t->Program, OPCODE_FRC, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]); + emit2(t->Program, OPCODE_ADD, inst->SaturateMode, inst->DstReg, + inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg))); +} + +/** + * Definition of LIT (from ARB_fragment_program): + * + * tmp = VectorLoad(op0); + * if (tmp.x < 0) tmp.x = 0; + * if (tmp.y < 0) tmp.y = 0; + * if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon); + * else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon; + * result.x = 1.0; + * result.y = tmp.x; + * result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0; + * result.w = 1.0; + * + * The longest path of computation is the one leading to result.z, + * consisting of 5 operations. This implementation of LIT takes + * 5 slots, if the subsequent optimization passes are clever enough + * to pair instructions correctly. + */ +static void transform_LIT(struct radeon_transform_context* t, struct prog_instruction* inst) { - int tempreg = radeonCompilerAllocateTemporary(ctx->compiler); - emit1(ctx, OPCODE_FRC, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0]); - emit2(ctx, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(srcreg(PROGRAM_TEMPORARY, tempreg))); + static const GLfloat LitConst[4] = { -127.999999 }; + + GLuint constant; + GLuint constant_swizzle; + GLuint temp; + int needTemporary = 0; + struct prog_src_register srctemp; + + constant = _mesa_add_unnamed_constant(t->Program->Parameters, LitConst, 1, &constant_swizzle); + + if (inst->DstReg.WriteMask != WRITEMASK_XYZW) { + needTemporary = 1; + } else if (inst->DstReg.File != PROGRAM_TEMPORARY) { + // LIT is typically followed by DP3/DP4, so there's no point + // in creating special code for this case + needTemporary = 1; + } + + if (needTemporary) { + temp = radeonFindFreeTemporary(t); + } else { + temp = inst->DstReg.Index; + } + srctemp = srcreg(PROGRAM_TEMPORARY, temp); + + // tmp.x = max(0.0, Src.x); + // tmp.y = max(0.0, Src.y); + // tmp.w = clamp(Src.z, -128+eps, 128-eps); + emit2(t->Program, OPCODE_MAX, 0, + dstregtmpmask(temp, WRITEMASK_XYW), + inst->SrcReg[0], + swizzle(srcreg(PROGRAM_CONSTANT, constant), + SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, constant_swizzle&3)); + emit2(t->Program, OPCODE_MIN, 0, + dstregtmpmask(temp, WRITEMASK_Z), + swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + negate(srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle))); + + // tmp.w = Pow(tmp.y, tmp.w) + emit1(t->Program, OPCODE_LG2, 0, + dstregtmpmask(temp, WRITEMASK_W), + swizzle(srctemp, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y)); + emit2(t->Program, OPCODE_MUL, 0, + dstregtmpmask(temp, WRITEMASK_W), + swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + swizzle(srctemp, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z)); + emit1(t->Program, OPCODE_EX2, 0, + dstregtmpmask(temp, WRITEMASK_W), + swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W)); + + // tmp.z = (tmp.x > 0) ? tmp.w : 0.0 + emit3(t->Program, OPCODE_CMP, inst->SaturateMode, + dstregtmpmask(temp, WRITEMASK_Z), + negate(swizzle(srctemp, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)), + swizzle(srctemp, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + builtin_zero); + + // tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 + emit1(t->Program, OPCODE_MOV, inst->SaturateMode, + dstregtmpmask(temp, WRITEMASK_XYW), + swizzle(srctemp, SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE)); + + if (needTemporary) + emit1(t->Program, OPCODE_MOV, 0, inst->DstReg, srctemp); } -static void transform_POW(struct radeon_program_transform_context* ctx, +static void transform_LRP(struct radeon_transform_context* t, struct prog_instruction* inst) { - int tempreg = radeonCompilerAllocateTemporary(ctx->compiler); + int tempreg = radeonFindFreeTemporary(t); + + emit2(t->Program, OPCODE_ADD, 0, + dstreg(PROGRAM_TEMPORARY, tempreg), + inst->SrcReg[1], negate(inst->SrcReg[2])); + emit3(t->Program, OPCODE_MAD, inst->SaturateMode, + inst->DstReg, + inst->SrcReg[0], srcreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[2]); +} + +static void transform_POW(struct radeon_transform_context* t, + struct prog_instruction* inst) +{ + int tempreg = radeonFindFreeTemporary(t); struct prog_dst_register tempdst = dstreg(PROGRAM_TEMPORARY, tempreg); struct prog_src_register tempsrc = srcreg(PROGRAM_TEMPORARY, tempreg); tempdst.WriteMask = WRITEMASK_W; tempsrc.Swizzle = SWIZZLE_WWWW; - emit1(ctx, OPCODE_LG2, tempdst, scalar(inst->SrcReg[0])); - emit2(ctx, OPCODE_MUL, tempdst, tempsrc, scalar(inst->SrcReg[1])); - emit1(ctx, OPCODE_EX2, inst->DstReg, tempsrc); + emit1(t->Program, OPCODE_LG2, 0, tempdst, scalar(inst->SrcReg[0])); + emit2(t->Program, OPCODE_MUL, 0, tempdst, tempsrc, scalar(inst->SrcReg[1])); + emit1(t->Program, OPCODE_EX2, inst->SaturateMode, inst->DstReg, tempsrc); } -static void transform_SGE(struct radeon_program_transform_context* ctx, +static void transform_RSQ(struct radeon_transform_context* t, struct prog_instruction* inst) { - int tempreg = radeonCompilerAllocateTemporary(ctx->compiler); + emit1(t->Program, OPCODE_RSQ, inst->SaturateMode, inst->DstReg, absolute(inst->SrcReg[0])); +} - emit2(ctx, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1])); - emit3(ctx, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_zero, builtin_one); +static void transform_SGE(struct radeon_transform_context* t, + struct prog_instruction* inst) +{ + int tempreg = radeonFindFreeTemporary(t); + + emit2(t->Program, OPCODE_ADD, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1])); + emit3(t->Program, OPCODE_CMP, inst->SaturateMode, inst->DstReg, + srcreg(PROGRAM_TEMPORARY, tempreg), builtin_zero, builtin_one); } -static void transform_SLT(struct radeon_program_transform_context* ctx, +static void transform_SLT(struct radeon_transform_context* t, struct prog_instruction* inst) { - int tempreg = radeonCompilerAllocateTemporary(ctx->compiler); + int tempreg = radeonFindFreeTemporary(t); - emit2(ctx, OPCODE_ADD, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1])); - emit3(ctx, OPCODE_CMP, inst->DstReg, srcreg(PROGRAM_TEMPORARY, tempreg), builtin_one, builtin_zero); + emit2(t->Program, OPCODE_ADD, 0, dstreg(PROGRAM_TEMPORARY, tempreg), inst->SrcReg[0], negate(inst->SrcReg[1])); + emit3(t->Program, OPCODE_CMP, inst->SaturateMode, inst->DstReg, + srcreg(PROGRAM_TEMPORARY, tempreg), builtin_one, builtin_zero); } -static void transform_SUB(struct radeon_program_transform_context* ctx, +static void transform_SUB(struct radeon_transform_context* t, struct prog_instruction* inst) { - emit2(ctx, OPCODE_ADD, inst->DstReg, inst->SrcReg[0], negate(inst->SrcReg[1])); + emit2(t->Program, OPCODE_ADD, inst->SaturateMode, inst->DstReg, inst->SrcReg[0], negate(inst->SrcReg[1])); } -static void transform_SWZ(struct radeon_program_transform_context* ctx, +static void transform_SWZ(struct radeon_transform_context* t, struct prog_instruction* inst) { - emit1(ctx, OPCODE_MOV, inst->DstReg, inst->SrcReg[0]); + emit1(t->Program, OPCODE_MOV, inst->SaturateMode, inst->DstReg, inst->SrcReg[0]); } -static void transform_XPD(struct radeon_program_transform_context* ctx, +static void transform_XPD(struct radeon_transform_context* t, struct prog_instruction* inst) { - int tempreg = radeonCompilerAllocateTemporary(ctx->compiler); + int tempreg = radeonFindFreeTemporary(t); - emit2(ctx, OPCODE_MUL, dstreg(PROGRAM_TEMPORARY, tempreg), + emit2(t->Program, OPCODE_MUL, 0, dstreg(PROGRAM_TEMPORARY, tempreg), swizzle(inst->SrcReg[0], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W), swizzle(inst->SrcReg[1], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W)); - emit3(ctx, OPCODE_MAD, inst->DstReg, + emit3(t->Program, OPCODE_MAD, inst->SaturateMode, inst->DstReg, swizzle(inst->SrcReg[0], SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_X, SWIZZLE_W), swizzle(inst->SrcReg[1], SWIZZLE_Z, SWIZZLE_X, SWIZZLE_Y, SWIZZLE_W), negate(srcreg(PROGRAM_TEMPORARY, tempreg))); @@ -255,30 +406,226 @@ static void transform_XPD(struct radeon_program_transform_context* ctx, * no userData necessary. * * Eliminates the following ALU instructions: - * ABS, DPH, FLR, POW, SGE, SLT, SUB, SWZ, XPD + * ABS, DPH, DST, FLR, LIT, LRP, POW, SGE, SLT, SUB, SWZ, XPD * using: * MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP * - * @note should be applicable to R300 and R500 fragment programs. + * Transforms RSQ to Radeon's native RSQ by explicitly setting + * absolute value. * - * @todo add LIT here as well? + * @note should be applicable to R300 and R500 fragment programs. */ -GLboolean radeonTransformALU( - struct radeon_program_transform_context* ctx, +GLboolean radeonTransformALU(struct radeon_transform_context* t, struct prog_instruction* inst, void* unused) { switch(inst->Opcode) { - case OPCODE_ABS: transform_ABS(ctx, inst); return GL_TRUE; - case OPCODE_DPH: transform_DPH(ctx, inst); return GL_TRUE; - case OPCODE_FLR: transform_FLR(ctx, inst); return GL_TRUE; - case OPCODE_POW: transform_POW(ctx, inst); return GL_TRUE; - case OPCODE_SGE: transform_SGE(ctx, inst); return GL_TRUE; - case OPCODE_SLT: transform_SLT(ctx, inst); return GL_TRUE; - case OPCODE_SUB: transform_SUB(ctx, inst); return GL_TRUE; - case OPCODE_SWZ: transform_SWZ(ctx, inst); return GL_TRUE; - case OPCODE_XPD: transform_XPD(ctx, inst); return GL_TRUE; + case OPCODE_ABS: transform_ABS(t, inst); return GL_TRUE; + case OPCODE_DPH: transform_DPH(t, inst); return GL_TRUE; + case OPCODE_DST: transform_DST(t, inst); return GL_TRUE; + case OPCODE_FLR: transform_FLR(t, inst); return GL_TRUE; + case OPCODE_LIT: transform_LIT(t, inst); return GL_TRUE; + case OPCODE_LRP: transform_LRP(t, inst); return GL_TRUE; + case OPCODE_POW: transform_POW(t, inst); return GL_TRUE; + case OPCODE_RSQ: transform_RSQ(t, inst); return GL_TRUE; + case OPCODE_SGE: transform_SGE(t, inst); return GL_TRUE; + case OPCODE_SLT: transform_SLT(t, inst); return GL_TRUE; + case OPCODE_SUB: transform_SUB(t, inst); return GL_TRUE; + case OPCODE_SWZ: transform_SWZ(t, inst); return GL_TRUE; + case OPCODE_XPD: transform_XPD(t, inst); return GL_TRUE; default: return GL_FALSE; } } + + +static void sincos_constants(struct radeon_transform_context* t, GLuint *constants) +{ + static const GLfloat SinCosConsts[2][4] = { + { + 1.273239545, // 4/PI + -0.405284735, // -4/(PI*PI) + 3.141592654, // PI + 0.2225 // weight + }, + { + 0.75, + 0.5, + 0.159154943, // 1/(2*PI) + 6.283185307 // 2*PI + } + }; + int i; + + for(i = 0; i < 2; ++i) { + GLuint swz; + constants[i] = _mesa_add_unnamed_constant(t->Program->Parameters, SinCosConsts[i], 4, &swz); + ASSERT(swz == SWIZZLE_NOOP); + } +} + +/** + * Approximate sin(x), where x is clamped to (-pi/2, pi/2). + * + * MUL tmp.xy, src, { 4/PI, -4/(PI^2) } + * MAD tmp.x, tmp.y, |src|, tmp.x + * MAD tmp.y, tmp.x, |tmp.x|, -tmp.x + * MAD dest, tmp.y, weight, tmp.x + */ +static void sin_approx(struct radeon_transform_context* t, + struct prog_dst_register dst, struct prog_src_register src, const GLuint* constants) +{ + GLuint tempreg = radeonFindFreeTemporary(t); + + emit2(t->Program, OPCODE_MUL, 0, dstregtmpmask(tempreg, WRITEMASK_XY), + swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + srcreg(PROGRAM_CONSTANT, constants[0])); + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_X), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y), + absolute(swizzle(src, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)); + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_Y), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + absolute(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)), + negate(swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X))); + emit3(t->Program, OPCODE_MAD, 0, dst, + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y), + swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)); +} + +/** + * Translate the trigonometric functions COS, SIN, and SCS + * using only the basic instructions + * MOV, ADD, MUL, MAD, FRC + */ +GLboolean radeonTransformTrigSimple(struct radeon_transform_context* t, + struct prog_instruction* inst, + void* unused) +{ + if (inst->Opcode != OPCODE_COS && + inst->Opcode != OPCODE_SIN && + inst->Opcode != OPCODE_SCS) + return GL_FALSE; + + GLuint constants[2]; + GLuint tempreg = radeonFindFreeTemporary(t); + + sincos_constants(t, constants); + + if (inst->Opcode == OPCODE_COS) { + // MAD tmp.x, src, 1/(2*PI), 0.75 + // FRC tmp.x, tmp.x + // MAD tmp.z, tmp.x, 2*PI, -PI + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W), + swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X)); + emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(tempreg, WRITEMASK_W), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W)); + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z))); + + sin_approx(t, inst->DstReg, + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + constants); + } else if (inst->Opcode == OPCODE_SIN) { + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W), + swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y)); + emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(tempreg, WRITEMASK_W), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W)); + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_W), + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z))); + + sin_approx(t, inst->DstReg, + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + constants); + } else { + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_XY), + swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W)); + emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(tempreg, WRITEMASK_XY), + srcreg(PROGRAM_TEMPORARY, tempreg)); + emit3(t->Program, OPCODE_MAD, 0, dstregtmpmask(tempreg, WRITEMASK_XY), + srcreg(PROGRAM_TEMPORARY, tempreg), + swizzle(srcreg(PROGRAM_CONSTANT, constants[1]), SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, SWIZZLE_W), + negate(swizzle(srcreg(PROGRAM_CONSTANT, constants[0]), SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z, SWIZZLE_Z))); + + struct prog_dst_register dst = inst->DstReg; + + dst.WriteMask = inst->DstReg.WriteMask & WRITEMASK_X; + sin_approx(t, dst, + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + constants); + + dst.WriteMask = inst->DstReg.WriteMask & WRITEMASK_Y; + sin_approx(t, dst, + swizzle(srcreg(PROGRAM_TEMPORARY, tempreg), SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y), + constants); + } + + return GL_TRUE; +} + + +/** + * Transform the trigonometric functions COS, SIN, and SCS + * to include pre-scaling by 1/(2*PI) and taking the fractional + * part, so that the input to COS and SIN is always in the range [0,1). + * SCS is replaced by one COS and one SIN instruction. + * + * @warning This transformation implicitly changes the semantics of SIN and COS! + */ +GLboolean radeonTransformTrigScale(struct radeon_transform_context* t, + struct prog_instruction* inst, + void* unused) +{ + if (inst->Opcode != OPCODE_COS && + inst->Opcode != OPCODE_SIN && + inst->Opcode != OPCODE_SCS) + return GL_FALSE; + + static const GLfloat RCP_2PI[] = { 0.15915494309189535 }; + GLuint temp; + GLuint constant; + GLuint constant_swizzle; + + temp = radeonFindFreeTemporary(t); + constant = _mesa_add_unnamed_constant(t->Program->Parameters, RCP_2PI, 1, &constant_swizzle); + + emit2(t->Program, OPCODE_MUL, 0, dstregtmpmask(temp, WRITEMASK_W), + swizzle(inst->SrcReg[0], SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X), + srcregswz(PROGRAM_CONSTANT, constant, constant_swizzle)); + emit1(t->Program, OPCODE_FRC, 0, dstregtmpmask(temp, WRITEMASK_W), + srcreg(PROGRAM_TEMPORARY, temp)); + + if (inst->Opcode == OPCODE_COS) { + emit1(t->Program, OPCODE_COS, inst->SaturateMode, inst->DstReg, + srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW)); + } else if (inst->Opcode == OPCODE_SIN) { + emit1(t->Program, OPCODE_SIN, inst->SaturateMode, + inst->DstReg, srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW)); + } else if (inst->Opcode == OPCODE_SCS) { + struct prog_dst_register moddst = inst->DstReg; + + if (inst->DstReg.WriteMask & WRITEMASK_X) { + moddst.WriteMask = WRITEMASK_X; + emit1(t->Program, OPCODE_COS, inst->SaturateMode, moddst, + srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW)); + } + if (inst->DstReg.WriteMask & WRITEMASK_Y) { + moddst.WriteMask = WRITEMASK_Y; + emit1(t->Program, OPCODE_SIN, inst->SaturateMode, moddst, + srcregswz(PROGRAM_TEMPORARY, temp, SWIZZLE_WWWW)); + } + } + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/r300/radeon_program_alu.h b/src/mesa/drivers/dri/r300/radeon_program_alu.h index 940459624fc..ea9d5bb669c 100644 --- a/src/mesa/drivers/dri/r300/radeon_program_alu.h +++ b/src/mesa/drivers/dri/r300/radeon_program_alu.h @@ -31,7 +31,17 @@ #include "radeon_program.h" GLboolean radeonTransformALU( - struct radeon_program_transform_context*, + struct radeon_transform_context *t, + struct prog_instruction*, + void*); + +GLboolean radeonTransformTrigSimple( + struct radeon_transform_context *t, + struct prog_instruction*, + void*); + +GLboolean radeonTransformTrigScale( + struct radeon_transform_context *t, struct prog_instruction*, void*); diff --git a/src/mesa/drivers/dri/r300/radeon_program_pair.c b/src/mesa/drivers/dri/r300/radeon_program_pair.c new file mode 100644 index 00000000000..8762422801e --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_program_pair.c @@ -0,0 +1,983 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/** + * @file + * + * Perform temporary register allocation and attempt to pair off instructions + * in RGB and Alpha pairs. Also attempts to optimize the TEX instruction + * vs. ALU instruction scheduling. + */ + +#include "radeon_program_pair.h" + +#include "radeon_context.h" + +#include "shader/prog_print.h" + +#define error(fmt, args...) do { \ + _mesa_problem(s->Ctx, "%s::%s(): " fmt "\n", \ + __FILE__, __FUNCTION__, ##args); \ + s->Error = GL_TRUE; \ +} while(0) + +struct pair_state_instruction { + GLuint IsTex:1; /**< Is a texture instruction */ + GLuint NeedRGB:1; /**< Needs the RGB ALU */ + GLuint NeedAlpha:1; /**< Needs the Alpha ALU */ + GLuint IsTranscendent:1; /**< Is a special transcendent instruction */ + + /** + * Number of (read and write) dependencies that must be resolved before + * this instruction can be scheduled. + */ + GLuint NumDependencies:5; + + /** + * Next instruction in the linked list of ready instructions. + */ + struct pair_state_instruction *NextReady; + + /** + * Values that this instruction writes + */ + struct reg_value *Values[4]; +}; + + +/** + * Used to keep track of which instructions read a value. + */ +struct reg_value_reader { + GLuint IP; /**< IP of the instruction that performs this access */ + struct reg_value_reader *Next; +}; + +/** + * Used to keep track which values are stored in each component of a + * PROGRAM_TEMPORARY. + */ +struct reg_value { + GLuint IP; /**< IP of the instruction that writes this value */ + struct reg_value *Next; /**< Pointer to the next value to be written to the same PROGRAM_TEMPORARY component */ + + /** + * Unordered linked list of instructions that read from this value. + */ + struct reg_value_reader *Readers; + + /** + * Number of readers of this value. This is calculated during @ref scan_instructions + * and continually decremented during code emission. + * When this count reaches zero, the instruction that writes the @ref Next value + * can be scheduled. + */ + GLuint NumReaders; +}; + +/** + * Used to translate a PROGRAM_INPUT or PROGRAM_TEMPORARY Mesa register + * to the proper hardware temporary. + */ +struct pair_register_translation { + GLuint Allocated:1; + GLuint HwIndex:8; + GLuint RefCount:23; /**< # of times this occurs in an unscheduled instruction SrcReg or DstReg */ + + /** + * Notes the value that is currently contained in each component + * (only used for PROGRAM_TEMPORARY registers). + */ + struct reg_value *Value[4]; +}; + +struct pair_state { + GLcontext *Ctx; + struct gl_program *Program; + const struct radeon_pair_handler *Handler; + GLboolean Error; + GLboolean Debug; + GLboolean Verbose; + void *UserData; + + /** + * Translate Mesa registers to hardware registers + */ + struct pair_register_translation Inputs[FRAG_ATTRIB_MAX]; + struct pair_register_translation Temps[MAX_PROGRAM_TEMPS]; + + /** + * Derived information about program instructions. + */ + struct pair_state_instruction *Instructions; + + struct { + GLuint RefCount; /**< # of times this occurs in an unscheduled SrcReg or DstReg */ + } HwTemps[128]; + + /** + * Linked list of instructions that can be scheduled right now, + * based on which ALU/TEX resources they require. + */ + struct pair_state_instruction *ReadyFullALU; + struct pair_state_instruction *ReadyRGB; + struct pair_state_instruction *ReadyAlpha; + struct pair_state_instruction *ReadyTEX; + + /** + * Pool of @ref reg_value structures for fast allocation. + */ + struct reg_value *ValuePool; + GLuint ValuePoolUsed; + struct reg_value_reader *ReaderPool; + GLuint ReaderPoolUsed; +}; + + +static struct pair_register_translation *get_register(struct pair_state *s, GLuint file, GLuint index) +{ + switch(file) { + case PROGRAM_TEMPORARY: return &s->Temps[index]; + case PROGRAM_INPUT: return &s->Inputs[index]; + default: return 0; + } +} + +static void alloc_hw_reg(struct pair_state *s, GLuint file, GLuint index, GLuint hwindex) +{ + struct pair_register_translation *t = get_register(s, file, index); + ASSERT(!s->HwTemps[hwindex].RefCount); + ASSERT(!t->Allocated); + s->HwTemps[hwindex].RefCount = t->RefCount; + t->Allocated = 1; + t->HwIndex = hwindex; +} + +static GLuint get_hw_reg(struct pair_state *s, GLuint file, GLuint index) +{ + GLuint hwindex; + + struct pair_register_translation *t = get_register(s, file, index); + if (!t) { + _mesa_problem(s->Ctx, "get_hw_reg: %i[%i]\n", file, index); + return 0; + } + + if (t->Allocated) + return t->HwIndex; + + for(hwindex = 0; hwindex < s->Handler->MaxHwTemps; ++hwindex) + if (!s->HwTemps[hwindex].RefCount) + break; + + if (hwindex >= s->Handler->MaxHwTemps) { + error("Ran out of hardware temporaries"); + return 0; + } + + alloc_hw_reg(s, file, index, hwindex); + return hwindex; +} + + +static void deref_hw_reg(struct pair_state *s, GLuint hwindex) +{ + if (!s->HwTemps[hwindex].RefCount) { + error("Hwindex %i refcount error", hwindex); + return; + } + + s->HwTemps[hwindex].RefCount--; +} + +static void add_pairinst_to_list(struct pair_state_instruction **list, struct pair_state_instruction *pairinst) +{ + pairinst->NextReady = *list; + *list = pairinst; +} + +/** + * The instruction at the given IP has become ready. Link it into the ready + * instructions. + */ +static void instruction_ready(struct pair_state *s, int ip) +{ + struct pair_state_instruction *pairinst = s->Instructions + ip; + + if (s->Verbose) + _mesa_printf("instruction_ready(%i)\n", ip); + + if (pairinst->IsTex) + add_pairinst_to_list(&s->ReadyTEX, pairinst); + else if (!pairinst->NeedAlpha) + add_pairinst_to_list(&s->ReadyRGB, pairinst); + else if (!pairinst->NeedRGB) + add_pairinst_to_list(&s->ReadyAlpha, pairinst); + else + add_pairinst_to_list(&s->ReadyFullALU, pairinst); +} + + +/** + * Finally rewrite ADD, MOV, MUL as the appropriate native instruction + * and reverse the order of arguments for CMP. + */ +static void final_rewrite(struct pair_state *s, struct prog_instruction *inst) +{ + struct prog_src_register tmp; + + switch(inst->Opcode) { + case OPCODE_ADD: + inst->SrcReg[2] = inst->SrcReg[1]; + inst->SrcReg[1].File = PROGRAM_BUILTIN; + inst->SrcReg[1].Swizzle = SWIZZLE_1111; + inst->SrcReg[1].NegateBase = 0; + inst->SrcReg[1].NegateAbs = 0; + inst->Opcode = OPCODE_MAD; + break; + case OPCODE_CMP: + tmp = inst->SrcReg[2]; + inst->SrcReg[2] = inst->SrcReg[0]; + inst->SrcReg[0] = tmp; + break; + case OPCODE_MOV: + inst->SrcReg[1] = inst->SrcReg[0]; + inst->SrcReg[2].File = PROGRAM_BUILTIN; + inst->SrcReg[2].Swizzle = SWIZZLE_0000; + inst->Opcode = OPCODE_CMP; + // TODO: disable output modifiers on R500 + break; + case OPCODE_MUL: + inst->SrcReg[2].File = PROGRAM_BUILTIN; + inst->SrcReg[2].Swizzle = SWIZZLE_0000; + inst->Opcode = OPCODE_MAD; + break; + default: + /* nothing to do */ + break; + } +} + + +/** + * Classify an instruction according to which ALUs etc. it needs + */ +static void classify_instruction(struct pair_state *s, + struct prog_instruction *inst, struct pair_state_instruction *pairinst) +{ + pairinst->NeedRGB = (inst->DstReg.WriteMask & WRITEMASK_XYZ) ? 1 : 0; + pairinst->NeedAlpha = (inst->DstReg.WriteMask & WRITEMASK_W) ? 1 : 0; + + switch(inst->Opcode) { + case OPCODE_ADD: + case OPCODE_CMP: + case OPCODE_FRC: + case OPCODE_MAD: + case OPCODE_MAX: + case OPCODE_MIN: + case OPCODE_MOV: + case OPCODE_MUL: + break; + case OPCODE_COS: + case OPCODE_EX2: + case OPCODE_LG2: + case OPCODE_RCP: + case OPCODE_RSQ: + case OPCODE_SIN: + pairinst->IsTranscendent = 1; + pairinst->NeedAlpha = 1; + break; + case OPCODE_DP4: + pairinst->NeedAlpha = 1; + /* fall through */ + case OPCODE_DP3: + pairinst->NeedRGB = 1; + break; + case OPCODE_KIL: + case OPCODE_TEX: + case OPCODE_TXB: + case OPCODE_TXP: + case OPCODE_END: + pairinst->IsTex = 1; + break; + default: + error("Unknown opcode %d\n", inst->Opcode); + break; + } +} + + +/** + * Count which (input, temporary) register is read and written how often, + * and scan the instruction stream to find dependencies. + */ +static void scan_instructions(struct pair_state *s) +{ + struct prog_instruction *inst; + struct pair_state_instruction *pairinst; + GLuint ip; + + for(inst = s->Program->Instructions, pairinst = s->Instructions, ip = 0; + inst->Opcode != OPCODE_END; + ++inst, ++pairinst, ++ip) { + final_rewrite(s, inst); + classify_instruction(s, inst, pairinst); + + int nsrc = _mesa_num_inst_src_regs(inst->Opcode); + int j; + for(j = 0; j < nsrc; j++) { + struct pair_register_translation *t = + get_register(s, inst->SrcReg[j].File, inst->SrcReg[j].Index); + if (!t) + continue; + + t->RefCount++; + + if (inst->SrcReg[j].File == PROGRAM_TEMPORARY) { + int i; + for(i = 0; i < 4; ++i) { + GLuint swz = GET_SWZ(inst->SrcReg[j].Swizzle, i); + if (swz >= 4) + continue; /* constant or NIL swizzle */ + if (!t->Value[swz]) + continue; /* this is an undefined read */ + + /* Do not add a dependency if this instruction + * also rewrites the value. The code below adds + * a dependency for the DstReg, which is a superset + * of the SrcReg dependency. */ + if (inst->DstReg.File == PROGRAM_TEMPORARY && + inst->DstReg.Index == inst->SrcReg[j].Index && + GET_BIT(inst->DstReg.WriteMask, swz)) + continue; + + struct reg_value_reader* r = &s->ReaderPool[s->ReaderPoolUsed++]; + pairinst->NumDependencies++; + t->Value[swz]->NumReaders++; + r->IP = ip; + r->Next = t->Value[swz]->Readers; + t->Value[swz]->Readers = r; + } + } + } + + int ndst = _mesa_num_inst_dst_regs(inst->Opcode); + if (ndst) { + struct pair_register_translation *t = + get_register(s, inst->DstReg.File, inst->DstReg.Index); + if (t) { + t->RefCount++; + + if (inst->DstReg.File == PROGRAM_TEMPORARY) { + int j; + for(j = 0; j < 4; ++j) { + if (!GET_BIT(inst->DstReg.WriteMask, j)) + continue; + + struct reg_value* v = &s->ValuePool[s->ValuePoolUsed++]; + v->IP = ip; + if (t->Value[j]) { + pairinst->NumDependencies++; + t->Value[j]->Next = v; + } + t->Value[j] = v; + pairinst->Values[j] = v; + } + } + } + } + + if (s->Verbose) + _mesa_printf("scan(%i): NumDeps = %i\n", ip, pairinst->NumDependencies); + + if (!pairinst->NumDependencies) + instruction_ready(s, ip); + } + + /* Clear the PROGRAM_TEMPORARY state */ + int i, j; + for(i = 0; i < MAX_PROGRAM_TEMPS; ++i) { + for(j = 0; j < 4; ++j) + s->Temps[i].Value[j] = 0; + } +} + + +/** + * Reserve hardware temporary registers for the program inputs. + * + * @note This allocation is performed explicitly, because the order of inputs + * is determined by the RS hardware. + */ +static void allocate_input_registers(struct pair_state *s) +{ + GLuint InputsRead = s->Program->InputsRead; + int i; + GLuint hwindex = 0; + + /* Texcoords come first */ + for (i = 0; i < s->Ctx->Const.MaxTextureUnits; i++) { + if (InputsRead & (FRAG_BIT_TEX0 << i)) + alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_TEX0+i, hwindex++); + } + InputsRead &= ~FRAG_BITS_TEX_ANY; + + /* fragment position treated as a texcoord */ + if (InputsRead & FRAG_BIT_WPOS) + alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_WPOS, hwindex++); + InputsRead &= ~FRAG_BIT_WPOS; + + /* Then primary colour */ + if (InputsRead & FRAG_BIT_COL0) + alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL0, hwindex++); + InputsRead &= ~FRAG_BIT_COL0; + + /* Secondary color */ + if (InputsRead & FRAG_BIT_COL1) + alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL1, hwindex++); + InputsRead &= ~FRAG_BIT_COL1; + + /* Anything else */ + if (InputsRead) + error("Don't know how to handle inputs 0x%x\n", InputsRead); +} + + +static void decrement_dependencies(struct pair_state *s, int ip) +{ + struct pair_state_instruction *pairinst = s->Instructions + ip; + ASSERT(pairinst->NumDependencies > 0); + if (!--pairinst->NumDependencies) + instruction_ready(s, ip); +} + +/** + * Update the dependency tracking state based on what the instruction + * at the given IP does. + */ +static void commit_instruction(struct pair_state *s, int ip) +{ + struct prog_instruction *inst = s->Program->Instructions + ip; + struct pair_state_instruction *pairinst = s->Instructions + ip; + + if (s->Verbose) + _mesa_printf("commit_instruction(%i)\n", ip); + + if (inst->DstReg.File == PROGRAM_TEMPORARY) { + struct pair_register_translation *t = &s->Temps[inst->DstReg.Index]; + deref_hw_reg(s, t->HwIndex); + + int i; + for(i = 0; i < 4; ++i) { + if (!GET_BIT(inst->DstReg.WriteMask, i)) + continue; + + t->Value[i] = pairinst->Values[i]; + if (t->Value[i]->NumReaders) { + struct reg_value_reader *r; + for(r = pairinst->Values[i]->Readers; r; r = r->Next) + decrement_dependencies(s, r->IP); + } else if (t->Value[i]->Next) { + /* This happens when the only reader writes + * the register at the same time */ + decrement_dependencies(s, t->Value[i]->Next->IP); + } + } + } + + int nsrc = _mesa_num_inst_src_regs(inst->Opcode); + int i; + for(i = 0; i < nsrc; i++) { + struct pair_register_translation *t = get_register(s, inst->SrcReg[i].File, inst->SrcReg[i].Index); + if (!t) + continue; + + deref_hw_reg(s, get_hw_reg(s, inst->SrcReg[i].File, inst->SrcReg[i].Index)); + + if (inst->SrcReg[i].File != PROGRAM_TEMPORARY) + continue; + + int j; + for(j = 0; j < 4; ++j) { + GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j); + if (swz >= 4) + continue; + if (!t->Value[swz]) + continue; + + /* Do not free a dependency if this instruction + * also rewrites the value. See scan_instructions. */ + if (inst->DstReg.File == PROGRAM_TEMPORARY && + inst->DstReg.Index == inst->SrcReg[i].Index && + GET_BIT(inst->DstReg.WriteMask, swz)) + continue; + + if (!--t->Value[swz]->NumReaders) { + if (t->Value[swz]->Next) + decrement_dependencies(s, t->Value[swz]->Next->IP); + } + } + } +} + + +/** + * Emit all ready texture instructions in a single block. + * + * Emit as a single block to (hopefully) sample many textures in parallel, + * and to avoid hardware indirections on R300. + * + * In R500, we don't really know when the result of a texture instruction + * arrives. So allocate all destinations first, to make sure they do not + * arrive early and overwrite a texture coordinate we're going to use later + * in the block. + */ +static void emit_all_tex(struct pair_state *s) +{ + struct pair_state_instruction *readytex; + struct pair_state_instruction *pairinst; + + ASSERT(s->ReadyTEX); + + // Don't let the ready list change under us! + readytex = s->ReadyTEX; + s->ReadyTEX = 0; + + // Allocate destination hardware registers in one block to avoid conflicts. + for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) { + int ip = pairinst - s->Instructions; + struct prog_instruction *inst = s->Program->Instructions + ip; + if (inst->Opcode != OPCODE_KIL) + get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index); + } + + if (s->Debug) + _mesa_printf(" BEGIN_TEX\n"); + + if (s->Handler->BeginTexBlock) + s->Error = s->Error || !s->Handler->BeginTexBlock(s->UserData); + + for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) { + int ip = pairinst - s->Instructions; + struct prog_instruction *inst = s->Program->Instructions + ip; + commit_instruction(s, ip); + + if (inst->Opcode != OPCODE_KIL) + inst->DstReg.Index = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index); + inst->SrcReg[0].Index = get_hw_reg(s, inst->SrcReg[0].File, inst->SrcReg[0].Index); + + if (s->Debug) { + _mesa_printf(" "); + _mesa_print_instruction(inst); + } + s->Error = s->Error || !s->Handler->EmitTex(s->UserData, inst); + } + + if (s->Debug) + _mesa_printf(" END_TEX\n"); +} + + +static int alloc_pair_source(struct pair_state *s, struct radeon_pair_instruction *pair, + struct prog_src_register src, GLboolean rgb, GLboolean alpha) +{ + int candidate = -1; + int candidate_quality = -1; + int i; + + if (!rgb && !alpha) + return 0; + + GLuint constant; + GLuint index; + + if (src.File == PROGRAM_TEMPORARY || src.File == PROGRAM_INPUT) { + constant = 0; + index = get_hw_reg(s, src.File, src.Index); + } else { + constant = 1; + s->Error |= !s->Handler->EmitConst(s->UserData, src.File, src.Index, &index); + } + + for(i = 0; i < 3; ++i) { + int q = 0; + if (rgb) { + if (pair->RGB.Src[i].Used) { + if (pair->RGB.Src[i].Constant != constant || + pair->RGB.Src[i].Index != index) + continue; + q++; + } + } + if (alpha) { + if (pair->Alpha.Src[i].Used) { + if (pair->Alpha.Src[i].Constant != constant || + pair->Alpha.Src[i].Index != index) + continue; + q++; + } + } + if (q > candidate_quality) { + candidate_quality = q; + candidate = i; + } + } + + if (candidate >= 0) { + if (rgb) { + pair->RGB.Src[candidate].Used = 1; + pair->RGB.Src[candidate].Constant = constant; + pair->RGB.Src[candidate].Index = index; + } + if (alpha) { + pair->Alpha.Src[candidate].Used = 1; + pair->Alpha.Src[candidate].Constant = constant; + pair->Alpha.Src[candidate].Index = index; + } + } + + return candidate; +} + + + +/** + * Fill the given ALU instruction's opcodes and source operands into the given pair, + * if possible. + */ +static GLboolean fill_instruction_into_pair(struct pair_state *s, struct radeon_pair_instruction *pair, int ip) +{ + struct pair_state_instruction *pairinst = s->Instructions + ip; + struct prog_instruction *inst = s->Program->Instructions + ip; + + ASSERT(!pairinst->NeedRGB || pair->RGB.Opcode == OPCODE_NOP); + ASSERT(!pairinst->NeedAlpha || pair->Alpha.Opcode == OPCODE_NOP); + + if (pairinst->NeedRGB) { + if (pairinst->IsTranscendent) + pair->RGB.Opcode = OPCODE_REPL_ALPHA; + else + pair->RGB.Opcode = inst->Opcode; + if (inst->SaturateMode == SATURATE_ZERO_ONE) + pair->RGB.Saturate = 1; + } + if (pairinst->NeedAlpha) { + pair->Alpha.Opcode = inst->Opcode; + if (inst->SaturateMode == SATURATE_ZERO_ONE) + pair->Alpha.Saturate = 1; + } + + int nargs = _mesa_num_inst_src_regs(inst->Opcode); + int i; + + for(i = 0; i < nargs; ++i) { + int source; + if (pairinst->NeedRGB && !pairinst->IsTranscendent) { + GLboolean srcrgb = GL_FALSE; + GLboolean srcalpha = GL_FALSE; + GLuint negatebase = 0; + int j; + for(j = 0; j < 3; ++j) { + GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j); + if (swz < 3) + srcrgb = GL_TRUE; + else if (swz < 4) + srcalpha = GL_TRUE; + if (swz != SWIZZLE_NIL && GET_BIT(inst->SrcReg[i].NegateBase, j)) + negatebase = 1; + } + source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha); + if (source < 0) + return GL_FALSE; + pair->RGB.Arg[i].Source = source; + pair->RGB.Arg[i].Swizzle = inst->SrcReg[i].Swizzle & 0x1ff; + pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs; + pair->RGB.Arg[i].Negate = (negatebase & ~pair->RGB.Arg[i].Abs) ^ inst->SrcReg[i].NegateAbs; + } + if (pairinst->NeedAlpha) { + GLboolean srcrgb = GL_FALSE; + GLboolean srcalpha = GL_FALSE; + GLuint negatebase = GET_BIT(inst->SrcReg[i].NegateBase, pairinst->IsTranscendent ? 0 : 3); + GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, pairinst->IsTranscendent ? 0 : 3); + if (swz < 3) + srcrgb = GL_TRUE; + else if (swz < 4) + srcalpha = GL_TRUE; + source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha); + if (source < 0) + return GL_FALSE; + pair->Alpha.Arg[i].Source = source; + pair->Alpha.Arg[i].Swizzle = swz; + pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs; + pair->Alpha.Arg[i].Negate = (negatebase & ~pair->RGB.Arg[i].Abs) ^ inst->SrcReg[i].NegateAbs; + } + } + + return GL_TRUE; +} + + +/** + * Fill in the destination register information. + * + * This is split from filling in source registers because we want + * to avoid allocating hardware temporaries for destinations until + * we are absolutely certain that we're going to emit a certain + * instruction pairing. + */ +static void fill_dest_into_pair(struct pair_state *s, struct radeon_pair_instruction *pair, int ip) +{ + struct pair_state_instruction *pairinst = s->Instructions + ip; + struct prog_instruction *inst = s->Program->Instructions + ip; + + if (inst->DstReg.File == PROGRAM_OUTPUT) { + if (inst->DstReg.Index == FRAG_RESULT_COLR) { + pair->RGB.OutputWriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ; + pair->Alpha.OutputWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); + } else if (inst->DstReg.Index == FRAG_RESULT_DEPR) { + pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); + } + } else { + GLuint hwindex = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index); + if (pairinst->NeedRGB) { + pair->RGB.DestIndex = hwindex; + pair->RGB.WriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ; + } + if (pairinst->NeedAlpha) { + pair->Alpha.DestIndex = hwindex; + pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); + } + } +} + + +/** + * Find a good ALU instruction or pair of ALU instruction and emit it. + * + * Prefer emitting full ALU instructions, so that when we reach a point + * where no full ALU instruction can be emitted, we have more candidates + * for RGB/Alpha pairing. + */ +static void emit_alu(struct pair_state *s) +{ + struct radeon_pair_instruction pair; + + if (s->ReadyFullALU || !(s->ReadyRGB && s->ReadyAlpha)) { + int ip; + if (s->ReadyFullALU) { + ip = s->ReadyFullALU - s->Instructions; + s->ReadyFullALU = s->ReadyFullALU->NextReady; + } else if (s->ReadyRGB) { + ip = s->ReadyRGB - s->Instructions; + s->ReadyRGB = s->ReadyRGB->NextReady; + } else { + ip = s->ReadyAlpha - s->Instructions; + s->ReadyAlpha = s->ReadyAlpha->NextReady; + } + + _mesa_bzero(&pair, sizeof(pair)); + fill_instruction_into_pair(s, &pair, ip); + fill_dest_into_pair(s, &pair, ip); + commit_instruction(s, ip); + } else { + struct pair_state_instruction **prgb; + struct pair_state_instruction **palpha; + + /* Some pairings might fail because they require too + * many source slots; try all possible pairings if necessary */ + for(prgb = &s->ReadyRGB; *prgb; prgb = &(*prgb)->NextReady) { + for(palpha = &s->ReadyAlpha; *palpha; palpha = &(*palpha)->NextReady) { + int rgbip = *prgb - s->Instructions; + int alphaip = *palpha - s->Instructions; + _mesa_bzero(&pair, sizeof(pair)); + fill_instruction_into_pair(s, &pair, rgbip); + if (!fill_instruction_into_pair(s, &pair, alphaip)) + continue; + *prgb = (*prgb)->NextReady; + *palpha = (*palpha)->NextReady; + fill_dest_into_pair(s, &pair, rgbip); + fill_dest_into_pair(s, &pair, alphaip); + commit_instruction(s, rgbip); + commit_instruction(s, alphaip); + goto success; + } + } + + /* No success in pairing; just take the first RGB instruction */ + int ip = s->ReadyRGB - s->Instructions; + s->ReadyRGB = s->ReadyRGB->NextReady; + _mesa_bzero(&pair, sizeof(pair)); + fill_instruction_into_pair(s, &pair, ip); + fill_dest_into_pair(s, &pair, ip); + commit_instruction(s, ip); + success: ; + } + + if (s->Debug) + radeonPrintPairInstruction(&pair); + + s->Error = s->Error || !s->Handler->EmitPaired(s->UserData, &pair); +} + + +GLboolean radeonPairProgram(GLcontext *ctx, struct gl_program *program, + const struct radeon_pair_handler* handler, void *userdata) +{ + struct pair_state s; + + _mesa_bzero(&s, sizeof(s)); + s.Ctx = ctx; + s.Program = program; + s.Handler = handler; + s.UserData = userdata; + s.Debug = (RADEON_DEBUG & DEBUG_PIXEL) ? GL_TRUE : GL_FALSE; + s.Verbose = GL_FALSE && s.Debug; + + s.Instructions = (struct pair_state_instruction*)_mesa_calloc( + sizeof(struct pair_state_instruction)*s.Program->NumInstructions); + s.ValuePool = (struct reg_value*)_mesa_calloc(sizeof(struct reg_value)*s.Program->NumInstructions*4); + s.ReaderPool = (struct reg_value_reader*)_mesa_calloc( + sizeof(struct reg_value_reader)*s.Program->NumInstructions*12); + + if (s.Debug) + _mesa_printf("Emit paired program\n"); + + scan_instructions(&s); + allocate_input_registers(&s); + + while(!s.Error && + (s.ReadyTEX || s.ReadyRGB || s.ReadyAlpha || s.ReadyFullALU)) { + if (s.ReadyTEX) + emit_all_tex(&s); + + while(s.ReadyFullALU || s.ReadyRGB || s.ReadyAlpha) + emit_alu(&s); + } + + if (s.Debug) + _mesa_printf(" END\n"); + + _mesa_free(s.Instructions); + _mesa_free(s.ValuePool); + _mesa_free(s.ReaderPool); + + return !s.Error; +} + + +static void print_pair_src(int i, struct radeon_pair_instruction_source* src) +{ + _mesa_printf(" Src%i = %s[%i]", i, src->Constant ? "CNST" : "TEMP", src->Index); +} + +static const char* opcode_string(GLuint opcode) +{ + if (opcode == OPCODE_REPL_ALPHA) + return "SOP"; + else + return _mesa_opcode_string(opcode); +} + +static int num_pairinst_args(GLuint opcode) +{ + if (opcode == OPCODE_REPL_ALPHA) + return 0; + else + return _mesa_num_inst_src_regs(opcode); +} + +static char swizzle_char(GLuint swz) +{ + switch(swz) { + case SWIZZLE_X: return 'x'; + case SWIZZLE_Y: return 'y'; + case SWIZZLE_Z: return 'z'; + case SWIZZLE_W: return 'w'; + case SWIZZLE_ZERO: return '0'; + case SWIZZLE_ONE: return '1'; + case SWIZZLE_NIL: return '_'; + default: return '?'; + } +} + +void radeonPrintPairInstruction(struct radeon_pair_instruction *inst) +{ + int nargs; + int i; + + _mesa_printf(" RGB: "); + for(i = 0; i < 3; ++i) { + if (inst->RGB.Src[i].Used) + print_pair_src(i, inst->RGB.Src + i); + } + _mesa_printf("\n"); + _mesa_printf(" Alpha:"); + for(i = 0; i < 3; ++i) { + if (inst->Alpha.Src[i].Used) + print_pair_src(i, inst->Alpha.Src + i); + } + _mesa_printf("\n"); + + _mesa_printf(" %s%s", opcode_string(inst->RGB.Opcode), inst->RGB.Saturate ? "_SAT" : ""); + if (inst->RGB.WriteMask) + _mesa_printf(" TEMP[%i].%s%s%s", inst->RGB.DestIndex, + (inst->RGB.WriteMask & 1) ? "x" : "", + (inst->RGB.WriteMask & 2) ? "y" : "", + (inst->RGB.WriteMask & 4) ? "z" : ""); + if (inst->RGB.OutputWriteMask) + _mesa_printf(" COLOR.%s%s%s", + (inst->RGB.OutputWriteMask & 1) ? "x" : "", + (inst->RGB.OutputWriteMask & 2) ? "y" : "", + (inst->RGB.OutputWriteMask & 4) ? "z" : ""); + nargs = num_pairinst_args(inst->RGB.Opcode); + for(i = 0; i < nargs; ++i) { + const char* abs = inst->RGB.Arg[i].Abs ? "|" : ""; + const char* neg = inst->RGB.Arg[i].Negate ? "-" : ""; + _mesa_printf(", %s%sSrc%i.%c%c%c%s", neg, abs, inst->RGB.Arg[i].Source, + swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 0)), + swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 1)), + swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 2)), + abs); + } + _mesa_printf("\n"); + + _mesa_printf(" %s%s", opcode_string(inst->Alpha.Opcode), inst->Alpha.Saturate ? "_SAT" : ""); + if (inst->Alpha.WriteMask) + _mesa_printf(" TEMP[%i].w", inst->Alpha.DestIndex); + if (inst->Alpha.OutputWriteMask) + _mesa_printf(" COLOR.w"); + if (inst->Alpha.DepthWriteMask) + _mesa_printf(" DEPTH.w"); + nargs = num_pairinst_args(inst->Alpha.Opcode); + for(i = 0; i < nargs; ++i) { + const char* abs = inst->Alpha.Arg[i].Abs ? "|" : ""; + const char* neg = inst->Alpha.Arg[i].Negate ? "-" : ""; + _mesa_printf(", %s%sSrc%i.%c%s", neg, abs, inst->Alpha.Arg[i].Source, + swizzle_char(inst->Alpha.Arg[i].Swizzle), abs); + } + _mesa_printf("\n"); +} diff --git a/src/mesa/drivers/dri/r300/radeon_program_pair.h b/src/mesa/drivers/dri/r300/radeon_program_pair.h new file mode 100644 index 00000000000..4624a246298 --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_program_pair.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RADEON_PROGRAM_PAIR_H_ +#define __RADEON_PROGRAM_PAIR_H_ + +#include "radeon_program.h" + + +/** + * Represents a paired instruction, as found in R300 and R500 + * fragment programs. + */ +struct radeon_pair_instruction_source { + GLuint Index:8; + GLuint Constant:1; + GLuint Used:1; +}; + +struct radeon_pair_instruction_rgb { + GLuint Opcode:8; + GLuint DestIndex:8; + GLuint WriteMask:3; + GLuint OutputWriteMask:3; + GLuint Saturate:1; + + struct radeon_pair_instruction_source Src[3]; + + struct { + GLuint Source:2; + GLuint Swizzle:9; + GLuint Abs:1; + GLuint Negate:1; + } Arg[3]; +}; + +struct radeon_pair_instruction_alpha { + GLuint Opcode:8; + GLuint DestIndex:8; + GLuint WriteMask:1; + GLuint OutputWriteMask:1; + GLuint DepthWriteMask:1; + GLuint Saturate:1; + + struct radeon_pair_instruction_source Src[3]; + + struct { + GLuint Source:2; + GLuint Swizzle:3; + GLuint Abs:1; + GLuint Negate:1; + } Arg[3]; +}; + +struct radeon_pair_instruction { + struct radeon_pair_instruction_rgb RGB; + struct radeon_pair_instruction_alpha Alpha; +}; + + +/** + * + */ +struct radeon_pair_handler { + /** + * Fill in the proper hardware index for the given constant register. + * + * @return GL_FALSE on error. + */ + GLboolean (*EmitConst)(void*, GLuint file, GLuint index, GLuint *hwindex); + + /** + * Write a paired instruction to the hardware. + * + * @return GL_FALSE on error. + */ + GLboolean (*EmitPaired)(void*, struct radeon_pair_instruction*); + + /** + * Write a texture instruction to the hardware. + * Register indices have already been rewritten to the allocated + * hardware register numbers. + * + * @return GL_FALSE on error. + */ + GLboolean (*EmitTex)(void*, struct prog_instruction*); + + /** + * Called before a block of contiguous, independent texture + * instructions is emitted. + */ + GLboolean (*BeginTexBlock)(void*); + + GLuint MaxHwTemps; +}; + +GLboolean radeonPairProgram(GLcontext *ctx, struct gl_program *program, + const struct radeon_pair_handler*, void *userdata); + +void radeonPrintPairInstruction(struct radeon_pair_instruction *inst); + +#endif /* __RADEON_PROGRAM_PAIR_H_ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 7c45c37b03e..bc43fc59601 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -161,6 +161,8 @@ struct radeon_tex_obj { drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; /* Six, for the cube faces */ + GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ + GLuint pp_txfilter; /* hardware register values */ GLuint pp_txformat; GLuint pp_txoffset; /* Image location in texmem. diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index b647cffa0e7..84b5c46bf16 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -49,6 +49,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #if !RADEON_COMMON #include "radeon_context.h" #include "radeon_span.h" +#include "radeon_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) #include "r200_context.h" #include "r200_ioctl.h" @@ -194,8 +195,7 @@ DRI_CONF_BEGIN DRI_CONF_SECTION_QUALITY DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") - DRI_CONF_NO_NEG_LOD_BIAS(false) - DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) DRI_CONF_DISABLE_S3TC(false) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) @@ -206,7 +206,7 @@ DRI_CONF_BEGIN DRI_CONF_NO_RAST(false) DRI_CONF_SECTION_END DRI_CONF_END; -static const GLuint __driNConfigOptions = 18; +static const GLuint __driNConfigOptions = 17; #ifndef RADEON_DEBUG int RADEON_DEBUG = 0; @@ -244,10 +244,10 @@ radeonGetParam(int fd, int param, void *value) { int ret; drm_radeon_getparam_t gp; - + gp.param = param; gp.value = value; - + ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); return ret; } @@ -280,7 +280,7 @@ radeonFillInModes( __DRIscreenPrivate *psp, depth_bits_array[0] = depth_bits; depth_bits_array[1] = depth_bits; - + /* Just like with the accumulation buffer, always provide some modes * with a stencil buffer. It will be a sw fallback, but some apps won't * care about that. @@ -322,6 +322,13 @@ radeonFillInModes( __DRIscreenPrivate *psp, return (const __DRIconfig **) configs; } +#if !RADEON_COMMON +static const __DRItexOffsetExtension radeonTexOffsetExtension = { + { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, + radeonSetTexOffset, +}; +#endif + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) static const __DRIallocateExtension r200AllocateExtension = { { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, @@ -384,7 +391,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) int ret; ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, &screen->gart_buffer_offset); - + if (ret) { FREE( screen ); fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); @@ -935,6 +942,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->extensions[i++] = &driMediaStreamCounterExtension.base; } +#if !RADEON_COMMON + screen->extensions[i++] = &radeonTexOffsetExtension.base; +#endif + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) if (IS_R200_CLASS(screen)) screen->extensions[i++] = &r200AllocateExtension.base; @@ -1133,7 +1144,7 @@ static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) /** * This is the driver specific part of the createNewScreen entry point. - * + * * \todo maybe fold this into intelInitDriver * * \return the __GLcontextModes supported by this driver diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h index a806981ae62..0b955eda146 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h @@ -38,6 +38,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_TEX_H__ #define __RADEON_TEX_H__ +extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); + extern void radeonUpdateTextureState( GLcontext *ctx ); extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c index 20f25dd34b4..0a3d745bd04 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texmem.c +++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c @@ -334,7 +334,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac { int numLevels; - if ( !t || t->base.totalSize == 0 ) + if ( !t || t->base.totalSize == 0 || t->image_override ) return 0; if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) { diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 37bb749223a..ecd375473bc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -40,6 +40,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "context.h" #include "macros.h" #include "texformat.h" +#include "texobj.h" #include "enums.h" #include "radeon_context.h" @@ -84,7 +85,7 @@ tx_table[] = _ALPHA_REV(RGBA8888), _ALPHA(ARGB8888), _ALPHA_REV(ARGB8888), - _INVALID(RGB888), + [ MESA_FORMAT_RGB888 ] = { RADEON_TXFORMAT_ARGB8888, 0 }, _COLOR(RGB565), _COLOR_REV(RGB565), _ALPHA(ARGB4444), @@ -134,18 +135,19 @@ static void radeonSetTexImages( radeonContextPtr rmesa, /* Set the hardware texture format */ - - t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | - RADEON_TXFORMAT_ALPHA_IN_MAP); - t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - - if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) { - t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter; - } - else { - _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; + if ( !t->image_override ) { + t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | + RADEON_TXFORMAT_ALPHA_IN_MAP); + t->pp_txfilter &= ~RADEON_YUV_TO_RGB; + + if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) { + t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format; + t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter; + } + else { + _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); + return; + } } texelBytes = baseImage->TexFormat->TexelBytes; @@ -341,11 +343,13 @@ static void radeonSetTexImages( radeonContextPtr rmesa, * requires 64-byte aligned pitches, and we may/may not need the * blitter. NPOT only! */ - if (baseImage->IsCompressed) - t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); - else - t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63); - t->pp_txpitch -= 32; + if ( !t->image_override ) { + if (baseImage->IsCompressed) + t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); + else + t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63); + t->pp_txpitch -= 32; + } t->dirty_state = TEX_ALL; @@ -840,6 +844,44 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit ) return GL_TRUE; } +void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, + unsigned long long offset, GLint depth, GLuint pitch) +{ + radeonContextPtr rmesa = pDRICtx->driverPrivate; + struct gl_texture_object *tObj = + _mesa_lookup_texture(rmesa->glCtx, texname); + radeonTexObjPtr t; + + if (tObj == NULL) + return; + + t = (radeonTexObjPtr) tObj->DriverData; + + t->image_override = GL_TRUE; + + if (!offset) + return; + + t->pp_txoffset = offset; + t->pp_txpitch = pitch - 32; + + switch (depth) { + case 32: + t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; + t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; + break; + case 24: + default: + t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; + t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter; + break; + case 16: + t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format; + t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; + break; + } +} + #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \ RADEON_MIN_FILTER_MASK | \ RADEON_MAG_FILTER_MASK | \ @@ -1136,7 +1178,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) RADEON_FIREVERTICES( rmesa ); radeonSetTexImages( rmesa, tObj ); radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock ) + if ( !t->base.memBlock && !t->image_override ) return GL_FALSE; } @@ -1203,7 +1245,8 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) RADEON_FIREVERTICES( rmesa ); radeonSetTexImages( rmesa, tObj ); radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock /* && !rmesa->prefer_gart_client_texturing FIXME */ ) { + if ( !t->base.memBlock && + !t->image_override /* && !rmesa->prefer_gart_client_texturing FIXME */ ) { fprintf(stderr, "%s: upload failed\n", __FUNCTION__); return GL_FALSE; } diff --git a/src/mesa/drivers/fbdev/Makefile b/src/mesa/drivers/fbdev/Makefile index c0ef54f604f..ee73f29a46a 100644 --- a/src/mesa/drivers/fbdev/Makefile +++ b/src/mesa/drivers/fbdev/Makefile @@ -25,8 +25,7 @@ default: $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME) $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME): $(CORE_MESA) $(OBJECTS) - @ $(TOP)/bin/mklib -o $(GL_LIB) \ - -linker '$(CC)' -ldflags '$(LDFLAGS)' \ + @ $(MKLIB) -o $(GL_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ -install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) \ $(CORE_MESA) $(OBJECTS) $(GL_LIB_DEPS) diff --git a/src/mesa/drivers/osmesa/Makefile b/src/mesa/drivers/osmesa/Makefile index fa8dffcb3ef..8b2feee6b0e 100644 --- a/src/mesa/drivers/osmesa/Makefile +++ b/src/mesa/drivers/osmesa/Makefile @@ -45,11 +45,9 @@ default: osmesa8: $(TOP)/lib/$(OSMESA_LIB_NAME) $(TOP)/lib/$(OSMESA_LIB_NAME): $(OBJECTS) - $(TOP)/bin/mklib -o $(OSMESA_LIB) \ - -linker "$(CC)" \ + $(MKLIB) -o $(OSMESA_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ - -install $(TOP)/$(LIB_DIR) \ - $(MKLIB_OPTIONS) \ + -install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) \ $(OSMESA_LIB_DEPS) $(OBJECTS) @@ -58,11 +56,9 @@ $(TOP)/lib/$(OSMESA_LIB_NAME): $(OBJECTS) # The libOSMesa16/libOSMesa32 libraries do not use libGL but rather are built # with all the other Mesa sources (compiled with -DCHAN_BITS=16/32 osmesa16: $(OBJECTS) $(CORE_MESA) - $(TOP)/bin/mklib -o $(OSMESA_LIB) \ - -linker "$(CC)" \ + $(MKLIB) -o $(OSMESA_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ - -install $(TOP)/$(LIB_DIR) \ - $(MKLIB_OPTIONS) \ + -install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) \ $(OSMESA_LIB_DEPS) $(OBJECTS) $(CORE_MESA) diff --git a/src/mesa/drivers/x11/Makefile b/src/mesa/drivers/x11/Makefile index 51226eeae11..b025246e634 100644 --- a/src/mesa/drivers/x11/Makefile +++ b/src/mesa/drivers/x11/Makefile @@ -55,11 +55,10 @@ default: $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME) $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME): $(OBJECTS) $(CORE_MESA) - @ $(TOP)/bin/mklib -o $(GL_LIB) \ - -linker '$(CC)' -ldflags '$(LDFLAGS)' \ + @ $(MKLIB) -o $(GL_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \ -major $(GL_MAJOR) -minor $(GL_MINOR) -patch $(GL_TINY) \ - -install $(TOP)/$(LIB_DIR) \ - $(MKLIB_OPTIONS) $(GL_LIB_DEPS) $(OBJECTS) $(CORE_MESA) + -install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) \ + $(GL_LIB_DEPS) $(OBJECTS) $(CORE_MESA) diff --git a/src/mesa/drivers/x11/xm_tri.c b/src/mesa/drivers/x11/xm_tri.c index c87a2937567..77fceec194c 100644 --- a/src/mesa/drivers/x11/xm_tri.c +++ b/src/mesa/drivers/x11/xm_tri.c @@ -66,7 +66,7 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLint x = span.x, y = YFLIP(xrb, span.y); \ GLuint i; \ for (i = 0; i < span.end; i++, x++) { \ @@ -82,7 +82,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -102,7 +102,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -117,7 +117,7 @@ span.blue += span.blueStep; \ span.alpha += span.alphaStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -137,7 +137,7 @@ #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -152,7 +152,7 @@ span.blue += span.blueStep; \ span.alpha += span.alphaStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -171,7 +171,7 @@ #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -184,7 +184,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -202,7 +202,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -217,7 +217,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -232,7 +232,7 @@ #define SETUP_CODE \ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -248,7 +248,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -265,7 +265,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -278,7 +278,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -296,7 +296,7 @@ #define SETUP_CODE \ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -310,7 +310,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -327,7 +327,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ XDITHER_SETUP(y); \ @@ -342,7 +342,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -357,7 +357,7 @@ #define SETUP_CODE \ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ XDITHER_SETUP(y); \ @@ -373,7 +373,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -390,7 +390,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ LOOKUP_SETUP; \ for (i = 0; i < span.end; i++) { \ @@ -404,7 +404,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -422,7 +422,7 @@ #define SETUP_CODE \ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -436,7 +436,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -453,7 +453,7 @@ XMesaImage *img = xrb->ximage; \ unsigned long pixel; \ PACK_TRUECOLOR(pixel, v2->color[0], v2->color[1], v2->color[2]); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -463,7 +463,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -481,7 +481,7 @@ GET_XRB(xrb); \ GLuint p = PACK_8A8B8G8R( v2->color[0], v2->color[1],\ v2->color[2], v2->color[3]); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -490,7 +490,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -508,7 +508,7 @@ GET_XRB(xrb); \ GLuint p = PACK_8A8R8G8B(v2->color[0], v2->color[1], \ v2->color[2], v2->color[3]); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -517,7 +517,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -534,7 +534,7 @@ #define SETUP_CODE \ GET_XRB(xrb); \ GLuint p = PACK_8R8G8B( v2->color[0], v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -543,7 +543,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -561,7 +561,7 @@ #define SETUP_CODE \ GET_XRB(xrb); \ const GLubyte *color = v2->color; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -573,7 +573,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -588,7 +588,7 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -601,7 +601,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -618,7 +618,7 @@ #define SETUP_CODE \ GET_XRB(xrb); \ GLushort p = PACK_5R6G5B( v2->color[0], v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -627,7 +627,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -645,7 +645,7 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); \ const GLubyte *color = v2->color; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -656,7 +656,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -673,7 +673,7 @@ #define SETUP_CODE \ GET_XRB(xrb); \ FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ FLAT_DITHER_ROW_SETUP(YFLIP(xrb, y)); \ @@ -684,7 +684,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -699,7 +699,7 @@ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; \ FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ FLAT_DITHER_ROW_SETUP(y); \ @@ -711,7 +711,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -731,7 +731,7 @@ GLubyte r = v2->color[0]; \ GLubyte g = v2->color[1]; \ GLubyte b = v2->color[2]; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -741,7 +741,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -762,7 +762,7 @@ GLubyte g = v2->color[1]; \ GLubyte b = v2->color[2]; \ GLubyte p = LOOKUP(r,g,b); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ const DEPTH_TYPE z = FixedToDepth(span.z); \ @@ -771,7 +771,7 @@ zRow[i] = z; \ } \ span.z += span.zStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -785,7 +785,7 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -796,7 +796,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -812,7 +812,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = PACK_8A8B8G8R(FixedToInt(span.red), \ @@ -822,7 +822,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.alpha += span.alphaStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -838,7 +838,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = PACK_8A8R8G8B(FixedToInt(span.red), \ @@ -848,7 +848,7 @@ span.green += span.greenStep; \ span.blue += span.blueStep; \ span.alpha += span.alphaStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -863,7 +863,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = PACK_8R8G8B(FixedToInt(span.red), \ @@ -871,7 +871,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -886,7 +886,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ PIXEL_TYPE *pixel = pRow; \ for (i = 0; i < span.end; i++, pixel++) { \ @@ -896,7 +896,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -910,7 +910,7 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -921,7 +921,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -936,7 +936,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = (PIXEL_TYPE) PACK_5R6G5B(FixedToInt(span.red), \ @@ -944,7 +944,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -960,7 +960,7 @@ #define SETUP_CODE \ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -969,7 +969,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -984,7 +984,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ XDITHER_SETUP(y); \ @@ -994,7 +994,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -1007,7 +1007,7 @@ #define SETUP_CODE \ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ XDITHER_SETUP(y); \ @@ -1018,7 +1018,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -1033,7 +1033,7 @@ #define BYTES_PER_ROW (xrb->ximage->bytes_per_line) #define SETUP_CODE \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ LOOKUP_SETUP; \ for (i = 0; i < span.end; i++) { \ @@ -1042,7 +1042,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -1058,7 +1058,7 @@ #define SETUP_CODE \ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -1067,7 +1067,7 @@ span.red += span.redStep; \ span.green += span.greenStep; \ span.blue += span.blueStep; \ - } + } } #include "swrast/s_tritemp.h" @@ -1082,12 +1082,12 @@ XMesaImage *img = xrb->ximage; \ unsigned long pixel; \ PACK_TRUECOLOR(pixel, v2->color[0], v2->color[1], v2->color[2]); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ XMesaPutPixel(img, x, y, pixel); \ - } + } } #include "swrast/s_tritemp.h" @@ -1103,11 +1103,11 @@ GET_XRB(xrb); \ unsigned long p = PACK_8B8G8R( v2->color[0], \ v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = (PIXEL_TYPE) p; \ - } + } } #include "swrast/s_tritemp.h" @@ -1123,11 +1123,11 @@ GET_XRB(xrb); \ unsigned long p = PACK_8R8G8B( v2->color[0], \ v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = (PIXEL_TYPE) p; \ - } + } } #include "swrast/s_tritemp.h" @@ -1143,11 +1143,11 @@ GET_XRB(xrb); \ unsigned long p = PACK_8R8G8B( v2->color[0], \ v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = (PIXEL_TYPE) p; \ - } + } } #include "swrast/s_tritemp.h" @@ -1162,14 +1162,14 @@ #define SETUP_CODE \ GET_XRB(xrb); \ const GLubyte *color = v2->color; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ PIXEL_TYPE *pixel = pRow; \ for (i = 0; i < span.end; i++, pixel++) { \ pixel->r = color[RCOMP]; \ pixel->g = color[GCOMP]; \ pixel->b = color[BCOMP]; \ - } + } } #include "swrast/s_tritemp.h" @@ -1182,7 +1182,7 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ @@ -1190,7 +1190,7 @@ PACK_TRUEDITHER(p, x, y, v2->color[0], \ v2->color[1], v2->color[2] ); \ XMesaPutPixel(img, x, y, p); \ - } + } } #include "swrast/s_tritemp.h" @@ -1206,11 +1206,11 @@ GET_XRB(xrb); \ unsigned long p = PACK_5R6G5B( v2->color[0], \ v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = (PIXEL_TYPE) p; \ - } + } } #include "swrast/s_tritemp.h" @@ -1226,13 +1226,13 @@ XMesaContext xmesa = XMESA_CONTEXT(ctx); \ GET_XRB(xrb); \ const GLubyte *color = v2->color; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ PACK_TRUEDITHER(pRow[i], x, y, color[RCOMP], \ color[GCOMP], color[BCOMP]); \ - } + } } #include "swrast/s_tritemp.h" @@ -1247,13 +1247,13 @@ #define SETUP_CODE \ GET_XRB(xrb); \ FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ FLAT_DITHER_ROW_SETUP(YFLIP(xrb, y)); \ for (i = 0; i < span.end; i++, x++) { \ pRow[i] = (PIXEL_TYPE) FLAT_DITHER(x); \ - } + } } #include "swrast/s_tritemp.h" @@ -1266,14 +1266,14 @@ GET_XRB(xrb); \ XMesaImage *img = xrb->ximage; \ FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] ); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ FLAT_DITHER_ROW_SETUP(y); \ for (i = 0; i < span.end; i++, x++) { \ unsigned long p = FLAT_DITHER(x); \ XMesaPutPixel(img, x, y, p ); \ - } + } } #include "swrast/s_tritemp.h" @@ -1291,12 +1291,12 @@ GLubyte r = v2->color[0]; \ GLubyte g = v2->color[1]; \ GLubyte b = v2->color[2]; -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ GLint x = span.x, y = YFLIP(xrb, span.y); \ for (i = 0; i < span.end; i++, x++) { \ pRow[i] = (PIXEL_TYPE) DITHER_HPCR(x, y, r, g, b); \ - } + } } #include "swrast/s_tritemp.h" @@ -1315,11 +1315,11 @@ GLubyte g = v2->color[1]; \ GLubyte b = v2->color[2]; \ GLubyte p = LOOKUP(r,g,b); -#define RENDER_SPAN( span ) \ +#define RENDER_SPAN( span ) { \ GLuint i; \ for (i = 0; i < span.end; i++) { \ pRow[i] = (PIXEL_TYPE) p; \ - } + } } #include "swrast/s_tritemp.h" |