diff options
author | Kenneth Graunke <[email protected]> | 2015-08-29 00:01:15 -0700 |
---|---|---|
committer | Kenneth Graunke <[email protected]> | 2015-09-26 11:59:56 -0700 |
commit | 6301af22bb80b2c177539074e3b2c68e65c15d41 (patch) | |
tree | 4161b8dab72e1150e3e301b407d478ee328230a3 /src/mesa/drivers | |
parent | 99df02ca26f6127c8fa24d38a8a069ac6159356a (diff) |
i965/gs: Remove the dependency on the VS VUE map.
Because we only support geometry shaders in core profile, we can safely
ignore any driver-extending of VS outputs.
Those are:
- Legacy userclipping (doesn't exist in core profile)
- Edgeflag copying (Gen4-5 only, no GS support)
- Point coord replacement (Gen4-5 only, no GS support)
- front/back color hacks (Gen4-5 only, no GS support)
v2: Rebase; leave a comment about why SSO works.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.c | 23 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_program.h | 2 |
2 files changed, 14 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 38b3e3a5cd9..77be9d9beda 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -243,8 +243,21 @@ brw_codegen_gs_prog(struct brw_context *brw, c.prog_data.output_topology = get_hw_prim_for_gl_prim(gp->program.OutputType); + /* The GLSL linker will have already matched up GS inputs and the outputs + * of prior stages. The driver does extend VS outputs in some cases, but + * only for legacy OpenGL or Gen4-5 hardware, neither of which offer + * geometry shader support. So we can safely ignore that. + * + * For SSO pipelines, we use a fixed VUE map layout based on variable + * locations, so we can rely on rendezvous-by-location making this work. + * + * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not + * written by previous stages and shows up via payload magic. + */ + GLbitfield64 inputs_read = + gp->program.Base.InputsRead & ~VARYING_BIT_PRIMITIVE_ID; brw_compute_vue_map(brw->intelScreen->devinfo, - &c.input_vue_map, c.key.input_varyings, + &c.input_vue_map, inputs_read, prog->SeparateShader); /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we @@ -305,9 +318,6 @@ brw_gs_populate_key(struct brw_context *brw, /* _NEW_TEXTURE */ brw_populate_sampler_prog_key_data(ctx, prog, stage_state->sampler_count, &key->tex); - - /* BRW_NEW_VUE_MAP_VS */ - key->input_varyings = brw->vue_map_vs.slots_valid; } void @@ -386,11 +396,6 @@ brw_gs_precompile(struct gl_context *ctx, brw_setup_tex_for_precompile(brw, &key.tex, prog); key.program_string_id = bgp->id; - /* Assume that the set of varyings coming in from the vertex shader exactly - * matches what the geometry shader requires. - */ - key.input_varyings = gp->Base.InputsRead; - success = brw_codegen_gs_prog(brw, shader_prog, bgp, &key); brw->gs.base.prog_offset = old_prog_offset; diff --git a/src/mesa/drivers/dri/i965/brw_program.h b/src/mesa/drivers/dri/i965/brw_program.h index 00e8f3f370e..72d68d869fc 100644 --- a/src/mesa/drivers/dri/i965/brw_program.h +++ b/src/mesa/drivers/dri/i965/brw_program.h @@ -118,8 +118,6 @@ struct brw_gs_prog_key { unsigned program_string_id; - uint64_t input_varyings; - struct brw_sampler_prog_key_data tex; }; |