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authorKenneth Graunke <[email protected]>2013-07-06 00:20:25 -0700
committerKenneth Graunke <[email protected]>2013-07-09 14:09:33 -0700
commit2e26afb37b83effe44b218d5b2a305020b8ad22f (patch)
tree1624d7bd43bed7bb8286ad60ad9f703bc6586610 /src/mesa/drivers
parent794de2f3873bcedc78300b3ba69656adc755894c (diff)
i965: Move intel_context::has_llc to brw_context.
Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h1
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c7
-rw-r--r--src/mesa/drivers/dri/i965/intel_context.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_context.h1
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex_subimage.c3
6 files changed, 7 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index c6e75d562a5..d5c60602e4f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -884,6 +884,7 @@ struct brw_context
bool has_hiz;
bool has_separate_stencil;
bool must_use_separate_stencil;
+ bool has_llc;
bool has_swizzling;
bool has_surface_tile_offset;
bool has_compr4;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index ea85066fdff..e40fe5224a1 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -71,7 +71,7 @@ intel_batchbuffer_init(struct brw_context *brw)
4096, 4096);
}
- if (!intel->has_llc) {
+ if (!brw->has_llc) {
brw->batch.cpu_map = malloc(BATCH_SZ);
brw->batch.map = brw->batch.cpu_map;
}
@@ -80,7 +80,6 @@ intel_batchbuffer_init(struct brw_context *brw)
static void
intel_batchbuffer_reset(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
if (brw->batch.last_bo != NULL) {
drm_intel_bo_unreference(brw->batch.last_bo);
brw->batch.last_bo = NULL;
@@ -91,7 +90,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer",
BATCH_SZ, 4096);
- if (intel->has_llc) {
+ if (brw->has_llc) {
drm_intel_bo_map(brw->batch.bo, true);
brw->batch.map = brw->batch.bo->virtual;
}
@@ -181,7 +180,7 @@ do_flush_locked(struct brw_context *brw)
struct intel_batchbuffer *batch = &brw->batch;
int ret = 0;
- if (intel->has_llc) {
+ if (brw->has_llc) {
drm_intel_bo_unmap(batch->bo);
} else {
ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index a3c1042e5f8..f2717c45090 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -498,7 +498,7 @@ intelInitContext(struct brw_context *brw,
brw->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil;
brw->must_use_separate_stencil = brw->intelScreen->hw_must_use_separate_stencil;
brw->has_hiz = intel->gen >= 6;
- intel->has_llc = brw->intelScreen->hw_has_llc;
+ brw->has_llc = brw->intelScreen->hw_has_llc;
brw->has_swizzling = brw->intelScreen->hw_has_swizzling;
memset(&ctx->TextureFormatSupported,
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 9194d0db04c..ade9f32c16d 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -118,7 +118,6 @@ struct intel_context
*/
int gen;
int gt;
- bool has_llc;
};
/**
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a14b28796e5..25ba85bff2a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2130,7 +2130,7 @@ intel_miptree_map_singlesample(struct brw_context *brw,
intel_miptree_map_depthstencil(brw, mt, map, level, slice);
}
/* See intel_miptree_blit() for details on the 32k pitch limit. */
- else if (intel->has_llc &&
+ else if (brw->has_llc &&
!(mode & GL_MAP_WRITE_BIT) &&
!mt->compressed &&
(mt->region->tiling == I915_TILING_X ||
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 1e4e98c2d7c..5604a7d8e79 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -170,7 +170,6 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
bool for_glTexImage)
{
struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = intel_context(ctx);
struct intel_texture_image *image = intel_texture_image(texImage);
/* The miptree's buffer. */
@@ -182,7 +181,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
* a 2D BGRA texture. It could be generalized to support more types by
* varying the arithmetic loop below.
*/
- if (!intel->has_llc ||
+ if (!brw->has_llc ||
format != GL_BGRA ||
type != GL_UNSIGNED_BYTE ||
texImage->TexFormat != MESA_FORMAT_ARGB8888 ||