diff options
| author | Vladimir Dergachev <[email protected]> | 2005-01-15 04:17:27 +0000 |
|---|---|---|
| committer | Vladimir Dergachev <[email protected]> | 2005-01-15 04:17:27 +0000 |
| commit | dbb3ec35a7acdc795d8d428f2ac35f6167aab464 (patch) | |
| tree | d2922f647c98a7e41f8056be9aa14af41754a7c4 /src/mesa/drivers | |
| parent | ffe7496ac37a61b94c1db676e105fda2c3e6eb18 (diff) | |
Use symbolic constants to describe pixel shader ALU instructions.
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/r300/r300_fixed_pipelines.h | 43 |
1 files changed, 38 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_fixed_pipelines.h b/src/mesa/drivers/dri/r300/r300_fixed_pipelines.h index 0e92ec71455..ab31ec039b6 100644 --- a/src/mesa/drivers/dri/r300/r300_fixed_pipelines.h +++ b/src/mesa/drivers/dri/r300/r300_fixed_pipelines.h @@ -100,8 +100,22 @@ static struct r300_pixel_shader_state FLAT_COLOR_PIXEL_SHADER={ alu: { length: 2, inst: { - {0x50a80, 0x1c020800, 0x40889, 0x1020800}, - {0x50a80, 0x1c020800, 0x40889, 0x1020800} + /* What are 0's ORed with flags ? They are register numbers that + just happen to be 0 */ + { + EASY_PFS_INSTR0(MAD, SRC0C_XYZ, ONE, ZERO), + EASY_PFS_INSTR1(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, NONE, ALL), + EASY_PFS_INSTR2(MAD, SRC0A, ONE, ZERO), + EASY_PFS_INSTR3(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, OUTPUT) + }, + + { + EASY_PFS_INSTR0(MAD, SRC0C_XYZ, ONE, ZERO), + EASY_PFS_INSTR1(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, NONE, ALL), + EASY_PFS_INSTR2(MAD, SRC0A, ONE, ZERO), + EASY_PFS_INSTR3(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, OUTPUT) + } + } }, node: { @@ -235,9 +249,28 @@ static struct r300_pixel_shader_state SINGLE_TEXTURE_PIXEL_SHADER={ alu: { length: 3, inst: { - {0x50a80, 0x1c020800, 0x40889, 0x1020800}, - {0x50200, 0x1c020040, 0x40889, 0x1020801}, - {0x50a80, 0x1c020800, 0x40889, 0x1020800} + /* What are 0's ORed with flags ? They are register numbers that + just happen to be 0 */ + { + EASY_PFS_INSTR0(MAD, SRC0C_XYZ, ONE, ZERO), + EASY_PFS_INSTR1(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, NONE, ALL), + EASY_PFS_INSTR2(MAD, SRC0A, ONE, ZERO), + EASY_PFS_INSTR3(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, OUTPUT) + }, + + { + EASY_PFS_INSTR0(MAD, SRC0C_XYZ, SRC1C_XYZ, ZERO), + EASY_PFS_INSTR1(0, 0, 1, 0 | PFS_FLAG_CONST, NONE, ALL), + EASY_PFS_INSTR2(MAD, SRC0A, ONE, ZERO), + EASY_PFS_INSTR3(0, 1, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, OUTPUT) + }, + + { + EASY_PFS_INSTR0(MAD, SRC0C_XYZ, ONE, ZERO), + EASY_PFS_INSTR1(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, NONE, ALL), + EASY_PFS_INSTR2(MAD, SRC0A, ONE, ZERO), + EASY_PFS_INSTR3(0, 0, 0 | PFS_FLAG_CONST, 0 | PFS_FLAG_CONST, OUTPUT) + } } }, node: { |