diff options
| author | Matt Turner <[email protected]> | 2015-02-15 14:03:09 -0800 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2015-02-24 14:08:04 -0800 |
| commit | b8582d18e6b0737c4a34777837c10898ed177e30 (patch) | |
| tree | 64d14ff55d3cace940c48542b45af744c4ca97e4 /src/mesa/drivers | |
| parent | 7a997a386375a98b70ae5e1d880c8d47f236de8d (diff) | |
i965/fs/nir: Optimize integer multiply by a 16-bit constant.
Gen8+ support was just broken, since MUL now consumes 32-bits from both
sources. Fixes 986 piglit tests on my BDW.
total instructions in shared programs: 7753873 -> 7753522 (-0.00%)
instructions in affected programs: 28164 -> 27813 (-1.25%)
helped: 77
GAINED: 47
Reviewed-by: Ian Romanick <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index d41e77d67c8..03e9ee80e13 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -832,7 +832,29 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_imul: { - /* TODO put in the 16-bit constant optimization once we have SSA */ + if (brw->gen >= 8) { + emit(MUL(result, op[0], op[1])); + break; + } else { + nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src); + nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src); + + if (value0 && value0->u[0] < (1 << 16)) { + if (brw->gen < 7) { + emit(MUL(result, op[0], op[1])); + } else { + emit(MUL(result, op[1], op[0])); + } + break; + } else if (value1 && value1->u[0] < (1 << 16)) { + if (brw->gen < 7) { + emit(MUL(result, op[1], op[0])); + } else { + emit(MUL(result, op[0], op[1])); + } + break; + } + } if (brw->gen >= 7) no16("SIMD16 explicit accumulator operands unsupported\n"); |