diff options
| author | Eric Anholt <[email protected]> | 2007-07-05 11:36:44 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2007-07-05 11:36:44 -0700 |
| commit | 3cf20ddbfc9d3a1dad4c058050595c54589257d3 (patch) | |
| tree | 57de53410bb0fb40979eed20d3c80d4c0ed68664 /src/mesa/drivers | |
| parent | 2ac17c68e2d64260168a54a275e839775828f534 (diff) | |
| parent | 4fe48b4e8568896cdbc822323aeec0a41c72ff2a (diff) | |
Merge branch 'i915-unification' of git+ssh://people.freedesktop.org/~anholt/mesa into i915-unification
Diffstat (limited to 'src/mesa/drivers')
39 files changed, 1323 insertions, 576 deletions
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c index c6202d969cc..e08b5b3c7fb 100644 --- a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c +++ b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c @@ -41,7 +41,11 @@ #include "mm.h" #include "imports.h" +#if 0 +#define DBG(...) _mesa_printf(__VA_ARGS__) +#else #define DBG(...) +#endif /* Internal flags: */ @@ -570,6 +574,9 @@ dri_fake_bo_alloc(dri_bufmgr *bufmgr, const char *name, bo_fake->flags = 0; bo_fake->is_static = GL_FALSE; + DBG("drm_bo_alloc: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); + return &bo_fake->bo; } @@ -592,10 +599,14 @@ dri_fake_bo_alloc_static(dri_bufmgr *bufmgr, const char *name, bo_fake->bo.virtual = virtual; bo_fake->bo.bufmgr = bufmgr; bo_fake->refcount = 1; + bo_fake->id = ++bufmgr_fake->buf_nr; bo_fake->name = name; bo_fake->flags = DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE; bo_fake->is_static = GL_TRUE; + DBG("drm_bo_alloc_static: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); + return &bo_fake->bo; } @@ -648,7 +659,8 @@ dri_fake_bo_map(dri_bo *bo, GLboolean write_enable) _glthread_LOCK_MUTEX(bufmgr_fake->mutex); { - DBG("bmMapBuffer %d\n", bo_fake->id); + DBG("drm_bo_map: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); if (bo->virtual != NULL) { _mesa_printf("%s: already mapped\n", __FUNCTION__); @@ -698,6 +710,9 @@ dri_fake_bo_unmap(dri_bo *bo) if (bo == NULL) return 0; + DBG("drm_bo_unmap: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); + bo->virtual = NULL; return 0; @@ -713,22 +728,32 @@ dri_fake_bo_validate(dri_bo *bo, unsigned int flags) * different flags. See drmAddValidateItem(). */ + DBG("drm_bo_validate: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr; _glthread_LOCK_MUTEX(bufmgr_fake->mutex); { + if (bo_fake->is_static) { + /* Add it to the needs-fence list */ + bufmgr_fake->need_fence = 1; + _glthread_UNLOCK_MUTEX(bufmgr_fake->mutex); + return 0; + } + /* Allocate the card memory */ if (!bo_fake->block && !evict_and_alloc_block(bo)) { bufmgr_fake->fail = 1; _glthread_UNLOCK_MUTEX(bufmgr_fake->mutex); + DBG("Failed to validate buf %d:%s\n", bo_fake->id, bo_fake->name); return -1; } assert(bo_fake->block); assert(bo_fake->block->bo == &bo_fake->bo); - DBG("Add buf %d (block %p, dirty %d) to referenced list\n", - bo_fake->id, bo_fake->block, bo_fake->dirty); + DBG("Add buf %d:%s (block %p, dirty %d) to referenced list\n", + bo_fake->id, bo_fake->name, bo_fake->block, bo_fake->dirty); move_to_tail(&bufmgr_fake->referenced, bo_fake->block); bo_fake->block->referenced = 1; @@ -737,8 +762,8 @@ dri_fake_bo_validate(dri_bo *bo, unsigned int flags) /* Upload the buffer contents if necessary */ if (bo_fake->dirty) { - DBG("Upload dirty buf %d (%s) sz %d offset 0x%x\n", bo_fake->id, - bo_fake->name, bo->size, block->mem->ofs); + DBG("Upload dirty buf %d:%s, sz %d offset 0x%x\n", bo_fake->id, + bo_fake->name, bo->size, bo_fake->block->mem->ofs); assert(!(bo_fake->flags & (BM_NO_BACKING_STORE|DRM_BO_FLAG_NO_EVICT))); @@ -786,6 +811,8 @@ dri_fake_fence_validated(dri_bufmgr *bufmgr, const char *name, fence_blocks(bufmgr_fake, cookie); _glthread_UNLOCK_MUTEX(bufmgr_fake->mutex); + DBG("drm_fence_validated: 0x%08x cookie\n", fence_fake->fence_cookie); + return &fence_fake->fence; } @@ -824,6 +851,8 @@ dri_fake_fence_wait(dri_fence *fence) dri_fence_fake *fence_fake = (dri_fence_fake *)fence; dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)fence->bufmgr; + DBG("drm_fence_wait: 0x%08x cookie\n", fence_fake->fence_cookie); + _glthread_LOCK_MUTEX(bufmgr_fake->mutex); _fence_wait_internal(bufmgr_fake, fence_fake->fence_cookie); _glthread_UNLOCK_MUTEX(bufmgr_fake->mutex); diff --git a/src/mesa/drivers/dri/common/dri_bufmgr_ttm.c b/src/mesa/drivers/dri/common/dri_bufmgr_ttm.c index 64248a1d871..fd432ba3f72 100644 --- a/src/mesa/drivers/dri/common/dri_bufmgr_ttm.c +++ b/src/mesa/drivers/dri/common/dri_bufmgr_ttm.c @@ -150,7 +150,7 @@ dri_ttm_alloc_static(dri_bufmgr *bufmgr, const char *name, * pass all of the allocation class flags. */ flags = location_mask | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | - DRM_BO_FLAG_EXE | DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE; + DRM_BO_FLAG_EXE | DRM_BO_FLAG_NO_MOVE; /* No hints we want to use. */ hint = 0; @@ -362,6 +362,7 @@ dri_bufmgr_ttm_init(int fd, unsigned int fence_type, unsigned int fence_type_flush) { dri_bufmgr_ttm *bufmgr_ttm; + dri_bo *test_alloc; bufmgr_ttm = malloc(sizeof(*bufmgr_ttm)); bufmgr_ttm->fd = fd; @@ -381,5 +382,17 @@ dri_bufmgr_ttm_init(int fd, unsigned int fence_type, bufmgr_ttm->bufmgr.fence_unreference = dri_ttm_fence_unreference; bufmgr_ttm->bufmgr.fence_wait = dri_ttm_fence_wait; + /* Attempt an allocation to make sure that the DRM was actually set up for + * TTM. + */ + test_alloc = dri_bo_alloc((dri_bufmgr *)bufmgr_ttm, "test allocation", + 4096, 4096, DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_MEM_TT); + if (test_alloc == NULL) { + _glthread_DESTROY_MUTEX(bufmgr_ttm->mutex); + free(bufmgr_ttm); + return NULL; + } + dri_bo_unreference(test_alloc); + return &bufmgr_ttm->bufmgr; } diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 9f0c9491b22..a19d4b65840 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -491,12 +491,19 @@ static void i915SetTexImages( i915ContextPtr i915, abort(); } - - if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G || - i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM) - i945LayoutTextureImages( i915, tObj ); - else - i915LayoutTextureImages( i915, tObj ); + switch (i915->intel.intelScreen->deviceID) { + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q33_G: + case PCI_CHIP_Q35_G: + i945LayoutTextureImages( i915, tObj ); + break; + default: + i915LayoutTextureImages( i915, tObj ); + break; + } t->Setup[I915_TEXREG_MS3] = (((tObj->Image[0][t->intel.base.firstLevel]->Height - 1) << MS3_HEIGHT_SHIFT) | diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c index e747fc6991b..11c23f24a1b 100644 --- a/src/mesa/drivers/dri/i915/intel_context.c +++ b/src/mesa/drivers/dri/i915/intel_context.c @@ -123,6 +123,14 @@ const GLubyte *intelGetString( GLcontext *ctx, GLenum name ) chipset = "Intel(R) 945G"; break; case PCI_CHIP_I945_GM: chipset = "Intel(R) 945GM"; break; + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; break; + case PCI_CHIP_G33_G: + chipset = "Intel(R) G33"; break; + case PCI_CHIP_Q35_G: + chipset = "Intel(R) Q35"; break; + case PCI_CHIP_Q33_G: + chipset = "Intel(R) Q33"; break; default: chipset = "Unknown Intel Chipset"; break; } diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index c48b074cc51..3b50107d73f 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -454,6 +454,10 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I915_GM 0x2592 #define PCI_CHIP_I945_G 0x2772 #define PCI_CHIP_I945_GM 0x27A2 +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q33_G 0x29D2 /* ================================================================ diff --git a/src/mesa/drivers/dri/i915/intel_pixel.c b/src/mesa/drivers/dri/i915/intel_pixel.c index 535cbfcb26e..d175870a0c5 100644 --- a/src/mesa/drivers/dri/i915/intel_pixel.c +++ b/src/mesa/drivers/dri/i915/intel_pixel.c @@ -439,10 +439,26 @@ intelDrawPixels( GLcontext *ctx, if (INTEL_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); - if (!intelTryDrawPixels( ctx, x, y, width, height, format, type, - unpack, pixels )) + if (intelTryDrawPixels( ctx, x, y, width, height, format, type, + unpack, pixels )) + return; + + if (ctx->FragmentProgram._Current == ctx->FragmentProgram._TexEnvProgram) { + /* + * We don't want the i915 texenv program to be applied to DrawPixels. + * This is really just a performance optimization (mesa will other- + * wise happily run the fragment program on each pixel in the image). + */ + struct gl_fragment_program *fpSave = ctx->FragmentProgram._Current; + ctx->FragmentProgram._Current = NULL; + _swrast_DrawPixels( ctx, x, y, width, height, format, type, + unpack, pixels ); + ctx->FragmentProgram._Current = fpSave; + } + else { _swrast_DrawPixels( ctx, x, y, width, height, format, type, - unpack, pixels ); + unpack, pixels ); + } } diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c index 67e176a1c6f..ca8610b4965 100644 --- a/src/mesa/drivers/dri/i915/intel_screen.c +++ b/src/mesa/drivers/dri/i915/intel_screen.c @@ -514,6 +514,10 @@ static GLboolean intelCreateContext( const __GLcontextModes *mesaVis, case PCI_CHIP_I915_GM: case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: return i915CreateContext( mesaVis, driContextPriv, sharedContextPrivate ); diff --git a/src/mesa/drivers/dri/i915/intel_tex.c b/src/mesa/drivers/dri/i915/intel_tex.c index 98ddc796724..5bd280652af 100644 --- a/src/mesa/drivers/dri/i915/intel_tex.c +++ b/src/mesa/drivers/dri/i915/intel_tex.c @@ -677,7 +677,11 @@ static void intelUploadTexImage( intelContextPtr intel, /* Time for another vtbl entry: */ else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G || - intel->intelScreen->deviceID == PCI_CHIP_I945_GM) { + intel->intelScreen->deviceID == PCI_CHIP_I945_GM || + intel->intelScreen->deviceID == PCI_CHIP_I945_GME || + intel->intelScreen->deviceID == PCI_CHIP_G33_G || + intel->intelScreen->deviceID == PCI_CHIP_Q33_G || + intel->intelScreen->deviceID == PCI_CHIP_Q35_G) { GLuint row_len = image->Width * image->TexFormat->TexelBytes; GLubyte *dst = (GLubyte *)(t->BufAddr + offset); GLubyte *src = (GLubyte *)image->Data; diff --git a/src/mesa/drivers/dri/i915tex/Makefile b/src/mesa/drivers/dri/i915tex/Makefile index c6a29149c77..eb704e1538b 100644 --- a/src/mesa/drivers/dri/i915tex/Makefile +++ b/src/mesa/drivers/dri/i915tex/Makefile @@ -33,6 +33,7 @@ DRIVER_SOURCES = \ intel_pixel_draw.c \ intel_buffers.c \ intel_blit.c \ + i915_disasm.c \ i915_tex.c \ i915_texstate.c \ i915_context.c \ diff --git a/src/mesa/drivers/dri/i915tex/i830_vtbl.c b/src/mesa/drivers/dri/i915tex/i830_vtbl.c index 441dc660acb..dc91af71815 100644 --- a/src/mesa/drivers/dri/i915tex/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915tex/i830_vtbl.c @@ -487,11 +487,13 @@ i830_emit_state(struct intel_context *intel) DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, state->tex_offset[i] | TM0S0_USE_FENCE); } - else { - assert(i == 0); - assert(state == &i830->meta); - OUT_BATCH(0); - } + else if (state == &i830->meta) { + assert(i == 0); + OUT_BATCH(0); + } + else { + OUT_BATCH(state->tex_offset[i]); + } OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]); diff --git a/src/mesa/drivers/dri/i915tex/i915_disasm.c b/src/mesa/drivers/dri/i915tex/i915_disasm.c new file mode 100644 index 00000000000..6ac34a14804 --- /dev/null +++ b/src/mesa/drivers/dri/i915tex/i915_disasm.c @@ -0,0 +1,740 @@ +/* -*- c-basic-offset: 4 -*- */ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt <[email protected]> + * + */ + +#include <stdio.h> +#include <stdarg.h> +#include <inttypes.h> + +#include "i915_disasm.h" +#include "i915_reg.h" + +#define BUFFER_FAIL(_count, _len, _name) do { \ + fprintf(out, "Buffer size too small in %s (%d < %d)\n", \ + (_name), (_count), (_len)); \ + (*failures)++; \ + return count; \ +} while (0) + +static FILE *out; +static uint32_t saved_s2 = 0, saved_s4 = 0; +static char saved_s2_set = 0, saved_s4_set = 0; + +static float +int_as_float(uint32_t intval) +{ + union intfloat { + uint32_t i; + float f; + } uval; + + uval.i = intval; + return uval.f; +} + +static void +instr_out(uint32_t *data, uint32_t hw_offset, unsigned int index, + char *fmt, ...) +{ + va_list va; + + fprintf(out, "0x%08x: 0x%08x: ", hw_offset + index * 4, data[index]); + va_start(va, fmt); + vfprintf(out, fmt, va); + va_end(va); +} + + +static int +decode_mi(uint32_t *data, int count, uint32_t hw_offset, int *failures) +{ + unsigned int opcode; + + struct { + uint32_t opcode; + int min_len; + int max_len; + char *name; + } opcodes_mi[] = { + { 0x08, 1, 1, "MI_ARB_ON_OFF" }, + { 0x0a, 1, 1, "MI_BATCH_BUFFER_END" }, + { 0x31, 2, 2, "MI_BATCH_BUFFER_START" }, + { 0x14, 3, 3, "MI_DISPLAY_BUFFER_INFO" }, + { 0x04, 1, 1, "MI_FLUSH" }, + { 0x22, 3, 3, "MI_LOAD_REGISTER_IMM" }, + { 0x13, 2, 2, "MI_LOAD_SCAN_LINES_EXCL" }, + { 0x12, 2, 2, "MI_LOAD_SCAN_LINES_INCL" }, + { 0x00, 1, 1, "MI_NOOP" }, + { 0x11, 2, 2, "MI_OVERLAY_FLIP" }, + { 0x07, 1, 1, "MI_REPORT_HEAD" }, + { 0x18, 2, 2, "MI_SET_CONTEXT" }, + { 0x20, 3, 4, "MI_STORE_DATA_IMM" }, + { 0x21, 3, 4, "MI_STORE_DATA_INDEX" }, + { 0x24, 3, 3, "MI_STORE_REGISTER_MEM" }, + { 0x02, 1, 1, "MI_USER_INTERRUPT" }, + { 0x03, 1, 1, "MI_WAIT_FOR_EVENT" }, + }; + + + for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); + opcode++) { + if ((data[0] & 0x1e000000) >> 23 == opcodes_mi[opcode].opcode) { + unsigned int len = 1, i; + + instr_out(data, hw_offset, 0, "%s\n", opcodes_mi[opcode].name); + if (opcodes_mi[opcode].max_len > 1) { + len = (data[0] & 0x000000ff) + 2; + if (len < opcodes_mi[opcode].min_len || + len > opcodes_mi[opcode].max_len) + { + fprintf(out, "Bad length in %s\n", + opcodes_mi[opcode].name); + } + } + + for (i = 1; i < len; i++) { + if (i >= count) + BUFFER_FAIL(count, len, opcodes_mi[opcode].name); + instr_out(data, hw_offset, i, "dword %d\n", i); + } + + return len; + } + } + + instr_out(data, hw_offset, 0, "MI UNKNOWN\n"); + (*failures)++; + return 1; +} + +static int +decode_2d(uint32_t *data, int count, uint32_t hw_offset, int *failures) +{ + unsigned int opcode; + + struct { + uint32_t opcode; + int min_len; + int max_len; + char *name; + } opcodes_2d[] = { + { 0x40, 5, 5, "COLOR_BLT" }, + { 0x43, 6, 6, "SRC_COPY_BLT" }, + { 0x01, 8, 8, "XY_SETUP_BLT" }, + { 0x11, 9, 9, "XY_SETUP_MONO_PATTERN_SL_BLT" }, + { 0x03, 3, 3, "XY_SETUP_CLIP_BLT" }, + { 0x24, 2, 2, "XY_PIXEL_BLT" }, + { 0x25, 3, 3, "XY_SCANLINES_BLT" }, + { 0x26, 4, 4, "Y_TEXT_BLT" }, + { 0x31, 5, 134, "XY_TEXT_IMMEDIATE_BLT" }, + { 0x50, 6, 6, "XY_COLOR_BLT" }, + { 0x51, 6, 6, "XY_PAT_BLT" }, + { 0x76, 8, 8, "XY_PAT_CHROMA_BLT" }, + { 0x72, 7, 135, "XY_PAT_BLT_IMMEDIATE" }, + { 0x77, 9, 137, "XY_PAT_CHROMA_BLT_IMMEDIATE" }, + { 0x52, 9, 9, "XY_MONO_PAT_BLT" }, + { 0x59, 7, 7, "XY_MONO_PAT_FIXED_BLT" }, + { 0x53, 8, 8, "XY_SRC_COPY_BLT" }, + { 0x54, 8, 8, "XY_MONO_SRC_COPY_BLT" }, + { 0x71, 9, 137, "XY_MONO_SRC_COPY_IMMEDIATE_BLT" }, + { 0x55, 9, 9, "XY_FULL_BLT" }, + { 0x55, 9, 137, "XY_FULL_IMMEDIATE_PATTERN_BLT" }, + { 0x56, 9, 9, "XY_FULL_MONO_SRC_BLT" }, + { 0x75, 10, 138, "XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT" }, + { 0x57, 12, 12, "XY_FULL_MONO_PATTERN_BLT" }, + { 0x58, 12, 12, "XY_FULL_MONO_PATTERN_MONO_SRC_BLT" }, + }; + + for (opcode = 0; opcode < sizeof(opcodes_2d) / sizeof(opcodes_2d[0]); + opcode++) { + if ((data[0] & 0x1fc00000) >> 22 == opcodes_2d[opcode].opcode) { + unsigned int len = 1, i; + + instr_out(data, hw_offset, 0, "%s\n", opcodes_2d[opcode].name); + if (opcodes_2d[opcode].max_len > 1) { + len = (data[0] & 0x000000ff) + 2; + if (len < opcodes_2d[opcode].min_len || + len > opcodes_2d[opcode].max_len) + { + fprintf(out, "Bad count in %s\n", opcodes_2d[opcode].name); + } + } + + for (i = 1; i < len; i++) { + if (i >= count) + BUFFER_FAIL(count, len, opcodes_2d[opcode].name); + instr_out(data, hw_offset, i, "dword %d\n", i); + } + + return len; + } + } + + instr_out(data, hw_offset, 0, "2D UNKNOWN\n"); + (*failures)++; + return 1; +} + +static int +decode_3d_1c(uint32_t *data, int count, uint32_t hw_offset, int *failures) +{ + switch ((data[0] & 0x00f80000) >> 19) { + case 0x11: + instr_out(data, hw_offset, 0, "3DSTATE_DEPTH_SUBRECTANGLE_DISALBE\n"); + return 1; + case 0x10: + instr_out(data, hw_offset, 0, "3DSTATE_SCISSOR_ENABLE\n"); + return 1; + } + + instr_out(data, hw_offset, 0, "3D UNKNOWN\n"); + (*failures)++; + return 1; +} + +static int +decode_3d_1d(uint32_t *data, int count, uint32_t hw_offset, int *failures) +{ + unsigned int len, i, c, opcode, word, map, sampler, instr; + + struct { + uint32_t opcode; + int min_len; + int max_len; + char *name; + } opcodes_3d_1d[] = { + { 0x8e, 3, 3, "3DSTATE_BUFFER_INFO" }, + { 0x86, 4, 4, "3DSTATE_CHROMA_KEY" }, + { 0x9c, 1, 1, "3DSTATE_CLEAR_PARAMETERS" }, + { 0x88, 2, 2, "3DSTATE_CONSTANT_BLEND_COLOR" }, + { 0x99, 2, 2, "3DSTATE_DEFAULT_DIFFUSE" }, + { 0x9a, 2, 2, "3DSTATE_DEFAULT_SPECULAR" }, + { 0x98, 2, 2, "3DSTATE_DEFAULT_Z" }, + { 0x97, 2, 2, "3DSTATE_DEPTH_OFFSET_SCALE" }, + { 0x85, 2, 2, "3DSTATE_DEST_BUFFER_VARIABLES" }, + { 0x80, 5, 5, "3DSTATE_DRAWING_RECTANGLE" }, + { 0x8e, 3, 3, "3DSTATE_BUFFER_INFO" }, + { 0x9d, 65, 65, "3DSTATE_FILTER_COEFFICIENTS_4X4" }, + { 0x9e, 4, 4, "3DSTATE_MONO_FILTER" }, + { 0x89, 4, 4, "3DSTATE_FOG_MODE" }, + { 0x8f, 2, 16, "3DSTATE_MAP_PALLETE_LOAD_32" }, + { 0x81, 3, 3, "3DSTATE_SCISSOR_RECTANGLE" }, + { 0x83, 2, 2, "3DSTATE_SPAN_STIPPLE" }, + }; + + switch ((data[0] & 0x00ff0000) >> 16) { + case 0x07: + /* This instruction is unusual. A 0 length means just 1 DWORD instead of + * 2. The 0 length is specified in one place to be unsupported, but + * stated to be required in another, and 0 length LOAD_INDIRECTs appear + * to cause no harm at least. + */ + instr_out(data, hw_offset, 0, "3DSTATE_LOAD_INDIRECT\n"); + len = (data[0] & 0x000000ff) + 1; + i = 1; + if (data[0] & (0x01 << 8)) { + if (i + 2 >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); + instr_out(data, hw_offset, i++, "SIS.0\n"); + instr_out(data, hw_offset, i++, "SIS.1\n"); + } + if (data[0] & (0x02 << 8)) { + if (i + 1 >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); + instr_out(data, hw_offset, i++, "DIS.0\n"); + } + if (data[0] & (0x04 << 8)) { + if (i + 2 >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); + instr_out(data, hw_offset, i++, "SSB.0\n"); + instr_out(data, hw_offset, i++, "SSB.1\n"); + } + if (data[0] & (0x08 << 8)) { + if (i + 2 >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); + instr_out(data, hw_offset, i++, "MSB.0\n"); + instr_out(data, hw_offset, i++, "MSB.1\n"); + } + if (data[0] & (0x10 << 8)) { + if (i + 2 >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); + instr_out(data, hw_offset, i++, "PSP.0\n"); + instr_out(data, hw_offset, i++, "PSP.1\n"); + } + if (data[0] & (0x20 << 8)) { + if (i + 2 >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_INDIRECT"); + instr_out(data, hw_offset, i++, "PSC.0\n"); + instr_out(data, hw_offset, i++, "PSC.1\n"); + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_LOAD_INDIRECT\n"); + (*failures)++; + return len; + } + return len; + case 0x04: + instr_out(data, hw_offset, 0, "3DSTATE_LOAD_STATE_IMMEDIATE_1\n"); + len = (data[0] & 0x0000000f) + 2; + i = 1; + for (word = 0; word <= 7; word++) { + if (data[0] & (1 << (4 + word))) { + if (i >= count) + BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_1"); + + /* save vertex state for decode */ + if (word == 2) { + saved_s2_set = 1; + saved_s2 = data[i]; + } + if (word == 4) { + saved_s4_set = 1; + saved_s4 = data[i]; + } + + instr_out(data, hw_offset, i++, "S%d\n", word); + } + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_LOAD_INDIRECT\n"); + (*failures)++; + } + return len; + case 0x00: + instr_out(data, hw_offset, 0, "3DSTATE_MAP_STATE\n"); + len = (data[0] & 0x0000003f) + 2; + + i = 1; + for (map = 0; map <= 15; map++) { + if (data[1] & (1 << map)) { + if (i + 3 >= count) + BUFFER_FAIL(count, len, "3DSTATE_MAP_STATE"); + instr_out(data, hw_offset, i++, "map %d MS2\n", map); + instr_out(data, hw_offset, i++, "map %d MS3\n", map); + instr_out(data, hw_offset, i++, "map %d MS4\n", map); + } + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_MAP_STATE\n"); + (*failures)++; + return len; + } + return len; + case 0x06: + instr_out(data, hw_offset, 0, "3DSTATE_PIXEL_SHADER_CONSTANTS\n"); + len = (data[0] & 0x000000ff) + 2; + + i = 1; + for (c = 0; c <= 31; c++) { + if (data[1] & (1 << c)) { + if (i + 4 >= count) + BUFFER_FAIL(count, len, "3DSTATE_PIXEL_SHADER_CONSTANTS"); + instr_out(data, hw_offset, i, "C%d.X = %f\n", + c, int_as_float(data[i])); + i++; + instr_out(data, hw_offset, i, "C%d.Y = %f\n", + c, int_as_float(data[i])); + i++; + instr_out(data, hw_offset, i, "C%d.Z = %f\n", + c, int_as_float(data[i])); + i++; + instr_out(data, hw_offset, i, "C%d.W = %f\n", + c, int_as_float(data[i])); + i++; + } + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_MAP_STATE\n"); + (*failures)++; + } + return len; + case 0x05: + instr_out(data, hw_offset, 0, "3DSTATE_PIXEL_SHADER_PROGRAM\n"); + len = (data[0] & 0x000000ff) + 2; + if ((len - 1) % 3 != 0 || len > 370) { + fprintf(out, "Bad count in 3DSTATE_PIXEL_SHADER_PROGRAM\n"); + (*failures)++; + } + i = 1; + for (instr = 0; instr < (len - 1) / 3; instr++) { + if (i + 3 >= count) + BUFFER_FAIL(count, len, "3DSTATE_MAP_STATE"); + instr_out(data, hw_offset, i++, "PS%03x\n", instr); + instr_out(data, hw_offset, i++, "PS%03x\n", instr); + instr_out(data, hw_offset, i++, "PS%03x\n", instr); + } + return len; + case 0x01: + instr_out(data, hw_offset, 0, "3DSTATE_SAMPLER_STATE\n"); + len = (data[0] & 0x0000003f) + 2; + i = 1; + for (sampler = 0; sampler <= 15; sampler++) { + if (data[1] & (1 << sampler)) { + if (i + 3 >= count) + BUFFER_FAIL(count, len, "3DSTATE_SAMPLER_STATE"); + instr_out(data, hw_offset, i++, "sampler %d SS2\n", + sampler); + instr_out(data, hw_offset, i++, "sampler %d SS3\n", + sampler); + instr_out(data, hw_offset, i++, "sampler %d SS4\n", + sampler); + } + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_SAMPLER_STATE\n"); + (*failures)++; + } + return len; + } + + for (opcode = 0; opcode < sizeof(opcodes_3d_1d) / sizeof(opcodes_3d_1d[0]); + opcode++) + { + if (((data[0] & 0x00ff0000) >> 16) == opcodes_3d_1d[opcode].opcode) { + len = 1; + + instr_out(data, hw_offset, 0, "%s\n", opcodes_3d_1d[opcode].name); + if (opcodes_3d_1d[opcode].max_len > 1) { + len = (data[0] & 0x0000ffff) + 2; + if (len < opcodes_3d_1d[opcode].min_len || + len > opcodes_3d_1d[opcode].max_len) + { + fprintf(out, "Bad count in %s\n", + opcodes_3d_1d[opcode].name); + (*failures)++; + } + } + + for (i = 1; i < len; i++) { + if (i >= count) + BUFFER_FAIL(count, len, opcodes_3d_1d[opcode].name); + instr_out(data, hw_offset, i, "dword %d\n", i); + } + + return len; + } + } + + instr_out(data, hw_offset, 0, "3D UNKNOWN\n"); + (*failures)++; + return 1; +} + +static int +decode_3d_primitive(uint32_t *data, int count, uint32_t hw_offset, + int *failures) +{ + char immediate = (data[0] & (1 << 23)) == 0; + unsigned int len, i; + char *primtype; + + switch ((data[0] >> 18) & 0xf) { + case 0x0: primtype = "TRILIST"; break; + case 0x1: primtype = "TRISTRIP"; break; + case 0x2: primtype = "TRISTRIP_REVERSE"; break; + case 0x3: primtype = "TRIFAN"; break; + case 0x4: primtype = "POLYGON"; break; + case 0x5: primtype = "LINELIST"; break; + case 0x6: primtype = "LINESTRIP"; break; + case 0x7: primtype = "RECTLIST"; break; + case 0x8: primtype = "POINTLIST"; break; + case 0x9: primtype = "DIB"; break; + case 0xa: primtype = "CLEAR_RECT"; break; + default: primtype = "unknown"; break; + } + + /* XXX: 3DPRIM_DIB not supported */ + if (immediate) { + len = (data[0] & 0x0003ffff) + 2; + instr_out(data, hw_offset, 0, "3DPRIMITIVE inline %s\n", primtype); + if (count < len) + BUFFER_FAIL(count, len, "3DPRIMITIVE inline"); + if (!saved_s2_set || !saved_s4_set) { + fprintf(out, "unknown vertex format\n"); + for (i = 1; i < len; i++) { + instr_out(data, hw_offset, i, + " vertex data (%f float)\n", + int_as_float(data[i])); + } + } else { + unsigned int vertex = 0; + for (i = 1; i < len;) { + unsigned int tc; + +#define VERTEX_OUT(fmt, ...) do { \ + if (i < len) \ + instr_out(data, hw_offset, i, " V%d."fmt"\n", vertex, __VA_ARGS__); \ + else \ + fprintf(out, " missing data in V%d\n", vertex); \ + i++; \ +} while (0) + + VERTEX_OUT("X = %f", int_as_float(data[i])); + VERTEX_OUT("Y = %f", int_as_float(data[i])); + switch (saved_s4 >> 6 & 0x7) { + case 0x1: + VERTEX_OUT("Z = %f", int_as_float(data[i])); + break; + case 0x2: + VERTEX_OUT("Z = %f", int_as_float(data[i])); + VERTEX_OUT("W = %f", int_as_float(data[i])); + break; + case 0x3: + break; + case 0x4: + VERTEX_OUT("W = %f", int_as_float(data[i])); + break; + default: + fprintf(out, "bad S4 position mask\n"); + } + + if (saved_s4 & (1 << 10)) { + VERTEX_OUT("color = (A=0x%02x, R=0x%02x, G=0x%02x, " + "B=0x%02x)", + data[i] >> 24, + (data[i] >> 16) & 0xff, + (data[i] >> 8) & 0xff, + data[i] & 0xff); + } + if (saved_s4 & (1 << 11)) { + VERTEX_OUT("spec = (A=0x%02x, R=0x%02x, G=0x%02x, " + "B=0x%02x)", + data[i] >> 24, + (data[i] >> 16) & 0xff, + (data[i] >> 8) & 0xff, + data[i] & 0xff); + } + if (saved_s4 & (1 << 12)) + VERTEX_OUT("width = 0x%08x)", data[i]); + + for (tc = 0; tc <= 7; tc++) { + switch ((saved_s2 >> (tc * 4)) & 0xf) { + case 0x0: + VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); + VERTEX_OUT("T%d.Y = %f", tc, int_as_float(data[i])); + break; + case 0x1: + VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); + VERTEX_OUT("T%d.Y = %f", tc, int_as_float(data[i])); + VERTEX_OUT("T%d.Z = %f", tc, int_as_float(data[i])); + break; + case 0x2: + VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); + VERTEX_OUT("T%d.Y = %f", tc, int_as_float(data[i])); + VERTEX_OUT("T%d.Z = %f", tc, int_as_float(data[i])); + VERTEX_OUT("T%d.W = %f", tc, int_as_float(data[i])); + break; + case 0x3: + VERTEX_OUT("T%d.X = %f", tc, int_as_float(data[i])); + break; + case 0x4: + VERTEX_OUT("T%d.XY = 0x%08x half-float", tc, data[i]); + break; + case 0x5: + VERTEX_OUT("T%d.XY = 0x%08x half-float", tc, data[i]); + VERTEX_OUT("T%d.ZW = 0x%08x half-float", tc, data[i]); + break; + case 0xf: + break; + default: + fprintf(out, "bad S2.T%d format\n", tc); + } + } + vertex++; + } + } + } else { + /* indirect vertices */ + len = data[0] & 0x0000ffff; /* index count */ + if (data[0] & (1 << 17)) { + /* random vertex access */ + if (count < (len + 1) / 2 + 1) { + BUFFER_FAIL(count, (len + 1) / 2 + 1, + "3DPRIMITIVE random indirect"); + } + instr_out(data, hw_offset, 0, + "3DPRIMITIVE random indirect %s (%d)\n", primtype, len); + if (len == 0) { + /* vertex indices continue until 0xffff is found */ + for (i = 1; i < count; i++) { + if ((data[i] & 0xffff) == 0xffff) { + instr_out(data, hw_offset, i, + " indices: (terminator)\n"); + return i; + } else if ((data[i] >> 16) == 0xffff) { + instr_out(data, hw_offset, i, + " indices: 0x%04x, " + "(terminator)\n", + data[i] & 0xffff); + return i; + } else { + instr_out(data, hw_offset, i, + " indices: 0x%04x, 0x%04x\n", + data[i] & 0xffff, data[i] >> 16); + } + } + fprintf(out, + "3DPRIMITIVE: no terminator found in index buffer\n"); + (*failures)++; + return count; + } else { + /* fixed size vertex index buffer */ + for (i = 0; i < len; i += 2) { + if (i * 2 == len - 1) { + instr_out(data, hw_offset, i, + " indices: 0x%04x\n", + data[i] & 0xffff); + } else { + instr_out(data, hw_offset, i, + " indices: 0x%04x, 0x%04x\n", + data[i] & 0xffff, data[i] >> 16); + } + } + } + return (len + 1) / 2 + 1; + } else { + /* sequential vertex access */ + if (count < 2) + BUFFER_FAIL(count, 2, "3DPRIMITIVE seq indirect"); + instr_out(data, hw_offset, 0, + "3DPRIMITIVE sequential indirect %s, %d starting from " + "%d\n", primtype, len, data[1] & 0xffff); + instr_out(data, hw_offset, 1, " start\n"); + return 2; + } + } + + return len; +} + +static int +decode_3d(uint32_t *data, int count, uint32_t hw_offset, int *failures) +{ + unsigned int opcode; + + struct { + uint32_t opcode; + int min_len; + int max_len; + char *name; + } opcodes_3d[] = { + { 0x06, 1, 1, "3DSTATE_ANTI_ALIASING" }, + { 0x08, 1, 1, "3DSTATE_BACKFACE_STENCIL_OPS" }, + { 0x09, 1, 1, "3DSTATE_BACKFACE_STENCIL_MASKS" }, + { 0x16, 1, 1, "3DSTATE_COORD_SET_BINDINGS" }, + { 0x15, 1, 1, "3DSTATE_FOG_COLOR" }, + { 0x0b, 1, 1, "3DSTATE_INDEPENDENT_ALPHA_BLEND" }, + { 0x0d, 1, 1, "3DSTATE_MODES_4" }, + { 0x0c, 1, 1, "3DSTATE_MODES_5" }, + { 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES" }, + }; + + switch ((data[0] & 0x1f000000) >> 24) { + case 0x1f: + return decode_3d_primitive(data, count, hw_offset, failures); + case 0x1d: + return decode_3d_1d(data, count, hw_offset, failures); + case 0x1c: + return decode_3d_1c(data, count, hw_offset, failures); + } + + for (opcode = 0; opcode < sizeof(opcodes_3d) / sizeof(opcodes_3d[0]); + opcode++) { + if ((data[0] & 0x1f000000) >> 24 == opcodes_3d[opcode].opcode) { + unsigned int len = 1, i; + + instr_out(data, hw_offset, 0, "%s\n", opcodes_3d[opcode].name); + if (opcodes_3d[opcode].max_len > 1) { + len = (data[0] & 0xff) + 2; + if (len < opcodes_3d[opcode].min_len || + len > opcodes_3d[opcode].max_len) + { + fprintf(out, "Bad count in %s\n", opcodes_3d[opcode].name); + } + } + + for (i = 1; i < len; i++) { + if (i >= count) + BUFFER_FAIL(count, len, opcodes_3d[opcode].name); + instr_out(data, hw_offset, i, "dword %d\n", i); + } + return len; + } + } + + instr_out(data, hw_offset, 0, "3D UNKNOWN\n"); + (*failures)++; + return 1; +} + +/** + * Decodes an i830-i915 batch buffer, writing the output to stdout. + * + * \param data batch buffer contents + * \param count number of DWORDs to decode in the batch buffer + * \param hw_offset hardware address for the buffer + */ +int +i915_disasm(uint32_t *data, int count, uint32_t hw_offset) +{ + int index = 0; + int failures = 0; + + out = stdout; + + while (index < count) { + switch ((data[index] & 0xe0000000) >> 29) { + case 0x0: + index += decode_mi(data + index, count - index, + hw_offset + index * 4, &failures); + break; + case 0x2: + index += decode_2d(data + index, count - index, + hw_offset + index * 4, &failures); + break; + case 0x3: + index += decode_3d(data + index, count - index, + hw_offset + index * 4, &failures); + break; + default: + instr_out(data, hw_offset, index, "UNKNOWN\n"); + failures++; + index++; + break; + } + fflush(out); + } + + return failures; +} + +void i915_disasm_context_reset() +{ + saved_s2_set = 0; + saved_s4_set = 1; +} + diff --git a/src/mesa/drivers/dri/i915tex/i915_disasm.h b/src/mesa/drivers/dri/i915tex/i915_disasm.h new file mode 100644 index 00000000000..5eb620f9a4e --- /dev/null +++ b/src/mesa/drivers/dri/i915tex/i915_disasm.h @@ -0,0 +1,29 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt <[email protected]> + * + */ + +int i915_disasm(uint32_t *data, int count, uint32_t hw_offset); +void i915_disasm_context_reset(); diff --git a/src/mesa/drivers/dri/i915tex/i915_vtbl.c b/src/mesa/drivers/dri/i915tex/i915_vtbl.c index 2a3ccd01a05..5d6ad8d86cf 100644 --- a/src/mesa/drivers/dri/i915tex/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915tex/i915_vtbl.c @@ -197,7 +197,7 @@ i915_emit_invarient_state(struct intel_context *intel) /* Need to initialize this to zero. */ - OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (1)); + OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 0); OUT_BATCH(0); /* XXX: Use this */ diff --git a/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c b/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c index 26eecb94409..1edbb618d34 100644 --- a/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c @@ -66,27 +66,6 @@ * modifying cliprects ??? */ -static void -intel_dump_batchbuffer(GLuint offset, GLuint * ptr, GLuint size) -{ - int i; - fprintf(stderr, "\n\n\nSTART BATCH (%d dwords):\n", size / 4); - for (i = 0; i < size / 4; i += 4) { - char dw1[11], dw2[11] = "", dw3[11] = "", dw4[11] = ""; - - sprintf(dw1, "0x%08x", ptr[i]); - if (i + 1 < size / 4) - sprintf(dw2, "0x%08x", ptr[i + 1]); - if (i + 2 < size / 4) - sprintf(dw3, "0x%08x", ptr[i + 2]); - if (i + 3 < size / 4) - sprintf(dw4, "0x%08x", ptr[i + 3]); - fprintf(stderr, "0x%x:\t%s %s %s %s\n", offset + i * 4, - dw1, dw2, dw3, dw4); - } - fprintf(stderr, "END BATCH\n\n\n"); -} - /*====================================================================== * Public functions */ @@ -166,7 +145,7 @@ do_flush_locked(struct intel_batchbuffer *batch, } if (INTEL_DEBUG & DEBUG_BATCH) - intel_dump_batchbuffer(0, ptr, used); + i915_disasm(ptr, used / 4, 0); dri_bo_unmap(batch->buf); batch->map = NULL; diff --git a/src/mesa/drivers/dri/i915tex/intel_context.c b/src/mesa/drivers/dri/i915tex/intel_context.c index 696845a7fc9..cd4333d0d34 100644 --- a/src/mesa/drivers/dri/i915tex/intel_context.c +++ b/src/mesa/drivers/dri/i915tex/intel_context.c @@ -59,6 +59,7 @@ #include "intel_regions.h" #include "intel_buffer_objects.h" #include "intel_fbo.h" +#include "i915_disasm.h" #include "drirenderbuffer.h" #include "vblank.h" @@ -130,6 +131,18 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_I945_GM: chipset = "Intel(R) 945GM"; break; + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; + break; + case PCI_CHIP_G33_G: + chipset = "Intel(R) G33"; + break; + case PCI_CHIP_Q35_G: + chipset = "Intel(R) Q35"; + break; + case PCI_CHIP_Q33_G: + chipset = "Intel(R) Q33"; + break; default: chipset = "Unknown Intel Chipset"; break; @@ -646,6 +659,8 @@ intelContendedLock(struct intel_context *intel, GLuint flags) if (!intel->intelScreen->ttm && sarea->texAge != intel->hHWContext) { sarea->texAge = intel->hHWContext; dri_bufmgr_fake_contended_lock_take(intel->intelScreen->bufmgr); + if (INTEL_DEBUG & DEBUG_BATCH) + i915_disasm_context_reset(); } if (sarea->width != intelScreen->width || diff --git a/src/mesa/drivers/dri/i915tex/intel_context.h b/src/mesa/drivers/dri/i915tex/intel_context.h index a55f7d984e3..8755f5703dc 100644 --- a/src/mesa/drivers/dri/i915tex/intel_context.h +++ b/src/mesa/drivers/dri/i915tex/intel_context.h @@ -378,6 +378,10 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I915_GM 0x2592 #define PCI_CHIP_I945_G 0x2772 #define PCI_CHIP_I945_GM 0x27A2 +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q33_G 0x29D2 /* ================================================================ diff --git a/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c index 8e83028b26c..843a78eb82b 100644 --- a/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c @@ -79,6 +79,10 @@ intel_miptree_create(struct intel_context *intel, switch (intel->intelScreen->deviceID) { case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q33_G: + case PCI_CHIP_Q35_G: ok = i945_miptree_layout(mt); break; case PCI_CHIP_I915_G: diff --git a/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c b/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c index cbb583d3a20..6d9fc6144a2 100644 --- a/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c @@ -363,5 +363,20 @@ intelDrawPixels(GLcontext * ctx, if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s: fallback to swrast\n", __FUNCTION__); - _swrast_DrawPixels(ctx, x, y, width, height, format, type, unpack, pixels); + if (ctx->FragmentProgram._Current == ctx->FragmentProgram._TexEnvProgram) { + /* + * We don't want the i915 texenv program to be applied to DrawPixels. + * This is really just a performance optimization (mesa will other- + * wise happily run the fragment program on each pixel in the image). + */ + struct gl_fragment_program *fpSave = ctx->FragmentProgram._Current; + ctx->FragmentProgram._Current = NULL; + _swrast_DrawPixels( ctx, x, y, width, height, format, type, + unpack, pixels ); + ctx->FragmentProgram._Current = fpSave; + } + else { + _swrast_DrawPixels( ctx, x, y, width, height, format, type, + unpack, pixels ); + } } diff --git a/src/mesa/drivers/dri/i915tex/intel_screen.c b/src/mesa/drivers/dri/i915tex/intel_screen.c index e3a631b6961..89cf3ea9139 100644 --- a/src/mesa/drivers/dri/i915tex/intel_screen.c +++ b/src/mesa/drivers/dri/i915tex/intel_screen.c @@ -123,8 +123,6 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv) if (0) _mesa_printf("TEX 0x%08x ", intelScreen->tex.handle); if (intelScreen->tex.size != 0) { - intelScreen->ttm = GL_FALSE; - if (drmMap(sPriv->fd, intelScreen->tex.handle, intelScreen->tex.size, @@ -132,8 +130,6 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv) intelUnmapScreenRegions(intelScreen); return GL_FALSE; } - } else { - intelScreen->ttm = GL_TRUE; } if (0) @@ -530,12 +526,16 @@ intelInitDriver(__DRIscreenPrivate * sPriv) (*glx_enable_extension) (psc, "GLX_SGI_make_current_read"); } - if (intelScreen->ttm) { - intelScreen->bufmgr = dri_bufmgr_ttm_init(sPriv->fd, - DRM_FENCE_TYPE_EXE, - DRM_FENCE_TYPE_EXE | - DRM_I915_FENCE_TYPE_RW); - } else { + intelScreen->bufmgr = dri_bufmgr_ttm_init(sPriv->fd, + DRM_FENCE_TYPE_EXE, + DRM_FENCE_TYPE_EXE | + DRM_I915_FENCE_TYPE_RW); + if (intelScreen->bufmgr == NULL) { + if (intelScreen->tex.size == 0) { + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); + return GL_FALSE; + } intelScreen->bufmgr = dri_bufmgr_fake_init(intelScreen->tex.offset, intelScreen->tex.map, intelScreen->tex.size, @@ -740,6 +740,10 @@ intelCreateContext(const __GLcontextModes * mesaVis, case PCI_CHIP_I915_GM: case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate); default: diff --git a/src/mesa/drivers/dri/i915tex/intel_tex_image.c b/src/mesa/drivers/dri/i915tex/intel_tex_image.c index b15569681a5..197cf35ebe6 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tex_image.c +++ b/src/mesa/drivers/dri/i915tex/intel_tex_image.c @@ -377,9 +377,6 @@ intelTexImage(GLcontext * ctx, assert(!intelObj->mt); } - if (!pixels) - return; - if (!intelObj->mt) { guess_and_alloc_mipmap_tree(intel, intelObj, intelImage); if (!intelObj->mt) { @@ -681,6 +678,9 @@ intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, if (!intelObj) return; + if (intelObj->mt) + intel_miptree_release(intel, &intelObj->mt); + intelObj->imageOverride = GL_TRUE; intelObj->depthOverride = depth; intelObj->pitchOverride = pitch; diff --git a/src/mesa/drivers/dri/i915tex/intel_tex_validate.c b/src/mesa/drivers/dri/i915tex/intel_tex_validate.c index 0ae4fee1ba0..af18c26d55c 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i915tex/intel_tex_validate.c @@ -116,7 +116,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* We know/require this is true by now: */ - assert(intelObj->base.Complete); + assert(intelObj->base._Complete); /* What levels must the tree include at a minimum? */ diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 422eb960979..9617cbebbfd 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -106,20 +106,23 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name ) case GL_RENDERER: switch (intel_context(ctx)->intelScreen->deviceID) { case PCI_CHIP_I965_Q: - chipset = "Intel(R) 965Q"; break; + chipset = "Intel(R) 965Q"; break; case PCI_CHIP_I965_G: case PCI_CHIP_I965_G_1: - chipset = "Intel(R) 965G"; break; + chipset = "Intel(R) 965G"; break; case PCI_CHIP_I946_GZ: - chipset = "Intel(R) 946GZ"; break; + chipset = "Intel(R) 946GZ"; break; case PCI_CHIP_I965_GM: - chipset = "Intel(R) 965GM"; break; + chipset = "Intel(R) 965GM"; + break; + case PCI_CHIP_I965_GME: + chipset = "Intel(R) 965GME/GLE"; break; default: - chipset = "Unknown Intel Chipset"; break; + chipset = "Unknown Intel Chipset"; } (void) driGetRendererString( buffer, chipset, DRIVER_VERSION, 0 ); diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index a3c65b66e08..406f8483dce 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -385,6 +385,7 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I965_G_1 0x2982 #define PCI_CHIP_I946_GZ 0x2972 #define PCI_CHIP_I965_GM 0x2A02 +#define PCI_CHIP_I965_GME 0x2A12 /* ================================================================ diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index cb23b9dd879..44ee94614d5 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -138,7 +138,7 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel, /* We know/require this is true by now: */ - assert(intelObj->base.Complete); + assert(intelObj->base._Complete); /* What levels must the tree include at a minimum? */ diff --git a/src/mesa/drivers/dri/nouveau/nv10_swtcl.c b/src/mesa/drivers/dri/nouveau/nv10_swtcl.c index 3bc84d862d3..4576c1ede4d 100644 --- a/src/mesa/drivers/dri/nouveau/nv10_swtcl.c +++ b/src/mesa/drivers/dri/nouveau/nv10_swtcl.c @@ -392,15 +392,6 @@ static inline void nv10OutputVertexFormat(struct nouveau_context* nmesa) int i; int slots=0; int total_size=0; - /* t_vertex_generic dereferences a NULL pointer if we - * pass NULL as the vp transform... - */ - const GLfloat ident_vp[16] = { - 1.0, 0.0, 0.0, 0.0, - 0.0, 1.0, 0.0, 0.0, - 0.0, 0.0, 1.0, 0.0, - 0.0, 0.0, 0.0, 1.0 - }; nmesa->vertex_attr_count = 0; RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset); @@ -431,28 +422,20 @@ static inline void nv10OutputVertexFormat(struct nouveau_context* nmesa) if (RENDERINPUTS_TEST(index, i)) { slots=i+1; - if (i==_TNL_ATTRIB_POS) - { - /* special-case POS */ - EMIT_ATTR(_TNL_ATTRIB_POS,EMIT_3F_VIEWPORT); - } - else + switch(attr_size[i]) { - switch(attr_size[i]) - { - case 1: - EMIT_ATTR(i,EMIT_1F); - break; - case 2: - EMIT_ATTR(i,EMIT_2F); - break; - case 3: - EMIT_ATTR(i,EMIT_3F); - break; - case 4: - EMIT_ATTR(i,EMIT_4F); - break; - } + case 1: + EMIT_ATTR(i,EMIT_1F); + break; + case 2: + EMIT_ATTR(i,EMIT_2F); + break; + case 3: + EMIT_ATTR(i,EMIT_3F); + break; + case 4: + EMIT_ATTR(i,EMIT_4F); + break; } if (i==_TNL_ATTRIB_COLOR0) nmesa->color_offset=total_size; @@ -465,7 +448,7 @@ static inline void nv10OutputVertexFormat(struct nouveau_context* nmesa) nmesa->vertex_size=_tnl_install_attrs( ctx, nmesa->vertex_attrs, nmesa->vertex_attr_count, - ident_vp, 0 ); + NULL, 0 ); assert(nmesa->vertex_size==total_size*4); /* diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 0351989b2e4..7055286ba95 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -133,13 +133,15 @@ static void r300PrintStateAtom(r300ContextPtr r300, struct r300_state_atom *stat int i; int dwords = (*state->check) (r300, state); - fprintf(stderr, " emit %s/%d/%d\n", state->name, dwords, + fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); - if (RADEON_DEBUG & DEBUG_VERBOSE) - for (i = 0; i < dwords; i++) - fprintf(stderr, " %s[%d]: %08X\n", + if (RADEON_DEBUG & DEBUG_VERBOSE) { + for (i = 0; i < dwords; i++) { + fprintf(stderr, " %s[%d]: %08x\n", state->name, i, state->cmd[i]); + } + } } /** @@ -152,24 +154,10 @@ static inline void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) { struct r300_state_atom *atom; uint32_t *dest; + int dwords; dest = r300->cmdbuf.cmd_buf + r300->cmdbuf.count_used; - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - foreach(atom, &r300->hw.atomlist) { - if ((atom->dirty || r300->hw.all_dirty) == dirty) { - int dwords = (*atom->check) (r300, atom); - - if (dwords) - r300PrintStateAtom(r300, atom); - else - fprintf(stderr, - " skip state %s\n", - atom->name); - } - } - } - /* Emit WAIT */ *dest = cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN); dest++; @@ -193,13 +181,20 @@ static inline void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) foreach(atom, &r300->hw.atomlist) { if ((atom->dirty || r300->hw.all_dirty) == dirty) { - int dwords = (*atom->check) (r300, atom); - + dwords = (*atom->check) (r300, atom); if (dwords) { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + r300PrintStateAtom(r300, atom); + } memcpy(dest, atom->cmd, dwords * 4); dest += dwords; r300->cmdbuf.count_used += dwords; atom->dirty = GL_FALSE; + } else { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } } } } @@ -245,22 +240,28 @@ void r300EmitState(r300ContextPtr r300) r300->hw.all_dirty = GL_FALSE; } -#define CHECK( NM, COUNT ) \ -static int check_##NM( r300ContextPtr r300, \ - struct r300_state_atom* atom ) \ -{ \ - (void) atom; (void) r300; \ - return (COUNT); \ -} - #define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count) #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) -CHECK(always, atom->cmd_size) - CHECK(variable, packet0_count(atom->cmd) ? (1 + packet0_count(atom->cmd)) : 0) - CHECK(vpu, vpu_count(atom->cmd) ? (1 + vpu_count(atom->cmd) * 4) : 0) -#undef packet0_count -#undef vpu_count +static int check_always(r300ContextPtr r300, struct r300_state_atom *atom) +{ + return atom->cmd_size; +} + +static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom) +{ + int cnt; + cnt = packet0_count(atom->cmd); + return cnt ? cnt + 1 : 0; +} + +static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) +{ + int cnt; + cnt = vpu_count(atom->cmd); + return cnt ? (cnt * 4) + 1 : 0; +} + #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \ do { \ r300->hw.ATOM.cmd_size = (SZ); \ @@ -318,8 +319,8 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.unk21DC.cmd[0] = cmdpacket0(0x21DC, 1); ALLOC_STATE(unk221C, always, 2, 0); r300->hw.unk221C.cmd[0] = cmdpacket0(R300_VAP_UNKNOWN_221C, 1); - ALLOC_STATE(unk2220, always, 5, 0); - r300->hw.unk2220.cmd[0] = cmdpacket0(0x2220, 4); + ALLOC_STATE(vap_clip, always, 5, 0); + r300->hw.vap_clip.cmd[0] = cmdpacket0(R300_VAP_CLIP_X_0, 4); ALLOC_STATE(unk2288, always, 2, 0); r300->hw.unk2288.cmd[0] = cmdpacket0(R300_VAP_UNKNOWN_2288, 1); ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 01caa617667..076bb49a006 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -49,8 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define USER_BUFFERS -//#define OPTIMIZE_ELTS - struct r300_context; typedef struct r300_context r300ContextRec; typedef struct r300_context *r300ContextPtr; @@ -149,7 +147,6 @@ struct r300_dma_region { int aos_offset; /* address in GART memory */ int aos_stride; /* distance between elements, in dwords */ int aos_size; /* number of components (1-4) */ - int aos_reg; /* VAP register assignment */ }; struct r300_dma { @@ -455,7 +452,7 @@ struct r300_hw_state { struct r300_state_atom vic; /* vap input control (2180) */ struct r300_state_atom unk21DC; /* (21DC) */ struct r300_state_atom unk221C; /* (221C) */ - struct r300_state_atom unk2220; /* (2220) */ + struct r300_state_atom vap_clip; struct r300_state_atom unk2288; /* (2288) */ struct r300_state_atom pvs; /* pvs_cntl (22D0) */ struct r300_state_atom gb_enable; /* (4008) */ @@ -783,11 +780,6 @@ struct r300_fragment_program { #define R300_MAX_AOS_ARRAYS 16 -#define AOS_FORMAT_USHORT 0 -#define AOS_FORMAT_FLOAT 1 -#define AOS_FORMAT_UBYTE 2 -#define AOS_FORMAT_FLOAT_COLOR 3 - #define REG_COORDS 0 #define REG_COLOR0 1 #define REG_TEX0 2 diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 9fb712f7b8f..4670c28a02f 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -86,16 +86,15 @@ do { \ } while (0) #endif -static void r300EmitVec4(GLcontext * ctx, - struct r300_dma_region *rvb, +static void r300EmitVec4(GLcontext * ctx, struct r300_dma_region *rvb, GLvoid * data, int stride, int count) { int i; int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); if (stride == 4) COPY_DWORDS(out, data, count); @@ -107,16 +106,15 @@ static void r300EmitVec4(GLcontext * ctx, } } -static void r300EmitVec8(GLcontext * ctx, - struct r300_dma_region *rvb, +static void r300EmitVec8(GLcontext * ctx, struct r300_dma_region *rvb, GLvoid * data, int stride, int count) { int i; int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); if (stride == 8) COPY_DWORDS(out, data, count * 2); @@ -129,8 +127,7 @@ static void r300EmitVec8(GLcontext * ctx, } } -static void r300EmitVec12(GLcontext * ctx, - struct r300_dma_region *rvb, +static void r300EmitVec12(GLcontext * ctx, struct r300_dma_region *rvb, GLvoid * data, int stride, int count) { int i; @@ -152,16 +149,15 @@ static void r300EmitVec12(GLcontext * ctx, } } -static void r300EmitVec16(GLcontext * ctx, - struct r300_dma_region *rvb, +static void r300EmitVec16(GLcontext * ctx, struct r300_dma_region *rvb, GLvoid * data, int stride, int count) { int i; int *out = (int *)(rvb->address + rvb->start); if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d\n", - __FUNCTION__, count, stride); + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); if (stride == 16) COPY_DWORDS(out, data, count * 4); @@ -176,32 +172,22 @@ static void r300EmitVec16(GLcontext * ctx, } } -static void r300EmitVec(GLcontext * ctx, - struct r300_dma_region *rvb, +static void r300EmitVec(GLcontext * ctx, struct r300_dma_region *rvb, GLvoid * data, int size, int stride, int count) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d size %d stride %d\n", - __FUNCTION__, count, size, stride); - - /* Gets triggered when playing with future_hw_tcl_on ... */ - //assert(!rvb->buf); - if (stride == 0) { r300AllocDmaRegion(rmesa, rvb, size * 4, 4); count = 1; rvb->aos_offset = GET_START(rvb); rvb->aos_stride = 0; } else { - r300AllocDmaRegion(rmesa, rvb, size * count * 4, 4); /* alignment? */ + r300AllocDmaRegion(rmesa, rvb, size * count * 4, 4); rvb->aos_offset = GET_START(rvb); rvb->aos_stride = size; } - /* Emit the data - */ switch (size) { case 1: r300EmitVec4(ctx, rvb, data, stride, count); @@ -217,57 +203,35 @@ static void r300EmitVec(GLcontext * ctx, break; default: assert(0); - _mesa_exit(-1); break; } - -} - -#define R300_VIR0_AOS_SIZE_SHIFT 0 -#define R300_VIR0_AOS_INPUT_SHIFT 8 -#define R300_VIR0_AOS_STOP_SHIFT 13 -#define R300_VIR0_AOS_TYPE_SHIFT 14 -#define R300_VIR0_HIGH_SHIFT 16 - -// Pack 4 elemets in a 16 bit (aos_size first 8, input next 5, 1 stop bit(Whild gues), aos_type last 2); -static inline GLuint t_vir_pack(GLvector4f ** dt, int *inputs, int i) -{ - GLuint dw; - dw = (dt[i]->size - 1) << R300_VIR0_AOS_SIZE_SHIFT; - dw |= inputs[i] << R300_VIR0_AOS_INPUT_SHIFT; - //dw |= t_type(&dt[i]) << R300_VIR0_AOS_TYPE_SHIFT; - return dw; } -static GLuint t_vir0(uint32_t * dst, GLvector4f ** dt, int *inputs, - GLint * tab, GLuint nr) +static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, + int *inputs, GLint * tab, GLuint nr) { - GLuint i, dw, dwInternel; + GLuint i, dw; + /* type, inputs, stop bit, size */ for (i = 0; i + 1 < nr; i += 2) { - dw = t_vir_pack(dt, inputs, tab[i]); - dwInternel = t_vir_pack(dt, inputs, tab[i + 1]); - dw |= dwInternel << R300_VIR0_HIGH_SHIFT; - + dw = R300_INPUT_ROUTE_FLOAT | (inputs[tab[i]] << 8) | (attribptr[tab[i]]->size - 1); + dw |= (R300_INPUT_ROUTE_FLOAT | (inputs[tab[i + 1]] << 8) | (attribptr[tab[i + 1]]->size - 1)) << 16; if (i + 2 == nr) { - dw |= - (1 << - (R300_VIR0_AOS_STOP_SHIFT + R300_VIR0_HIGH_SHIFT)); + dw |= (1 << (13 + 16)); } - dst[i >> 1] = dw; // Is the same as i/2 + dst[i >> 1] = dw; } if (nr & 1) { - dw = t_vir_pack(dt, inputs, tab[nr - 1]); - dw |= 1 << R300_VIR0_AOS_STOP_SHIFT; - + dw = R300_INPUT_ROUTE_FLOAT | (inputs[tab[nr - 1]] << 8) | (attribptr[tab[nr - 1]]->size - 1); + dw |= 1 << 13; dst[nr >> 1] = dw; } - return (nr + 1) >> 1; // Is the same as (nr+1)/2 + return (nr + 1) >> 1; } -static GLuint t_swizzle(int swizzle[4]) +static GLuint r300VAPInputRoute1Swizzle(int swizzle[4]) { return (swizzle[0] << R300_INPUT_ROUTE_X_SHIFT) | (swizzle[1] << R300_INPUT_ROUTE_Y_SHIFT) | @@ -275,27 +239,32 @@ static GLuint t_swizzle(int swizzle[4]) (swizzle[3] << R300_INPUT_ROUTE_W_SHIFT); } -static GLuint t_vir1(uint32_t * dst, int swizzle[][4], GLuint nr) +static GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr) { GLuint i; for (i = 0; i + 1 < nr; i += 2) { - dst[i >> 1] = t_swizzle(swizzle[i]) | R300_INPUT_ROUTE_ENABLE; - dst[i >> 1] |= - (t_swizzle(swizzle[i + 1]) | R300_INPUT_ROUTE_ENABLE) - << 16; + dst[i >> 1] = r300VAPInputRoute1Swizzle(swizzle[i]) | R300_INPUT_ROUTE_ENABLE; + dst[i >> 1] |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) | R300_INPUT_ROUTE_ENABLE) << 16; } - if (nr & 1) - dst[nr >> 1] = - t_swizzle(swizzle[nr - 1]) | R300_INPUT_ROUTE_ENABLE; + if (nr & 1) { + dst[nr >> 1] = r300VAPInputRoute1Swizzle(swizzle[nr - 1]) | R300_INPUT_ROUTE_ENABLE; + } return (nr + 1) >> 1; } -static GLuint t_vic(GLcontext * ctx, GLuint InputsRead) +static GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead) +{ + /* No idea what this value means. I have seen other values written to + * this register... */ + return 0x5555; +} + +static GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r300ContextPtr rmesa = R300_CONTEXT(ctx); GLuint i, vic_1 = 0; if (InputsRead & (1 << VERT_ATTRIB_POS)) @@ -307,25 +276,65 @@ static GLuint t_vic(GLcontext * ctx, GLuint InputsRead) if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) vic_1 |= R300_INPUT_CNTL_COLOR; - r300->state.texture.tc_count = 0; + rmesa->state.texture.tc_count = 0; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) { - r300->state.texture.tc_count++; + rmesa->state.texture.tc_count++; vic_1 |= R300_INPUT_CNTL_TC0 << i; } return vic_1; } +static GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten) +{ + GLuint ret = 0; + + if (OutputsWritten & (1 << VERT_RESULT_HPOS)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; + + if (OutputsWritten & (1 << VERT_RESULT_COL0)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT; + + if (OutputsWritten & (1 << VERT_RESULT_COL1)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; + +#if 0 + if (OutputsWritten & (1 << VERT_RESULT_BFC0)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT; + + if (OutputsWritten & (1 << VERT_RESULT_BFC1)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; + + if (OutputsWritten & (1 << VERT_RESULT_FOGC)) ; +#endif + + if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) + ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; + + return ret; +} + +static GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) +{ + GLuint i, ret = 0; + + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { + if (OutputsWritten & (1 << (VERT_RESULT_TEX0 + i))) { + ret |= (4 << (3 * i)); + } + } + + return ret; +} + /* Emit vertex data to GART memory * Route inputs to the vertex processor * This function should never return R300_FALLBACK_TCL when using software tcl. */ - int r300EmitArrays(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - r300ContextPtr r300 = rmesa; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; GLuint nr; @@ -336,114 +345,105 @@ int r300EmitArrays(GLcontext * ctx) int vir_inputs[VERT_ATTRIB_MAX]; GLint tab[VERT_ATTRIB_MAX]; int swizzle[VERT_ATTRIB_MAX][4]; + struct r300_vertex_program *prog = + (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); if (hw_tcl_on) { - struct r300_vertex_program *prog = - (struct r300_vertex_program *) - CURRENT_VERTEX_SHADER(ctx); inputs = prog->inputs; - InputsRead = CURRENT_VERTEX_SHADER(ctx)->key.InputsRead; - OutputsWritten = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; + InputsRead = prog->key.InputsRead; + OutputsWritten = prog->key.OutputsWritten; } else { - DECLARE_RENDERINPUTS(inputs_bitset); - inputs = r300->state.sw_tcl_inputs; + inputs = rmesa->state.sw_tcl_inputs; - RENDERINPUTS_COPY(inputs_bitset, - TNL_CONTEXT(ctx)->render_inputs_bitset); + DECLARE_RENDERINPUTS(render_inputs_bitset); + RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset); - assert(RENDERINPUTS_TEST(inputs_bitset, _TNL_ATTRIB_POS)); - InputsRead |= 1 << VERT_ATTRIB_POS; - OutputsWritten |= 1 << VERT_RESULT_HPOS; + assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)); + assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_NORMAL) == 0); + assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR0)); - assert(RENDERINPUTS_TEST(inputs_bitset, _TNL_ATTRIB_NORMAL) - == 0); + if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)) { + InputsRead |= 1 << VERT_ATTRIB_POS; + OutputsWritten |= 1 << VERT_RESULT_HPOS; + } - assert(RENDERINPUTS_TEST(inputs_bitset, _TNL_ATTRIB_COLOR0)); - InputsRead |= 1 << VERT_ATTRIB_COLOR0; - OutputsWritten |= 1 << VERT_RESULT_COL0; + if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR0)) { + InputsRead |= 1 << VERT_ATTRIB_COLOR0; + OutputsWritten |= 1 << VERT_RESULT_COL0; + } - if (RENDERINPUTS_TEST(inputs_bitset, _TNL_ATTRIB_COLOR1)) { + if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR1)) { InputsRead |= 1 << VERT_ATTRIB_COLOR1; OutputsWritten |= 1 << VERT_RESULT_COL1; } - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) - if (RENDERINPUTS_TEST - (inputs_bitset, _TNL_ATTRIB_TEX(i))) { + for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { + if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_TEX(i))) { InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); } + } - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) - if (InputsRead & (1 << i)) + for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { + if (InputsRead & (1 << i)) { inputs[i] = nr++; - else + } else { inputs[i] = -1; + } + } - if (! - (r300->radeon.radeonScreen-> - chip_flags & RADEON_CHIPSET_TCL)) { + if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { /* Fixed, apply to vir0 only */ - memcpy(vir_inputs, inputs, - VERT_ATTRIB_MAX * sizeof(int)); + memcpy(vir_inputs, inputs, VERT_ATTRIB_MAX * sizeof(int)); inputs = vir_inputs; - if (InputsRead & VERT_ATTRIB_POS) inputs[VERT_ATTRIB_POS] = 0; - if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) inputs[VERT_ATTRIB_COLOR0] = 2; - if (InputsRead & (1 << VERT_ATTRIB_COLOR1)) inputs[VERT_ATTRIB_COLOR1] = 3; - for (i = VERT_ATTRIB_TEX0; i <= VERT_ATTRIB_TEX7; i++) if (InputsRead & (1 << i)) inputs[i] = 6 + (i - VERT_ATTRIB_TEX0); } - RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, - inputs_bitset); + RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset); } + assert(InputsRead); assert(OutputsWritten); - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) - if (InputsRead & (1 << i)) + for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { + if (InputsRead & (1 << i)) { tab[nr++] = i; + } + } - if (nr > R300_MAX_AOS_ARRAYS) + if (nr > R300_MAX_AOS_ARRAYS) { return R300_FALLBACK_TCL; + } for (i = 0; i < nr; i++) { - int ci; - int comp_size, fix, found = 0; + int ci, fix, found = 0; swizzle[i][0] = SWIZZLE_ZERO; swizzle[i][1] = SWIZZLE_ZERO; swizzle[i][2] = SWIZZLE_ZERO; swizzle[i][3] = SWIZZLE_ONE; - for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) + for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] = ci; + } - if (r300IsGartMemory(rmesa, vb->AttribPtr[tab[i]]->data, - /*(count-1)*stride */ 4)) { - if (vb->AttribPtr[tab[i]]->stride % 4) + if (r300IsGartMemory(rmesa, vb->AttribPtr[tab[i]]->data, 4)) { + if (vb->AttribPtr[tab[i]]->stride % 4) { return R300_FALLBACK_TCL; - - rmesa->state.aos[i].address = - (void *)(vb->AttribPtr[tab[i]]->data); + } + rmesa->state.aos[i].address = (void *)(vb->AttribPtr[tab[i]]->data); rmesa->state.aos[i].start = 0; - rmesa->state.aos[i].aos_offset = - r300GartOffsetFromVirtual(rmesa, - vb-> - AttribPtr[tab[i]]->data); - rmesa->state.aos[i].aos_stride = - vb->AttribPtr[tab[i]]->stride / 4; - - rmesa->state.aos[i].aos_size = - vb->AttribPtr[tab[i]]->size; + rmesa->state.aos[i].aos_offset = r300GartOffsetFromVirtual(rmesa, vb->AttribPtr[tab[i]]->data); + rmesa->state.aos[i].aos_stride = vb->AttribPtr[tab[i]]->stride / 4; + rmesa->state.aos[i].aos_size = vb->AttribPtr[tab[i]]->size; } else { r300EmitVec(ctx, &rmesa->state.aos[i], vb->AttribPtr[tab[i]]->data, @@ -453,13 +453,10 @@ int r300EmitArrays(GLcontext * ctx) rmesa->state.aos[i].aos_size = vb->AttribPtr[tab[i]]->size; - comp_size = _mesa_sizeof_type(GL_FLOAT); - for (fix = 0; fix <= 4 - vb->AttribPtr[tab[i]]->size; fix++) { - if ((rmesa->state.aos[i].aos_offset - - comp_size * fix) % 4) + if ((rmesa->state.aos[i].aos_offset - _mesa_sizeof_type(GL_FLOAT) * fix) % 4) { continue; - + } found = 1; break; } @@ -468,11 +465,10 @@ int r300EmitArrays(GLcontext * ctx) if (fix > 0) { WARN_ONCE("Feeling lucky?\n"); } - - rmesa->state.aos[i].aos_offset -= comp_size * fix; - - for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) + rmesa->state.aos[i].aos_offset -= _mesa_sizeof_type(GL_FLOAT) * fix; + for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] += fix; + } } else { WARN_ONCE ("Cannot handle offset %x with stride %d, comp %d\n", @@ -483,55 +479,27 @@ int r300EmitArrays(GLcontext * ctx) } } - /* setup INPUT_ROUTE */ - R300_STATECHANGE(r300, vir[0]); - ((drm_r300_cmd_header_t *) r300->hw.vir[0].cmd)->packet0.count = - t_vir0(&r300->hw.vir[0].cmd[R300_VIR_CNTL_0], vb->AttribPtr, - inputs, tab, nr); - - R300_STATECHANGE(r300, vir[1]); - ((drm_r300_cmd_header_t *) r300->hw.vir[1].cmd)->packet0.count = - t_vir1(&r300->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, nr); - - /* Set up input_cntl */ - /* I don't think this is needed for vertex buffers, but it doesn't hurt anything */ - R300_STATECHANGE(r300, vic); - r300->hw.vic.cmd[R300_VIC_CNTL_0] = 0x5555; /* Hard coded value, no idea what it means */ - r300->hw.vic.cmd[R300_VIC_CNTL_1] = t_vic(ctx, InputsRead); - - /* Stage 3: VAP output */ - - R300_STATECHANGE(r300, vof); - - r300->hw.vof.cmd[R300_VOF_CNTL_0] = 0; - r300->hw.vof.cmd[R300_VOF_CNTL_1] = 0; - - if (OutputsWritten & (1 << VERT_RESULT_HPOS)) - r300->hw.vof.cmd[R300_VOF_CNTL_0] |= - R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; - - if (OutputsWritten & (1 << VERT_RESULT_COL0)) - r300->hw.vof.cmd[R300_VOF_CNTL_0] |= - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT; - - if (OutputsWritten & (1 << VERT_RESULT_COL1)) - r300->hw.vof.cmd[R300_VOF_CNTL_0] |= - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; - - /*if(OutputsWritten & (1 << VERT_RESULT_BFC0)) - r300->hw.vof.cmd[R300_VOF_CNTL_0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT; - - if(OutputsWritten & (1 << VERT_RESULT_BFC1)) - r300->hw.vof.cmd[R300_VOF_CNTL_0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; */ - //if(OutputsWritten & (1 << VERT_RESULT_FOGC)) - - if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) - r300->hw.vof.cmd[R300_VOF_CNTL_0] |= - R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) - if (OutputsWritten & (1 << (VERT_RESULT_TEX0 + i))) - r300->hw.vof.cmd[R300_VOF_CNTL_1] |= (4 << (3 * i)); + /* Setup INPUT_ROUTE. */ + R300_STATECHANGE(rmesa, vir[0]); + ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = + r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + vb->AttribPtr, inputs, tab, nr); + R300_STATECHANGE(rmesa, vir[1]); + ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = + r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + nr); + + /* Setup INPUT_CNTL. */ + R300_STATECHANGE(rmesa, vic); + rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); + rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); + + /* Setup OUTPUT_VTX_FMT. */ + R300_STATECHANGE(rmesa, vof); + rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = + r300VAPOutputCntl0(ctx, OutputsWritten); + rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = + r300VAPOutputCntl1(ctx, OutputsWritten); rmesa->state.aos_count = nr; diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 4f841a54139..2f79ee3a23a 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -44,20 +44,11 @@ #include "r300_cmdbuf.h" #include "radeon_reg.h" -/* - * CP type-3 packets - */ -#define RADEON_CP_PACKET3_UNK1B 0xC0001B00 -#define RADEON_CP_PACKET3_INDX_BUFFER 0xC0003300 -#define RADEON_CP_PACKET3_3D_DRAW_VBUF_2 0xC0003400 -#define RADEON_CP_PACKET3_3D_DRAW_IMMD_2 0xC0003500 -#define RADEON_CP_PACKET3_3D_DRAW_INDX_2 0xC0003600 -#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 -#define RADEON_CP_PACKET3_3D_CLEAR_ZMASK 0xC0003202 -#define RADEON_CP_PACKET3_3D_CLEAR_CMASK 0xC0003802 -#define RADEON_CP_PACKET3_3D_CLEAR_HIZ 0xC0003702 - +/* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up + * with DRM */ #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) static inline uint32_t cmdpacket0(int reg, int count) { diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 416ea7f231d..15c2cf3ad7b 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -224,25 +224,23 @@ static void r300EmitClearState(GLcontext * ctx) e32(R300_INPUT_CNTL_0_COLOR); e32(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0); - if (!has_tcl) { - R300_STATECHANGE(r300, vte); - /* comes from fglrx startup of clear */ - reg_start(R300_SE_VTE_CNTL, 1); - e32(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | - R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | - R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | - R300_VPORT_Z_OFFSET_ENA); - e32(0x8); - - reg_start(0x21dc, 0); - e32(0xaaaaaaaa); - } + R300_STATECHANGE(r300, vte); + /* comes from fglrx startup of clear */ + reg_start(R300_SE_VTE_CNTL, 1); + e32(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | + R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | + R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | + R300_VPORT_Z_OFFSET_ENA); + e32(0x8); + + reg_start(0x21dc, 0); + e32(0xaaaaaaaa); R300_STATECHANGE(r300, vof); reg_start(R300_VAP_OUTPUT_VTX_FMT_0, 1); e32(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT); - e32(0x0); /* no textures */ + e32(0x0); /* no textures */ R300_STATECHANGE(r300, txe); reg_start(R300_TX_ENABLE, 0); diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index e64f5095bc5..3ce09c16d3f 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -116,6 +116,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 + /* each of the following is 3 bits wide, specifies number + of components */ # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 @@ -299,6 +301,18 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_221C_NORMAL 0x00000000 # define R300_221C_CLEAR 0x0001C000 +/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first + * plane is per-pixel and the second plane is per-vertex. + * + * This was determined by experimentation alone but I believe it is correct. + * + * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. + */ +#define R300_VAP_CLIP_X_0 0x2220 +#define R300_VAP_CLIP_X_1 0x2224 +#define R300_VAP_CLIP_Y_0 0x2228 +#define R300_VAP_CLIP_Y_1 0x2230 + /* gap */ /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between @@ -628,11 +642,17 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Set INTERP_USED on all interpolators that produce data used by * the fragment program. INTERP_USED looks like a swizzling mask, * but I haven't seen it used that way. + * + * Note: The _UNKNOWN constants are always set in their respective + * register. I don't know if this is necessary. */ #define R300_RS_INTERP_0 0x4310 #define R300_RS_INTERP_1 0x4314 +# define R300_RS_INTERP_1_UNKNOWN 0x40 #define R300_RS_INTERP_2 0x4318 +# define R300_RS_INTERP_2_UNKNOWN 0x80 #define R300_RS_INTERP_3 0x431C +# define R300_RS_INTERP_3_UNKNOWN 0xC0 #define R300_RS_INTERP_4 0x4320 #define R300_RS_INTERP_5 0x4324 #define R300_RS_INTERP_6 0x4328 @@ -961,7 +981,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * first node is stored in NODE_2, the second node is stored in NODE_3. * * Offsets are relative to the master offset from PFS_CNTL_2. - * LAST_NODE is set for the last node, and only for the last node. */ #define R300_PFS_NODE_0 0x4610 #define R300_PFS_NODE_1 0x4614 @@ -975,7 +994,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) # define R300_PFS_NODE_TEX_END_SHIFT 17 # define R300_PFS_NODE_TEX_END_MASK (31 << 17) -/*# define R300_PFS_NODE_LAST_NODE (1 << 22) */ # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) @@ -1585,6 +1603,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_EB_UNK1_SHIFT 24 # define R300_EB_UNK1 (0x80<<24) # define R300_EB_UNK2 0x0810 +#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 /* END: Packet 3 commands */ diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 143fe9fd35d..83999307b56 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -171,16 +171,13 @@ static int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim) return num_verts - verts_off; } -static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts, - int elt_size) +static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) { r300ContextPtr rmesa = R300_CONTEXT(ctx); struct r300_dma_region *rvb = &rmesa->state.elt_dma; void *out; - assert(elt_size == 2 || elt_size == 4); - - if (r300IsGartMemory(rmesa, elts, n_elts * elt_size)) { + if (r300IsGartMemory(rmesa, elts, n_elts * 4)) { rvb->address = rmesa->radeon.radeonScreen->gartTextures.map; rvb->start = ((char *)elts) - rvb->address; rvb->aos_offset = @@ -192,66 +189,27 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts, _mesa_exit(-1); } - r300AllocDmaRegion(rmesa, rvb, n_elts * elt_size, elt_size); + r300AllocDmaRegion(rmesa, rvb, n_elts * 4, 4); rvb->aos_offset = GET_START(rvb); out = rvb->address + rvb->start; - memcpy(out, elts, n_elts * elt_size); + memcpy(out, elts, n_elts * 4); } static void r300FireEB(r300ContextPtr rmesa, unsigned long addr, - int vertex_count, int type, int elt_size) + int vertex_count, int type) { int cmd_reserved = 0; int cmd_written = 0; drm_radeon_cmd_header_t *cmd = NULL; - unsigned long t_addr; - unsigned long magic_1, magic_2; - - assert(elt_size == 2 || elt_size == 4); - - if (addr & (elt_size - 1)) { - WARN_ONCE("Badly aligned buffer\n"); - return; - } - magic_1 = (addr % 32) / 4; - t_addr = addr & ~0x1d; - magic_2 = (vertex_count + 1 + (t_addr & 0x2)) / 2 + magic_1; + start_packet3(CP_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0), 0); + e32(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (vertex_count << 16) | type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - start_packet3(RADEON_CP_PACKET3_3D_DRAW_INDX_2, 0); - if (elt_size == 4) { - e32(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - (vertex_count << 16) | type | - R300_VAP_VF_CNTL__INDEX_SIZE_32bit); - } else { - e32(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | - (vertex_count << 16) | type); - } - - start_packet3(RADEON_CP_PACKET3_INDX_BUFFER, 2); -#ifdef OPTIMIZE_ELTS - if (elt_size == 4) { - e32(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - e32(addr); - } else { - e32(R300_EB_UNK1 | (magic_1 << 16) | R300_EB_UNK2); - e32(t_addr); - } -#else + start_packet3(CP_PACKET3(R300_PACKET3_INDX_BUFFER, 2), 2); e32(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); e32(addr); -#endif - - if (elt_size == 4) { - e32(vertex_count); - } else { -#ifdef OPTIMIZE_ELTS - e32(magic_2); -#else - e32((vertex_count + 1) / 2); -#endif - } + e32(vertex_count); } static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) @@ -266,26 +224,23 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); - start_packet3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); + start_packet3(CP_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1), sz - 1); e32(nr); + for (i = 0; i + 1 < nr; i += 2) { - e32((rmesa->state.aos[i].aos_size << 0) - | (rmesa->state.aos[i].aos_stride << 8) - | (rmesa->state.aos[i + 1].aos_size << 16) - | (rmesa->state.aos[i + 1].aos_stride << 24) - ); - e32(rmesa->state.aos[i].aos_offset + - offset * 4 * rmesa->state.aos[i].aos_stride); - e32(rmesa->state.aos[i + 1].aos_offset + - offset * 4 * rmesa->state.aos[i + 1].aos_stride); + e32((rmesa->state.aos[i].aos_size << 0) | + (rmesa->state.aos[i].aos_stride << 8) | + (rmesa->state.aos[i + 1].aos_size << 16) | + (rmesa->state.aos[i + 1].aos_stride << 24)); + + e32(rmesa->state.aos[i].aos_offset + offset * 4 * rmesa->state.aos[i].aos_stride); + e32(rmesa->state.aos[i + 1].aos_offset + offset * 4 * rmesa->state.aos[i + 1].aos_stride); } if (nr & 1) { - e32((rmesa->state.aos[nr - 1].aos_size << 0) - | (rmesa->state.aos[nr - 1].aos_stride << 8) - ); - e32(rmesa->state.aos[nr - 1].aos_offset + - offset * 4 * rmesa->state.aos[nr - 1].aos_stride); + e32((rmesa->state.aos[nr - 1].aos_size << 0) | + (rmesa->state.aos[nr - 1].aos_stride << 8)); + e32(rmesa->state.aos[nr - 1].aos_offset + offset * 4 * rmesa->state.aos[nr - 1].aos_stride); } } @@ -295,9 +250,8 @@ static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) int cmd_written = 0; drm_radeon_cmd_header_t *cmd = NULL; - start_packet3(RADEON_CP_PACKET3_3D_DRAW_VBUF_2, 0); - e32(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) - | type); + start_packet3(CP_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0), 0); + e32(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); } static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, @@ -320,9 +274,8 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, WARN_ONCE("Too many elts\n"); return; } - r300EmitElts(ctx, vb->Elts, num_verts, 4); - r300FireEB(rmesa, rmesa->state.elt_dma.aos_offset, - num_verts, type, 4); + r300EmitElts(ctx, vb->Elts, num_verts); + r300FireEB(rmesa, rmesa->state.elt_dma.aos_offset, num_verts, type); } else { r300EmitAOS(rmesa, rmesa->state.aos_count, start); r300FireAOS(rmesa, num_verts, type); @@ -343,6 +296,8 @@ static GLboolean r300RunRender(GLcontext * ctx, if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); + if (hw_tcl_on == GL_FALSE) + vb->AttribPtr[VERT_ATTRIB_POS] = vb->ClipPtr; r300UpdateShaders(rmesa); if (r300EmitArrays(ctx)) return GL_TRUE; @@ -416,8 +371,6 @@ static int r300Fallback(GLcontext * ctx) FALLBACK_IF(ctx->Point.PointSprite); if (!r300->disable_lowimpact_fallback) { - FALLBACK_IF(ctx->Polygon.OffsetPoint); - FALLBACK_IF(ctx->Polygon.OffsetLine); FALLBACK_IF(ctx->Polygon.StippleFlag); FALLBACK_IF(ctx->Multisample.Enabled); FALLBACK_IF(ctx->Line.StippleFlag); diff --git a/src/mesa/drivers/dri/r300/r300_shader.c b/src/mesa/drivers/dri/r300/r300_shader.c index 59fe17ba10e..5f5ac7c4c71 100644 --- a/src/mesa/drivers/dri/r300/r300_shader.c +++ b/src/mesa/drivers/dri/r300/r300_shader.c @@ -54,6 +54,7 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) fp->translated = GL_FALSE; break; } + /* need this for tcl fallbacks */ _tnl_program_string(ctx, target, prog); } @@ -61,7 +62,7 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) static GLboolean r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) { - return 1; + return GL_TRUE; } void r300InitShaderFuncs(struct dd_function_table *functions) diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index b235baaf10f..bdd6855802b 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -715,8 +715,8 @@ static void r300LineWidth(GLcontext * ctx, GLfloat widthf) widthf = ctx->Line._Width; R300_STATECHANGE(r300, lcntl); - r300->hw.lcntl.cmd[1] = (int)(widthf * 6.0); - r300->hw.lcntl.cmd[1] |= R300_LINE_CNT_VE; + r300->hw.lcntl.cmd[1] = + R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0); } static void r300PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) @@ -1354,6 +1354,17 @@ union r300_outputs_written { static void r300SetupRSUnit(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); + /* I'm still unsure if these are needed */ + GLuint interp_magic[8] = { + 0x00, + R300_RS_INTERP_1_UNKNOWN, + R300_RS_INTERP_2_UNKNOWN, + R300_RS_INTERP_3_UNKNOWN, + 0x00, + 0x00, + 0x00, + 0x00 + }; union r300_outputs_written OutputsWritten; GLuint InputsRead; int fp_reg, high_rr; @@ -1361,11 +1372,9 @@ static void r300SetupRSUnit(GLcontext * ctx) int i; if (hw_tcl_on) - OutputsWritten.vp_outputs = - CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; + OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, - r300->state.render_inputs_bitset); + RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset); if (ctx->FragmentProgram._Current) InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; @@ -1397,9 +1406,8 @@ static void r300SetupRSUnit(GLcontext * ctx) } for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 - | R300_RS_INTERP_USED - | (in_texcoords << R300_RS_INTERP_SRC_SHIFT); + r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_INTERP_USED | (in_texcoords << R300_RS_INTERP_SRC_SHIFT) + | interp_magic[i]; r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] = 0; if (InputsRead & (FRAG_BIT_TEX0 << i)) { @@ -1408,65 +1416,45 @@ static void r300SetupRSUnit(GLcontext * ctx) | (fp_reg << R300_RS_ROUTE_DEST_SHIFT); high_rr = fp_reg; - if (!R300_OUTPUTS_WRITTEN_TEST - (OutputsWritten, VERT_RESULT_TEX0 + i, - _TNL_ATTRIB_TEX(i))) { - /* Passing invalid data here can lock the GPU. */ - WARN_ONCE - ("fragprog wants coords for tex%d, vp doesn't provide them!\n", - i); - //_mesa_print_program(&CURRENT_VERTEX_SHADER(ctx)->Base); - //_mesa_exit(-1); + /* Passing invalid data here can lock the GPU. */ + if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { + InputsRead &= ~(FRAG_BIT_TEX0 << i); + fp_reg++; + } else { + WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i); } - InputsRead &= ~(FRAG_BIT_TEX0 << i); - fp_reg++; } /* Need to count all coords enabled at vof */ - if (R300_OUTPUTS_WRITTEN_TEST - (OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) + if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { in_texcoords++; + } } if (InputsRead & FRAG_BIT_COL0) { - if (!R300_OUTPUTS_WRITTEN_TEST - (OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { - WARN_ONCE - ("fragprog wants col0, vp doesn't provide it\n"); - goto out; /* FIXME */ - //_mesa_print_program(&CURRENT_VERTEX_SHADER(ctx)->Base); - //_mesa_exit(-1); + if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { + r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT); + InputsRead &= ~FRAG_BIT_COL0; + col_interp_nr++; + } else { + WARN_ONCE("fragprog wants col0, vp doesn't provide it\n"); } - - r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 - | R300_RS_ROUTE_0_COLOR - | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT); - InputsRead &= ~FRAG_BIT_COL0; - col_interp_nr++; } - out: if (InputsRead & FRAG_BIT_COL1) { - if (!R300_OUTPUTS_WRITTEN_TEST - (OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { - WARN_ONCE - ("fragprog wants col1, vp doesn't provide it\n"); - //_mesa_exit(-1); + if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { + r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT); + InputsRead &= ~FRAG_BIT_COL1; + if (high_rr < 1) + high_rr = 1; + col_interp_nr++; + } else { + WARN_ONCE("fragprog wants col1, vp doesn't provide it\n"); } - - r300->hw.rr.cmd[R300_RR_ROUTE_1] |= - R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | - (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT); - InputsRead &= ~FRAG_BIT_COL1; - if (high_rr < 1) - high_rr = 1; - col_interp_nr++; } /* Need at least one. This might still lock as the values are undefined... */ if (in_texcoords == 0 && col_interp_nr == 0) { - r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 - | R300_RS_ROUTE_0_COLOR - | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT); + r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT); col_interp_nr++; } @@ -1475,17 +1463,13 @@ static void r300SetupRSUnit(GLcontext * ctx) | R300_RS_CNTL_0_UNKNOWN_18; assert(high_rr >= 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = - cmdpacket0(R300_RS_ROUTE_0, high_rr + 1); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_ROUTE_0, high_rr + 1); r300->hw.rc.cmd[2] = 0xC0 | high_rr; if (InputsRead) - WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", - InputsRead); + WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); } -#define vpucount(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) - #define bump_vpu_count(ptr, new_count) do{\ drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ int _nc=(new_count)/4; \ @@ -1785,8 +1769,6 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_POLYGON_OFFSET_POINT: case GL_POLYGON_OFFSET_LINE: - break; - case GL_POLYGON_OFFSET_FILL: R300_STATECHANGE(r300, occlusion_cntl); if (state) { @@ -1859,10 +1841,12 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.unk2134.cmd[1] = 0x00FFFFFF; r300->hw.unk2134.cmd[2] = 0x00000000; - if (_mesa_little_endian()) - r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP; - else - r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP; + +#ifdef MESA_LITTLE_ENDIAN + r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP; +#else + r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP; +#endif /* disable VAP/TCL on non-TCL capable chips */ if (!has_tcl) @@ -1872,10 +1856,10 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.unk221C.cmd[1] = R300_221C_NORMAL; - r300->hw.unk2220.cmd[1] = r300PackFloat32(1.0); - r300->hw.unk2220.cmd[2] = r300PackFloat32(1.0); - r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0); - r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0); + r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */ + r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */ + r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */ + r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */ /* XXX: Other families? */ switch (r300->radeon.radeonScreen->chip_family) { @@ -1930,13 +1914,13 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.unk4214.cmd[1] = 0x00050005; - r300PointSize(ctx, 0.0); + r300PointSize(ctx, 1.0); r300->hw.unk4230.cmd[1] = 0x18000006; r300->hw.unk4230.cmd[2] = 0x00020006; r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0); - r300LineWidth(ctx, 0.0); + r300LineWidth(ctx, 1.0); r300->hw.unk4260.cmd[1] = 0; r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0); @@ -2152,7 +2136,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) tex_offset << R300_PFS_NODE_TEX_OFFSET_SHIFT) | (fp->node[i]. tex_end << R300_PFS_NODE_TEX_END_SHIFT) - | fp->node[i].flags; /* ( (k==3) ? R300_PFS_NODE_LAST_NODE : 0); */ + | fp->node[i].flags; } else { rmesa->hw.fp.cmd[R300_FP_NODE0 + (3 - i)] = 0; } diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 2a21c611629..1805cecd0af 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -294,27 +294,20 @@ static const struct gl_texture_format *r300Choose8888TexFormat(GLenum srcFormat, const GLubyte littleEndian = *((const GLubyte *)&ui); if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE - && !littleEndian) || (srcFormat == GL_ABGR_EXT - && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) - || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE - && littleEndian)) { + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { return &_mesa_texformat_rgba8888; - } else - if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) - || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE - && littleEndian) || (srcFormat == GL_ABGR_EXT - && srcType == GL_UNSIGNED_INT_8_8_8_8) - || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE - && !littleEndian)) { + } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { return &_mesa_texformat_rgba8888_rev; - } else if (srcFormat == GL_BGRA && - ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8)) { + } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8)) { return &_mesa_texformat_argb8888_rev; - } else if (srcFormat == GL_BGRA && - ((srcType == GL_UNSIGNED_BYTE && littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { + } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { return &_mesa_texformat_argb8888; } else return _dri_texformat_argb8888; @@ -563,34 +556,31 @@ r300ValidateClientStorage(GLcontext * ctx, GLenum target, return 0; } - { - GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, - format, type); + GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, + format, type); - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "%s: srcRowStride %d/%x\n", - __FUNCTION__, srcRowStride, srcRowStride); + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "%s: srcRowStride %d/%x\n", + __FUNCTION__, srcRowStride, srcRowStride); - /* Could check this later in upload, pitch restrictions could be - * relaxed, but would need to store the image pitch somewhere, - * as packing details might change before image is uploaded: - */ - if (!r300IsGartMemory(rmesa, pixels, srcHeight * srcRowStride) - || (srcRowStride & 63)) - return 0; + /* Could check this later in upload, pitch restrictions could be + * relaxed, but would need to store the image pitch somewhere, + * as packing details might change before image is uploaded: + */ + if (!r300IsGartMemory(rmesa, pixels, srcHeight * srcRowStride) + || (srcRowStride & 63)) + return 0; - /* Have validated that _mesa_transfer_teximage would be a straight - * memcpy at this point. NOTE: future calls to TexSubImage will - * overwrite the client data. This is explicitly mentioned in the - * extension spec. - */ - texImage->Data = (void *)pixels; - texImage->IsClientData = GL_TRUE; - texImage->RowStride = - srcRowStride / texImage->TexFormat->TexelBytes; + /* Have validated that _mesa_transfer_teximage would be a straight + * memcpy at this point. NOTE: future calls to TexSubImage will + * overwrite the client data. This is explicitly mentioned in the + * extension spec. + */ + texImage->Data = (void *)pixels; + texImage->IsClientData = GL_TRUE; + texImage->RowStride = srcRowStride / texImage->TexFormat->TexelBytes; - return 1; - } + return 1; } static void r300TexImage1D(GLcontext * ctx, GLenum target, GLint level, diff --git a/src/mesa/drivers/dri/r300/r300_texmem.c b/src/mesa/drivers/dri/r300/r300_texmem.c index e2e8355d275..38f0da8b7c0 100644 --- a/src/mesa/drivers/dri/r300/r300_texmem.c +++ b/src/mesa/drivers/dri/r300/r300_texmem.c @@ -63,29 +63,16 @@ SOFTWARE. */ void r300DestroyTexObj(r300ContextPtr rmesa, r300TexObjPtr t) { + int i; + if (RADEON_DEBUG & DEBUG_TEXTURE) { fprintf(stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj); } - if (rmesa != NULL) { - unsigned i; - - for (i = 0; i < rmesa->radeon.glCtx->Const.MaxTextureUnits; i++) { - if (t == rmesa->state.texture.unit[i].texobj) { - rmesa->state.texture.unit[i].texobj = NULL; - /* This code below is meant to shorten state - pushed to the hardware by not programming - unneeded units. - - This does not appear to be worthwhile on R300 */ -#if 0 - remove_from_list(&rmesa->hw.tex[i]); - make_empty_list(&rmesa->hw.tex[i]); - remove_from_list(&rmesa->hw.cube[i]); - make_empty_list(&rmesa->hw.cube[i]); -#endif - } + for (i = 0; i < rmesa->radeon.glCtx->Const.MaxTextureUnits; i++) { + if (rmesa->state.texture.unit[i].texobj == t) { + rmesa->state.texture.unit[i].texobj = NULL; } } } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index eeaba584df8..1d2909fd214 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -480,11 +480,11 @@ static GLboolean r300UpdateTexture(GLcontext * ctx, int unit) */ rmesa->state.texture.unit[unit].texobj->base.bound &= - ~(1UL << unit); + ~(1 << unit); } rmesa->state.texture.unit[unit].texobj = t; - t->base.bound |= (1UL << unit); + t->base.bound |= (1 << unit); t->dirty_state |= 1 << unit; driUpdateTextureLRU((driTextureObject *) t); /* XXX: should be locked! */ } @@ -501,7 +501,6 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); r300TexObjPtr t; - int idx; if (!tObj) return; @@ -518,24 +517,24 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, switch (depth) { case 32: - idx = 2; + t->format = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + t->filter |= tx_table[2].filter; t->pitch_reg /= 4; break; case 24: default: - idx = 4; + t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + t->filter |= tx_table[4].filter; t->pitch_reg /= 4; break; case 16: - idx = 5; + t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); + t->filter |= tx_table[5].filter; t->pitch_reg /= 2; break; } t->pitch_reg--; - - t->format = tx_table[idx].format; - t->filter |= tx_table[idx].filter; } static GLboolean r300UpdateTextureUnit(GLcontext * ctx, int unit) diff --git a/src/mesa/drivers/x11/glxapi.c b/src/mesa/drivers/x11/glxapi.c index 5f11c90c13c..309a0008d76 100644 --- a/src/mesa/drivers/x11/glxapi.c +++ b/src/mesa/drivers/x11/glxapi.c @@ -141,7 +141,7 @@ static void SetCurrentContext(GLXContext c) { #if defined(GLX_USE_TLS) - CurrentContext = context; + CurrentContext = c; #elif defined(THREADS) _glthread_SetTSD(&ContextTSD, c); #else @@ -1169,7 +1169,7 @@ _glxapi_get_extensions(void) #ifdef GLX_SGIX_pbuffer "GLX_SGIX_pbuffer", #endif -#ifdef GLX_EXT_texture_from_pixmap, +#ifdef GLX_EXT_texture_from_pixmap "GLX_EXT_texture_from_pixmap", #endif NULL diff --git a/src/mesa/drivers/x11/xm_api.c b/src/mesa/drivers/x11/xm_api.c index cff64d17ade..eaa277db4ad 100644 --- a/src/mesa/drivers/x11/xm_api.c +++ b/src/mesa/drivers/x11/xm_api.c @@ -63,7 +63,6 @@ #endif #include "glxheader.h" -#include "GL/glxtokens.h" #include "GL/xmesa.h" #include "xmesaP.h" #include "context.h" |