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authorFrancisco Jerez <[email protected]>2015-03-18 19:51:01 +0200
committerFrancisco Jerez <[email protected]>2015-03-23 14:12:56 +0200
commit1db9c0cd0c0f4a1a0a4409e4c90cd0f0d0bce68d (patch)
treeada462e031d85d3eaaa970ed6cfc0bde31c818d1 /src/mesa/drivers
parentd041a43c0f3e01c9d6f81244cbf1c85d4f3a17d5 (diff)
i965/vec4: Fix handling of multiple register reads and writes in opt_cse().
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_cse.cpp25
1 files changed, 17 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
index 2c29d9f8999..0a687313a4e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
@@ -114,6 +114,7 @@ instructions_match(vec4_instruction *a, vec4_instruction *b)
a->conditional_mod == b->conditional_mod &&
a->dst.type == b->dst.type &&
a->dst.writemask == b->dst.writemask &&
+ a->regs_written == b->regs_written &&
operands_match(a, b);
}
@@ -160,21 +161,29 @@ vec4_visitor::opt_cse_local(bblock_t *block)
*/
bool no_existing_temp = entry->tmp.file == BAD_FILE;
if (no_existing_temp && !entry->generator->dst.is_null()) {
- entry->tmp = src_reg(this, glsl_type::float_type);
- entry->tmp.type = inst->dst.type;
- entry->tmp.swizzle = BRW_SWIZZLE_XYZW;
+ entry->tmp = retype(src_reg(GRF, alloc.allocate(
+ entry->generator->regs_written),
+ NULL), inst->dst.type);
+
+ for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
+ vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
+ offset(entry->tmp, i));
+ entry->generator->insert_after(block, copy);
+ }
- vec4_instruction *copy = MOV(entry->generator->dst, entry->tmp);
- entry->generator->insert_after(block, copy);
entry->generator->dst = dst_reg(entry->tmp);
}
/* dest <- temp */
if (!inst->dst.is_null()) {
assert(inst->dst.type == entry->tmp.type);
- vec4_instruction *copy = MOV(inst->dst, entry->tmp);
- copy->force_writemask_all = inst->force_writemask_all;
- inst->insert_before(block, copy);
+
+ for (unsigned i = 0; i < inst->regs_written; ++i) {
+ vec4_instruction *copy = MOV(offset(inst->dst, i),
+ offset(entry->tmp, i));
+ copy->force_writemask_all = inst->force_writemask_all;
+ inst->insert_before(block, copy);
+ }
}
/* Set our iterator so that next time through the loop inst->next