i965/mesa/st/swrast: set fs shader_info directly and switch to using it

Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.

Reviewed-by: Jason Ekstrand <[email protected]>

8 files changed, 19 insertions, 26 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 68f0073b942..2048beaaa57 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -305,7 +305,7 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
    /* Resolve color buffers for non-coherent framebuffer fetch. */
    if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
        ctx->FragmentProgram._Current &&
-       ctx->FragmentProgram._Current->Base.nir->info->outputs_read) {
+       ctx->FragmentProgram._Current->Base.info.outputs_read) {
       const struct gl_framebuffer *fb = ctx->DrawBuffer;
 
       for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index f3f5a800ae1..0e94d156a6e 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -325,8 +325,7 @@ emit:
     * BRW_NEW_FRAGMENT_PROGRAM
     */
    if (brw->gen == 4 && !brw->is_g4x &&
-       (brw->fragment_program->Base.nir->info->inputs_read &
-        (1 << VARYING_SLOT_POS))) {
+       (brw->fragment_program->Base.info.inputs_read & (1 << VARYING_SLOT_POS))) {
       BEGIN_BATCH(2);
       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
       OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index b0ed712f0a3..cf512f8bbff 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -191,7 +191,7 @@ brw_upload_sf_prog(struct brw_context *brw)
    if (key.do_point_sprite) {
       key.point_sprite_coord_replace = ctx->Point.CoordReplace & 0xff;
    }
-   if (brw->fragment_program->Base.nir->info->inputs_read &
+   if (brw->fragment_program->Base.info.inputs_read &
        BITFIELD64_BIT(VARYING_SLOT_PNTC)) {
       key.do_point_coord = 1;
    }
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 53b7d9bd91e..ce815254d58 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -450,13 +450,11 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
     */
    if (brw->gen < 6) {
       /* _NEW_COLOR */
-      if (fp->program.Base.nir->info->fs.uses_discard ||
-          ctx->Color.AlphaEnabled) {
+      if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) {
          lookup |= IZ_PS_KILL_ALPHATEST_BIT;
       }
 
-      if (fp->program.Base.nir->info->outputs_written &
-          BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+      if (prog->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
          lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
       }
 
@@ -545,9 +543,8 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
    }
 
    /* BRW_NEW_VUE_MAP_GEOM_OUT */
-   if (brw->gen < 6 ||
-       _mesa_bitcount_64(fp->program.Base.nir->info->inputs_read &
-                         BRW_FS_VARYING_INPUT_MASK) > 16) {
+   if (brw->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
+                                         BRW_FS_VARYING_INPUT_MASK) > 16) {
       key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
    }
 
@@ -609,10 +606,10 @@ brw_fs_precompile(struct gl_context *ctx,
 
    memset(&key, 0, sizeof(key));
 
-   uint64_t outputs_written = fp->Base.nir->info->outputs_written;
+   uint64_t outputs_written = prog->info.outputs_written;
 
    if (brw->gen < 6) {
-      if (fp->Base.nir->info->fs.uses_discard)
+      if (prog->info.fs.uses_discard)
          key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 
       if (outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
@@ -623,10 +620,9 @@ brw_fs_precompile(struct gl_context *ctx,
       key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
    }
 
-   if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.nir->info->inputs_read &
+   if (brw->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
                                          BRW_FS_VARYING_INPUT_MASK) > 16) {
-      key.input_slots_valid =
-         fp->Base.nir->info->inputs_read | VARYING_BIT_POS;
+      key.input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS;
    }
 
    brw_setup_tex_for_precompile(brw, &key.tex, &fp->Base);
@@ -647,7 +643,7 @@ brw_fs_precompile(struct gl_context *ctx,
    struct brw_vue_map vue_map;
    if (brw->gen < 6) {
       brw_compute_vue_map(&brw->screen->devinfo, &vue_map,
-                          fp->Base.nir->info->inputs_read | VARYING_BIT_POS,
+                          prog->info.inputs_read | VARYING_BIT_POS,
                           false);
    }
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ad5e2331143..8808ac1d4d6 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -48,13 +48,13 @@ brw_color_buffer_write_enabled(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_FRAGMENT_PROGRAM */
-   const struct gl_fragment_program *fp = brw->fragment_program;
+   const struct gl_program *fp = &brw->fragment_program->Base;
    unsigned i;
 
    /* _NEW_BUFFERS */
    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
-      uint64_t outputs_written = fp->Base.nir->info->outputs_written;
+      uint64_t outputs_written = fp->info.outputs_written;
 
       /* _NEW_COLOR */
       if (rb && (outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
@@ -79,7 +79,7 @@ brw_upload_wm_unit(struct brw_context *brw)
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_FRAGMENT_PROGRAM */
-   const struct gl_fragment_program *fp = brw->fragment_program;
+   const struct gl_program *fp = &brw->fragment_program->Base;
    /* BRW_NEW_FS_PROG_DATA */
    const struct brw_wm_prog_data *prog_data =
       brw_wm_prog_data(brw->wm.base.prog_data);
@@ -168,7 +168,7 @@ brw_upload_wm_unit(struct brw_context *brw)
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
    wm->wm5.program_uses_depth = prog_data->uses_src_depth;
-   wm->wm5.program_computes_depth = (fp->Base.nir->info->outputs_written &
+   wm->wm5.program_computes_depth = (fp->info.outputs_written &
 				     BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
    /* _NEW_BUFFERS
     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d2cbf50ef86..b64f1225a89 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1146,8 +1146,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
    if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
-       brw->fragment_program &&
-       brw->fragment_program->Base.nir->info->outputs_read) {
+       brw->fragment_program && brw->fragment_program->Base.info.outputs_read) {
       /* _NEW_BUFFERS */
       const struct gl_framebuffer *fb = ctx->DrawBuffer;
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 3824e6e92d1..bb2498965b3 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -177,8 +177,7 @@ calculate_attr_overrides(const struct brw_context *brw,
     * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
     */
 
-   bool fs_needs_vue_header =
-      brw->fragment_program->Base.nir->info->inputs_read &
+   bool fs_needs_vue_header = brw->fragment_program->Base.info.inputs_read &
       (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT);
 
    *urb_entry_read_offset = fs_needs_vue_header ? 0 : 1;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 528d8350825..107c02bafa5 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -95,7 +95,7 @@ upload_sbe(struct brw_context *brw)
       /* prepare the active component dwords */
       int input_index = 0;
       for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
-         if (!(brw->fragment_program->Base.nir->info->inputs_read &
+         if (!(brw->fragment_program->Base.info.inputs_read &
                BITFIELD64_BIT(attr))) {
             continue;
          }