[r300] rename all unkown structs r300_hw_state to readable names

4 files changed, 86 insertions, 82 deletions

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 657a00b0640..b6d52b8bf23 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -303,8 +303,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.vap_cntl.cmd[0] = cmdpacket0(R300_VAP_CNTL, 1);
 	ALLOC_STATE(vte, always, 3, 0);
 	r300->hw.vte.cmd[0] = cmdpacket0(R300_SE_VTE_CNTL, 2);
-	ALLOC_STATE(unk2134, always, 3, 0);
-	r300->hw.unk2134.cmd[0] = cmdpacket0(R300_VAP_VF_MAX_VTX_INDX, 2);
+	ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
+	r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(R300_VAP_VF_MAX_VTX_INDX, 2);
 	ALLOC_STATE(vap_cntl_status, always, 2, 0);
 	r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1);
 	ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
@@ -315,16 +315,16 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	    cmdpacket0(R300_VAP_INPUT_ROUTE_1_0, 1);
 	ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 	r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_INPUT_CNTL_0, 2);
-	ALLOC_STATE(unk21DC, always, 2, 0);
-	r300->hw.unk21DC.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
+	ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
+	r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 
 	if (has_tcl) {
 		ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 		r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(R300_VAP_CLIP_CNTL, 1);
 		ALLOC_STATE(vap_clip, always, 5, 0);
 		r300->hw.vap_clip.cmd[0] = cmdpacket0(R300_VAP_CLIP_X_0, 4);
-		ALLOC_STATE(unk2288, always, 2, 0);
-		r300->hw.unk2288.cmd[0] = cmdpacket0(R300_VAP_UNKNOWN_2288, 1);
+		ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
+		r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(VAP_PVS_VTX_TIMEOUT_REG, 1);
 	}
 
 	ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
@@ -343,18 +343,18 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.gb_misc.cmd[0] = cmdpacket0(R300_GB_MSPOS0, 5);
 	ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 	r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(R300_TX_ENABLE, 1);
-	ALLOC_STATE(unk4200, always, 5, 0);
-	r300->hw.unk4200.cmd[0] = cmdpacket0(R300_GA_POINT_S0, 4);
-	ALLOC_STATE(unk4214, always, 2, 0);
-	r300->hw.unk4214.cmd[0] = cmdpacket0(R300_GA_TRIANGLE_STIPPLE, 1);
+	ALLOC_STATE(ga_point_s0, always, 5, 0);
+	r300->hw.ga_point_s0.cmd[0] = cmdpacket0(R300_GA_POINT_S0, 4);
+	ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
+	r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(R300_GA_TRIANGLE_STIPPLE, 1);
 	ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 	r300->hw.ps.cmd[0] = cmdpacket0(R300_GA_POINT_SIZE, 1);
-	ALLOC_STATE(unk4230, always, 4, 0);
-	r300->hw.unk4230.cmd[0] = cmdpacket0(R300_GA_POINT_MINMAX, 3);
+	ALLOC_STATE(ga_point_minmax, always, 4, 0);
+	r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(R300_GA_POINT_MINMAX, 3);
 	ALLOC_STATE(lcntl, always, 2, 0);
 	r300->hw.lcntl.cmd[0] = cmdpacket0(R300_GA_LINE_CNTL, 1);
-	ALLOC_STATE(unk4260, always, 4, 0);
-	r300->hw.unk4260.cmd[0] = cmdpacket0(R300_GA_LINE_STIPPLE_VALUE, 3);
+	ALLOC_STATE(ga_line_stipple, always, 4, 0);
+	r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(R300_GA_LINE_STIPPLE_VALUE, 3);
 	ALLOC_STATE(shade, always, 5, 0);
 	r300->hw.shade.cmd[0] = cmdpacket0(R300_GA_ENHANCE, 4);
 	ALLOC_STATE(polygon_mode, always, 4, 0);
@@ -370,25 +370,25 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(R300_RE_OCCLUSION_CNTL, 1);
 	ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 	r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(R300_RE_CULL_CNTL, 1);
-	ALLOC_STATE(unk42C0, always, 3, 0);
-	r300->hw.unk42C0.cmd[0] = cmdpacket0(R300_SU_DEPTH_SCALE, 2);
+	ALLOC_STATE(su_depth_scale, always, 3, 0);
+	r300->hw.su_depth_scale.cmd[0] = cmdpacket0(R300_SU_DEPTH_SCALE, 2);
 	ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 	r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(R300_RS_COUNT, 2);
 	ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 	r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_INTERP_0, 8);
 	ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 	r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_ROUTE_0, 1);
-	ALLOC_STATE(unk43A4, always, 3, 0);
-	r300->hw.unk43A4.cmd[0] = cmdpacket0(R300_SC_HYPERZ, 2);
-	ALLOC_STATE(unk43E8, always, 2, 0);
-	r300->hw.unk43E8.cmd[0] = cmdpacket0(R300_SC_SCREENDOOR, 1);
+	ALLOC_STATE(sc_hyperz, always, 3, 0);
+	r300->hw.sc_hyperz.cmd[0] = cmdpacket0(R300_SC_HYPERZ, 2);
+	ALLOC_STATE(sc_screendoor, always, 2, 0);
+	r300->hw.sc_screendoor.cmd[0] = cmdpacket0(R300_SC_SCREENDOOR, 1);
 	ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 	r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_PFS_CNTL_0, 3);
 	r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_PFS_NODE_0, 4);
 	ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 	r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_PFS_TEXI_0, 0);
-	ALLOC_STATE(unk46A4, always, 6, 0);
-	r300->hw.unk46A4.cmd[0] = cmdpacket0(R500_US_OUT_FMT, R500_US_OUT_FMT_C4_16);
+	ALLOC_STATE(us_out_fmt, always, 6, 0);
+	r300->hw.us_out_fmt.cmd[0] = cmdpacket0(R500_US_OUT_FMT, R500_US_OUT_FMT_C4_16);
 	ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 	r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR0_0, 1);
 	ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
@@ -403,12 +403,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(R300_FOG_COLOR_R, 3);
 	ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 	r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(R300_PP_ALPHA_TEST, 2);
-	ALLOC_STATE(unk4BD8, always, 2, 0);
-	r300->hw.unk4BD8.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
+	ALLOC_STATE(fg_depth_src, always, 2, 0);
+	r300->hw.fg_depth_src.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
 	ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 	r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
-	ALLOC_STATE(unk4E00, always, 2, 0);
-	r300->hw.unk4E00.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1);
+	ALLOC_STATE(rb3d_cctl, always, 2, 0);
+	r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1);
 	ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 	r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2);
 	ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
@@ -418,8 +418,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 	r300->hw.cb.cmd[R300_CB_CMD_0] = cmdpacket0(R300_RB3D_COLOROFFSET0, 1);
 	r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1);
-	ALLOC_STATE(unk4E50, always, 10, 0);
-	r300->hw.unk4E50.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND | R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT);
+	ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
+	r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND | R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT);
 	ALLOC_STATE(unk4E88, always, 2, 0);
 	r300->hw.unk4E88.cmd[0] = cmdpacket0(R300_RB3D_AARESOLVE_CTL, R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE);
 	ALLOC_STATE(unk4EA0, always, 3, 0);
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 795cd4d98df..17148929d08 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -453,23 +453,23 @@ struct r300_hw_state {
 	struct r300_state_atom vap_cntl;
 	struct r300_state_atom vof;	/* VAP output format register 0x2090 */
 	struct r300_state_atom vte;	/* (20B0) */
-	struct r300_state_atom unk2134;	/* (2134) */
+	struct r300_state_atom vap_vf_max_vtx_indx;	/* Maximum Vertex Indx Clamp (2134) */
 	struct r300_state_atom vap_cntl_status;
 	struct r300_state_atom vir[2];	/* vap input route (2150/21E0) */
 	struct r300_state_atom vic;	/* vap input control (2180) */
-	struct r300_state_atom unk21DC;	/* (21DC) */
+	struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 	struct r300_state_atom vap_clip_cntl;
 	struct r300_state_atom vap_clip;
-	struct r300_state_atom unk2288;	/* (2288) */
+	struct r300_state_atom vap_pvs_vtx_timeout_reg;	/* Vertex timeout register (2288) */
 	struct r300_state_atom pvs;	/* pvs_cntl (22D0) */
 	struct r300_state_atom gb_enable;	/* (4008) */
 	struct r300_state_atom gb_misc;	/* Multisampling position shifts ? (4010) */
-	struct r300_state_atom unk4200;	/* (4200) */
-	struct r300_state_atom unk4214;	/* (4214) */
+	struct r300_state_atom ga_point_s0;	/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
+	struct r300_state_atom ga_triangle_stipple;	/* (4214) */
 	struct r300_state_atom ps;	/* pointsize (421C) */
-	struct r300_state_atom unk4230;	/* (4230) */
+	struct r300_state_atom ga_point_minmax;	/* (4230) */
 	struct r300_state_atom lcntl;	/* line control */
-	struct r300_state_atom unk4260;	/* (4260) */
+	struct r300_state_atom ga_line_stipple;	/* (4260) */
 	struct r300_state_atom shade;
 	struct r300_state_atom polygon_mode;
 	struct r300_state_atom fogp;	/* fog parameters (4294) */
@@ -478,27 +478,27 @@ struct r300_hw_state {
 	struct r300_state_atom zbs;	/* zbias (42A4) */
 	struct r300_state_atom occlusion_cntl;
 	struct r300_state_atom cul;	/* cull cntl (42B8) */
-	struct r300_state_atom unk42C0;	/* (42C0) */
+	struct r300_state_atom su_depth_scale;	/* (42C0) */
 	struct r300_state_atom rc;	/* rs control (4300) */
 	struct r300_state_atom ri;	/* rs interpolators (4310) */
 	struct r300_state_atom rr;	/* rs route (4330) */
-	struct r300_state_atom unk43A4;	/* (43A4) */
-	struct r300_state_atom unk43E8;	/* (43E8) */
+	struct r300_state_atom sc_hyperz;	/* (43A4) */
+	struct r300_state_atom sc_screendoor;	/* (43E8) */
 	struct r300_state_atom fp;	/* fragment program cntl + nodes (4600) */
 	struct r300_state_atom fpt;	/* texi - (4620) */
-	struct r300_state_atom unk46A4;	/* (46A4) */
+	struct r300_state_atom us_out_fmt;	/* (46A4) */
 	struct r300_state_atom fpi[4];	/* fp instructions (46C0/47C0/48C0/49C0) */
 	struct r300_state_atom fogs;	/* fog state (4BC0) */
 	struct r300_state_atom fogc;	/* fog color (4BC8) */
 	struct r300_state_atom at;	/* alpha test (4BD4) */
-	struct r300_state_atom unk4BD8;	/* (4BD8) */
+	struct r300_state_atom fg_depth_src;	/* (4BD8) */
 	struct r300_state_atom fpp;	/* 0x4C00 and following */
-	struct r300_state_atom unk4E00;	/* (4E00) */
+	struct r300_state_atom rb3d_cctl;	/* (4E00) */
 	struct r300_state_atom bld;	/* blending (4E04) */
 	struct r300_state_atom cmk;	/* colormask (4E0C) */
 	struct r300_state_atom blend_color;	/* constant blend color */
 	struct r300_state_atom cb;	/* colorbuffer (4E28) */
-	struct r300_state_atom unk4E50;	/* (4E50) */
+	struct r300_state_atom rb3d_dither_ctl;	/* (4E50) */
 	struct r300_state_atom unk4E88;	/* (4E88) */
 	struct r300_state_atom unk4EA0;	/* (4E88) I saw it only written on RV350 hardware..  */
 	struct r300_state_atom zs;	/* zstencil control (4F00) */
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 80c2816d83d..6ceb99db50b 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -254,7 +254,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R300_INPUT_CNTL_TC6               0x00010000 /* GUESS */
 #       define R300_INPUT_CNTL_TC7               0x00020000 /* GUESS */
 
-
+/* Programmable Stream Control Signed Normalize Control */
 #define R300_VAP_PSC_SGN_NORM_CNTL         0x21dc
 #	define SGN_NORM_ZERO                 0
 #	define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1
@@ -398,8 +398,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define R300_VAP_PVS_WAITIDLE               0x2284 /* GUESS */
 
-/* Absolutely no clue what this register is about. */
-#define R300_VAP_UNKNOWN_2288               0x2288
+/* This register is used to define the number of core clocks to wait for a
+ * vertex to be received by the VAP input controller (while the primitive
+ * path is backed up) before forcing any accumulated vertices to be submitted
+ * to the vertex processing path.
+ */
+#define VAP_PVS_VTX_TIMEOUT_REG             0x2288
 #       define R300_2288_R300                    0x00750000 /* -- nh */
 #       define R300_2288_RV350                   0x0000FFFF /* -- Vladimir */
 
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 4596fbb9d24..f9ef8bd3959 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1825,8 +1825,8 @@ static void r300ResetHwState(r300ContextPtr r300)
 	    | R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT;
 	r300->hw.vte.cmd[2] = 0x00000008;
 
-	r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
-	r300->hw.unk2134.cmd[2] = 0x00000000;
+	r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF;
+	r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000;
 
 #ifdef MESA_LITTLE_ENDIAN
 	r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP;
@@ -1838,7 +1838,7 @@ static void r300ResetHwState(r300ContextPtr r300)
 	if (!has_tcl)
 		r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
 
-	r300->hw.unk21DC.cmd[1] = 0xAAAAAAAA;
+	r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
 
 	/* XXX: Other families? */
 	if (has_tcl) {
@@ -1851,10 +1851,10 @@ static void r300ResetHwState(r300ContextPtr r300)
 
 		switch (r300->radeon.radeonScreen->chip_family) {
 		case CHIP_FAMILY_R300:
-			r300->hw.unk2288.cmd[1] = R300_2288_R300;
+			r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300;
 			break;
 		default:
-			r300->hw.unk2288.cmd[1] = R300_2288_RV350;
+			r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350;
 			break;
 		}
 	}
@@ -1895,24 +1895,24 @@ static void r300ResetHwState(r300ContextPtr r300)
 	/* XXX: Enable anti-aliasing? */
 	r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = R300_AA_DISABLE;
 
-	r300->hw.unk4200.cmd[1] = r300PackFloat32(0.0);
-	r300->hw.unk4200.cmd[2] = r300PackFloat32(0.0);
-	r300->hw.unk4200.cmd[3] = r300PackFloat32(1.0);
-	r300->hw.unk4200.cmd[4] = r300PackFloat32(1.0);
+	r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0);
+	r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0);
+	r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0);
+	r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0);
 
-	r300->hw.unk4214.cmd[1] = 0x00050005;
+	r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005;
 
 	r300PointSize(ctx, 1.0);
 
-	r300->hw.unk4230.cmd[1] = 0x18000006;
-	r300->hw.unk4230.cmd[2] = 0x00020006;
-	r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0);
+	r300->hw.ga_point_minmax.cmd[1] = 0x18000006;
+	r300->hw.ga_point_minmax.cmd[2] = 0x00020006;
+	r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0);
 
 	r300LineWidth(ctx, 1.0);
 
-	r300->hw.unk4260.cmd[1] = 0;
-	r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
-	r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
+	r300->hw.ga_line_stipple.cmd[1] = 0;
+	r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0);
+	r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0);
 
 	r300ShadeModel(ctx, ctx->Light.ShadeModel);
 
@@ -1926,19 +1926,19 @@ static void r300ResetHwState(r300ContextPtr r300)
 	r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
 	r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
 
-	r300->hw.unk42C0.cmd[1] = 0x4B7FFFFF;
-	r300->hw.unk42C0.cmd[2] = 0x00000000;
+	r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF;
+	r300->hw.su_depth_scale.cmd[2] = 0x00000000;
 
-	r300->hw.unk43A4.cmd[1] = 0x0000001C;
-	r300->hw.unk43A4.cmd[2] = 0x2DA49525;
+	r300->hw.sc_hyperz.cmd[1] = 0x0000001C;
+	r300->hw.sc_hyperz.cmd[2] = 0x2DA49525;
 
-	r300->hw.unk43E8.cmd[1] = 0x00FFFFFF;
+	r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
 
-	r300->hw.unk46A4.cmd[1] = 0x00001B01;
-	r300->hw.unk46A4.cmd[2] = 0x00001B0F;
-	r300->hw.unk46A4.cmd[3] = 0x00001B0F;
-	r300->hw.unk46A4.cmd[4] = 0x00001B0F;
-	r300->hw.unk46A4.cmd[5] = 0x00000001;
+	r300->hw.us_out_fmt.cmd[1] = 0x00001B01;
+	r300->hw.us_out_fmt.cmd[2] = 0x00001B0F;
+	r300->hw.us_out_fmt.cmd[3] = 0x00001B0F;
+	r300->hw.us_out_fmt.cmd[4] = 0x00001B0F;
+	r300->hw.us_out_fmt.cmd[5] = 0x00000001;
 
 	r300Enable(ctx, GL_FOG, ctx->Fog.Enabled);
 	r300Fogfv(ctx, GL_FOG_MODE, NULL);
@@ -1948,9 +1948,9 @@ static void r300ResetHwState(r300ContextPtr r300)
 	r300Fogfv(ctx, GL_FOG_COLOR, ctx->Fog.Color);
 	r300Fogfv(ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL);
 
-	r300->hw.unk4BD8.cmd[1] = 0;
+	r300->hw.fg_depth_src.cmd[1] = 0;
 
-	r300->hw.unk4E00.cmd[1] = 0;
+	r300->hw.rb3d_cctl.cmd[1] = 0;
 
 	r300BlendColor(ctx, ctx->Color.BlendColor);
 
@@ -1968,15 +1968,15 @@ static void r300ResetHwState(r300ContextPtr r300)
 	if (r300->radeon.sarea->tiling_enabled)
 		r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_TILE_ENABLE;
 
-	r300->hw.unk4E50.cmd[1] = 0;
-	r300->hw.unk4E50.cmd[2] = 0;
-	r300->hw.unk4E50.cmd[3] = 0;
-	r300->hw.unk4E50.cmd[4] = 0;
-	r300->hw.unk4E50.cmd[5] = 0;
-	r300->hw.unk4E50.cmd[6] = 0;
-	r300->hw.unk4E50.cmd[7] = 0;
-	r300->hw.unk4E50.cmd[8] = 0;
-	r300->hw.unk4E50.cmd[9] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[1] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[2] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[3] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[4] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[5] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[6] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[7] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[8] = 0;
+	r300->hw.rb3d_dither_ctl.cmd[9] = 0;
 
 	r300->hw.unk4E88.cmd[1] = 0;