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authorEric Anholt <[email protected]>2009-12-03 17:08:32 -0800
committerEric Anholt <[email protected]>2010-02-25 10:53:06 -0800
commitc9dc6d425e645f2988118ff51cabe167a0cd3971 (patch)
tree9d86ba52f852ce0916f41bba30c8e002e3e35b81 /src/mesa/drivers
parent0da50fa67009535577dc84dde21672db5ec45134 (diff)
i965: Set up the SNB URB.
even with vs disabled, still doesn't work.
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/Makefile1
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h6
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen6_urb.c81
6 files changed, 92 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 3bf14e8a77c..35093f014b4 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -89,6 +89,7 @@ DRIVER_SOURCES = \
gen6_clip_state.c \
gen6_depthstencil.c \
gen6_gs_state.c \
+ gen6_urb.c \
gen6_vs_state.c
C_SOURCES = \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ea89d4f6fa8..c4b68ca05bc 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -544,7 +544,8 @@ struct brw_context
GLuint nr_sf_entries;
GLuint nr_cs_entries;
-/* GLuint vs_size; */
+ /* gen6 */
+ GLuint vs_size;
/* GLuint gs_size; */
/* GLuint clip_size; */
/* GLuint sf_size; */
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 52960da6827..08eb2b2d91e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -812,6 +812,12 @@
#define CMD_VF_STATISTICS_GM45 0x680b
#define CMD_3D_CC_STATE_POINTERS 0x780e /* GEN6+ */
+#define CMD_URB 0x7805 /* GEN6+ */
+# define GEN6_URB_VS_SIZE_SHIFT 16
+# define GEN6_URB_VS_ENTRIES_SHIFT 0
+# define GEN6_URB_GS_SIZE_SHIFT 8
+# define GEN6_URB_GS_ENTRIES_SHIFT 0
+
#define CMD_3D_VS_STATE 0x7810 /* GEN6+ */
/* DW2 */
# define GEN6_VS_SPF_MODE (1 << 31)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 596a9cd3a0b..11489d477c7 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -97,6 +97,7 @@ const struct brw_tracked_state gen6_clip_state;
const struct brw_tracked_state gen6_color_calc_state;
const struct brw_tracked_state gen6_depth_stencil_state;
const struct brw_tracked_state gen6_gs_state;
+const struct brw_tracked_state gen6_urb;
const struct brw_tracked_state gen6_vs_state;
/**
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index f5446ed73bc..fc30e60087b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -118,11 +118,11 @@ const struct brw_tracked_state *gen6_atoms[] =
* layout.
*/
&brw_curbe_offsets,
- &brw_recalculate_urb_fence,
&brw_cc_vp,
#endif
+ &gen6_urb,
&gen6_blend_state, /* must do before cc unit */
&gen6_color_calc_state, /* must do before cc unit */
&gen6_depth_stencil_state, /* must do before cc unit */
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
new file mode 100644
index 00000000000..dea0aa71007
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <[email protected]>
+ *
+ */
+
+#include "main/macros.h"
+#include "intel_batchbuffer.h"
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+
+static void
+prepare_urb( struct brw_context *brw )
+{
+ brw->urb.nr_vs_entries = 24;
+ if (brw->gs.prog_bo)
+ brw->urb.nr_gs_entries = 4;
+ else
+ brw->urb.nr_gs_entries = 0;
+ /* CACHE_NEW_VS_PROG */
+ brw->urb.vs_size = MIN2(brw->vs.prog_data->urb_entry_size, 1);
+
+ /* Check that the number of URB rows (8 floats each) allocated is less
+ * than the URB space.
+ */
+ assert((brw->urb.nr_vs_entries +
+ brw->urb.nr_gs_entries) * brw->urb.vs_size * 8 < 64 * 1024);
+}
+
+static void
+upload_urb(struct brw_context *brw)
+{
+ struct intel_context *intel = &brw->intel;
+
+ assert(brw->urb.nr_vs_entries % 4 == 0);
+ assert(brw->urb.nr_gs_entries % 4 == 0);
+ /* GS requirement */
+ assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
+
+ intel_batchbuffer_emit_mi_flush(intel->batch);
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(CMD_URB << 16 | (3 - 2));
+ OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
+ ((brw->urb.nr_vs_entries) << GEN6_URB_VS_SIZE_SHIFT));
+ OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
+ ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT));
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_urb = {
+ .dirty = {
+ .mesa = 0,
+ .brw = BRW_NEW_CONTEXT,
+ .cache = CACHE_NEW_VS_PROG,
+ },
+ .prepare = prepare_urb,
+ .emit = upload_urb,
+};