diff options
| author | Topi Pohjolainen <[email protected]> | 2017-01-11 10:26:32 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <[email protected]> | 2017-01-27 08:57:26 +0200 |
| commit | 56094cfb9e04b729c5b7eade7ca461651ef8906d (patch) | |
| tree | f253da751c9f388fccda8a8fa8a6cd451ee02e91 /src/mesa/drivers | |
| parent | b13d30a72ba06187ba7398c1a56c34980a021005 (diff) | |
i965/hiz/gen6: Stop setting false qpitch
which is not applicable for "all slices at each lod". Current
logic makes one to believe it has some purpose. When miptree
layout is calculated brw_miptree_layout_texture_array() sets
the qpitch unconditionally but later on ignores it altogether
for ALL_SLICES_AT_EACH_LOD.
Reviewed-by: Jason Ekstrand <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 53dac330ef6..31049b3f4ac 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1904,7 +1904,13 @@ intel_hiz_miptree_buf_create(struct brw_context *brw, buf->aux_base.bo = buf->mt->bo; buf->aux_base.size = buf->mt->total_height * buf->mt->pitch; buf->aux_base.pitch = buf->mt->pitch; - buf->aux_base.qpitch = buf->mt->qpitch; + + /* On gen6 hiz is unconditionally laid out packing all slices + * at each level-of-detail (LOD). This means there is no valid qpitch + * setting. In fact, this is ignored when hardware is setup - there is no + * hardware qpitch setting of hiz on gen6. + */ + buf->aux_base.qpitch = 0; return buf; } |