diff options
| author | Kenneth Graunke <[email protected]> | 2013-04-08 19:27:38 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-04-08 16:15:07 -0700 |
| commit | 55ecc448b9d05e9f1e5ceb88ab35606e80e3adee (patch) | |
| tree | 7410749cad96eb15825780c7ccb7a9e04c4d31e9 /src/mesa/drivers | |
| parent | 40e30c1ca1d537c286f6c88fc494846464aa3a8b (diff) | |
i965: Prefer Y-tiling on Gen6+.
In the past, we preferred X-tiling for color buffers because our BLT
code couldn't handle Y-tiling. However, the BLT paths have been largely
replaced by BLORP on Gen6+, which can handle any kind of tiling.
We hadn't measured any performance improvement in the past, but that's
probably because compressed textures were all untiled anyway.
Improves performance in GLB27_TRex_C24Z16_FixedTime by 7.69231%.
v2: Rebase on top of Eric's untiled-for-larger-than-aperture changes.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 859bcd6d831..38c0149b262 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -346,7 +346,7 @@ intel_miptree_choose_tiling(struct intel_context *intel, if (width0 >= 64) { if (ALIGN(mt->total_width * mt->cpp, 512) < 32768) - return I915_TILING_X; + return intel->gen >= 6 ? I915_TILING_Y : I915_TILING_X; perf_debug("%dx%d miptree too large to blit, falling back to untiled", mt->total_width, mt->total_height); |