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authorKenneth Graunke <[email protected]>2013-12-10 01:21:54 -0800
committerKenneth Graunke <[email protected]>2013-12-20 12:34:36 -0800
commit4e95a099373c7e3f3f5f0f2854bc4eb582724a0a (patch)
tree9a69d480f9d4c877b0a35fd159a0f651ecf0a2d3 /src/mesa/drivers
parentd10242c5f7dd5913edbd0a12bed44ecddf226ff9 (diff)
i965: Disassemble UV types, not UB types.
UB types have never been supported as immediates. On Gen4-5, register encoding 4 is "Reserved." On Gen6+, it means UV. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_disasm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index ade7e7fcc54..4c435beaa3b 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -900,8 +900,8 @@ static int imm (FILE *file, unsigned type, struct brw_instruction *inst) {
case BRW_REGISTER_TYPE_W:
format (file, "%dW", (int16_t) inst->bits3.d);
break;
- case BRW_REGISTER_TYPE_UB:
- format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
+ case BRW_REGISTER_TYPE_UV:
+ format (file, "0x%08xUV", inst->bits3.ud);
break;
case BRW_REGISTER_TYPE_VF:
format (file, "Vector Float");