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authorChristian König <[email protected]>2011-04-23 14:27:40 +0200
committerChristian König <[email protected]>2011-04-23 14:27:40 +0200
commitfa31b1095eeea97695125ad5770239805bed37da (patch)
tree6c421666719a9a1afc419de33d06f4e66584a8a1 /src/mesa/drivers
parent24d76d2966a5c666c9627034e6751621b17024c8 (diff)
parent15eaf8297ecb39337109b95480e61f37a6b20f0a (diff)
Merge remote branch 'origin/master' into pipe-video
Conflicts: configs/linux-dri src/gallium/drivers/r600/r600_pipe.c src/gallium/drivers/r600/r600_state.c src/gallium/include/pipe/p_format.h src/gallium/tests/graw/fragment-shader/frag-abs.sh src/gallium/tests/graw/fragment-shader/frag-add.sh src/gallium/tests/graw/fragment-shader/frag-cb-1d.sh src/gallium/tests/graw/fragment-shader/frag-cb-2d.sh src/gallium/tests/graw/fragment-shader/frag-dp3.sh src/gallium/tests/graw/fragment-shader/frag-dp4.sh src/gallium/tests/graw/fragment-shader/frag-dst.sh src/gallium/tests/graw/fragment-shader/frag-ex2.sh src/gallium/tests/graw/fragment-shader/frag-face.sh src/gallium/tests/graw/fragment-shader/frag-flr.sh src/gallium/tests/graw/fragment-shader/frag-frc.sh src/gallium/tests/graw/fragment-shader/frag-kil.sh src/gallium/tests/graw/fragment-shader/frag-lg2.sh src/gallium/tests/graw/fragment-shader/frag-lit.sh src/gallium/tests/graw/fragment-shader/frag-lrp.sh src/gallium/tests/graw/fragment-shader/frag-mad-immx.sh src/gallium/tests/graw/fragment-shader/frag-mad.sh src/gallium/tests/graw/fragment-shader/frag-max.sh src/gallium/tests/graw/fragment-shader/frag-min.sh src/gallium/tests/graw/fragment-shader/frag-mov.sh src/gallium/tests/graw/fragment-shader/frag-mul.sh src/gallium/tests/graw/fragment-shader/frag-rcp.sh src/gallium/tests/graw/fragment-shader/frag-rsq.sh src/gallium/tests/graw/fragment-shader/frag-sge.sh src/gallium/tests/graw/fragment-shader/frag-slt.sh src/gallium/tests/graw/fragment-shader/frag-srcmod-abs.sh src/gallium/tests/graw/fragment-shader/frag-srcmod-absneg.sh src/gallium/tests/graw/fragment-shader/frag-srcmod-neg.sh src/gallium/tests/graw/fragment-shader/frag-srcmod-swz.sh src/gallium/tests/graw/fragment-shader/frag-sub.sh src/gallium/tests/graw/fragment-shader/frag-tempx.sh src/gallium/tests/graw/fragment-shader/frag-xpd.sh src/gallium/tests/graw/vertex-shader/vert-abs.sh src/gallium/tests/graw/vertex-shader/vert-add.sh src/gallium/tests/graw/vertex-shader/vert-arl.sh src/gallium/tests/graw/vertex-shader/vert-arr.sh src/gallium/tests/graw/vertex-shader/vert-cb-1d.sh src/gallium/tests/graw/vertex-shader/vert-cb-2d.sh src/gallium/tests/graw/vertex-shader/vert-dp3.sh src/gallium/tests/graw/vertex-shader/vert-dp4.sh src/gallium/tests/graw/vertex-shader/vert-dst.sh src/gallium/tests/graw/vertex-shader/vert-ex2.sh src/gallium/tests/graw/vertex-shader/vert-flr.sh src/gallium/tests/graw/vertex-shader/vert-frc.sh src/gallium/tests/graw/vertex-shader/vert-lg2.sh src/gallium/tests/graw/vertex-shader/vert-lit.sh src/gallium/tests/graw/vertex-shader/vert-lrp.sh src/gallium/tests/graw/vertex-shader/vert-mad.sh src/gallium/tests/graw/vertex-shader/vert-max.sh src/gallium/tests/graw/vertex-shader/vert-min.sh src/gallium/tests/graw/vertex-shader/vert-mov.sh src/gallium/tests/graw/vertex-shader/vert-mul.sh src/gallium/tests/graw/vertex-shader/vert-rcp.sh src/gallium/tests/graw/vertex-shader/vert-rsq.sh src/gallium/tests/graw/vertex-shader/vert-sge.sh src/gallium/tests/graw/vertex-shader/vert-slt.sh src/gallium/tests/graw/vertex-shader/vert-srcmod-abs.sh src/gallium/tests/graw/vertex-shader/vert-srcmod-absneg.sh src/gallium/tests/graw/vertex-shader/vert-srcmod-neg.sh src/gallium/tests/graw/vertex-shader/vert-srcmod-swz.sh src/gallium/tests/graw/vertex-shader/vert-sub.sh src/gallium/tests/graw/vertex-shader/vert-xpd.sh src/gallium/tools/trace/dump.py src/gallium/tools/trace/format.py src/gallium/tools/trace/model.py src/gallium/tools/trace/parse.py
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/SConscript6
-rw-r--r--src/mesa/drivers/common/meta.c74
-rw-r--r--src/mesa/drivers/dri/common/spantmp2.h122
-rw-r--r--src/mesa/drivers/dri/common/texmem.c7
-rw-r--r--src/mesa/drivers/dri/common/utils.c5
-rw-r--r--src/mesa/drivers/dri/common/utils.h2
-rw-r--r--src/mesa/drivers/dri/common/xmlconfig.c20
-rw-r--r--src/mesa/drivers/dri/i810/i810context.c4
-rw-r--r--src/mesa/drivers/dri/i810/i810tex.c12
-rw-r--r--src/mesa/drivers/dri/i915/i830_texstate.c24
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.c8
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.h15
-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c11
-rw-r--r--src/mesa/drivers/dri/i915/i915_state.c171
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c38
-rw-r--r--src/mesa/drivers/dri/i915/i915_vtbl.c13
-rw-r--r--src/mesa/drivers/dri/i965/brw_cc.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c18
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h36
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h12
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c65
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.c27
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c120
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp572
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h32
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp8
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs.c52
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs.h5
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs_emit.c32
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf_state.c273
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_dump.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_structs.h44
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs.c6
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_emit.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_vtbl.c10
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.c27
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_emit.c6
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_sampler_state.c34
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_state.c20
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c41
-rw-r--r--src/mesa/drivers/dri/i965/gen6_cc.c8
-rw-r--r--src/mesa/drivers/dri/i965/gen6_gs_state.c48
-rw-r--r--src/mesa/drivers/dri/i965/gen6_urb.c34
-rw-r--r--src/mesa/drivers/dri/i965/gen6_vs_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen6_wm_state.c9
-rw-r--r--src/mesa/drivers/dri/intel/intel_batchbuffer.c4
-rw-r--r--src/mesa/drivers/dri/intel/intel_blit.c59
-rw-r--r--src/mesa/drivers/dri/intel/intel_chipset.h15
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c22
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h30
-rw-r--r--src/mesa/drivers/dri/intel/intel_extensions.c4
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c82
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_format.c11
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_image.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_subimage.c16
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_validate.c2
-rw-r--r--src/mesa/drivers/dri/mach64/mach64_dd.c5
-rw-r--r--src/mesa/drivers/dri/mach64/mach64_tex.c12
-rw-r--r--src/mesa/drivers/dri/mga/mgadd.c4
-rw-r--r--src/mesa/drivers/dri/mga/mgatex.c12
-rw-r--r--src/mesa/drivers/dri/nouveau/nouveau_driver.c2
-rw-r--r--src/mesa/drivers/dri/nouveau/nouveau_driver.h1
-rw-r--r--src/mesa/drivers/dri/nouveau/nouveau_texture.c4
-rw-r--r--src/mesa/drivers/dri/nouveau/nv04_state_tex.c20
-rw-r--r--src/mesa/drivers/dri/nouveau/nv10_state_tex.c20
-rw-r--r--src/mesa/drivers/dri/nouveau/nv20_state_tex.c22
-rw-r--r--src/mesa/drivers/dri/r128/r128_dd.c6
-rw-r--r--src/mesa/drivers/dri/r128/r128_span.c4
-rw-r--r--src/mesa/drivers/dri/r128/r128_tex.c12
-rw-r--r--src/mesa/drivers/dri/r200/r200_context.c17
-rw-r--r--src/mesa/drivers/dri/r200/r200_tex.c18
-rw-r--r--src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c4
-rw-r--r--src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c18
-rw-r--r--src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c12
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_code.h12
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_compiler.c4
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c7
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c7
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h3
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_optimize.c24
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c3
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h2
-rw-r--r--src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c81
-rw-r--r--src/mesa/drivers/dri/r300/r300_context.c1
-rw-r--r--src/mesa/drivers/dri/r300/r300_fragprog_common.c4
-rw-r--r--src/mesa/drivers/dri/r300/r300_reg.h2
-rw-r--r--src/mesa/drivers/dri/r300/r300_state.c4
-rw-r--r--src/mesa/drivers/dri/r300/r300_tex.c18
-rw-r--r--src/mesa/drivers/dri/r300/r300_texstate.c2
-rw-r--r--src/mesa/drivers/dri/r600/defaultendian.h4
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_blit.c114
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_blit_shaders.h8
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_chip.c14
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_oglprog.c6
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_render.c20
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_tex.c173
-rw-r--r--src/mesa/drivers/dri/r600/evergreen_vertprog.c12
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.c117
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit_shaders.h4
-rw-r--r--src/mesa/drivers/dri/r600/r600_context.c1
-rw-r--r--src/mesa/drivers/dri/r600/r600_emit.c16
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.c16
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c161
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c13
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.h133
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c11
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c21
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_chipset.h2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common_context.c5
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_debug.h16
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c6
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_span.c93
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_tex.c18
-rw-r--r--src/mesa/drivers/dri/savage/savagedd.c4
-rw-r--r--src/mesa/drivers/dri/savage/savagerender.c12
-rw-r--r--src/mesa/drivers/dri/savage/savagetex.c12
-rw-r--r--src/mesa/drivers/dri/sis/sis_dd.c4
-rw-r--r--src/mesa/drivers/dri/sis/sis_texstate.c22
-rw-r--r--src/mesa/drivers/dri/tdfx/tdfx_dd.c5
-rw-r--r--src/mesa/drivers/dri/tdfx/tdfx_tex.c8
-rw-r--r--src/mesa/drivers/dri/unichrome/via_context.c4
-rw-r--r--src/mesa/drivers/dri/unichrome/via_state.c32
-rw-r--r--src/mesa/drivers/dri/unichrome/via_tex.c6
-rw-r--r--src/mesa/drivers/osmesa/SConscript36
-rw-r--r--src/mesa/drivers/osmesa/osmesa.c17
-rw-r--r--src/mesa/drivers/windows/gdi/SConscript38
-rw-r--r--src/mesa/drivers/windows/gdi/mesa.def107
-rw-r--r--src/mesa/drivers/windows/gdi/wgl.c4
-rw-r--r--src/mesa/drivers/windows/gdi/wmesa.c11
-rw-r--r--src/mesa/drivers/windows/gdi/wmesadef.h2
141 files changed, 2328 insertions, 1737 deletions
diff --git a/src/mesa/drivers/SConscript b/src/mesa/drivers/SConscript
new file mode 100644
index 00000000000..ab0f8943290
--- /dev/null
+++ b/src/mesa/drivers/SConscript
@@ -0,0 +1,6 @@
+Import('*')
+
+SConscript('osmesa/SConscript')
+
+if env['platform'] == 'windows':
+ SConscript('windows/gdi/SConscript')
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 2b00e8979d2..6c35fa10d8a 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -92,6 +92,8 @@
#define META_TEXTURE 0x1000
#define META_VERTEX 0x2000
#define META_VIEWPORT 0x4000
+#define META_CLAMP_FRAGMENT_COLOR 0x8000
+#define META_CLAMP_VERTEX_COLOR 0x10000
/*@}*/
@@ -180,6 +182,12 @@ struct save_state
GLint ViewportX, ViewportY, ViewportW, ViewportH;
GLclampd DepthNear, DepthFar;
+ /** META_CLAMP_FRAGMENT_COLOR */
+ GLenum ClampFragmentColor;
+
+ /** META_CLAMP_VERTEX_COLOR */
+ GLenum ClampVertexColor;
+
/** Miscellaneous (always disabled) */
GLboolean Lighting;
};
@@ -569,6 +577,26 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
_mesa_DepthRange(0.0, 1.0);
}
+ if (state & META_CLAMP_FRAGMENT_COLOR) {
+ save->ClampFragmentColor = ctx->Color.ClampFragmentColor;
+
+ /* Generally in here we want to do clamping according to whether
+ * it's for the pixel path (ClampFragmentColor is GL_TRUE),
+ * regardless of the internal implementation of the metaops.
+ */
+ if (ctx->Color.ClampFragmentColor != GL_TRUE)
+ _mesa_ClampColorARB(GL_CLAMP_FRAGMENT_COLOR, GL_FALSE);
+ }
+
+ if (state & META_CLAMP_VERTEX_COLOR) {
+ save->ClampVertexColor = ctx->Light.ClampVertexColor;
+
+ /* Generally in here we never want vertex color clamping --
+ * result clamping is only dependent on fragment clamping.
+ */
+ _mesa_ClampColorARB(GL_CLAMP_VERTEX_COLOR, GL_FALSE);
+ }
+
/* misc */
{
save->Lighting = ctx->Light.Enabled;
@@ -833,6 +861,14 @@ _mesa_meta_end(struct gl_context *ctx)
_mesa_DepthRange(save->DepthNear, save->DepthFar);
}
+ if (state & META_CLAMP_FRAGMENT_COLOR) {
+ _mesa_ClampColorARB(GL_CLAMP_FRAGMENT_COLOR, save->ClampFragmentColor);
+ }
+
+ if (state & META_CLAMP_VERTEX_COLOR) {
+ _mesa_ClampColorARB(GL_CLAMP_VERTEX_COLOR, save->ClampVertexColor);
+ }
+
/* misc */
if (save->Lighting) {
_mesa_set_enable(ctx, GL_LIGHTING, GL_TRUE);
@@ -1124,12 +1160,12 @@ blitframebuffer_texture(struct gl_context *ctx,
if (readAtt && readAtt->Texture) {
const struct gl_texture_object *texObj = readAtt->Texture;
const GLuint srcLevel = readAtt->TextureLevel;
- const GLenum minFilterSave = texObj->MinFilter;
- const GLenum magFilterSave = texObj->MagFilter;
+ const GLenum minFilterSave = texObj->Sampler.MinFilter;
+ const GLenum magFilterSave = texObj->Sampler.MagFilter;
const GLint baseLevelSave = texObj->BaseLevel;
const GLint maxLevelSave = texObj->MaxLevel;
- const GLenum wrapSSave = texObj->WrapS;
- const GLenum wrapTSave = texObj->WrapT;
+ const GLenum wrapSSave = texObj->Sampler.WrapS;
+ const GLenum wrapTSave = texObj->Sampler.WrapT;
const GLenum target = texObj->Target;
if (drawAtt->Texture == readAtt->Texture) {
@@ -1441,6 +1477,9 @@ _mesa_meta_Clear(struct gl_context *ctx, GLbitfield buffers)
/* GL_COLOR_BUFFER_BIT */
if (buffers & BUFFER_BITS_COLOR) {
/* leave colormask, glDrawBuffer state as-is */
+
+ /* Clears never have the color clamped. */
+ _mesa_ClampColorARB(GL_CLAMP_FRAGMENT_COLOR, GL_FALSE);
}
else {
ASSERT(metaSave & META_COLOR_MASK);
@@ -1494,10 +1533,10 @@ _mesa_meta_Clear(struct gl_context *ctx, GLbitfield buffers)
/* vertex colors */
for (i = 0; i < 4; i++) {
- verts[i].r = ctx->Color.ClearColor[0];
- verts[i].g = ctx->Color.ClearColor[1];
- verts[i].b = ctx->Color.ClearColor[2];
- verts[i].a = ctx->Color.ClearColor[3];
+ verts[i].r = ctx->Color.ClearColorUnclamped[0];
+ verts[i].g = ctx->Color.ClearColorUnclamped[1];
+ verts[i].b = ctx->Color.ClearColorUnclamped[2];
+ verts[i].a = ctx->Color.ClearColorUnclamped[3];
}
/* upload new vertex data */
@@ -1803,6 +1842,14 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
texIntFormat = format;
else
texIntFormat = GL_RGBA;
+
+ /* If we're not supposed to clamp the resulting color, then just
+ * promote our texture to fully float. We could do better by
+ * just going for the matching set of channels, in floating
+ * point.
+ */
+ if (ctx->Color.ClampFragmentColor != GL_TRUE)
+ texIntFormat = GL_RGBA32F;
}
else if (_mesa_is_stencil_format(format)) {
if (ctx->Extensions.ARB_fragment_program &&
@@ -1861,6 +1908,7 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
META_TRANSFORM |
META_VERTEX |
META_VIEWPORT |
+ META_CLAMP_FRAGMENT_COLOR |
metaExtraSave));
newTex = alloc_texture(tex, width, height, texIntFormat);
@@ -2259,13 +2307,13 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
struct vertex verts[4];
const GLuint baseLevel = texObj->BaseLevel;
const GLuint maxLevel = texObj->MaxLevel;
- const GLenum minFilterSave = texObj->MinFilter;
- const GLenum magFilterSave = texObj->MagFilter;
+ const GLenum minFilterSave = texObj->Sampler.MinFilter;
+ const GLenum magFilterSave = texObj->Sampler.MagFilter;
const GLint maxLevelSave = texObj->MaxLevel;
const GLboolean genMipmapSave = texObj->GenerateMipmap;
- const GLenum wrapSSave = texObj->WrapS;
- const GLenum wrapTSave = texObj->WrapT;
- const GLenum wrapRSave = texObj->WrapR;
+ const GLenum wrapSSave = texObj->Sampler.WrapS;
+ const GLenum wrapTSave = texObj->Sampler.WrapT;
+ const GLenum wrapRSave = texObj->Sampler.WrapR;
const GLuint fboSave = ctx->DrawBuffer->Name;
const GLuint original_active_unit = ctx->Texture.CurrentUnit;
GLenum faceTarget;
diff --git a/src/mesa/drivers/dri/common/spantmp2.h b/src/mesa/drivers/dri/common/spantmp2.h
index f436d1398c2..abd79562f98 100644
--- a/src/mesa/drivers/dri/common/spantmp2.h
+++ b/src/mesa/drivers/dri/common/spantmp2.h
@@ -48,15 +48,6 @@
#define HW_WRITE_CLIPLOOP() HW_CLIPLOOP()
#endif
-#ifdef SPANTMP_MESA_FMT
-#define SPANTMP_PIXEL_FMT GL_NONE
-#define SPANTMP_PIXEL_TYPE GL_NONE
-#endif
-
-#ifndef SPANTMP_MESA_FMT
-#define SPANTMP_MESA_FMT MESA_FORMAT_COUNT
-#endif
-
#if (SPANTMP_PIXEL_FMT == GL_RGB) && (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_SHORT_5_6_5)
/**
@@ -454,118 +445,6 @@
rgba[3] = p; \
} while (0)
-#elif (SPANTMP_MESA_FMT == MESA_FORMAT_R8)
-
-#ifndef GET_VALUE
-#ifndef GET_PTR
-#define GET_PTR(_x, _y) ( buf + (_x) + (_y) * pitch)
-#endif
-
-#define GET_VALUE(_x, _y) *(volatile GLubyte *)(GET_PTR(_x, _y))
-#define PUT_VALUE(_x, _y, _v) *(volatile GLubyte *)(GET_PTR(_x, _y)) = (_v)
-#endif /* GET_VALUE */
-
-# define INIT_MONO_PIXEL(p, color) \
- p = color[0]
-
-# define WRITE_RGBA(_x, _y, r, g, b, a) \
- PUT_VALUE(_x, _y, r)
-
-#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
-
-#define READ_RGBA( rgba, _x, _y ) \
- do { \
- GLubyte p = GET_VALUE(_x, _y); \
- rgba[0] = p; \
- rgba[1] = 0; \
- rgba[2] = 0; \
- rgba[3] = 0; \
- } while (0)
-
-#elif (SPANTMP_MESA_FMT == MESA_FORMAT_RG88)
-
-#ifndef GET_VALUE
-#ifndef GET_PTR
-#define GET_PTR(_x, _y) ( buf + (_x) * 2 + (_y) * pitch)
-#endif
-
-#define GET_VALUE(_x, _y) *(volatile GLushort *)(GET_PTR(_x, _y))
-#define PUT_VALUE(_x, _y, _v) *(volatile GLushort *)(GET_PTR(_x, _y)) = (_v)
-#endif /* GET_VALUE */
-
-# define INIT_MONO_PIXEL(p, color) \
- PACK_COLOR_8888(color[0], color[1], 0, 0)
-
-# define WRITE_RGBA(_x, _y, r, g, b, a) \
- PUT_VALUE(_x, _y, r)
-
-#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
-
-#define READ_RGBA( rgba, _x, _y ) \
- do { \
- GLushort p = GET_VALUE(_x, _y); \
- rgba[0] = p & 0xff; \
- rgba[1] = (p >> 8) & 0xff; \
- rgba[2] = 0; \
- rgba[3] = 0; \
- } while (0)
-
-#elif (SPANTMP_MESA_FMT == MESA_FORMAT_R16)
-
-#ifndef GET_VALUE
-#ifndef GET_PTR
-#define GET_PTR(_x, _y) ( buf + (_x) * 2 + (_y) * pitch)
-#endif
-
-#define GET_VALUE(_x, _y) *(volatile GLushort *)(GET_PTR(_x, _y))
-#define PUT_VALUE(_x, _y, _v) *(volatile GLushort *)(GET_PTR(_x, _y)) = (_v)
-#endif /* GET_VALUE */
-
-# define INIT_MONO_PIXEL(p, color) \
- p = color[0]
-
-# define WRITE_RGBA(_x, _y, r, g, b, a) \
- PUT_VALUE(_x, _y, r)
-
-#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
-
-#define READ_RGBA( rgba, _x, _y ) \
- do { \
- GLushort p = GET_VALUE(_x, _y); \
- rgba[0] = p; \
- rgba[1] = 0; \
- rgba[2] = 0; \
- rgba[3] = 0; \
- } while (0)
-
-#elif (SPANTMP_MESA_FMT == MESA_FORMAT_RG1616)
-
-#ifndef GET_VALUE
-#ifndef GET_PTR
-#define GET_PTR(_x, _y) ( buf + (_x) * 4 + (_y) * pitch)
-#endif
-
-#define GET_VALUE(_x, _y) *(volatile GLuint *)(GET_PTR(_x, _y))
-#define PUT_VALUE(_x, _y, _v) *(volatile GLuint *)(GET_PTR(_x, _y)) = (_v)
-#endif /* GET_VALUE */
-
-# define INIT_MONO_PIXEL(p, color) \
- ((color[1] << 16) | (color[0]))
-
-# define WRITE_RGBA(_x, _y, r, g, b, a) \
- PUT_VALUE(_x, _y, r)
-
-#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
-
-#define READ_RGBA( rgba, _x, _y ) \
- do { \
- GLuint p = GET_VALUE(_x, _y); \
- rgba[0] = p & 0xffff; \
- rgba[1] = (p >> 16) & 0xffff; \
- rgba[2] = 0; \
- rgba[3] = 0; \
- } while (0)
-
#else
#error SPANTMP_PIXEL_FMT must be set to a valid value!
#endif
@@ -1035,4 +914,3 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
#undef GET_PTR
#undef SPANTMP_PIXEL_FMT
#undef SPANTMP_PIXEL_TYPE
-#undef SPANTMP_MESA_FMT
diff --git a/src/mesa/drivers/dri/common/texmem.c b/src/mesa/drivers/dri/common/texmem.c
index 8eec07d5bcc..e927cf0addd 100644
--- a/src/mesa/drivers/dri/common/texmem.c
+++ b/src/mesa/drivers/dri/common/texmem.c
@@ -1264,17 +1264,18 @@ driCalculateTextureFirstLastLevel( driTextureObject * t )
case GL_TEXTURE_2D:
case GL_TEXTURE_3D:
case GL_TEXTURE_CUBE_MAP:
- if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
+ if (tObj->Sampler.MinFilter == GL_NEAREST ||
+ tObj->Sampler.MinFilter == GL_LINEAR) {
/* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
*/
firstLevel = lastLevel = tObj->BaseLevel;
}
else {
- firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5);
+ firstLevel = tObj->BaseLevel + (GLint)(tObj->Sampler.MinLod + 0.5);
firstLevel = MAX2(firstLevel, tObj->BaseLevel);
firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2);
- lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
+ lastLevel = tObj->BaseLevel + (GLint)(tObj->Sampler.MaxLod + 0.5);
lastLevel = MAX2(lastLevel, t->tObj->BaseLevel);
lastLevel = MIN2(lastLevel, t->tObj->BaseLevel + baseImage->MaxLog2);
lastLevel = MIN2(lastLevel, t->tObj->MaxLevel);
diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c
index 083edfaa9b4..d8281838233 100644
--- a/src/mesa/drivers/dri/common/utils.c
+++ b/src/mesa/drivers/dri/common/utils.c
@@ -96,7 +96,6 @@ driParseDebugString( const char * debug,
*
* \param buffer Buffer to hold the \c GL_RENDERER string.
* \param hardware_name Name of the hardware.
- * \param driver_date Driver date.
* \param agp_mode AGP mode (speed).
*
* \returns
@@ -105,12 +104,12 @@ driParseDebugString( const char * debug,
*/
unsigned
driGetRendererString( char * buffer, const char * hardware_name,
- const char * driver_date, GLuint agp_mode )
+ GLuint agp_mode )
{
unsigned offset;
char *cpu;
- offset = sprintf( buffer, "Mesa DRI %s %s", hardware_name, driver_date );
+ offset = sprintf( buffer, "Mesa DRI %s", hardware_name );
/* Append any AGP-specific information.
*/
diff --git a/src/mesa/drivers/dri/common/utils.h b/src/mesa/drivers/dri/common/utils.h
index 6349fb4b95c..a1c9ea604ee 100644
--- a/src/mesa/drivers/dri/common/utils.h
+++ b/src/mesa/drivers/dri/common/utils.h
@@ -76,7 +76,7 @@ extern unsigned driParseDebugString( const char * debug,
const struct dri_debug_control * control );
extern unsigned driGetRendererString( char * buffer,
- const char * hardware_name, const char * driver_date, GLuint agp_mode );
+ const char * hardware_name, GLuint agp_mode );
extern void driInitExtensions( struct gl_context * ctx,
const struct dri_extension * card_extensions, GLboolean enable_imaging );
diff --git a/src/mesa/drivers/dri/common/xmlconfig.c b/src/mesa/drivers/dri/common/xmlconfig.c
index 0312c072437..0226b38c4fc 100644
--- a/src/mesa/drivers/dri/common/xmlconfig.c
+++ b/src/mesa/drivers/dri/common/xmlconfig.c
@@ -64,7 +64,25 @@ extern char *program_invocation_name, *program_invocation_short_name;
the basename to match BSD getprogname() */
# include <stdlib.h>
# include <libgen.h>
-# define GET_PROGRAM_NAME() basename(getexecname())
+
+static const char *__getProgramName () {
+ static const char *progname;
+
+ if (progname == NULL) {
+ const char *e = getexecname();
+ if (e != NULL) {
+ /* Have to make a copy since getexecname can return a readonly
+ string, but basename expects to be able to modify its arg. */
+ char *n = strdup(e);
+ if (n != NULL) {
+ progname = basename(n);
+ }
+ }
+ }
+ return progname;
+}
+
+# define GET_PROGRAM_NAME() __getProgramName()
#endif
#if !defined(GET_PROGRAM_NAME)
diff --git a/src/mesa/drivers/dri/i810/i810context.c b/src/mesa/drivers/dri/i810/i810context.c
index 90dbb6bbe80..604b1e36f97 100644
--- a/src/mesa/drivers/dri/i810/i810context.c
+++ b/src/mesa/drivers/dri/i810/i810context.c
@@ -67,8 +67,6 @@ int I810_DEBUG = (0);
PUBLIC const char __driConfigOptions[] = { 0 };
const GLuint __driNConfigOptions = 0;
-#define DRIVER_DATE "20050821"
-
static const GLubyte *i810GetString( struct gl_context *ctx, GLenum name )
{
static char buffer[128];
@@ -88,7 +86,7 @@ static const GLubyte *i810GetString( struct gl_context *ctx, GLenum name )
default: chipset = "Unknown i810-class Chipset"; break;
}
- (void) driGetRendererString( buffer, chipset, DRIVER_DATE, 0 );
+ (void) driGetRendererString( buffer, chipset, 0 );
return (GLubyte *) buffer;
}
default:
diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c
index 49364aeb225..dba4ebaa5c7 100644
--- a/src/mesa/drivers/dri/i810/i810tex.c
+++ b/src/mesa/drivers/dri/i810/i810tex.c
@@ -204,10 +204,10 @@ i810AllocTexObj( struct gl_context *ctx, struct gl_texture_object *texObj )
make_empty_list( & t->base );
- i810SetTexWrapping( t, texObj->WrapS, texObj->WrapT );
+ i810SetTexWrapping( t, texObj->Sampler.WrapS, texObj->Sampler.WrapT );
/*i830SetTexMaxAnisotropy( t, texObj->MaxAnisotropy );*/
- i810SetTexFilter( imesa, t, texObj->MinFilter, texObj->MagFilter, bias );
- i810SetTexBorderColor( t, texObj->BorderColor.f );
+ i810SetTexFilter( imesa, t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, bias );
+ i810SetTexBorderColor( t, texObj->Sampler.BorderColor.f );
}
return t;
@@ -238,17 +238,17 @@ static void i810TexParameter( struct gl_context *ctx, GLenum target,
case GL_TEXTURE_MAG_FILTER:
{
GLfloat bias = ctx->Texture.Unit[ctx->Texture.CurrentUnit].LodBias;
- i810SetTexFilter( imesa, t, tObj->MinFilter, tObj->MagFilter, bias );
+ i810SetTexFilter( imesa, t, tObj->Sampler.MinFilter, tObj->Sampler.MagFilter, bias );
}
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
- i810SetTexWrapping( t, tObj->WrapS, tObj->WrapT );
+ i810SetTexWrapping( t, tObj->Sampler.WrapS, tObj->Sampler.WrapT );
break;
case GL_TEXTURE_BORDER_COLOR:
- i810SetTexBorderColor( t, tObj->BorderColor.f );
+ i810SetTexBorderColor( t, tObj->Sampler.BorderColor.f );
break;
case GL_TEXTURE_BASE_LEVEL:
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index c35b4b5ed06..7554bd5e7b9 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -193,7 +193,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
float maxlod;
uint32_t minlod_fixed, maxlod_fixed;
- switch (tObj->MinFilter) {
+ switch (tObj->Sampler.MinFilter) {
case GL_NEAREST:
minFilt = FILTER_NEAREST;
mipFilt = MIPFILTER_NONE;
@@ -222,12 +222,12 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
return GL_FALSE;
}
- if (tObj->MaxAnisotropy > 1.0) {
+ if (tObj->Sampler.MaxAnisotropy > 1.0) {
minFilt = FILTER_ANISOTROPIC;
magFilt = FILTER_ANISOTROPIC;
}
else {
- switch (tObj->MagFilter) {
+ switch (tObj->Sampler.MagFilter) {
case GL_NEAREST:
magFilt = FILTER_NEAREST;
break;
@@ -239,7 +239,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
}
- lodbias = (int) ((tUnit->LodBias + tObj->LodBias) * 16.0);
+ lodbias = (int) ((tUnit->LodBias + tObj->Sampler.LodBias) * 16.0);
if (lodbias < -64)
lodbias = -64;
if (lodbias > 63)
@@ -259,8 +259,8 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
* addressable (smallest resolution) LOD. Use it to cover both
* MAX_LEVEL and MAX_LOD.
*/
- minlod_fixed = U_FIXED(CLAMP(tObj->MinLod, 0.0, 11), 4);
- maxlod = MIN2(tObj->MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
+ minlod_fixed = U_FIXED(CLAMP(tObj->Sampler.MinLod, 0.0, 11), 4);
+ maxlod = MIN2(tObj->Sampler.MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
if (intel->intelScreen->deviceID == PCI_CHIP_I855_GM ||
intel->intelScreen->deviceID == PCI_CHIP_I865_G) {
maxlod_fixed = U_FIXED(CLAMP(maxlod, 0.0, 11.75), 2);
@@ -279,8 +279,8 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
{
- GLenum ws = tObj->WrapS;
- GLenum wt = tObj->WrapT;
+ GLenum ws = tObj->Sampler.WrapS;
+ GLenum wt = tObj->Sampler.WrapT;
/* 3D textures not available on i830
@@ -300,10 +300,10 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->Sampler.BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->Sampler.BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->Sampler.BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->Sampler.BorderColor.f[3]);
state[I830_TEXREG_TM0S4] = PACK_COLOR_8888(border[3],
border[0],
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 7389a1d57a9..f02f2d78267 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -69,8 +69,6 @@ i915InvalidateState(struct gl_context * ctx, GLuint new_state)
p->params_uptodate = 0;
}
- if (new_state & (_NEW_FOG | _NEW_HINT | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS))
- i915_update_fog(ctx);
if (new_state & (_NEW_STENCIL | _NEW_BUFFERS | _NEW_POLYGON))
i915_update_stencil(ctx);
if (new_state & (_NEW_LIGHT))
@@ -209,5 +207,11 @@ i915CreateContext(int api,
i915InitState(i915);
+ /* Always enable pixel fog. Vertex fog using fog coord will conflict
+ * with fog code appended onto fragment program.
+ */
+ _tnl_allow_vertex_fog(ctx, 0);
+ _tnl_allow_pixel_fog(ctx, 1);
+
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h
index 601620275f4..577a01e290c 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -46,7 +46,6 @@
#define I915_UPLOAD_STIPPLE 0x4
#define I915_UPLOAD_PROGRAM 0x8
#define I915_UPLOAD_CONSTANTS 0x10
-#define I915_UPLOAD_FOG 0x20
#define I915_UPLOAD_INVARIENT 0x40
#define I915_UPLOAD_DEFAULTS 0x80
#define I915_UPLOAD_RASTER_RULES 0x100
@@ -91,13 +90,6 @@
#define I915_BLENDREG_BLENDCOLOR1 2
#define I915_BLEND_SETUP_SIZE 3
-#define I915_FOGREG_COLOR 0
-#define I915_FOGREG_MODE0 1
-#define I915_FOGREG_MODE1 2
-#define I915_FOGREG_MODE2 3
-#define I915_FOGREG_MODE3 4
-#define I915_FOG_SETUP_SIZE 5
-
#define I915_STPREG_ST0 0
#define I915_STPREG_ST1 1
#define I915_STP_SETUP_SIZE 2
@@ -227,7 +219,6 @@ struct i915_hw_state
GLuint Blend[I915_BLEND_SETUP_SIZE];
GLuint Buffer[I915_DEST_SETUP_SIZE];
GLuint Stipple[I915_STP_SETUP_SIZE];
- GLuint Fog[I915_FOG_SETUP_SIZE];
GLuint Defaults[I915_DEF_SETUP_SIZE];
GLuint RasterRules[I915_RASTER_RULES_SETUP_SIZE];
GLuint Tex[I915_TEX_UNITS][I915_TEX_SETUP_SIZE];
@@ -254,16 +245,11 @@ struct i915_hw_state
GLuint emitted; /* I915_UPLOAD_* */
};
-#define I915_FOG_PIXEL 2
-#define I915_FOG_VERTEX 1
-#define I915_FOG_NONE 0
-
struct i915_context
{
struct intel_context intel;
GLuint last_ReallyEnabled;
- GLuint vertex_fog;
GLuint lodbias_ss2[MAX_TEXTURE_UNITS];
@@ -350,7 +336,6 @@ extern void i915_print_ureg(const char *msg, GLuint ureg);
*/
extern void i915InitStateFunctions(struct dd_function_table *functions);
extern void i915InitState(struct i915_context *i915);
-extern void i915_update_fog(struct gl_context * ctx);
extern void i915_update_stencil(struct gl_context * ctx);
extern void i915_update_provoking_vertex(struct gl_context *ctx);
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 2bfe665cb65..b67ebb9a1ec 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1285,15 +1285,6 @@ i915ProgramStringNotify(struct gl_context * ctx,
if (target == GL_FRAGMENT_PROGRAM_ARB) {
struct i915_fragment_program *p = (struct i915_fragment_program *) prog;
p->translated = 0;
-
- /* Hack: make sure fog is correctly enabled according to this
- * fragment program's fog options.
- */
- if (p->FragProg.FogOption) {
- /* add extra instructions to do fog, then turn off FogOption field */
- _mesa_append_fog_code(ctx, &p->FragProg);
- p->FragProg.FogOption = GL_NONE;
- }
}
(void) _tnl_program_string(ctx, target, prog);
@@ -1371,7 +1362,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_4UB_4F_BGRA, S4_VFMT_SPEC_FOG, 4);
}
- if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE) {
+ if ((inputsRead & FRAG_BIT_FOGC)) {
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4);
}
diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c
index 3b1af4c455e..99212ad4fd1 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -724,157 +724,17 @@ i915ShadeModel(struct gl_context * ctx, GLenum mode)
/* =============================================================
* Fog
+ *
+ * This empty function remains because _mesa_init_driver_state calls
+ * dd_function_table::Fogfv unconditionally. We have to have some function
+ * there so that it doesn't try to call a NULL pointer.
*/
-void
-i915_update_fog(struct gl_context * ctx)
-{
- struct i915_context *i915 = I915_CONTEXT(ctx);
- GLenum mode;
- GLboolean enabled;
- GLboolean try_pixel_fog;
- GLuint dw;
-
- if (ctx->FragmentProgram._Current) {
- /* Pull in static fog state from program */
- mode = ctx->FragmentProgram._Current->FogOption;
- enabled = (mode != GL_NONE);
- try_pixel_fog = 0;
- }
- else {
- enabled = ctx->Fog.Enabled;
- mode = ctx->Fog.Mode;
-#if 0
- /* XXX - DISABLED -- Need ortho fallback */
- try_pixel_fog = (ctx->Fog.FogCoordinateSource == GL_FRAGMENT_DEPTH_EXT
- && ctx->Hint.Fog == GL_NICEST);
-#else
- try_pixel_fog = 0;
-#endif
- }
-
- if (!enabled) {
- i915->vertex_fog = I915_FOG_NONE;
- }
- else if (try_pixel_fog) {
- I915_STATECHANGE(i915, I915_UPLOAD_FOG);
- i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_FOGFUNC_MASK;
- i915->vertex_fog = I915_FOG_PIXEL;
-
- switch (mode) {
- case GL_LINEAR:
- if (ctx->Fog.End <= ctx->Fog.Start) {
- /* XXX - this won't work with fragment programs. Need to
- * either fallback or append fog instructions to end of
- * program in the case of linear fog.
- */
- printf("vertex fog!\n");
- i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_VERTEX;
- i915->vertex_fog = I915_FOG_VERTEX;
- }
- else {
- GLfloat c2 = 1.0 / (ctx->Fog.End - ctx->Fog.Start);
- GLfloat c1 = ctx->Fog.End * c2;
-
- i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_C1_MASK;
- i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_LINEAR;
- i915->state.Fog[I915_FOGREG_MODE1] |=
- ((GLuint) (c1 * FMC1_C1_ONE)) & FMC1_C1_MASK;
-
- if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) {
- i915->state.Fog[I915_FOGREG_MODE2]
- = (GLuint) (c2 * FMC2_C2_ONE);
- }
- else {
- fi_type fi;
- fi.f = c2;
- i915->state.Fog[I915_FOGREG_MODE2] = fi.i;
- }
- }
- break;
- case GL_EXP:
- i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_EXP;
- break;
- case GL_EXP2:
- i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_EXP2;
- break;
- default:
- break;
- }
- }
- else { /* if (i915->vertex_fog != I915_FOG_VERTEX) */
- I915_STATECHANGE(i915, I915_UPLOAD_FOG);
- i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_FOGFUNC_MASK;
- i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_VERTEX;
- i915->vertex_fog = I915_FOG_VERTEX;
- }
-
- I915_ACTIVESTATE(i915, I915_UPLOAD_FOG, enabled);
- dw = i915->state.Ctx[I915_CTXREG_LIS5];
- if (enabled)
- dw |= S5_FOG_ENABLE;
- else
- dw &= ~S5_FOG_ENABLE;
- if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
- i915->state.Ctx[I915_CTXREG_LIS5] = dw;
- I915_STATECHANGE(i915, I915_UPLOAD_CTX);
- }
-
- /* Always enable pixel fog. Vertex fog using fog coord will conflict
- * with fog code appended onto fragment program.
- */
- _tnl_allow_vertex_fog( ctx, 0 );
- _tnl_allow_pixel_fog( ctx, 1 );
-}
-
static void
i915Fogfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
{
- struct i915_context *i915 = I915_CONTEXT(ctx);
-
- switch (pname) {
- case GL_FOG_COORDINATE_SOURCE_EXT:
- case GL_FOG_MODE:
- case GL_FOG_START:
- case GL_FOG_END:
- break;
-
- case GL_FOG_DENSITY:
- I915_STATECHANGE(i915, I915_UPLOAD_FOG);
-
- if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) {
- i915->state.Fog[I915_FOGREG_MODE3] =
- (GLuint) (ctx->Fog.Density * FMC3_D_ONE);
- }
- else {
- fi_type fi;
- fi.f = ctx->Fog.Density;
- i915->state.Fog[I915_FOGREG_MODE3] = fi.i;
- }
- break;
-
- case GL_FOG_COLOR:
- I915_STATECHANGE(i915, I915_UPLOAD_FOG);
- i915->state.Fog[I915_FOGREG_COLOR] =
- (_3DSTATE_FOG_COLOR_CMD |
- ((GLubyte) (ctx->Fog.Color[0] * 255.0F) << 16) |
- ((GLubyte) (ctx->Fog.Color[1] * 255.0F) << 8) |
- ((GLubyte) (ctx->Fog.Color[2] * 255.0F) << 0));
- break;
-
- default:
- break;
- }
-}
-
-static void
-i915Hint(struct gl_context * ctx, GLenum target, GLenum state)
-{
- switch (target) {
- case GL_FOG_HINT:
- break;
- default:
- break;
- }
+ (void) ctx;
+ (void) pname;
+ (void) param;
}
/* =============================================================
@@ -971,9 +831,6 @@ i915Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
}
break;
- case GL_FOG:
- break;
-
case GL_CULL_FACE:
i915CullFaceFrontFace(ctx, 0);
break;
@@ -1107,19 +964,6 @@ i915_init_packets(struct i915_context *i915)
i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
}
-
- {
- I915_STATECHANGE(i915, I915_UPLOAD_FOG);
- i915->state.Fog[I915_FOGREG_MODE0] = _3DSTATE_FOG_MODE_CMD;
- i915->state.Fog[I915_FOGREG_MODE1] = (FMC1_FOGFUNC_MODIFY_ENABLE |
- FMC1_FOGFUNC_VERTEX |
- FMC1_FOGINDEX_MODIFY_ENABLE |
- FMC1_FOGINDEX_W |
- FMC1_C1_C2_MODIFY_ENABLE |
- FMC1_DENSITY_MODIFY_ENABLE);
- i915->state.Fog[I915_FOGREG_COLOR] = _3DSTATE_FOG_COLOR_CMD;
- }
-
{
i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
@@ -1202,7 +1046,6 @@ i915InitStateFunctions(struct dd_function_table *functions)
functions->Enable = i915Enable;
functions->Fogfv = i915Fogfv;
functions->FrontFace = i915CullFaceFrontFace;
- functions->Hint = i915Hint;
functions->LightModelfv = i915LightModelfv;
functions->LineWidth = i915LineWidth;
functions->LogicOpcode = i915LogicOp;
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index af140c85f50..742bb994adb 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -164,7 +164,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
format = translate_texture_format(firstImage->TexFormat,
firstImage->InternalFormat,
- tObj->DepthMode);
+ tObj->Sampler.DepthMode);
pitch = intelObj->mt->region->pitch * intelObj->mt->cpp;
state[I915_TEXREG_MS3] =
@@ -181,7 +181,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
* (lowest resolution) LOD. Use it to cover both MAX_LEVEL and
* MAX_LOD.
*/
- maxlod = MIN2(tObj->MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
+ maxlod = MIN2(tObj->Sampler.MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
state[I915_TEXREG_MS4] =
((((pitch / 4) - 1) << MS4_PITCH_SHIFT) |
MS4_CUBE_FACE_ENA_MASK |
@@ -192,7 +192,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
{
GLuint minFilt, mipFilt, magFilt;
- switch (tObj->MinFilter) {
+ switch (tObj->Sampler.MinFilter) {
case GL_NEAREST:
minFilt = FILTER_NEAREST;
mipFilt = MIPFILTER_NONE;
@@ -221,16 +221,16 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
return GL_FALSE;
}
- if (tObj->MaxAnisotropy > 1.0) {
+ if (tObj->Sampler.MaxAnisotropy > 1.0) {
minFilt = FILTER_ANISOTROPIC;
magFilt = FILTER_ANISOTROPIC;
- if (tObj->MaxAnisotropy > 2.0)
+ if (tObj->Sampler.MaxAnisotropy > 2.0)
aniso = SS2_MAX_ANISO_4;
else
aniso = SS2_MAX_ANISO_2;
}
else {
- switch (tObj->MagFilter) {
+ switch (tObj->Sampler.MagFilter) {
case GL_NEAREST:
magFilt = FILTER_NEAREST;
break;
@@ -242,7 +242,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
}
- lodbias = (int) ((tUnit->LodBias + tObj->LodBias) * 16.0);
+ lodbias = (int) ((tUnit->LodBias + tObj->Sampler.LodBias) * 16.0);
if (lodbias < -256)
lodbias = -256;
if (lodbias > 255)
@@ -258,14 +258,14 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
/* Shadow:
*/
- if (tObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB &&
+ if (tObj->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB &&
tObj->Target != GL_TEXTURE_3D) {
if (tObj->Target == GL_TEXTURE_1D)
return GL_FALSE;
state[I915_TEXREG_SS2] |=
(SS2_SHADOW_ENABLE |
- intel_translate_shadow_compare_func(tObj->CompareFunc));
+ intel_translate_shadow_compare_func(tObj->Sampler.CompareFunc));
minFilt = FILTER_4X4_FLAT;
magFilt = FILTER_4X4_FLAT;
@@ -278,9 +278,9 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
{
- GLenum ws = tObj->WrapS;
- GLenum wt = tObj->WrapT;
- GLenum wr = tObj->WrapR;
+ GLenum ws = tObj->Sampler.WrapS;
+ GLenum wt = tObj->Sampler.WrapT;
+ GLenum wr = tObj->Sampler.WrapR;
float minlod;
/* We program 1D textures as 2D textures, so the 2D texcoord could
@@ -298,8 +298,8 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
* clamp_to_border.
*/
if (tObj->Target == GL_TEXTURE_3D &&
- (tObj->MinFilter != GL_NEAREST ||
- tObj->MagFilter != GL_NEAREST) &&
+ (tObj->Sampler.MinFilter != GL_NEAREST ||
+ tObj->Sampler.MagFilter != GL_NEAREST) &&
(ws == GL_CLAMP ||
wt == GL_CLAMP ||
wr == GL_CLAMP ||
@@ -322,7 +322,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
(translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) |
(translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT));
- minlod = MIN2(tObj->MinLod, tObj->_MaxLevel - tObj->BaseLevel);
+ minlod = MIN2(tObj->Sampler.MinLod, tObj->_MaxLevel - tObj->BaseLevel);
state[I915_TEXREG_SS3] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT);
state[I915_TEXREG_SS3] |= (U_FIXED(CLAMP(minlod, 0.0, 11.0), 4) <<
SS3_MIN_LOD_SHIFT);
@@ -330,10 +330,10 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
}
/* convert border color from float to ubyte */
- CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]);
- CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]);
- CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]);
- CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]);
+ CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->Sampler.BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->Sampler.BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->Sampler.BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->Sampler.BorderColor.f[3]);
if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
/* GL specs that border color for depth textures is taken from the
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 921183b81df..89650b618e4 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -260,9 +260,6 @@ get_state_size(struct i915_hw_state *state)
if (dirty & I915_UPLOAD_STIPPLE)
sz += sizeof(state->Stipple);
- if (dirty & I915_UPLOAD_FOG)
- sz += sizeof(state->Fog);
-
if (dirty & I915_UPLOAD_TEX_ALL) {
int nr = 0;
for (i = 0; i < I915_TEX_UNITS; i++)
@@ -307,6 +304,10 @@ i915_emit_state(struct intel_context *intel)
false);
count = 0;
again:
+ if (intel->batch.bo == NULL) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
+ assert(0);
+ }
aper_count = 0;
dirty = get_dirty(state);
@@ -425,12 +426,6 @@ i915_emit_state(struct intel_context *intel)
emit(intel, state->Stipple, sizeof(state->Stipple));
}
- if (dirty & I915_UPLOAD_FOG) {
- if (INTEL_DEBUG & DEBUG_STATE)
- fprintf(stderr, "I915_UPLOAD_FOG:\n");
- emit(intel, state->Fog, sizeof(state->Fog));
- }
-
/* Combine all the dirty texture state into a single command to
* avoid lockups on I915 hardware.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 412d82ab3ca..74a66af31a5 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -238,10 +238,10 @@ static void upload_blend_constant_color(struct brw_context *brw)
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2));
- OUT_BATCH_F(ctx->Color.BlendColor[0]);
- OUT_BATCH_F(ctx->Color.BlendColor[1]);
- OUT_BATCH_F(ctx->Color.BlendColor[2]);
- OUT_BATCH_F(ctx->Color.BlendColor[3]);
+ OUT_BATCH_F(ctx->Color.BlendColorUnclamped[0]);
+ OUT_BATCH_F(ctx->Color.BlendColorUnclamped[1]);
+ OUT_BATCH_F(ctx->Color.BlendColorUnclamped[2]);
+ OUT_BATCH_F(ctx->Color.BlendColorUnclamped[3]);
CACHED_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 9483ec69d96..230d326fa12 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -182,9 +182,21 @@ GLboolean brwCreateContext( int api,
/* WM maximum threads is number of EUs times number of threads per EU. */
if (intel->gen >= 6) {
- brw->urb.size = 1024;
- brw->vs_max_threads = 60;
- brw->wm_max_threads = 80;
+ if (IS_GT2(intel->intelScreen->deviceID)) {
+ /* This could possibly be 80, but is supposed to require
+ * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
+ * GPU reset to change.
+ */
+ brw->wm_max_threads = 40;
+ brw->vs_max_threads = 60;
+ brw->urb.size = 64; /* volume 5c.5 section 5.1 */
+ brw->urb.max_vs_handles = 128; /* volume 2a (see 3DSTATE_URB) */
+ } else {
+ brw->wm_max_threads = 40;
+ brw->vs_max_threads = 24;
+ brw->urb.size = 32; /* volume 5c.5 section 5.1 */
+ brw->urb.max_vs_handles = 256; /* volume 2a (see 3DSTATE_URB) */
+ }
} else if (intel->gen == 5) {
brw->urb.size = 1024;
brw->vs_max_threads = 72;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 7b0551a92bc..1daa49abfb3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -139,7 +139,7 @@ struct brw_context;
* by any 3D rendering.
*/
#define BRW_NEW_BATCH 0x10000
-/** brw->depth_region updated */
+/** \see brw.state.depth_region */
#define BRW_NEW_DEPTH_BUFFER 0x20000
#define BRW_NEW_NR_WM_SURFACES 0x40000
#define BRW_NEW_NR_VS_SURFACES 0x80000
@@ -464,8 +464,27 @@ struct brw_context
struct {
struct brw_state_flags dirty;
+ /**
+ * \name Cached region pointers
+ *
+ * When the draw buffer is updated, often the depth buffer is not
+ * changed. Caching the pointer to the buffer's region allows us to
+ * detect when the buffer has in fact changed, and allows us to avoid
+ * updating the buffer's GPU state when it has not.
+ *
+ * The original of each cached pointer is an instance of
+ * \c intel_renderbuffer.region.
+ *
+ * \see brw_set_draw_region()
+ *
+ * \{
+ */
+
+ /** \see struct brw_tracked_state brw_depthbuffer */
struct intel_region *depth_region;
+ /** \} */
+
/**
* List of buffers accumulated in brw_validate_state to receive
* drm_intel_bo_check_aperture treatment before exec, so we can
@@ -549,18 +568,21 @@ struct brw_context
GLboolean constrained;
+ GLuint max_vs_handles; /* Maximum number of VS handles */
+ GLuint max_gs_handles; /* Maximum number of GS handles */
+
GLuint nr_vs_entries;
GLuint nr_gs_entries;
GLuint nr_clip_entries;
GLuint nr_sf_entries;
GLuint nr_cs_entries;
- /* gen6 */
+ /* gen6:
+ * The length of each URB entry owned by the VS (or GS), as
+ * a number of 1024-bit (128-byte) rows. Should be >= 1.
+ */
GLuint vs_size;
-/* GLuint gs_size; */
-/* GLuint clip_size; */
-/* GLuint sf_size; */
-/* GLuint cs_size; */
+ GLuint gs_size;
GLuint vs_start;
GLuint gs_start;
@@ -639,7 +661,9 @@ struct brw_context
drm_intel_bo *prog_bo;
drm_intel_bo *state_bo;
+ uint32_t state_offset;
drm_intel_bo *vp_bo;
+ uint32_t vp_offset;
} sf;
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 6c61aefd7d3..effcb6c1c4a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -43,6 +43,12 @@
#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00
#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01
+#define CMD_3D_PRIM 0x7b00 /* 3DPRIMITIVE */
+/* DW0 */
+# define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT 10
+# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15)
+# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 15)
+
#define _3DPRIM_POINTLIST 0x01
#define _3DPRIM_LINELIST 0x02
#define _3DPRIM_LINESTRIP 0x03
@@ -65,9 +71,6 @@
#define _3DPRIM_LINESTRIP_CONT_BF 0x14
#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15
-#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0
-#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1
-
#define BRW_ANISORATIO_2 0
#define BRW_ANISORATIO_4 1
#define BRW_ANISORATIO_6 2
@@ -147,6 +150,7 @@
#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
#define BRW_DEPTHFORMAT_D32_FLOAT 1
#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2
+#define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT 3 /* GEN5 */
#define BRW_DEPTHFORMAT_D16_UNORM 5
#define BRW_FLOATING_POINT_IEEE_754 0
@@ -1131,8 +1135,6 @@
#define CMD_PIPE_CONTROL 0x7a00
-#define CMD_3D_PRIM 0x7b00
-
#define CMD_MI_FLUSH 0x0200
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index f5abe021c43..2db70c543ea 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -129,30 +129,31 @@ static void brw_emit_prim(struct brw_context *brw,
const struct _mesa_prim *prim,
uint32_t hw_prim)
{
- struct brw_3d_primitive prim_packet;
struct intel_context *intel = &brw->intel;
+ int verts_per_instance;
+ int vertex_access_type;
+ int start_vertex_location;
+ int base_vertex_location;
DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode),
prim->start, prim->count);
- prim_packet.header.opcode = CMD_3D_PRIM;
- prim_packet.header.length = sizeof(prim_packet)/4 - 2;
- prim_packet.header.pad = 0;
- prim_packet.header.topology = hw_prim;
- prim_packet.header.indexed = prim->indexed;
-
- prim_packet.verts_per_instance = trim(prim->mode, prim->count);
- prim_packet.start_vert_location = prim->start;
- if (prim->indexed)
- prim_packet.start_vert_location += brw->ib.start_vertex_offset;
- else
- prim_packet.start_vert_location += brw->vb.start_vertex_bias;
- prim_packet.instance_count = 1;
- prim_packet.start_instance_location = 0;
- prim_packet.base_vert_location = prim->basevertex;
- if (prim->indexed)
- prim_packet.base_vert_location += brw->vb.start_vertex_bias;
+ start_vertex_location = prim->start;
+ base_vertex_location = prim->basevertex;
+ if (prim->indexed) {
+ vertex_access_type = GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
+ start_vertex_location += brw->ib.start_vertex_offset;
+ base_vertex_location += brw->vb.start_vertex_bias;
+ } else {
+ vertex_access_type = GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
+ start_vertex_location += brw->vb.start_vertex_bias;
+ }
+
+ verts_per_instance = trim(prim->mode, prim->count);
+ /* If nothing to emit, just return. */
+ if (verts_per_instance == 0)
+ return;
/* If we're set to always flush, do it before and after the primitive emit.
* We want to catch both missed flushes that hurt instruction/state cache
@@ -162,10 +163,18 @@ static void brw_emit_prim(struct brw_context *brw,
if (intel->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(intel);
}
- if (prim_packet.verts_per_instance) {
- intel_batchbuffer_data(&brw->intel, &prim_packet,
- sizeof(prim_packet), false);
- }
+
+ BEGIN_BATCH(6);
+ OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
+ hw_prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
+ vertex_access_type);
+ OUT_BATCH(verts_per_instance);
+ OUT_BATCH(start_vertex_location);
+ OUT_BATCH(1); // instance count
+ OUT_BATCH(0); // start instance location
+ OUT_BATCH(base_vertex_location);
+ ADVANCE_BATCH();
+
if (intel->always_flush_cache) {
intel_batchbuffer_emit_mi_flush(intel);
}
@@ -271,20 +280,20 @@ static GLboolean check_fallbacks( struct brw_context *brw,
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[u];
if (texUnit->Enabled) {
if (texUnit->Enabled & TEXTURE_1D_BIT) {
- if (texUnit->CurrentTex[TEXTURE_1D_INDEX]->WrapS == GL_CLAMP) {
+ if (texUnit->CurrentTex[TEXTURE_1D_INDEX]->Sampler.WrapS == GL_CLAMP) {
return GL_TRUE;
}
}
if (texUnit->Enabled & TEXTURE_2D_BIT) {
- if (texUnit->CurrentTex[TEXTURE_2D_INDEX]->WrapS == GL_CLAMP ||
- texUnit->CurrentTex[TEXTURE_2D_INDEX]->WrapT == GL_CLAMP) {
+ if (texUnit->CurrentTex[TEXTURE_2D_INDEX]->Sampler.WrapS == GL_CLAMP ||
+ texUnit->CurrentTex[TEXTURE_2D_INDEX]->Sampler.WrapT == GL_CLAMP) {
return GL_TRUE;
}
}
if (texUnit->Enabled & TEXTURE_3D_BIT) {
- if (texUnit->CurrentTex[TEXTURE_3D_INDEX]->WrapS == GL_CLAMP ||
- texUnit->CurrentTex[TEXTURE_3D_INDEX]->WrapT == GL_CLAMP ||
- texUnit->CurrentTex[TEXTURE_3D_INDEX]->WrapR == GL_CLAMP) {
+ if (texUnit->CurrentTex[TEXTURE_3D_INDEX]->Sampler.WrapS == GL_CLAMP ||
+ texUnit->CurrentTex[TEXTURE_3D_INDEX]->Sampler.WrapT == GL_CLAMP ||
+ texUnit->CurrentTex[TEXTURE_3D_INDEX]->Sampler.WrapR == GL_CLAMP) {
return GL_TRUE;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f1d00693168..9389eb6733f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -575,7 +575,7 @@ static void brw_emit_vertices(struct brw_context *brw)
if (intel->gen >= 5) {
OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1);
} else
- OUT_BATCH(buffer->bo->size / buffer->stride);
+ OUT_BATCH(0);
OUT_BATCH(0); /* Instance data step rate */
brw->vb.current_buffers[i].handle = buffer->bo->handle;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 3b5c4c071e3..7e63482d8fa 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -34,6 +34,28 @@
#include "brw_defines.h"
#include "brw_eu.h"
+/* Returns the corresponding conditional mod for swapping src0 and
+ * src1 in e.g. CMP.
+ */
+uint32_t
+brw_swap_cmod(uint32_t cmod)
+{
+ switch (cmod) {
+ case BRW_CONDITIONAL_Z:
+ case BRW_CONDITIONAL_NZ:
+ return cmod;
+ case BRW_CONDITIONAL_G:
+ return BRW_CONDITIONAL_LE;
+ case BRW_CONDITIONAL_GE:
+ return BRW_CONDITIONAL_L;
+ case BRW_CONDITIONAL_L:
+ return BRW_CONDITIONAL_GE;
+ case BRW_CONDITIONAL_LE:
+ return BRW_CONDITIONAL_G;
+ default:
+ return ~0;
+ }
+}
/* How does predicate control work when execution_size != 8? Do I
@@ -60,6 +82,11 @@ void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
p->current->header.predicate_control = pc;
}
+void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
+{
+ p->current->header.predicate_inverse = predicate_inverse;
+}
+
void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
{
p->current->header.destreg__conditionalmod = conditional;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 2d2ed9de985..718b3800423 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -772,6 +772,7 @@ void brw_set_access_mode( struct brw_compile *p, GLuint access_mode );
void brw_set_compression_control( struct brw_compile *p, GLboolean control );
void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );
void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
+void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
void brw_set_acc_write_control(struct brw_compile *p, GLuint value);
@@ -1017,6 +1018,8 @@ void brw_set_src1( struct brw_instruction *insn,
void brw_set_uip_jip(struct brw_compile *p);
+uint32_t brw_swap_cmod(uint32_t cmod);
+
/* brw_optimize.c */
void brw_optimize(struct brw_compile *p);
void brw_remove_duplicate_mrf_moves(struct brw_compile *p);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 21ce92c9173..71485cd1f71 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -52,6 +52,34 @@ static void guess_execution_size(struct brw_compile *p,
}
+/**
+ * Prior to Sandybridge, the SEND instruction accepted non-MRF source
+ * registers, implicitly moving the operand to a message register.
+ *
+ * On Sandybridge, this is no longer the case. This function performs the
+ * explicit move; it should be called before emitting a SEND instruction.
+ */
+static void
+gen6_resolve_implied_move(struct brw_compile *p,
+ struct brw_reg *src,
+ GLuint msg_reg_nr)
+{
+ struct intel_context *intel = &p->brw->intel;
+ if (intel->gen != 6)
+ return;
+
+ if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) {
+ brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
+ brw_set_compression_control(p, BRW_COMPRESSION_NONE);
+ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
+ retype(*src, BRW_REGISTER_TYPE_UD));
+ brw_pop_insn_state(p);
+ }
+ *src = brw_message_reg(msg_reg_nr);
+}
+
+
static void brw_set_dest(struct brw_compile *p,
struct brw_instruction *insn,
struct brw_reg dest)
@@ -468,10 +496,9 @@ static void brw_set_dp_write_message( struct brw_context *brw,
insn->bits3.dp_render_cache.response_length = response_length;
insn->bits3.dp_render_cache.msg_length = msg_length;
insn->bits3.dp_render_cache.end_of_thread = end_of_thread;
+
+ /* We always use the render cache for write messages */
insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
- /* XXX really need below? */
- insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
- insn->bits2.send_gen5.end_of_thread = end_of_thread;
} else if (intel->gen == 5) {
insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_write_gen5.msg_control = msg_control;
@@ -511,6 +538,13 @@ brw_set_dp_read_message(struct brw_context *brw,
brw_set_src1(insn, brw_imm_d(0));
if (intel->gen >= 6) {
+ uint32_t target_function;
+
+ if (target_cache == BRW_DATAPORT_READ_TARGET_DATA_CACHE)
+ target_function = BRW_MESSAGE_TARGET_DATAPORT_READ; /* data cache */
+ else
+ target_function = BRW_MESSAGE_TARGET_DATAPORT_WRITE; /* render cache */
+
insn->bits3.dp_render_cache.binding_table_index = binding_table_index;
insn->bits3.dp_render_cache.msg_control = msg_control;
insn->bits3.dp_render_cache.pixel_scoreboard_clear = 0;
@@ -520,10 +554,7 @@ brw_set_dp_read_message(struct brw_context *brw,
insn->bits3.dp_render_cache.response_length = response_length;
insn->bits3.dp_render_cache.msg_length = msg_length;
insn->bits3.dp_render_cache.end_of_thread = 0;
- insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_DATAPORT_READ;
- /* XXX really need below? */
- insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
- insn->bits2.send_gen5.end_of_thread = 0;
+ insn->header.destreg__conditionalmod = target_function;
} else if (intel->gen == 5) {
insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_read_gen5.msg_control = msg_control;
@@ -1458,9 +1489,12 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
GLuint offset)
{
struct intel_context *intel = &p->brw->intel;
- uint32_t msg_control;
+ uint32_t msg_control, msg_type;
int mlen;
+ if (intel->gen >= 6)
+ offset /= 16;
+
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
if (num_regs == 1) {
@@ -1526,13 +1560,22 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
}
brw_set_dest(p, insn, dest);
- brw_set_src0(insn, brw_null_reg());
+ if (intel->gen >= 6) {
+ brw_set_src0(insn, mrf);
+ } else {
+ brw_set_src0(insn, brw_null_reg());
+ }
+
+ if (intel->gen >= 6)
+ msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
+ else
+ msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
brw_set_dp_write_message(p->brw,
insn,
255, /* binding table index (255=stateless) */
msg_control,
- BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, /* msg_type */
+ msg_type,
mlen,
GL_TRUE, /* header_present */
0, /* pixel scoreboard */
@@ -1557,9 +1600,13 @@ brw_oword_block_read_scratch(struct brw_compile *p,
int num_regs,
GLuint offset)
{
+ struct intel_context *intel = &p->brw->intel;
uint32_t msg_control;
int rlen;
+ if (intel->gen >= 6)
+ offset /= 16;
+
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
dest = retype(dest, BRW_REGISTER_TYPE_UW);
@@ -1596,14 +1643,18 @@ brw_oword_block_read_scratch(struct brw_compile *p,
insn->header.destreg__conditionalmod = mrf.nr;
brw_set_dest(p, insn, dest); /* UW? */
- brw_set_src0(insn, brw_null_reg());
+ if (intel->gen >= 6) {
+ brw_set_src0(insn, mrf);
+ } else {
+ brw_set_src0(insn, brw_null_reg());
+ }
brw_set_dp_read_message(p->brw,
insn,
255, /* binding table index (255=stateless) */
msg_control,
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
- 1, /* target cache (render/scratch) */
+ BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
1, /* msg_length */
rlen);
}
@@ -1771,6 +1822,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
GLuint bind_table_index)
{
struct intel_context *intel = &p->brw->intel;
+ struct brw_reg src = brw_vec8_grf(0, 0);
int msg_type;
/* Setup MRF[1] with offset into const buffer */
@@ -1787,6 +1839,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
addr_reg, brw_imm_d(offset));
brw_pop_insn_state(p);
+ gen6_resolve_implied_move(p, &src, 0);
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = BRW_PREDICATE_NONE;
@@ -1795,7 +1848,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
insn->header.mask_control = BRW_MASK_DISABLE;
brw_set_dest(p, insn, dest);
- brw_set_src0(insn, brw_vec8_grf(0, 0));
+ brw_set_src0(insn, src);
if (intel->gen == 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
@@ -1809,7 +1862,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
bind_table_index,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
msg_type,
- 0, /* source cache = data cache */
+ BRW_DATAPORT_READ_TARGET_DATA_CACHE,
2, /* msg_length */
1); /* response_length */
}
@@ -1966,20 +2019,7 @@ void brw_SAMPLE(struct brw_compile *p,
{
struct brw_instruction *insn;
- /* Sandybridge doesn't have the implied move for SENDs,
- * and the first message register index comes from src0.
- */
- if (intel->gen >= 6) {
- if (src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
- src0.nr != BRW_ARF_NULL) {
- brw_push_insn_state(p);
- brw_set_mask_control( p, BRW_MASK_DISABLE );
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_MOV(p, retype(brw_message_reg(msg_reg_nr), src0.type), src0);
- brw_pop_insn_state(p);
- }
- src0 = brw_message_reg(msg_reg_nr);
- }
+ gen6_resolve_implied_move(p, &src0, msg_reg_nr);
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
@@ -2034,17 +2074,7 @@ void brw_urb_WRITE(struct brw_compile *p,
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
- /* Sandybridge doesn't have the implied move for SENDs,
- * and the first message register index comes from src0.
- */
- if (intel->gen >= 6) {
- brw_push_insn_state(p);
- brw_set_mask_control( p, BRW_MASK_DISABLE );
- brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
- retype(src0, BRW_REGISTER_TYPE_UD));
- brw_pop_insn_state(p);
- src0 = brw_message_reg(msg_reg_nr);
- }
+ gen6_resolve_implied_move(p, &src0, msg_reg_nr);
insn = next_insn(p, BRW_OPCODE_SEND);
@@ -2154,17 +2184,7 @@ void brw_ff_sync(struct brw_compile *p,
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
- /* Sandybridge doesn't have the implied move for SENDs,
- * and the first message register index comes from src0.
- */
- if (intel->gen >= 6) {
- brw_push_insn_state(p);
- brw_set_mask_control( p, BRW_MASK_DISABLE );
- brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
- retype(src0, BRW_REGISTER_TYPE_UD));
- brw_pop_insn_state(p);
- src0 = brw_message_reg(msg_reg_nr);
- }
+ gen6_resolve_implied_move(p, &src0, msg_reg_nr);
insn = next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, dest);
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8b3f5adb9f9..5426925e372 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -177,6 +177,23 @@ type_size(const struct glsl_type *type)
}
}
+void
+fs_visitor::fail(const char *format, ...)
+{
+ if (!failed) {
+ failed = true;
+
+ if (INTEL_DEBUG & DEBUG_WM) {
+ fprintf(stderr, "FS compile failed: ");
+
+ va_list va;
+ va_start(va, format);
+ vfprintf(stderr, format, va);
+ va_end(va);
+ }
+ }
+}
+
/**
* Returns how many MRFs an FS opcode will write over.
*
@@ -382,60 +399,32 @@ fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
void
fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
{
- const struct gl_builtin_uniform_desc *statevar = NULL;
-
- for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
- statevar = &_mesa_builtin_uniform_desc[i];
- if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
- break;
- }
-
- if (!statevar->name) {
- this->fail = true;
- printf("Failed to find builtin uniform `%s'\n", ir->name);
- return;
- }
-
- int array_count;
- if (ir->type->is_array()) {
- array_count = ir->type->length;
- } else {
- array_count = 1;
- }
+ const ir_state_slot *const slots = ir->state_slots;
+ assert(ir->state_slots != NULL);
- for (int a = 0; a < array_count; a++) {
- for (unsigned int i = 0; i < statevar->num_elements; i++) {
- struct gl_builtin_uniform_element *element = &statevar->elements[i];
- int tokens[STATE_LENGTH];
-
- memcpy(tokens, element->tokens, sizeof(element->tokens));
- if (ir->type->is_array()) {
- tokens[1] = a;
- }
-
- /* This state reference has already been setup by ir_to_mesa,
- * but we'll get the same index back here.
- */
- int index = _mesa_add_state_reference(this->fp->Base.Parameters,
- (gl_state_index *)tokens);
+ for (unsigned int i = 0; i < ir->num_state_slots; i++) {
+ /* This state reference has already been setup by ir_to_mesa, but we'll
+ * get the same index back here.
+ */
+ int index = _mesa_add_state_reference(this->fp->Base.Parameters,
+ (gl_state_index *)slots[i].tokens);
- /* Add each of the unique swizzles of the element as a
- * parameter. This'll end up matching the expected layout of
- * the array/matrix/structure we're trying to fill in.
- */
- int last_swiz = -1;
- for (unsigned int i = 0; i < 4; i++) {
- int swiz = GET_SWZ(element->swizzle, i);
- if (swiz == last_swiz)
- break;
- last_swiz = swiz;
+ /* Add each of the unique swizzles of the element as a parameter.
+ * This'll end up matching the expected layout of the
+ * array/matrix/structure we're trying to fill in.
+ */
+ int last_swiz = -1;
+ for (unsigned int j = 0; j < 4; j++) {
+ int swiz = GET_SWZ(slots[i].swizzle, j);
+ if (swiz == last_swiz)
+ break;
+ last_swiz = swiz;
- c->prog_data.param_convert[c->prog_data.nr_params] =
- PARAM_NO_CONVERT;
- this->param_index[c->prog_data.nr_params] = index;
- this->param_offset[c->prog_data.nr_params] = swiz;
- c->prog_data.nr_params++;
- }
+ c->prog_data.param_convert[c->prog_data.nr_params] =
+ PARAM_NO_CONVERT;
+ this->param_index[c->prog_data.nr_params] = index;
+ this->param_offset[c->prog_data.nr_params] = swiz;
+ c->prog_data.nr_params++;
}
}
}
@@ -451,15 +440,15 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
/* gl_FragCoord.x */
if (ir->pixel_center_integer) {
- emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x));
+ emit(BRW_OPCODE_MOV, wpos, this->pixel_x);
} else {
- emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)));
+ emit(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f));
}
wpos.reg_offset++;
/* gl_FragCoord.y */
if (!flip && ir->pixel_center_integer) {
- emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
+ emit(BRW_OPCODE_MOV, wpos, this->pixel_y);
} else {
fs_reg pixel_y = this->pixel_y;
float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
@@ -469,22 +458,22 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
offset += c->key.drawable_height - 1.0;
}
- emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)));
+ emit(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset));
}
wpos.reg_offset++;
/* gl_FragCoord.z */
if (intel->gen >= 6) {
- emit(fs_inst(BRW_OPCODE_MOV, wpos,
- fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
+ emit(BRW_OPCODE_MOV, wpos,
+ fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
} else {
- emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
- interp_reg(FRAG_ATTRIB_WPOS, 2)));
+ emit(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
+ interp_reg(FRAG_ATTRIB_WPOS, 2));
}
wpos.reg_offset++;
/* gl_FragCoord.w: Already set up in emit_interpolation */
- emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
+ emit(BRW_OPCODE_MOV, wpos, this->wpos_w);
return reg;
}
@@ -503,7 +492,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
if (ir->type->is_array()) {
array_elements = ir->type->length;
if (array_elements == 0) {
- this->fail = true;
+ fail("dereferenced array '%s' has length 0\n", ir->name);
}
type = ir->type->fields.array;
} else {
@@ -523,37 +512,33 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
continue;
}
- if (c->key.flat_shade && (location == FRAG_ATTRIB_COL0 ||
- location == FRAG_ATTRIB_COL1)) {
+ bool is_gl_Color =
+ location == FRAG_ATTRIB_COL0 || location == FRAG_ATTRIB_COL1;
+
+ if (c->key.flat_shade && is_gl_Color) {
/* Constant interpolation (flat shading) case. The SF has
* handed us defined values in only the constant offset
* field of the setup reg.
*/
- for (unsigned int c = 0; c < type->vector_elements; c++) {
- struct brw_reg interp = interp_reg(location, c);
+ for (unsigned int k = 0; k < type->vector_elements; k++) {
+ struct brw_reg interp = interp_reg(location, k);
interp = suboffset(interp, 3);
- emit(fs_inst(FS_OPCODE_CINTERP, attr, fs_reg(interp)));
+ emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
attr.reg_offset++;
}
} else {
/* Perspective interpolation case. */
- for (unsigned int c = 0; c < type->vector_elements; c++) {
- struct brw_reg interp = interp_reg(location, c);
- emit(fs_inst(FS_OPCODE_LINTERP,
- attr,
- this->delta_x,
- this->delta_y,
- fs_reg(interp)));
+ for (unsigned int k = 0; k < type->vector_elements; k++) {
+ struct brw_reg interp = interp_reg(location, k);
+ emit(FS_OPCODE_LINTERP, attr,
+ this->delta_x, this->delta_y, fs_reg(interp));
attr.reg_offset++;
}
- if (intel->gen < 6) {
+ if (intel->gen < 6 && !(is_gl_Color && c->key.linear_color)) {
attr.reg_offset -= type->vector_elements;
- for (unsigned int c = 0; c < type->vector_elements; c++) {
- emit(fs_inst(BRW_OPCODE_MUL,
- attr,
- attr,
- this->pixel_w));
+ for (unsigned int k = 0; k < type->vector_elements; k++) {
+ emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
attr.reg_offset++;
}
}
@@ -572,28 +557,21 @@ fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
/* The frontfacing comes in as a bit in the thread payload. */
if (intel->gen >= 6) {
- emit(fs_inst(BRW_OPCODE_ASR,
- *reg,
- fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
- fs_reg(15)));
- emit(fs_inst(BRW_OPCODE_NOT,
- *reg,
- *reg));
- emit(fs_inst(BRW_OPCODE_AND,
- *reg,
- *reg,
- fs_reg(1)));
+ emit(BRW_OPCODE_ASR, *reg,
+ fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
+ fs_reg(15));
+ emit(BRW_OPCODE_NOT, *reg, *reg);
+ emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1));
} else {
struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
/* bit 31 is "primitive is back face", so checking < (1 << 31) gives
* us front face
*/
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
- *reg,
- fs_reg(r1_6ud),
- fs_reg(1u << 31)));
+ fs_inst *inst = emit(BRW_OPCODE_CMP, *reg,
+ fs_reg(r1_6ud),
+ fs_reg(1u << 31));
inst->conditional_mod = BRW_CONDITIONAL_L;
- emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
+ emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u));
}
return reg;
@@ -628,11 +606,11 @@ fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
src.abs ||
src.negate)) {
fs_reg expanded = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(BRW_OPCODE_MOV, expanded, src));
+ emit(BRW_OPCODE_MOV, expanded, src);
src = expanded;
}
- fs_inst *inst = emit(fs_inst(opcode, dst, src));
+ fs_inst *inst = emit(opcode, dst, src);
if (intel->gen < 6) {
inst->base_mrf = 2;
@@ -658,20 +636,20 @@ fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
*/
if (src0.file == UNIFORM || src0.abs || src0.negate) {
fs_reg expanded = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(BRW_OPCODE_MOV, expanded, src0));
+ emit(BRW_OPCODE_MOV, expanded, src0);
src0 = expanded;
}
if (src1.file == UNIFORM || src1.abs || src1.negate) {
fs_reg expanded = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(BRW_OPCODE_MOV, expanded, src1));
+ emit(BRW_OPCODE_MOV, expanded, src1);
src1 = expanded;
}
- inst = emit(fs_inst(opcode, dst, src0, src1));
+ inst = emit(opcode, dst, src0, src1);
} else {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1));
- inst = emit(fs_inst(opcode, dst, src0, reg_null_f));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1);
+ inst = emit(opcode, dst, src0, reg_null_f);
inst->base_mrf = base_mrf;
inst->mlen = 2;
@@ -788,7 +766,7 @@ fs_visitor::try_emit_saturate(ir_expression *ir)
fs_reg src = this->result;
this->result = fs_reg(this, ir->type);
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, src));
+ fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src);
inst->saturate = true;
return true;
@@ -834,9 +812,8 @@ fs_visitor::visit(ir_expression *ir)
ir->operands[operand]->accept(this);
if (this->result.file == BAD_FILE) {
ir_print_visitor v;
- printf("Failed to get tree for expression operand:\n");
+ fail("Failed to get tree for expression operand:\n");
ir->operands[operand]->accept(&v);
- this->fail = true;
}
op[operand] = this->result;
@@ -859,7 +836,7 @@ fs_visitor::visit(ir_expression *ir)
/* Note that BRW_OPCODE_NOT is not appropriate here, since it is
* ones complement of the whole register, not just bit 0.
*/
- emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)));
+ emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1));
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
@@ -873,16 +850,16 @@ fs_visitor::visit(ir_expression *ir)
case ir_unop_sign:
temp = fs_reg(this, ir->type);
- emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
+ emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f));
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
+ inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_G;
- inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
+ inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f));
inst->predicated = true;
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
+ inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_L;
- inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
+ inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f));
inst->predicated = true;
break;
@@ -910,21 +887,21 @@ fs_visitor::visit(ir_expression *ir)
break;
case ir_unop_dFdx:
- emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
+ emit(FS_OPCODE_DDX, this->result, op[0]);
break;
case ir_unop_dFdy:
- emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
+ emit(FS_OPCODE_DDY, this->result, op[0]);
break;
case ir_binop_add:
- emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
+ emit(BRW_OPCODE_ADD, this->result, op[0], op[1]);
break;
case ir_binop_sub:
assert(!"not reached: should be handled by ir_sub_to_add_neg");
break;
case ir_binop_mul:
- emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
+ emit(BRW_OPCODE_MUL, this->result, op[0], op[1]);
break;
case ir_binop_div:
assert(!"not reached: should be handled by ir_div_to_mul_rcp");
@@ -946,21 +923,21 @@ fs_visitor::visit(ir_expression *ir)
if (intel->gen < 5)
temp.type = op[0].type;
- inst = emit(fs_inst(BRW_OPCODE_CMP, temp, op[0], op[1]));
+ inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]);
inst->conditional_mod = brw_conditional_for_comparison(ir->operation);
- emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
+ emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1));
break;
case ir_binop_logic_xor:
- emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
+ emit(BRW_OPCODE_XOR, this->result, op[0], op[1]);
break;
case ir_binop_logic_or:
- emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
+ emit(BRW_OPCODE_OR, this->result, op[0], op[1]);
break;
case ir_binop_logic_and:
- emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
+ emit(BRW_OPCODE_AND, this->result, op[0], op[1]);
break;
case ir_binop_dot:
@@ -988,7 +965,7 @@ fs_visitor::visit(ir_expression *ir)
case ir_unop_b2f:
case ir_unop_b2i:
case ir_unop_f2i:
- emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
+ emit(BRW_OPCODE_MOV, this->result, op[0]);
break;
case ir_unop_f2b:
case ir_unop_i2b:
@@ -997,42 +974,41 @@ fs_visitor::visit(ir_expression *ir)
if (intel->gen < 5)
temp.type = op[0].type;
- inst = emit(fs_inst(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)));
+ inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
- inst = emit(fs_inst(BRW_OPCODE_AND, this->result,
- this->result, fs_reg(1)));
+ inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1));
break;
case ir_unop_trunc:
- emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0]));
+ emit(BRW_OPCODE_RNDZ, this->result, op[0]);
break;
case ir_unop_ceil:
op[0].negate = !op[0].negate;
- inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
+ inst = emit(BRW_OPCODE_RNDD, this->result, op[0]);
this->result.negate = true;
break;
case ir_unop_floor:
- inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
+ inst = emit(BRW_OPCODE_RNDD, this->result, op[0]);
break;
case ir_unop_fract:
- inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
+ inst = emit(BRW_OPCODE_FRC, this->result, op[0]);
break;
case ir_unop_round_even:
- emit(fs_inst(BRW_OPCODE_RNDE, this->result, op[0]));
+ emit(BRW_OPCODE_RNDE, this->result, op[0]);
break;
case ir_binop_min:
- inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_L;
- inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]);
inst->predicated = true;
break;
case ir_binop_max:
- inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_G;
- inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]);
inst->predicated = true;
break;
@@ -1041,16 +1017,16 @@ fs_visitor::visit(ir_expression *ir)
break;
case ir_unop_bit_not:
- inst = emit(fs_inst(BRW_OPCODE_NOT, this->result, op[0]));
+ inst = emit(BRW_OPCODE_NOT, this->result, op[0]);
break;
case ir_binop_bit_and:
- inst = emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]);
break;
case ir_binop_bit_xor:
- inst = emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]);
break;
case ir_binop_bit_or:
- inst = emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
+ inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]);
break;
case ir_unop_u2f:
@@ -1074,7 +1050,7 @@ fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
l.type = brw_type_for_base_type(type);
r.type = brw_type_for_base_type(type);
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
+ fs_inst *inst = emit(BRW_OPCODE_MOV, l, r);
inst->predicated = predicated;
l.reg_offset++;
@@ -1127,7 +1103,7 @@ fs_visitor::visit(ir_assignment *ir)
ir->lhs->type->is_vector()) {
for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
if (ir->write_mask & (1 << i)) {
- inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
+ inst = emit(BRW_OPCODE_MOV, l, r);
if (ir->condition)
inst->predicated = true;
r.reg_offset++;
@@ -1152,8 +1128,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
if (ir->shadow_comparitor) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
- coordinate));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate);
coordinate.reg_offset++;
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
@@ -1163,29 +1138,25 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
/* There's no plain shadow compare message, so we use shadow
* compare with a bias of 0.0.
*/
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
- fs_reg(0.0f)));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f));
mlen++;
} else if (ir->op == ir_txb) {
ir->lod_info.bias->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
- this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
} else {
assert(ir->op == ir_txl);
ir->lod_info.lod->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
- this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
}
ir->shadow_comparitor->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
} else if (ir->op == ir_tex) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
- coordinate));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate);
coordinate.reg_offset++;
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
@@ -1199,8 +1170,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
assert(ir->op == ir_txb || ir->op == ir_txl);
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2),
- coordinate));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), coordinate);
coordinate.reg_offset++;
}
@@ -1209,13 +1179,11 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
if (ir->op == ir_txb) {
ir->lod_info.bias->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
- this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
} else {
ir->lod_info.lod->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
- this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
}
@@ -1236,16 +1204,16 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
fs_inst *inst = NULL;
switch (ir->op) {
case ir_tex:
- inst = emit(fs_inst(FS_OPCODE_TEX, dst));
+ inst = emit(FS_OPCODE_TEX, dst);
break;
case ir_txb:
- inst = emit(fs_inst(FS_OPCODE_TXB, dst));
+ inst = emit(FS_OPCODE_TXB, dst);
break;
case ir_txl:
- inst = emit(fs_inst(FS_OPCODE_TXL, dst));
+ inst = emit(FS_OPCODE_TXL, dst);
break;
case ir_txd:
- inst = emit(fs_inst(FS_OPCODE_TXD, dst));
+ inst = emit(FS_OPCODE_TXD, dst);
break;
case ir_txf:
assert(!"GLSL 1.30 features unsupported");
@@ -1256,7 +1224,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
if (simd16) {
for (int i = 0; i < 4; i++) {
- emit(fs_inst(BRW_OPCODE_MOV, orig_dst, dst));
+ emit(BRW_OPCODE_MOV, orig_dst, dst);
orig_dst.reg_offset++;
dst.reg_offset += 2;
}
@@ -1280,8 +1248,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate)
int base_mrf = 1;
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
- coordinate));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate);
coordinate.reg_offset++;
}
mlen += ir->coordinate->type->vector_elements;
@@ -1290,30 +1257,30 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate)
mlen = MAX2(mlen, 5);
ir->shadow_comparitor->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
}
fs_inst *inst = NULL;
switch (ir->op) {
case ir_tex:
- inst = emit(fs_inst(FS_OPCODE_TEX, dst));
+ inst = emit(FS_OPCODE_TEX, dst);
break;
case ir_txb:
ir->lod_info.bias->accept(this);
mlen = MAX2(mlen, 5);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
- inst = emit(fs_inst(FS_OPCODE_TXB, dst));
+ inst = emit(FS_OPCODE_TXB, dst);
break;
case ir_txl:
ir->lod_info.lod->accept(this);
mlen = MAX2(mlen, 5);
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
- inst = emit(fs_inst(FS_OPCODE_TXL, dst));
+ inst = emit(FS_OPCODE_TXL, dst);
break;
case ir_txd:
case ir_txf:
@@ -1356,14 +1323,14 @@ fs_visitor::visit(ir_texture *ir)
}
/* Explicitly set up the message header by copying g0 to msg reg m1. */
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD),
- fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD),
+ fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD));
/* Then set the offset bits in DWord 2 of the message header. */
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2),
- BRW_REGISTER_TYPE_UD)),
- fs_reg(brw_imm_uw(offset_bits))));
+ emit(BRW_OPCODE_MOV,
+ fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2),
+ BRW_REGISTER_TYPE_UD)),
+ fs_reg(brw_imm_uw(offset_bits)));
}
/* Should be lowered by do_lower_texture_projection */
@@ -1409,10 +1376,10 @@ fs_visitor::visit(ir_texture *ir)
fs_reg src = coordinate;
coordinate = dst;
- emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_x));
+ emit(BRW_OPCODE_MUL, dst, src, scale_x);
dst.reg_offset++;
src.reg_offset++;
- emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_y));
+ emit(BRW_OPCODE_MUL, dst, src, scale_y);
}
/* Writemasking doesn't eliminate channels on SIMD8 texture
@@ -1453,13 +1420,13 @@ fs_visitor::visit(ir_texture *ir)
l.reg_offset += i;
if (swiz == SWIZZLE_ZERO) {
- emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(0.0f)));
+ emit(BRW_OPCODE_MOV, l, fs_reg(0.0f));
} else if (swiz == SWIZZLE_ONE) {
- emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(1.0f)));
+ emit(BRW_OPCODE_MOV, l, fs_reg(1.0f));
} else {
fs_reg r = dst;
r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
- emit(fs_inst(BRW_OPCODE_MOV, l, r));
+ emit(BRW_OPCODE_MOV, l, r);
}
}
this->result = swizzle_dst;
@@ -1500,7 +1467,7 @@ fs_visitor::visit(ir_swizzle *ir)
}
channel.reg_offset += swiz;
- emit(fs_inst(BRW_OPCODE_MOV, result, channel));
+ emit(BRW_OPCODE_MOV, result, channel);
result.reg_offset++;
}
}
@@ -1512,8 +1479,8 @@ fs_visitor::visit(ir_discard *ir)
assert(ir->condition == NULL); /* FINISHME */
- emit(fs_inst(FS_OPCODE_DISCARD_NOT, temp, reg_null_d));
- emit(fs_inst(FS_OPCODE_DISCARD_AND, reg_null_d, temp));
+ emit(FS_OPCODE_DISCARD_NOT, temp, reg_null_d);
+ emit(FS_OPCODE_DISCARD_AND, reg_null_d, temp);
kill_emitted = true;
}
@@ -1539,7 +1506,7 @@ fs_visitor::visit(ir_constant *ir)
dst_reg.type = src_reg.type;
for (unsigned j = 0; j < size; j++) {
- emit(fs_inst(BRW_OPCODE_MOV, dst_reg, src_reg));
+ emit(BRW_OPCODE_MOV, dst_reg, src_reg);
src_reg.reg_offset++;
dst_reg.reg_offset++;
}
@@ -1554,7 +1521,7 @@ fs_visitor::visit(ir_constant *ir)
dst_reg.type = src_reg.type;
for (unsigned j = 0; j < size; j++) {
- emit(fs_inst(BRW_OPCODE_MOV, dst_reg, src_reg));
+ emit(BRW_OPCODE_MOV, dst_reg, src_reg);
src_reg.reg_offset++;
dst_reg.reg_offset++;
}
@@ -1565,16 +1532,16 @@ fs_visitor::visit(ir_constant *ir)
for (unsigned i = 0; i < size; i++) {
switch (ir->type->base_type) {
case GLSL_TYPE_FLOAT:
- emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])));
+ emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i]));
break;
case GLSL_TYPE_UINT:
- emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])));
+ emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i]));
break;
case GLSL_TYPE_INT:
- emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])));
+ emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i]));
break;
case GLSL_TYPE_BOOL:
- emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])));
+ emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i]));
break;
default:
assert(!"Non-float/uint/int/bool constant");
@@ -1605,40 +1572,39 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
switch (expr->operation) {
case ir_unop_logic_not:
- inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)));
+ inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1));
inst->conditional_mod = BRW_CONDITIONAL_Z;
break;
case ir_binop_logic_xor:
- inst = emit(fs_inst(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]));
+ inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_binop_logic_or:
- inst = emit(fs_inst(BRW_OPCODE_OR, reg_null_d, op[0], op[1]));
+ inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_binop_logic_and:
- inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], op[1]));
+ inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_unop_f2b:
if (intel->gen >= 6) {
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
- op[0], fs_reg(0.0f)));
+ inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f));
} else {
- inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_f, op[0]));
+ inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]);
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_unop_i2b:
if (intel->gen >= 6) {
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)));
+ inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0));
} else {
- inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
+ inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]);
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
@@ -1651,14 +1617,14 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]));
+ inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]);
inst->conditional_mod =
brw_conditional_for_comparison(expr->operation);
break;
default:
assert(!"not reached");
- this->fail = true;
+ fail("bad cond code\n");
break;
}
return;
@@ -1667,11 +1633,10 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
ir->accept(this);
if (intel->gen >= 6) {
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d,
- this->result, fs_reg(1)));
+ fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
} else {
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, this->result));
+ fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result);
inst->conditional_mod = BRW_CONDITIONAL_NZ;
}
}
@@ -1700,36 +1665,36 @@ fs_visitor::emit_if_gen6(ir_if *ir)
switch (expr->operation) {
case ir_unop_logic_not:
- inst = emit(fs_inst(BRW_OPCODE_IF, temp, op[0], fs_reg(0)));
+ inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_Z;
return;
case ir_binop_logic_xor:
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
+ inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]);
inst->conditional_mod = BRW_CONDITIONAL_NZ;
return;
case ir_binop_logic_or:
temp = fs_reg(this, glsl_type::bool_type);
- emit(fs_inst(BRW_OPCODE_OR, temp, op[0], op[1]));
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)));
+ emit(BRW_OPCODE_OR, temp, op[0], op[1]);
+ inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
return;
case ir_binop_logic_and:
temp = fs_reg(this, glsl_type::bool_type);
- emit(fs_inst(BRW_OPCODE_AND, temp, op[0], op[1]));
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)));
+ emit(BRW_OPCODE_AND, temp, op[0], op[1]);
+ inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
return;
case ir_unop_f2b:
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)));
+ inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
return;
case ir_unop_i2b:
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)));
+ inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
return;
@@ -1741,15 +1706,15 @@ fs_visitor::emit_if_gen6(ir_if *ir)
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
+ inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]);
inst->conditional_mod =
brw_conditional_for_comparison(expr->operation);
return;
default:
assert(!"not reached");
- inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)));
+ inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
- this->fail = true;
+ fail("bad condition\n");
return;
}
return;
@@ -1757,7 +1722,7 @@ fs_visitor::emit_if_gen6(ir_if *ir)
ir->condition->accept(this);
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)));
+ fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
}
@@ -1776,7 +1741,7 @@ fs_visitor::visit(ir_if *ir)
} else {
emit_bool_to_cond_code(ir->condition);
- inst = emit(fs_inst(BRW_OPCODE_IF));
+ inst = emit(BRW_OPCODE_IF);
inst->predicated = true;
}
@@ -1788,7 +1753,7 @@ fs_visitor::visit(ir_if *ir)
}
if (!ir->else_instructions.is_empty()) {
- emit(fs_inst(BRW_OPCODE_ELSE));
+ emit(BRW_OPCODE_ELSE);
foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
ir_instruction *ir = (ir_instruction *)iter.get();
@@ -1798,7 +1763,7 @@ fs_visitor::visit(ir_if *ir)
}
}
- emit(fs_inst(BRW_OPCODE_ENDIF));
+ emit(BRW_OPCODE_ENDIF);
}
void
@@ -1815,21 +1780,20 @@ fs_visitor::visit(ir_loop *ir)
this->base_ir = ir->from;
ir->from->accept(this);
- emit(fs_inst(BRW_OPCODE_MOV, counter, this->result));
+ emit(BRW_OPCODE_MOV, counter, this->result);
}
}
- emit(fs_inst(BRW_OPCODE_DO));
+ emit(BRW_OPCODE_DO);
if (ir->to) {
this->base_ir = ir->to;
ir->to->accept(this);
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_cmp,
- counter, this->result));
+ fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result);
inst->conditional_mod = brw_conditional_for_comparison(ir->cmp);
- inst = emit(fs_inst(BRW_OPCODE_BREAK));
+ inst = emit(BRW_OPCODE_BREAK);
inst->predicated = true;
}
@@ -1843,10 +1807,10 @@ fs_visitor::visit(ir_loop *ir)
if (ir->increment) {
this->base_ir = ir->increment;
ir->increment->accept(this);
- emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result));
+ emit(BRW_OPCODE_ADD, counter, counter, this->result);
}
- emit(fs_inst(BRW_OPCODE_WHILE));
+ emit(BRW_OPCODE_WHILE);
}
void
@@ -1854,10 +1818,10 @@ fs_visitor::visit(ir_loop_jump *ir)
{
switch (ir->mode) {
case ir_loop_jump::jump_break:
- emit(fs_inst(BRW_OPCODE_BREAK));
+ emit(BRW_OPCODE_BREAK);
break;
case ir_loop_jump::jump_continue:
- emit(fs_inst(BRW_OPCODE_CONTINUE));
+ emit(BRW_OPCODE_CONTINUE);
break;
}
}
@@ -1923,23 +1887,13 @@ void
fs_visitor::emit_dummy_fs()
{
/* Everyone's favorite color. */
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(MRF, 2),
- fs_reg(1.0f)));
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(MRF, 3),
- fs_reg(0.0f)));
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(MRF, 4),
- fs_reg(1.0f)));
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(MRF, 5),
- fs_reg(0.0f)));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f));
fs_inst *write;
- write = emit(fs_inst(FS_OPCODE_FB_WRITE,
- fs_reg(0),
- fs_reg(0)));
+ write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
write->base_mrf = 0;
}
@@ -1969,14 +1923,14 @@ fs_visitor::emit_interpolation_setup_gen4()
this->pixel_y = fs_reg(this, glsl_type::uint_type);
this->pixel_x.type = BRW_REGISTER_TYPE_UW;
this->pixel_y.type = BRW_REGISTER_TYPE_UW;
- emit(fs_inst(BRW_OPCODE_ADD,
- this->pixel_x,
- fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
- fs_reg(brw_imm_v(0x10101010))));
- emit(fs_inst(BRW_OPCODE_ADD,
- this->pixel_y,
- fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
- fs_reg(brw_imm_v(0x11001100))));
+ emit(BRW_OPCODE_ADD,
+ this->pixel_x,
+ fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010)));
+ emit(BRW_OPCODE_ADD,
+ this->pixel_y,
+ fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100)));
this->current_annotation = "compute pixel deltas from v0";
if (brw->has_pln) {
@@ -1987,22 +1941,18 @@ fs_visitor::emit_interpolation_setup_gen4()
this->delta_x = fs_reg(this, glsl_type::float_type);
this->delta_y = fs_reg(this, glsl_type::float_type);
}
- emit(fs_inst(BRW_OPCODE_ADD,
- this->delta_x,
- this->pixel_x,
- fs_reg(negate(brw_vec1_grf(1, 0)))));
- emit(fs_inst(BRW_OPCODE_ADD,
- this->delta_y,
- this->pixel_y,
- fs_reg(negate(brw_vec1_grf(1, 1)))));
+ emit(BRW_OPCODE_ADD, this->delta_x,
+ this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0))));
+ emit(BRW_OPCODE_ADD, this->delta_y,
+ this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1))));
this->current_annotation = "compute pos.w and 1/pos.w";
/* Compute wpos.w. It's always in our setup, since it's needed to
* interpolate the other attributes.
*/
this->wpos_w = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
- interp_reg(FRAG_ATTRIB_WPOS, 3)));
+ emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
+ interp_reg(FRAG_ATTRIB_WPOS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = fs_reg(this, glsl_type::float_type);
emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
@@ -2021,14 +1971,14 @@ fs_visitor::emit_interpolation_setup_gen6()
fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
int_pixel_x.type = BRW_REGISTER_TYPE_UW;
int_pixel_y.type = BRW_REGISTER_TYPE_UW;
- emit(fs_inst(BRW_OPCODE_ADD,
- int_pixel_x,
- fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
- fs_reg(brw_imm_v(0x10101010))));
- emit(fs_inst(BRW_OPCODE_ADD,
- int_pixel_y,
- fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
- fs_reg(brw_imm_v(0x11001100))));
+ emit(BRW_OPCODE_ADD,
+ int_pixel_x,
+ fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010)));
+ emit(BRW_OPCODE_ADD,
+ int_pixel_y,
+ fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100)));
/* As of gen6, we can no longer mix float and int sources. We have
* to turn the integer pixel centers into floats for their actual
@@ -2036,13 +1986,13 @@ fs_visitor::emit_interpolation_setup_gen6()
*/
this->pixel_x = fs_reg(this, glsl_type::float_type);
this->pixel_y = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x));
- emit(fs_inst(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y));
+ emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x);
+ emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y);
- this->current_annotation = "compute 1/pos.w";
- this->wpos_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
- this->pixel_w = fs_reg(this, glsl_type::float_type);
- emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
+ this->current_annotation = "compute pos.w";
+ this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
+ this->wpos_w = fs_reg(this, glsl_type::float_type);
+ emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w);
this->delta_x = fs_reg(brw_vec8_grf(2, 0));
this->delta_y = fs_reg(brw_vec8_grf(3, 0));
@@ -2069,8 +2019,8 @@ fs_visitor::emit_fb_writes()
}
if (c->aa_dest_stencil_reg) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
- fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
+ fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0)));
}
/* Reserve space for color. It'll be filled in per MRT below. */
@@ -2083,17 +2033,17 @@ fs_visitor::emit_fb_writes()
assert(this->frag_depth);
fs_reg depth = *(variable_storage(this->frag_depth));
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth);
} else {
/* Pass through the payload depth. */
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
- fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
+ fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
}
}
if (c->dest_depth_reg) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
- fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
+ fs_reg(brw_vec8_grf(c->dest_depth_reg, 0)));
}
fs_reg color = reg_undef;
@@ -2110,9 +2060,7 @@ fs_visitor::emit_fb_writes()
target);
if (this->frag_color || this->frag_data) {
for (int i = 0; i < 4; i++) {
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(MRF, color_mrf + i),
- color));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, color_mrf + i), color);
color.reg_offset++;
}
}
@@ -2120,8 +2068,7 @@ fs_visitor::emit_fb_writes()
if (this->frag_color)
color.reg_offset -= 4;
- fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
- reg_undef, reg_undef));
+ fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->target = target;
inst->base_mrf = 0;
inst->mlen = nr;
@@ -2137,13 +2084,10 @@ fs_visitor::emit_fb_writes()
* renderbuffer.
*/
color.reg_offset += 3;
- emit(fs_inst(BRW_OPCODE_MOV,
- fs_reg(MRF, color_mrf + 3),
- color));
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, color_mrf + 3), color);
}
- fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
- reg_undef, reg_undef));
+ fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->base_mrf = 0;
inst->mlen = nr;
inst->eot = true;
@@ -2868,8 +2812,7 @@ fs_visitor::calculate_live_intervals()
if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
int reg = inst->src[i].reg;
- if (!loop_depth || (this->virtual_grf_sizes[reg] == 1 &&
- def[reg] >= bb_header_ip)) {
+ if (!loop_depth) {
use[reg] = ip;
} else {
def[reg] = MIN2(loop_start, def[reg]);
@@ -2885,8 +2828,7 @@ fs_visitor::calculate_live_intervals()
if (inst->dst.file == GRF && inst->dst.reg != 0) {
int reg = inst->dst.reg;
- if (!loop_depth || (this->virtual_grf_sizes[reg] == 1 &&
- !inst->predicated)) {
+ if (!loop_depth) {
def[reg] = MIN2(def[reg], ip);
} else {
def[reg] = MIN2(def[reg], loop_start);
@@ -2996,12 +2938,41 @@ fs_visitor::propagate_constants()
progress = true;
}
break;
+
case BRW_OPCODE_CMP:
+ if (i == 1) {
+ scan_inst->src[i] = inst->src[0];
+ progress = true;
+ } else if (i == 0 && scan_inst->src[1].file != IMM) {
+ uint32_t new_cmod;
+
+ new_cmod = brw_swap_cmod(scan_inst->conditional_mod);
+ if (new_cmod != ~0u) {
+ /* Fit this constant in by swapping the operands and
+ * flipping the test
+ */
+ scan_inst->src[0] = scan_inst->src[1];
+ scan_inst->src[1] = inst->src[0];
+ scan_inst->conditional_mod = new_cmod;
+ progress = true;
+ }
+ }
+ break;
+
case BRW_OPCODE_SEL:
if (i == 1) {
scan_inst->src[i] = inst->src[0];
progress = true;
+ } else if (i == 0 && scan_inst->src[1].file != IMM) {
+ /* Fit this constant in by swapping the operands and
+ * flipping the predicate
+ */
+ scan_inst->src[0] = scan_inst->src[1];
+ scan_inst->src[1] = inst->src[0];
+ scan_inst->predicate_inverse = !scan_inst->predicate_inverse;
+ progress = true;
}
+ break;
}
}
@@ -3487,6 +3458,7 @@ fs_visitor::generate_code()
brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicated);
+ brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
switch (inst->opcode) {
@@ -3677,7 +3649,7 @@ fs_visitor::generate_code()
} else {
_mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
}
- this->fail = true;
+ fail("unsupported opcode in FS\n");
}
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
@@ -3808,18 +3780,18 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
v.assign_regs_trivial();
else {
while (!v.assign_regs()) {
- if (v.fail)
+ if (v.failed)
break;
}
}
}
- if (!v.fail)
+ if (!v.failed)
v.generate_code();
- assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
+ assert(!v.failed); /* FINISHME: Cleanly fail, tested at link time, etc. */
- if (v.fail)
+ if (v.failed)
return GL_FALSE;
c->prog_data.total_grf = v.grf_used;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index dc030ae5b50..f792906cfe7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -331,6 +331,7 @@ public:
fs_reg src[3];
bool saturate;
bool predicated;
+ bool predicate_inverse;
int conditional_mod; /**< BRW_CONDITIONAL_* */
int mlen; /**< SEND message length */
@@ -364,7 +365,7 @@ public:
this->ctx = &intel->ctx;
this->mem_ctx = ralloc_context(NULL);
this->shader = shader;
- this->fail = false;
+ this->failed = false;
this->variable_ht = hash_table_ctor(0,
hash_table_pointer_hash,
hash_table_pointer_compare);
@@ -432,6 +433,32 @@ public:
void visit(ir_function_signature *ir);
fs_inst *emit(fs_inst inst);
+
+ fs_inst *emit(int opcode)
+ {
+ return emit(fs_inst(opcode));
+ }
+
+ fs_inst *emit(int opcode, fs_reg dst)
+ {
+ return emit(fs_inst(opcode, dst));
+ }
+
+ fs_inst *emit(int opcode, fs_reg dst, fs_reg src0)
+ {
+ return emit(fs_inst(opcode, dst, src0));
+ }
+
+ fs_inst *emit(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
+ {
+ return emit(fs_inst(opcode, dst, src0, src1));
+ }
+
+ fs_inst *emit(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
+ {
+ return emit(fs_inst(opcode, dst, src0, src1, src2));
+ }
+
void setup_paramvalues_refs();
void assign_curb_setup();
void calculate_urb_setup();
@@ -450,6 +477,7 @@ public:
bool remove_duplicate_mrf_writes();
bool virtual_grf_interferes(int a, int b);
void schedule_instructions();
+ void fail(const char *msg, ...);
void generate_code();
void generate_fb_write(fs_inst *inst);
@@ -523,7 +551,7 @@ public:
ir_instruction *base_ir;
/** @} */
- bool fail;
+ bool failed;
/* Result of last visit() method. */
fs_reg result;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index f0277423170..67f29ce1816 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -119,8 +119,7 @@ fs_visitor::assign_regs()
}
if (i == class_count) {
if (this->virtual_grf_sizes[r] >= base_reg_count) {
- fprintf(stderr, "Object too large to register allocate.\n");
- this->fail = true;
+ fail("Object too large to register allocate.\n");
}
class_sizes[class_count++] = this->virtual_grf_sizes[r];
@@ -226,8 +225,9 @@ fs_visitor::assign_regs()
* loop back into here to try again.
*/
int reg = choose_spill_reg(g);
- if (reg == -1 || intel->gen >= 6) {
- this->fail = true;
+
+ if (reg == -1) {
+ fail("no register to spill\n");
} else {
spill_reg(reg);
}
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 70c451d071d..14ee6767cd5 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -83,45 +83,23 @@ static void compile_gs_prog( struct brw_context *brw,
/* Note that primitives which don't require a GS program have
* already been weeded out by this stage:
*/
+
+ /* Gen6: VF has already converted into polygon, and LINELOOP is
+ * converted to LINESTRIP at the beginning of the 3D pipeline.
+ */
+ if (intel->gen == 6)
+ return;
+
switch (key->primitive) {
case GL_QUADS:
- /* Gen6: VF has already converted into polygon. */
- if (intel->gen == 6)
- return;
brw_gs_quads( &c, key );
break;
case GL_QUAD_STRIP:
- if (intel->gen == 6)
- return;
brw_gs_quad_strip( &c, key );
break;
case GL_LINE_LOOP:
- /* Gen6: LINELOOP is converted to LINESTRIP at the beginning of the 3D pipeline */
- if (intel->gen == 6)
- return;
brw_gs_lines( &c );
break;
- case GL_LINES:
- if (key->hint_gs_always)
- brw_gs_lines( &c );
- else {
- return;
- }
- break;
- case GL_TRIANGLES:
- if (key->hint_gs_always)
- brw_gs_tris( &c );
- else {
- return;
- }
- break;
- case GL_POINTS:
- if (key->hint_gs_always)
- brw_gs_points( &c );
- else {
- return;
- }
- break;
default:
return;
}
@@ -170,7 +148,6 @@ static void populate_key( struct brw_context *brw,
{
struct gl_context *ctx = &brw->intel.ctx;
struct intel_context *intel = &brw->intel;
- int prim_gs_always;
memset(key, 0, sizeof(*key));
@@ -180,8 +157,6 @@ static void populate_key( struct brw_context *brw,
/* BRW_NEW_PRIMITIVE */
key->primitive = gs_prim[brw->primitive];
- key->hint_gs_always = 0; /* debug code? */
-
/* _NEW_LIGHT */
key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
if (key->primitive == GL_QUADS && ctx->Light.ShadeModel != GL_FLAT) {
@@ -191,14 +166,11 @@ static void populate_key( struct brw_context *brw,
key->pv_first = GL_TRUE;
}
- if (intel->gen == 6)
- prim_gs_always = 0;
- else
- prim_gs_always = brw->primitive == GL_QUADS ||
- brw->primitive == GL_QUAD_STRIP ||
- brw->primitive == GL_LINE_LOOP;
-
- key->need_gs_prog = (key->hint_gs_always || prim_gs_always);
+ key->need_gs_prog = (intel->gen == 6)
+ ? 0
+ : (brw->primitive == GL_QUADS ||
+ brw->primitive == GL_QUAD_STRIP ||
+ brw->primitive == GL_LINE_LOOP);
}
/* Calculate interpolants for triangle and line rasterization.
diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h
index 7e3531086f9..c33528e4577 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.h
+++ b/src/mesa/drivers/dri/i965/brw_gs.h
@@ -42,10 +42,9 @@
struct brw_gs_prog_key {
GLbitfield64 attrs;
GLuint primitive:4;
- GLuint hint_gs_always:1;
GLuint pv_first:1;
GLuint need_gs_prog:1;
- GLuint pad:25;
+ GLuint pad:26;
};
struct brw_gs_compile {
@@ -70,8 +69,6 @@ struct brw_gs_compile {
void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key );
void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key );
-void brw_gs_tris( struct brw_gs_compile *c );
void brw_gs_lines( struct brw_gs_compile *c );
-void brw_gs_points( struct brw_gs_compile *c );
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index e1f751fdaa4..3bb526b63af 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -193,19 +193,6 @@ void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
}
}
-void brw_gs_tris( struct brw_gs_compile *c )
-{
- struct intel_context *intel = &c->func.brw->intel;
-
- brw_gs_alloc_regs(c, 3);
-
- if (intel->needs_ff_sync)
- brw_gs_ff_sync(c, 1);
- brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_TRILIST << 2) | R02_PRIM_START));
- brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_TRILIST << 2));
- brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_TRILIST << 2) | R02_PRIM_END));
-}
-
void brw_gs_lines( struct brw_gs_compile *c )
{
struct intel_context *intel = &c->func.brw->intel;
@@ -217,22 +204,3 @@ void brw_gs_lines( struct brw_gs_compile *c )
brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_START));
brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_END));
}
-
-void brw_gs_points( struct brw_gs_compile *c )
-{
- struct intel_context *intel = &c->func.brw->intel;
-
- brw_gs_alloc_regs(c, 1);
-
- if (intel->needs_ff_sync)
- brw_gs_ff_sync(c, 1);
- brw_gs_emit_vue(c, c->reg.vertex[0], 1, ((_3DPRIM_POINTLIST << 2) | R02_PRIM_START | R02_PRIM_END));
-}
-
-
-
-
-
-
-
-
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c768be23fa7..19eea07ebc6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -149,7 +149,8 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
else
OUT_BATCH(0);
OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
- OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ brw->sf.state_offset);
OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->cc.state_offset);
@@ -247,8 +248,7 @@ static void emit_depthbuffer(struct brw_context *brw)
}
assert(region->tiling != I915_TILING_X);
- if (intel->gen >= 6)
- assert(region->tiling != I915_TILING_NONE);
+ assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
@@ -283,6 +283,9 @@ static void emit_depthbuffer(struct brw_context *brw)
}
}
+/**
+ * \see brw_context.state.depth_region
+ */
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
.mesa = 0,
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index ee68095fceb..6674f1640c8 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -134,11 +134,6 @@ static GLboolean brwProgramStringNotify( struct gl_context *ctx,
brw_fragment_program_const(brw->fragment_program);
struct gl_shader_program *shader_program;
- if (fprog->FogOption) {
- _mesa_append_fog_code(ctx, fprog);
- fprog->FogOption = GL_NONE;
- }
-
if (newFP == curFP)
brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
newFP->id = brw->program_id++;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index bd3a21ed9e2..66d91a0bde7 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -38,14 +38,16 @@
static void upload_sf_vp(struct brw_context *brw)
{
+ struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &brw->intel.ctx;
const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
- struct brw_sf_viewport sfv;
+ struct brw_sf_viewport *sfv;
GLfloat y_scale, y_bias;
const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
const GLfloat *v = ctx->Viewport._WindowMap.m;
- memset(&sfv, 0, sizeof(sfv));
+ sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
+ memset(sfv, 0, sizeof(*sfv));
if (render_to_fbo) {
y_scale = 1.0;
@@ -58,12 +60,12 @@ static void upload_sf_vp(struct brw_context *brw)
/* _NEW_VIEWPORT */
- sfv.viewport.m00 = v[MAT_SX];
- sfv.viewport.m11 = v[MAT_SY] * y_scale;
- sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
- sfv.viewport.m30 = v[MAT_TX];
- sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
- sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
+ sfv->viewport.m00 = v[MAT_SX];
+ sfv->viewport.m11 = v[MAT_SY] * y_scale;
+ sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
+ sfv->viewport.m30 = v[MAT_TX];
+ sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
+ sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
/* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
* for DrawBuffer->_[XY]{min,max}
@@ -85,27 +87,31 @@ static void upload_sf_vp(struct brw_context *brw)
* anything. Instead, just provide a min > max scissor inside
* the bounds, which produces the expected no rendering.
*/
- sfv.scissor.xmin = 1;
- sfv.scissor.xmax = 0;
- sfv.scissor.ymin = 1;
- sfv.scissor.ymax = 0;
+ sfv->scissor.xmin = 1;
+ sfv->scissor.xmax = 0;
+ sfv->scissor.ymin = 1;
+ sfv->scissor.ymax = 0;
} else if (render_to_fbo) {
/* texmemory: Y=0=bottom */
- sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
- sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
- sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
- sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
+ sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
+ sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
+ sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
+ sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
}
else {
/* memory: Y=0=top */
- sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
- sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
- sfv.scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
- sfv.scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
+ sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
+ sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
+ sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
+ sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
}
+ /* Keep a pointer to it for brw_state_dump.c */
drm_intel_bo_unreference(brw->sf.vp_bo);
- brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP, &sfv, sizeof(sfv));
+ drm_intel_bo_reference(intel->batch.bo);
+ brw->sf.vp_bo = intel->batch.bo;
+
+ brw->state.dirty.cache |= CACHE_NEW_SF_VP;
}
const struct brw_tracked_state brw_sf_vp = {
@@ -113,92 +119,44 @@ const struct brw_tracked_state brw_sf_vp = {
.mesa = (_NEW_VIEWPORT |
_NEW_SCISSOR |
_NEW_BUFFERS),
- .brw = 0,
+ .brw = BRW_NEW_BATCH,
.cache = 0
},
.prepare = upload_sf_vp
};
-struct brw_sf_unit_key {
- unsigned int total_grf;
- unsigned int urb_entry_read_length;
-
- unsigned int nr_urb_entries, urb_size, sfsize;
-
- GLenum front_face, cull_face;
- unsigned pv_first:1;
- unsigned scissor:1;
- unsigned line_smooth:1;
- unsigned point_sprite:1;
- unsigned use_vs_point_size:1;
- unsigned render_to_fbo:1;
- float line_width;
- float point_size;
-};
-
-static void
-sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
-{
- struct gl_context *ctx = &brw->intel.ctx;
- memset(key, 0, sizeof(*key));
-
- /* CACHE_NEW_SF_PROG */
- key->total_grf = brw->sf.prog_data->total_grf;
- key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
-
- /* BRW_NEW_URB_FENCE */
- key->nr_urb_entries = brw->urb.nr_sf_entries;
- key->urb_size = brw->urb.vsize;
- key->sfsize = brw->urb.sfsize;
-
- key->scissor = ctx->Scissor.Enabled;
- key->front_face = ctx->Polygon.FrontFace;
-
- if (ctx->Polygon.CullFlag)
- key->cull_face = ctx->Polygon.CullFaceMode;
- else
- key->cull_face = GL_NONE;
-
- key->line_width = ctx->Line.Width;
- key->line_smooth = ctx->Line.SmoothFlag;
-
- key->point_sprite = ctx->Point.PointSprite;
- key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
- key->use_vs_point_size = (ctx->VertexProgram.PointSizeEnabled ||
- ctx->Point._Attenuated);
-
- /* _NEW_LIGHT */
- key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
-
- key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
-}
-
-static drm_intel_bo *
-sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
- drm_intel_bo **reloc_bufs)
+static void upload_sf_unit( struct brw_context *brw )
{
struct intel_context *intel = &brw->intel;
- struct brw_sf_unit_state sf;
- drm_intel_bo *bo;
+ struct gl_context *ctx = &intel->ctx;
+ struct brw_sf_unit_state *sf;
+ drm_intel_bo *bo = intel->batch.bo;
int chipset_max_threads;
- memset(&sf, 0, sizeof(sf));
+ bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+
+ sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
- sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
- sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
+ memset(sf, 0, sizeof(*sf));
+
+ /* CACHE_NEW_SF_PROG */
+ sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
+ sf->thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
- sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+ sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
- sf.thread3.dispatch_grf_start_reg = 3;
+ sf->thread3.dispatch_grf_start_reg = 3;
if (intel->gen == 5)
- sf.thread3.urb_entry_read_offset = 3;
+ sf->thread3.urb_entry_read_offset = 3;
else
- sf.thread3.urb_entry_read_offset = 1;
+ sf->thread3.urb_entry_read_offset = 1;
- sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
+ /* CACHE_NEW_SF_PROG */
+ sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
- sf.thread4.nr_urb_entries = key->nr_urb_entries;
- sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
+ /* BRW_NEW_URB_FENCE */
+ sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
+ sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
/* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
* 48 (Ironlake) threads.
@@ -208,46 +166,51 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
else
chipset_max_threads = 24;
- sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
+ /* BRW_NEW_URB_FENCE */
+ sf->thread4.max_threads = MIN2(chipset_max_threads,
+ brw->urb.nr_sf_entries) - 1;
if (unlikely(INTEL_DEBUG & DEBUG_SINGLE_THREAD))
- sf.thread4.max_threads = 0;
+ sf->thread4.max_threads = 0;
if (unlikely(INTEL_DEBUG & DEBUG_STATS))
- sf.thread4.stats_enable = 1;
+ sf->thread4.stats_enable = 1;
/* CACHE_NEW_SF_VP */
- sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
+ sf->sf5.sf_viewport_state_offset = (brw->sf.vp_bo->offset +
+ brw->sf.vp_offset) >> 5; /* reloc */
- sf.sf5.viewport_transform = 1;
+ sf->sf5.viewport_transform = 1;
/* _NEW_SCISSOR */
- if (key->scissor)
- sf.sf6.scissor = 1;
+ if (ctx->Scissor.Enabled)
+ sf->sf6.scissor = 1;
/* _NEW_POLYGON */
- if (key->front_face == GL_CCW)
- sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
+ if (ctx->Polygon.FrontFace == GL_CCW)
+ sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
else
- sf.sf5.front_winding = BRW_FRONTWINDING_CW;
+ sf->sf5.front_winding = BRW_FRONTWINDING_CW;
- /* The viewport is inverted for rendering to a FBO, and that inverts
+ /* _NEW_BUFFERS
+ * The viewport is inverted for rendering to a FBO, and that inverts
* polygon front/back orientation.
*/
- sf.sf5.front_winding ^= key->render_to_fbo;
+ sf->sf5.front_winding ^= render_to_fbo;
- switch (key->cull_face) {
+ /* _NEW_POLYGON */
+ switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
case GL_FRONT:
- sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
+ sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
break;
case GL_BACK:
- sf.sf6.cull_mode = BRW_CULLMODE_BACK;
+ sf->sf6.cull_mode = BRW_CULLMODE_BACK;
break;
case GL_FRONT_AND_BACK:
- sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
+ sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
break;
case GL_NONE:
- sf.sf6.cull_mode = BRW_CULLMODE_NONE;
+ sf->sf6.cull_mode = BRW_CULLMODE_NONE;
break;
default:
assert(0);
@@ -256,19 +219,18 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
/* _NEW_LINE */
/* XXX use ctx->Const.Min/MaxLineWidth here */
- sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
+ sf->sf6.line_width = CLAMP(ctx->Line.Width, 1.0, 5.0) * (1<<1);
- sf.sf6.line_endcap_aa_region_width = 1;
- if (key->line_smooth)
- sf.sf6.aa_enable = 1;
- else if (sf.sf6.line_width <= 0x2)
- sf.sf6.line_width = 0;
+ sf->sf6.line_endcap_aa_region_width = 1;
+ if (ctx->Line.SmoothFlag)
+ sf->sf6.aa_enable = 1;
+ else if (sf->sf6.line_width <= 0x2)
+ sf->sf6.line_width = 0;
/* _NEW_BUFFERS */
- key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
- if (!key->render_to_fbo) {
+ if (!render_to_fbo) {
/* Rendering to an OpenGL window */
- sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
+ sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
}
else {
/* If rendering to an FBO, the pixel coordinate system is
@@ -290,74 +252,56 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
* incorrectly, which is no worse than occurs without
* the value, so we're using it here.
*/
- sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
+ sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
}
/* XXX clamp max depends on AA vs. non-AA */
/* _NEW_POINT */
- sf.sf7.sprite_point = key->point_sprite;
- sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
- sf.sf7.use_point_size_state = !key->use_vs_point_size;
- sf.sf7.aa_line_distance_mode = 0;
+ sf->sf7.sprite_point = ctx->Point.PointSprite;
+ sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
+ ctx->Point.MinSize,
+ ctx->Point.MaxSize)), 1, 255) * (1<<3);
+ sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
+ ctx->Point._Attenuated);
+ sf->sf7.aa_line_distance_mode = 0;
/* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
+ * _NEW_LIGHT
*/
- if (!key->pv_first) {
- sf.sf7.trifan_pv = 2;
- sf.sf7.linestrip_pv = 1;
- sf.sf7.tristrip_pv = 2;
+ if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
+ sf->sf7.trifan_pv = 2;
+ sf->sf7.linestrip_pv = 1;
+ sf->sf7.tristrip_pv = 2;
} else {
- sf.sf7.trifan_pv = 1;
- sf.sf7.linestrip_pv = 0;
- sf.sf7.tristrip_pv = 0;
+ sf->sf7.trifan_pv = 1;
+ sf->sf7.linestrip_pv = 0;
+ sf->sf7.tristrip_pv = 0;
}
- sf.sf7.line_last_pixel_enable = 0;
+ sf->sf7.line_last_pixel_enable = 0;
/* Set bias for OpenGL rasterization rules:
*/
- sf.sf6.dest_org_vbias = 0x8;
- sf.sf6.dest_org_hbias = 0x8;
-
- bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
- key, sizeof(*key),
- reloc_bufs, 2,
- &sf, sizeof(sf));
+ sf->sf6.dest_org_vbias = 0x8;
+ sf->sf6.dest_org_hbias = 0x8;
/* STATE_PREFETCH command description describes this state as being
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
*/
/* Emit SF program relocation */
- drm_intel_bo_emit_reloc(bo, offsetof(struct brw_sf_unit_state, thread0),
- brw->sf.prog_bo, sf.thread0.grf_reg_count << 1,
+ drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
+ offsetof(struct brw_sf_unit_state, thread0)),
+ brw->sf.prog_bo, sf->thread0.grf_reg_count << 1,
I915_GEM_DOMAIN_INSTRUCTION, 0);
/* Emit SF viewport relocation */
- drm_intel_bo_emit_reloc(bo, offsetof(struct brw_sf_unit_state, sf5),
- brw->sf.vp_bo, (sf.sf5.front_winding |
- (sf.sf5.viewport_transform << 1)),
+ drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
+ offsetof(struct brw_sf_unit_state, sf5)),
+ intel->batch.bo, (brw->sf.vp_offset |
+ sf->sf5.front_winding |
+ (sf->sf5.viewport_transform << 1)),
I915_GEM_DOMAIN_INSTRUCTION, 0);
- return bo;
-}
-
-static void upload_sf_unit( struct brw_context *brw )
-{
- struct brw_sf_unit_key key;
- drm_intel_bo *reloc_bufs[2];
-
- sf_unit_populate_key(brw, &key);
-
- reloc_bufs[0] = brw->sf.prog_bo;
- reloc_bufs[1] = brw->sf.vp_bo;
-
- drm_intel_bo_unreference(brw->sf.state_bo);
- brw->sf.state_bo = brw_search_cache(&brw->cache, BRW_SF_UNIT,
- &key, sizeof(key),
- reloc_bufs, 2,
- NULL);
- if (brw->sf.state_bo == NULL) {
- brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
- }
+ brw->state.dirty.cache |= CACHE_NEW_SF_UNIT;
}
const struct brw_tracked_state brw_sf_unit = {
@@ -368,7 +312,8 @@ const struct brw_tracked_state brw_sf_unit = {
_NEW_POINT |
_NEW_SCISSOR |
_NEW_BUFFERS),
- .brw = BRW_NEW_URB_FENCE,
+ .brw = (BRW_NEW_BATCH |
+ BRW_NEW_URB_FENCE),
.cache = (CACHE_NEW_SF_VP |
CACHE_NEW_SF_PROG)
},
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
index fdce79da2f4..b393259c915 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -195,8 +195,8 @@ static void dump_sf_viewport_state(struct brw_context *brw)
drm_intel_bo_map(brw->sf.vp_bo, GL_FALSE);
- vp = brw->sf.vp_bo->virtual;
- vp_off = brw->sf.vp_bo->offset;
+ vp = brw->sf.vp_bo->virtual + brw->sf.vp_offset;
+ vp_off = brw->sf.vp_bo->offset + brw->sf.vp_offset;
state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
state_out(name, vp, vp_off, 1, "m11 = %f\n", vp->viewport.m11);
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 6687a89e80a..8d4797fb675 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -80,25 +80,6 @@ struct brw_3d_control
GLuint dword3;
};
-
-struct brw_3d_primitive
-{
- struct
- {
- GLuint length:8;
- GLuint pad:2;
- GLuint topology:5;
- GLuint indexed:1;
- GLuint opcode:16;
- } header;
-
- GLuint verts_per_instance;
- GLuint start_vert_location;
- GLuint instance_count;
- GLuint start_instance_location;
- GLuint base_vert_location;
-};
-
/* These seem to be passed around as function args, so it works out
* better to keep them as #defines:
*/
@@ -1247,31 +1228,6 @@ struct brw_surface_state
};
-
-struct brw_vertex_buffer_state
-{
- struct {
- GLuint pitch:11;
- GLuint pad:15;
- GLuint access_type:1;
- GLuint vb_index:5;
- } vb0;
-
- GLuint start_addr;
- GLuint max_index;
-#if 1
- GLuint instance_data_step_rate; /* not included for sequential/random vertices? */
-#endif
-};
-
-#define BRW_VBP_MAX 17
-
-struct brw_vb_array_state {
- struct header header;
- struct brw_vertex_buffer_state vb[BRW_VBP_MAX];
-};
-
-
struct brw_vertex_element_state
{
struct
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 6ae75d22c14..63ae13191f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -132,6 +132,9 @@ static void brw_upload_vs_prog(struct brw_context *brw)
ctx->Polygon.BackMode != GL_FILL);
key.two_side_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
+ /* _NEW_LIGHT | _NEW_BUFFERS */
+ key.clamp_vertex_color = ctx->Light._ClampVertexColor;
+
/* _NEW_POINT */
if (ctx->Point.PointSprite) {
for (i = 0; i < 8; i++) {
@@ -158,7 +161,8 @@ static void brw_upload_vs_prog(struct brw_context *brw)
*/
const struct brw_tracked_state brw_vs_prog = {
.dirty = {
- .mesa = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT,
+ .mesa = (_NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT |
+ _NEW_BUFFERS),
.brw = BRW_NEW_VERTEX_PROGRAM,
.cache = 0
},
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h
index 0b88cc1ec76..7ca84a54b01 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -45,6 +45,7 @@ struct brw_vs_prog_key {
GLuint copy_edgeflag:1;
GLuint point_coord_replace:8;
GLuint two_side_color: 1;
+ GLuint clamp_vertex_color:1;
};
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index acacf374b75..dd4e1e6c6ad 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -437,8 +437,14 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
if (c->key.nr_userclip)
header_regs += 2;
+ /* Each attribute is 16 bytes (1 vec4), so dividing by 8 gives us the
+ * number of 128-byte (1024-bit) units.
+ */
c->prog_data.urb_entry_size = (attributes_in_vue + header_regs + 7) / 8;
} else if (intel->gen == 5)
+ /* Each attribute is 16 bytes (1 vec4), so dividing by 4 gives us the
+ * number of 64-byte (512-bit) units.
+ */
c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
else
c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
@@ -2215,7 +2221,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
* instructions. Instead, we directly modify the header
* of the last (already stored) instruction.
*/
- if (inst->DstReg.File == PROGRAM_OUTPUT) {
+ if (inst->DstReg.File == PROGRAM_OUTPUT &&
+ c->key.clamp_vertex_color) {
if ((inst->DstReg.Index == VERT_RESULT_COL0)
|| (inst->DstReg.Index == VERT_RESULT_COL1)
|| (inst->DstReg.Index == VERT_RESULT_BFC0)
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 152ee141568..ce8712a260f 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -115,13 +115,11 @@ static void brw_set_draw_region( struct intel_context *intel,
{
struct brw_context *brw = brw_context(&intel->ctx);
- /* release old color/depth regions */
- if (brw->state.depth_region != depth_region)
+ if (brw->state.depth_region != depth_region) {
brw->state.dirty.brw |= BRW_NEW_DEPTH_BUFFER;
- intel_region_release(&brw->state.depth_region);
-
- /* reference new color/depth regions */
- intel_region_reference(&brw->state.depth_region, depth_region);
+ intel_region_release(&brw->state.depth_region);
+ intel_region_reference(&brw->state.depth_region, depth_region);
+ }
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index ca51d1599a4..65af227d831 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -185,6 +185,7 @@ static void do_wm_prog( struct brw_context *brw,
struct brw_fragment_program *fp,
struct brw_wm_prog_key *key)
{
+ struct intel_context *intel = &brw->intel;
struct brw_wm_compile *c;
const GLuint *program;
GLuint program_size;
@@ -238,12 +239,26 @@ static void do_wm_prog( struct brw_context *brw,
/* Scratch space is used for register spilling */
if (c->last_scratch) {
+ uint32_t total_scratch;
+
/* Per-thread scratch space is power-of-two sized. */
for (c->prog_data.total_scratch = 1024;
c->prog_data.total_scratch <= c->last_scratch;
c->prog_data.total_scratch *= 2) {
/* empty */
}
+ total_scratch = c->prog_data.total_scratch * brw->wm_max_threads;
+
+ if (brw->wm.scratch_bo && total_scratch > brw->wm.scratch_bo->size) {
+ drm_intel_bo_unreference(brw->wm.scratch_bo);
+ brw->wm.scratch_bo = NULL;
+ }
+ if (brw->wm.scratch_bo == NULL) {
+ brw->wm.scratch_bo = drm_intel_bo_alloc(intel->bufmgr,
+ "wm scratch",
+ total_scratch,
+ 4096);
+ }
}
else {
c->prog_data.total_scratch = 0;
@@ -348,6 +363,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
/* _NEW_HINT */
key->linear_color = (ctx->Hint.PerspectiveCorrection == GL_FASTEST);
+ /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
+ key->clamp_fragment_color = ctx->Color._ClampFragmentColor;
+
/* _NEW_TEXTURE */
for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
@@ -370,14 +388,14 @@ static void brw_wm_populate_key( struct brw_context *brw,
* well and our shadow compares always return the result in
* all 4 channels.
*/
- if (t->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB) {
- if (t->DepthMode == GL_ALPHA) {
+ if (t->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB) {
+ if (t->Sampler.DepthMode == GL_ALPHA) {
swizzles[0] = SWIZZLE_ZERO;
swizzles[1] = SWIZZLE_ZERO;
swizzles[2] = SWIZZLE_ZERO;
- } else if (t->DepthMode == GL_LUMINANCE) {
+ } else if (t->Sampler.DepthMode == GL_LUMINANCE) {
swizzles[3] = SWIZZLE_ONE;
- } else if (t->DepthMode == GL_RED) {
+ } else if (t->Sampler.DepthMode == GL_RED) {
/* See table 3.23 of the GL 3.0 spec. */
swizzles[1] = SWIZZLE_ZERO;
swizzles[2] = SWIZZLE_ZERO;
@@ -471,6 +489,7 @@ const struct brw_tracked_state brw_wm_prog = {
_NEW_POLYGON |
_NEW_LINE |
_NEW_LIGHT |
+ _NEW_FRAG_CLAMP |
_NEW_BUFFERS |
_NEW_TEXTURE),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index c40d7bfae0a..40659f26025 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -65,6 +65,7 @@ struct brw_wm_prog_key {
GLuint nr_color_regions:5;
GLuint render_to_fbo:1;
GLuint alpha_test:1;
+ GLuint clamp_fragment_color:1;
GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
GLuint shadowtex_mask:16;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index ecfd21d4399..cdc1f367e5c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1408,6 +1408,9 @@ void emit_fb_write(struct brw_wm_compile *c,
*/
brw_push_insn_state(p);
+ if (c->key.clamp_fragment_color)
+ brw_set_saturate(p, 1);
+
for (channel = 0; channel < 4; channel++) {
if (intel->gen >= 6) {
/* gen6 SIMD16 single source DP write looks like:
@@ -1459,6 +1462,9 @@ void emit_fb_write(struct brw_wm_compile *c,
}
}
}
+
+ brw_set_saturate(p, 0);
+
/* skip over the regs populated above:
*/
if (c->dispatch_width == 16)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 30672b4251b..cfc30d8613f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -288,26 +288,26 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
entry->seamless_cube_map = (texObj->Target == GL_TEXTURE_CUBE_MAP)
? ctx->Texture.CubeMapSeamless : GL_FALSE;
- entry->wrap_r = texObj->WrapR;
- entry->wrap_s = texObj->WrapS;
- entry->wrap_t = texObj->WrapT;
-
- entry->maxlod = texObj->MaxLod;
- entry->minlod = texObj->MinLod;
- entry->lod_bias = texUnit->LodBias + texObj->LodBias;
- entry->max_aniso = texObj->MaxAnisotropy;
- entry->minfilter = texObj->MinFilter;
- entry->magfilter = texObj->MagFilter;
- entry->comparemode = texObj->CompareMode;
- entry->comparefunc = texObj->CompareFunc;
+ entry->wrap_r = texObj->Sampler.WrapR;
+ entry->wrap_s = texObj->Sampler.WrapS;
+ entry->wrap_t = texObj->Sampler.WrapT;
+
+ entry->maxlod = texObj->Sampler.MaxLod;
+ entry->minlod = texObj->Sampler.MinLod;
+ entry->lod_bias = texUnit->LodBias + texObj->Sampler.LodBias;
+ entry->max_aniso = texObj->Sampler.MaxAnisotropy;
+ entry->minfilter = texObj->Sampler.MinFilter;
+ entry->magfilter = texObj->Sampler.MagFilter;
+ entry->comparemode = texObj->Sampler.CompareMode;
+ entry->comparefunc = texObj->Sampler.CompareFunc;
drm_intel_bo_unreference(brw->wm.sdc_bo[unit]);
if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
float bordercolor[4] = {
- texObj->BorderColor.f[0],
- texObj->BorderColor.f[0],
- texObj->BorderColor.f[0],
- texObj->BorderColor.f[0]
+ texObj->Sampler.BorderColor.f[0],
+ texObj->Sampler.BorderColor.f[0],
+ texObj->Sampler.BorderColor.f[0],
+ texObj->Sampler.BorderColor.f[0]
};
/* GL specs that border color for depth textures is taken from the
* R channel, while the hardware uses A. Spam R into all the
@@ -316,7 +316,7 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
brw->wm.sdc_bo[unit] = upload_default_color(brw, bordercolor);
} else {
brw->wm.sdc_bo[unit] = upload_default_color(brw,
- texObj->BorderColor.f);
+ texObj->Sampler.BorderColor.f);
}
key->sampler_count = unit + 1;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 5b5afc4626b..be4b260a5ff 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -278,30 +278,10 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
static void upload_wm_unit( struct brw_context *brw )
{
- struct intel_context *intel = &brw->intel;
struct brw_wm_unit_key key;
drm_intel_bo *reloc_bufs[3];
wm_unit_populate_key(brw, &key);
- /* Allocate the necessary scratch space if we haven't already. Don't
- * bother reducing the allocation later, since we use scratch so
- * rarely.
- */
- if (key.total_scratch) {
- GLuint total = key.total_scratch * brw->wm_max_threads;
-
- if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) {
- drm_intel_bo_unreference(brw->wm.scratch_bo);
- brw->wm.scratch_bo = NULL;
- }
- if (brw->wm.scratch_bo == NULL) {
- brw->wm.scratch_bo = drm_intel_bo_alloc(intel->bufmgr,
- "wm scratch",
- total,
- 4096);
- }
- }
-
reloc_bufs[0] = brw->wm.prog_bo;
reloc_bufs[1] = brw->wm.scratch_bo;
reloc_bufs[2] = brw->wm.sampler_bo;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 1010d9f6f9c..e3396a3cbd4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -100,18 +100,37 @@ static uint32_t brw_format_for_mesa_format[MESA_FORMAT_COUNT] =
[MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
[MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
[MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
+ [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
+ [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
[MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
+ [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
+ [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
+ [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
+ [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
+ [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
+ [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
+ [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
+ [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
+ [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
};
bool
brw_render_target_supported(gl_format format)
{
+ /* These are not color render targets like the table holds, but we
+ * ask the question for FBO completeness.
+ */
if (format == MESA_FORMAT_S8_Z24 ||
format == MESA_FORMAT_X8_Z24 ||
format == MESA_FORMAT_Z16) {
return true;
}
+ /* The value of this BRW_SURFACEFORMAT is 0, so hardcode it.
+ */
+ if (format == MESA_FORMAT_RGBA_FLOAT32)
+ return true;
+
/* Not exactly true, as some of those formats are not renderable.
* But at least we know how to translate them.
*/
@@ -155,6 +174,13 @@ static GLuint translate_tex_format( gl_format mesa_format,
return brw_format_for_mesa_format[mesa_format];
else if (srgb_decode == GL_SKIP_DECODE_EXT)
return brw_format_for_mesa_format[_mesa_get_srgb_format_linear(mesa_format)];
+
+ case MESA_FORMAT_RGBA_FLOAT32:
+ /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
+ * assertion below.
+ */
+ return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+
default:
assert(brw_format_for_mesa_format[mesa_format] != 0);
return brw_format_for_mesa_format[mesa_format];
@@ -197,8 +223,9 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
surf->ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
surf->ss0.surface_type = translate_tex_target(tObj->Target);
surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat,
- firstImage->InternalFormat,
- tObj->DepthMode, tObj->sRGBDecode);
+ firstImage->InternalFormat,
+ tObj->Sampler.DepthMode,
+ tObj->Sampler.sRGBDecode);
/* This is ok for all textures with channel width 8bit or less:
*/
@@ -425,6 +452,14 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
*/
surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
break;
+ case MESA_FORMAT_INTENSITY_FLOAT32:
+ case MESA_FORMAT_LUMINANCE_FLOAT32:
+ /* For these formats, we just need to read/write the first
+ * channel into R, which is to say that we just treat them as
+ * GL_RED.
+ */
+ surf->ss0.surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
+ break;
case MESA_FORMAT_SARGB8:
/* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
surfaces to the blend/update as sRGB */
@@ -434,8 +469,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
break;
default:
+ assert(brw_render_target_supported(irb->Base.Format));
surf->ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
- assert(surf->ss0.surface_format != 0);
}
surf->ss0.surface_type = BRW_SURFACE_2D;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index d1648a102d4..1b935fb5e70 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -210,10 +210,10 @@ color_calc_state_populate_key(struct brw_context *brw,
if (ctx->Color.AlphaEnabled)
key->alpha_ref = ctx->Color.AlphaRef;
- key->blend_constant_color[0] = ctx->Color.BlendColor[0];
- key->blend_constant_color[1] = ctx->Color.BlendColor[1];
- key->blend_constant_color[2] = ctx->Color.BlendColor[2];
- key->blend_constant_color[3] = ctx->Color.BlendColor[3];
+ key->blend_constant_color[0] = ctx->Color.BlendColorUnclamped[0];
+ key->blend_constant_color[1] = ctx->Color.BlendColorUnclamped[1];
+ key->blend_constant_color[2] = ctx->Color.BlendColorUnclamped[2];
+ key->blend_constant_color[3] = ctx->Color.BlendColorUnclamped[3];
}
/**
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 7296c7cd1b0..c1d0a739394 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -44,38 +44,22 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- if (brw->gs.prog_bo) {
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
- OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_BATCH(GEN6_GS_SPF_MODE |
- (0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
- (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
- OUT_BATCH(0); /* scratch space base offset */
- OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
- (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) |
- (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
- OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
- GEN6_GS_STATISTICS_ENABLE |
- GEN6_GS_RENDERING_ENABLE);
- OUT_BATCH(GEN6_GS_ENABLE);
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
- OUT_BATCH(0); /* prog_bo */
- OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
- (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
- OUT_BATCH(0); /* scratch space base offset */
- OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
- (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
- (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
- OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
- GEN6_GS_STATISTICS_ENABLE |
- GEN6_GS_RENDERING_ENABLE);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- }
+ // GS should never be used on Gen6. Disable it.
+ assert(brw->gs.prog_bo == NULL);
+ BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
+ OUT_BATCH(0); /* prog_bo */
+ OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
+ (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+ OUT_BATCH(0); /* scratch space base offset */
+ OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
+ (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
+ (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
+ OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
+ GEN6_GS_STATISTICS_ENABLE |
+ GEN6_GS_RENDERING_ENABLE);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
}
const struct brw_tracked_state gen6_gs_state = {
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index c3819f9b360..909e1bbe9ba 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -34,26 +34,25 @@
static void
prepare_urb( struct brw_context *brw )
{
- int urb_size, max_urb_entry;
- struct intel_context *intel = &brw->intel;
-
- if (IS_GT1(intel->intelScreen->deviceID)) {
- urb_size = 32 * 1024;
- max_urb_entry = 128;
- } else {
- urb_size = 64 * 1024;
- max_urb_entry = 256;
- }
-
- brw->urb.nr_vs_entries = max_urb_entry;
- brw->urb.nr_gs_entries = max_urb_entry;
+ int nr_vs_entries;
/* CACHE_NEW_VS_PROG */
brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
- if (2 * brw->urb.vs_size > urb_size)
- brw->urb.nr_vs_entries = brw->urb.nr_gs_entries =
- (urb_size ) / (2 * brw->urb.vs_size);
+ /* Calculate how many VS URB entries fit in the total URB size */
+ nr_vs_entries = (brw->urb.size * 1024) / (brw->urb.vs_size * 128);
+
+ if (nr_vs_entries > brw->urb.max_vs_handles)
+ nr_vs_entries = brw->urb.max_vs_handles;
+
+ /* According to volume 2a, nr_vs_entries must be a multiple of 4. */
+ brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4);
+
+ /* Since we currently don't support Geometry Shaders, we always put the
+ * GS unit in passthrough mode and don't allocate it any URB space.
+ */
+ brw->urb.nr_gs_entries = 0;
+ brw->urb.gs_size = 1; /* Incorrect, but with 0 GS entries it doesn't matter. */
}
static void
@@ -61,6 +60,7 @@ upload_urb(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
+ assert(brw->urb.nr_vs_entries >= 24);
assert(brw->urb.nr_vs_entries % 4 == 0);
assert(brw->urb.nr_gs_entries % 4 == 0);
/* GS requirement */
@@ -70,7 +70,7 @@ upload_urb(struct brw_context *brw)
OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
- OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
+ OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index ce0b8ea7eaa..a10cec318d6 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -137,7 +137,7 @@ upload_vs_state(struct brw_context *brw)
(brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
- OUT_BATCH(((60 - 1) << GEN6_VS_MAX_THREADS_SHIFT) | /* max 60 threads for gen6 */
+ OUT_BATCH(((brw->vs_max_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
GEN6_VS_STATISTICS_ENABLE |
GEN6_VS_ENABLE);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 78901ecac57..8215cb15a9c 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -144,7 +144,7 @@ upload_wm_state(struct brw_context *brw)
dw4 |= (brw->wm.prog_data->first_curbe_grf <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
- dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
+ dw5 |= (brw->wm_max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
/* CACHE_NEW_WM_PROG */
if (brw->wm.prog_data->dispatch_width == 8)
@@ -184,7 +184,12 @@ upload_wm_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_BATCH(dw2);
- OUT_BATCH(0); /* scratch space base offset */
+ if (brw->wm.prog_data->total_scratch) {
+ OUT_RELOC(brw->wm.scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(brw->wm.prog_data->total_scratch) - 11);
+ } else {
+ OUT_BATCH(0);
+ }
OUT_BATCH(dw4);
OUT_BATCH(dw5);
OUT_BATCH(dw6);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 42b4f923e0c..53d6e7c6acc 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -176,8 +176,6 @@ intel_batchbuffer_emit_reloc(struct intel_context *intel,
{
int ret;
- assert(delta < buffer->size);
-
ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
buffer, delta,
read_domains, write_domain);
@@ -203,8 +201,6 @@ intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
{
int ret;
- assert(delta < buffer->size);
-
ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
buffer, delta,
read_domains, write_domain);
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index e1ab7f16371..5aac1f6fa24 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -146,6 +146,17 @@ intelEmitCopyBlit(struct intel_context *intel,
src_pitch *= cpp;
dst_pitch *= cpp;
+ /* For big formats (such as floating point), do the copy using 32bpp and
+ * multiply the coordinates.
+ */
+ if (cpp > 4) {
+ assert(cpp % 4 == 0);
+ dst_x *= cpp / 4;
+ dst_x2 *= cpp / 4;
+ src_x *= cpp / 4;
+ cpp = 4;
+ }
+
BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
switch (cpp) {
@@ -211,7 +222,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
{
struct intel_context *intel = intel_context(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
- GLuint clear_depth;
+ GLuint clear_depth_value, clear_depth_mask;
GLboolean all;
GLint cx, cy, cw, ch;
GLbitfield fail_mask = 0;
@@ -220,12 +231,15 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
/*
* Compute values for clearing the buffers.
*/
- clear_depth = 0;
+ clear_depth_value = 0;
+ clear_depth_mask = 0;
if (mask & BUFFER_BIT_DEPTH) {
- clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
+ clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
+ clear_depth_mask = XY_BLT_WRITE_RGB;
}
if (mask & BUFFER_BIT_STENCIL) {
- clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
+ clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
+ clear_depth_mask |= XY_BLT_WRITE_ALPHA;
}
cx = fb->_Xmin;
@@ -239,12 +253,13 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
if (cw == 0 || ch == 0)
return 0;
- GLuint buf;
all = (cw == fb->Width && ch == fb->Height);
/* Loop over all renderbuffers */
- for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
- const GLbitfield bufBit = 1 << buf;
+ mask &= (1 << BUFFER_COUNT) - 1;
+ while (mask) {
+ GLuint buf = _mesa_ffs(mask) - 1;
+ GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
struct intel_renderbuffer *irb;
drm_intel_bo *write_buffer;
int x1, y1, x2, y2;
@@ -253,11 +268,15 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
int pitch, cpp;
drm_intel_bo *aper_array[2];
- if (!(mask & bufBit))
- continue;
+ mask &= ~(1 << buf);
- /* OK, clear this renderbuffer */
irb = intel_get_renderbuffer(fb, buf);
+ if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) {
+ fail_mask |= 1 << buf;
+ continue;
+ }
+
+ /* OK, clear this renderbuffer */
write_buffer = intel_region_buffer(intel, irb->region,
all ? INTEL_WRITE_FULL :
INTEL_WRITE_PART);
@@ -274,16 +293,13 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
irb->region->buffer, (pitch * cpp),
x1, y1, x2 - x1, y2 - y1);
- BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
+ BR13 = 0xf0 << 16;
CMD = XY_COLOR_BLT_CMD;
/* Setup the blit command */
if (cpp == 4) {
- if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
- if (mask & BUFFER_BIT_DEPTH)
- CMD |= XY_BLT_WRITE_RGB;
- if (mask & BUFFER_BIT_STENCIL)
- CMD |= XY_BLT_WRITE_ALPHA;
+ if (is_depth_stencil) {
+ CMD |= clear_depth_mask;
} else {
/* clearing RGBA */
CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
@@ -300,8 +316,8 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
#endif
BR13 |= (pitch * cpp);
- if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
- clear_val = clear_depth;
+ if (is_depth_stencil) {
+ clear_val = clear_depth_value;
} else {
uint8_t clear[4];
GLclampf *color = ctx->Color.ClearColor;
@@ -333,12 +349,13 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
clear[3], clear[3]);
break;
default:
- fail_mask |= bufBit;
- mask &= ~bufBit;
+ fail_mask |= 1 << buf;
continue;
}
}
+ BR13 |= br13_for_cpp(cpp);
+
assert(x1 < x2);
assert(y1 < y2);
@@ -367,8 +384,6 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
- else
- mask &= ~bufBit; /* turn off bit, for faster loop exit */
}
return fail_mask;
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index 4ff9140d56e..a3f40effc35 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -125,18 +125,17 @@
/* Compat macro for intel_decode.c */
#define IS_IRONLAKE(devid) IS_GEN5(devid)
-#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
- devid == PCI_CHIP_SANDYBRIDGE_S)
-
#define IS_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_S)
+#define IS_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
+ devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+ devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+ devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
+
+#define IS_GEN6(devid) (IS_GT1(devid) || IS_GT2(devid))
+
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
IS_GEN5(devid) || \
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index c2e2a98af5e..02e7f7717fc 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -62,10 +62,6 @@ int INTEL_DEBUG = (0);
#endif
-#define DRIVER_DATE "20100330 DEVELOPMENT"
-#define DRIVER_DATE_GEM "GEM " DRIVER_DATE
-
-
static const GLubyte *
intelGetString(struct gl_context * ctx, GLenum name)
{
@@ -182,7 +178,7 @@ intelGetString(struct gl_context * ctx, GLenum name)
break;
}
- (void) driGetRendererString(buffer, chipset, DRIVER_DATE_GEM, 0);
+ (void) driGetRendererString(buffer, chipset, 0);
return (GLubyte *) buffer;
default:
@@ -728,8 +724,13 @@ intelInitContext(struct intel_context *intel,
ctx->TextureFormatSupported[MESA_FORMAT_RG88] = GL_TRUE;
ctx->TextureFormatSupported[MESA_FORMAT_RG1616] = GL_TRUE;
+ /* GL_MESA_texture_signed_rgba / GL_EXT_texture_snorm */
ctx->TextureFormatSupported[MESA_FORMAT_DUDV8] = GL_TRUE;
ctx->TextureFormatSupported[MESA_FORMAT_SIGNED_RGBA8888_REV] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_SIGNED_R8] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_SIGNED_RG88_REV] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_SIGNED_R16] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_SIGNED_GR1616] = GL_TRUE;
/* GL_EXT_texture_sRGB */
ctx->TextureFormatSupported[MESA_FORMAT_SARGB8] = GL_TRUE;
@@ -742,8 +743,19 @@ intelInitContext(struct intel_context *intel,
ctx->TextureFormatSupported[MESA_FORMAT_SL8] = GL_TRUE;
ctx->TextureFormatSupported[MESA_FORMAT_SLA8] = GL_TRUE;
}
+
+#ifdef TEXTURE_FLOAT_ENABLED
+ ctx->TextureFormatSupported[MESA_FORMAT_RGBA_FLOAT32] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_RG_FLOAT32] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_R_FLOAT32] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_INTENSITY_FLOAT32] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_LUMINANCE_FLOAT32] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_ALPHA_FLOAT32] = GL_TRUE;
+ ctx->TextureFormatSupported[MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = GL_TRUE;
#endif
+#endif /* !I915 */
+
driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
if (intel->gen < 4)
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 772b2fba5a8..c59119373da 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -295,9 +295,33 @@ extern char *__progname;
#define SUBPIXEL_Y 0.125
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1))
-#define ROUND_DOWN_TO(value, alignment) (ALIGN(value - alignment - 1, \
- alignment))
+
+/**
+ * Align a value up to an alignment value
+ *
+ * If \c value is not already aligned to the requested alignment value, it
+ * will be rounded up.
+ *
+ * \param value Value to be rounded
+ * \param alignment Alignment value to be used. This must be a power of two.
+ *
+ * \sa ROUND_DOWN_TO()
+ */
+#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
+
+/**
+ * Align a value down to an alignment value
+ *
+ * If \c value is not already aligned to the requested alignment value, it
+ * will be rounded down.
+ *
+ * \param value Value to be rounded
+ * \param alignment Alignment value to be used. This must be a power of two.
+ *
+ * \sa ALIGN()
+ */
+#define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
+
#define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0)
static INLINE uint32_t
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c
index febc1d4f859..e107534a4da 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -160,6 +160,7 @@ static const struct dri_extension i915_extensions[] = {
/** i965-only extensions */
static const struct dri_extension brw_extensions[] = {
+ { "GL_ARB_color_buffer_float", NULL },
{ "GL_ARB_depth_clamp", NULL },
{ "GL_ARB_depth_texture", NULL },
{ "GL_ARB_fragment_coord_conventions", NULL },
@@ -171,6 +172,9 @@ static const struct dri_extension brw_extensions[] = {
{ "GL_ARB_point_sprite", NULL },
{ "GL_ARB_seamless_cube_map", NULL },
{ "GL_ARB_shadow", NULL },
+#ifdef TEXTURE_FLOAT_ENABLED
+ { "GL_ARB_texture_float", NULL },
+#endif
{ "GL_MESA_texture_signed_rgba", NULL },
{ "GL_ARB_texture_non_power_of_two", NULL },
{ "GL_ARB_texture_rg", NULL },
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 8b57eb19f56..ad2468a3237 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -385,7 +385,7 @@ intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
irb->Base.Format = texImage->TexFormat;
irb->Base.DataType = intel_mesa_format_to_rb_datatype(texImage->TexFormat);
irb->Base.InternalFormat = texImage->InternalFormat;
- irb->Base._BaseFormat = _mesa_base_fbo_format(ctx, irb->Base.InternalFormat);
+ irb->Base._BaseFormat = _mesa_base_tex_format(ctx, irb->Base.InternalFormat);
irb->Base.Width = texImage->Width;
irb->Base.Height = texImage->Height;
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 1f41518535c..16bce20317e 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -30,6 +30,7 @@
#include "main/macros.h"
#include "main/mtypes.h"
#include "main/colormac.h"
+#include "main/renderbuffer.h"
#include "intel_buffers.h"
#include "intel_fbo.h"
@@ -114,57 +115,6 @@ intel_set_span_functions(struct intel_context *intel,
#define TAG2(x,y) intel_##x##y##_A8
#include "spantmp2.h"
-#define SPANTMP_MESA_FMT MESA_FORMAT_R8
-#define TAG(x) intel_##x##_R8
-#define TAG2(x,y) intel_##x##y##_R8
-#include "spantmp2.h"
-
-#define SPANTMP_MESA_FMT MESA_FORMAT_RG88
-#define TAG(x) intel_##x##_RG88
-#define TAG2(x,y) intel_##x##y##_RG88
-#include "spantmp2.h"
-
-#define SPANTMP_MESA_FMT MESA_FORMAT_R16
-#define TAG(x) intel_##x##_R16
-#define TAG2(x,y) intel_##x##y##_R16
-#include "spantmp2.h"
-
-#define SPANTMP_MESA_FMT MESA_FORMAT_RG1616
-#define TAG(x) intel_##x##_RG1616
-#define TAG2(x,y) intel_##x##y##_RG1616
-#include "spantmp2.h"
-
-#define LOCAL_DEPTH_VARS \
- struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
- const GLint yScale = rb->Name ? 1 : -1; \
- const GLint yBias = rb->Name ? 0 : rb->Height - 1; \
- int minx = 0, miny = 0; \
- int maxx = rb->Width; \
- int maxy = rb->Height; \
- int pitch = irb->region->pitch * irb->region->cpp; \
- void *buf = irb->region->buffer->virtual; \
- (void)buf; (void)pitch; /* unused for non-gttmap. */ \
-
-#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
-
-/* z16 depthbuffer functions. */
-#define VALUE_TYPE GLushort
-#define WRITE_DEPTH(_x, _y, d) \
- (*(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
-#define READ_DEPTH(d, _x, _y) \
- d = *(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
-#define TAG(x) intel_##x##_z16
-#include "depthtmp.h"
-
-/* z24_s8 and z24_x8 depthbuffer functions. */
-#define VALUE_TYPE GLuint
-#define WRITE_DEPTH(_x, _y, d) \
- (*(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
-#define READ_DEPTH(d, _x, _y) \
- d = *(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
-#define TAG(x) intel_##x##_z24_s8
-#include "depthtmp.h"
-
void
intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
{
@@ -175,6 +125,15 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
drm_intel_gem_bo_map_gtt(irb->region->buffer);
+ rb->Data = irb->region->buffer->virtual;
+ rb->RowStride = irb->region->pitch;
+
+ /* Flip orientation if it's the window system buffer */
+ if (!rb->Name) {
+ rb->Data += rb->RowStride * (irb->region->height - 1) * irb->region->cpp;
+ rb->RowStride = -rb->RowStride;
+ }
+
intel_set_span_functions(intel, rb);
}
@@ -191,6 +150,8 @@ intel_renderbuffer_unmap(struct intel_context *intel,
rb->GetRow = NULL;
rb->PutRow = NULL;
+ rb->Data = NULL;
+ rb->RowStride = 0;
}
/**
@@ -371,13 +332,18 @@ static span_init_func intel_span_init_funcs[MESA_FORMAT_COUNT] =
[MESA_FORMAT_XRGB8888] = intel_InitPointers_xRGB8888,
[MESA_FORMAT_ARGB8888] = intel_InitPointers_ARGB8888,
[MESA_FORMAT_SARGB8] = intel_InitPointers_ARGB8888,
- [MESA_FORMAT_Z16] = intel_InitDepthPointers_z16,
- [MESA_FORMAT_X8_Z24] = intel_InitDepthPointers_z24_s8,
- [MESA_FORMAT_S8_Z24] = intel_InitDepthPointers_z24_s8,
- [MESA_FORMAT_R8] = intel_InitPointers_R8,
- [MESA_FORMAT_RG88] = intel_InitPointers_RG88,
- [MESA_FORMAT_R16] = intel_InitPointers_R16,
- [MESA_FORMAT_RG1616] = intel_InitPointers_RG1616,
+ [MESA_FORMAT_Z16] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_X8_Z24] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_S8_Z24] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_R8] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_RG88] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_R16] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_RG1616] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_RGBA_FLOAT32] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_RG_FLOAT32] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_R_FLOAT32] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_INTENSITY_FLOAT32] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_LUMINANCE_FLOAT32] = _mesa_set_renderbuffer_accessors,
};
bool
diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c
index 87745bc66d4..befa615d1e6 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_format.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_format.c
@@ -16,6 +16,8 @@ intel_mesa_format_to_rb_datatype(gl_format format)
case MESA_FORMAT_R8:
case MESA_FORMAT_RG88:
case MESA_FORMAT_A8:
+ case MESA_FORMAT_I8:
+ case MESA_FORMAT_L8:
case MESA_FORMAT_AL88:
case MESA_FORMAT_RGB565:
case MESA_FORMAT_ARGB1555:
@@ -29,6 +31,15 @@ intel_mesa_format_to_rb_datatype(gl_format format)
return GL_UNSIGNED_INT;
case MESA_FORMAT_S8_Z24:
return GL_UNSIGNED_INT_24_8_EXT;
+ case MESA_FORMAT_RGBA_FLOAT32:
+ case MESA_FORMAT_RG_FLOAT32:
+ case MESA_FORMAT_R_FLOAT32:
+ case MESA_FORMAT_INTENSITY_FLOAT32:
+ case MESA_FORMAT_LUMINANCE_FLOAT32:
+ case MESA_FORMAT_ALPHA_FLOAT32:
+ case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
+ return GL_FLOAT;
+
default:
_mesa_problem(NULL, "unexpected MESA_FORMAT for renderbuffer");
return GL_UNSIGNED_BYTE;
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 906f8a62710..775fd1008f9 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -112,8 +112,8 @@ intel_miptree_create_for_teximage(struct intel_context *intel,
* resizable buffers, or require that buffers implement lazy
* pagetable arrangements.
*/
- if ((intelObj->base.MinFilter == GL_NEAREST ||
- intelObj->base.MinFilter == GL_LINEAR) &&
+ if ((intelObj->base.Sampler.MinFilter == GL_NEAREST ||
+ intelObj->base.Sampler.MinFilter == GL_LINEAR) &&
intelImage->level == firstLevel &&
(intel->gen < 4 || firstLevel == 0)) {
lastLevel = firstLevel;
@@ -370,8 +370,10 @@ intelTexImage(struct gl_context * ctx,
* whole object since our level didn't fit what was there
* before, and any lower levels would fit into our miptree.
*/
- if (intelImage->mt)
+ if (intelImage->mt) {
+ intel_miptree_release(intel, &intelObj->mt);
intel_miptree_reference(&intelObj->mt, intelImage->mt);
+ }
}
/* PBO fastpaths:
diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
index d0f8294113a..8b43c406cf9 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c
@@ -90,10 +90,17 @@ intelTexSubimage(struct gl_context * ctx,
intel->gen < 6 && target == GL_TEXTURE_2D &&
drm_intel_bo_busy(dst_bo))
{
- dstRowStride = width * intelImage->mt->cpp;
- temp_bo = drm_intel_bo_alloc(intel->bufmgr, "subimage blit bo",
- dstRowStride * height, 0);
- if (!temp_bo)
+ unsigned long pitch;
+ uint32_t tiling_mode = I915_TILING_NONE;
+
+ temp_bo = drm_intel_bo_alloc_tiled(intel->bufmgr,
+ "subimage blit bo",
+ width, height,
+ intelImage->mt->cpp,
+ &tiling_mode,
+ &pitch,
+ 0);
+ if (temp_bo == NULL)
return;
if (drm_intel_gem_bo_map_gtt(temp_bo)) {
@@ -103,6 +110,7 @@ intelTexSubimage(struct gl_context * ctx,
texImage->Data = temp_bo->virtual;
texImage->ImageOffsets[0] = 0;
+ dstRowStride = pitch;
intel_miptree_get_image_offset(intelImage->mt, level,
intelImage->face, 0,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index a11b07ed09d..5e705c93619 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -18,7 +18,7 @@ intel_update_max_level(struct intel_context *intel,
{
struct gl_texture_object *tObj = &intelObj->base;
- if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
+ if (tObj->Sampler.MinFilter == GL_NEAREST || tObj->Sampler.MinFilter == GL_LINEAR) {
intelObj->_MaxLevel = tObj->BaseLevel;
} else {
intelObj->_MaxLevel = tObj->_MaxLevel;
diff --git a/src/mesa/drivers/dri/mach64/mach64_dd.c b/src/mesa/drivers/dri/mach64/mach64_dd.c
index 9cb2c107597..2b557a70202 100644
--- a/src/mesa/drivers/dri/mach64/mach64_dd.c
+++ b/src/mesa/drivers/dri/mach64/mach64_dd.c
@@ -37,8 +37,6 @@
#include "utils.h"
-#define DRIVER_DATE "20051019"
-
/* Return the current color buffer size.
*/
static void mach64DDGetBufferSize( struct gl_framebuffer *buffer,
@@ -70,8 +68,7 @@ static const GLubyte *mach64DDGetString( struct gl_context *ctx, GLenum name )
case GL_RENDERER:
- offset = driGetRendererString( buffer, card_name, DRIVER_DATE,
- agp_mode );
+ offset = driGetRendererString( buffer, card_name, agp_mode );
return (GLubyte *)buffer;
default:
diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c
index 68d273a3e75..8e10b314b64 100644
--- a/src/mesa/drivers/dri/mach64/mach64_tex.c
+++ b/src/mesa/drivers/dri/mach64/mach64_tex.c
@@ -123,9 +123,9 @@ mach64AllocTexObj( struct gl_texture_object *texObj )
make_empty_list( (driTextureObject *) t );
- mach64SetTexWrap( t, texObj->WrapS, texObj->WrapT );
- mach64SetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
- mach64SetTexBorderColor( t, texObj->BorderColor.f );
+ mach64SetTexWrap( t, texObj->Sampler.WrapS, texObj->Sampler.WrapT );
+ mach64SetTexFilter( t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter );
+ mach64SetTexBorderColor( t, texObj->Sampler.BorderColor.f );
return t;
}
@@ -454,18 +454,18 @@ static void mach64DDTexParameter( struct gl_context *ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
if ( t->base.bound ) FLUSH_BATCH( mmesa );
- mach64SetTexFilter( t, tObj->MinFilter, tObj->MagFilter );
+ mach64SetTexFilter( t, tObj->Sampler.MinFilter, tObj->Sampler.MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
if ( t->base.bound ) FLUSH_BATCH( mmesa );
- mach64SetTexWrap( t, tObj->WrapS, tObj->WrapT );
+ mach64SetTexWrap( t, tObj->Sampler.WrapS, tObj->Sampler.WrapT );
break;
case GL_TEXTURE_BORDER_COLOR:
if ( t->base.bound ) FLUSH_BATCH( mmesa );
- mach64SetTexBorderColor( t, tObj->BorderColor.f );
+ mach64SetTexBorderColor( t, tObj->Sampler.BorderColor.f );
break;
case GL_TEXTURE_BASE_LEVEL:
diff --git a/src/mesa/drivers/dri/mga/mgadd.c b/src/mesa/drivers/dri/mga/mgadd.c
index 1b39813e379..2e3e9f2c43c 100644
--- a/src/mesa/drivers/dri/mga/mgadd.c
+++ b/src/mesa/drivers/dri/mga/mgadd.c
@@ -35,9 +35,6 @@
#include "mga_xmesa.h"
#include "utils.h"
-#define DRIVER_DATE "20071017"
-
-
/***************************************
* Mesa's Driver Functions
***************************************/
@@ -57,7 +54,6 @@ static const GLubyte *mgaGetString( struct gl_context *ctx, GLenum name )
offset = driGetRendererString( buffer,
MGA_IS_G400(mmesa) ? "G400" :
MGA_IS_G200(mmesa) ? "G200" : "MGA",
- DRIVER_DATE,
mmesa->mgaScreen->agpMode );
return (GLubyte *)buffer;
diff --git a/src/mesa/drivers/dri/mga/mgatex.c b/src/mesa/drivers/dri/mga/mgatex.c
index 11ab9b6117d..ebbfec36556 100644
--- a/src/mesa/drivers/dri/mga/mgatex.c
+++ b/src/mesa/drivers/dri/mga/mgatex.c
@@ -327,9 +327,9 @@ mgaAllocTexObj( struct gl_texture_object *tObj )
make_empty_list( & t->base );
- mgaSetTexWrapping( t, tObj->WrapS, tObj->WrapT );
- mgaSetTexFilter( t, tObj->MinFilter, tObj->MagFilter );
- mgaSetTexBorderColor( t, tObj->BorderColor.f );
+ mgaSetTexWrapping( t, tObj->Sampler.WrapS, tObj->Sampler.WrapT );
+ mgaSetTexFilter( t, tObj->Sampler.MinFilter, tObj->Sampler.MagFilter );
+ mgaSetTexBorderColor( t, tObj->Sampler.BorderColor.f );
}
return( t );
@@ -447,18 +447,18 @@ mgaTexParameter( struct gl_context *ctx, GLenum target,
/* FALLTHROUGH */
case GL_TEXTURE_MAG_FILTER:
FLUSH_BATCH(mmesa);
- mgaSetTexFilter( t, tObj->MinFilter, tObj->MagFilter );
+ mgaSetTexFilter( t, tObj->Sampler.MinFilter, tObj->Sampler.MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
FLUSH_BATCH(mmesa);
- mgaSetTexWrapping(t,tObj->WrapS,tObj->WrapT);
+ mgaSetTexWrapping(t,tObj->Sampler.WrapS,tObj->Sampler.WrapT);
break;
case GL_TEXTURE_BORDER_COLOR:
FLUSH_BATCH(mmesa);
- mgaSetTexBorderColor(t, tObj->BorderColor.f);
+ mgaSetTexBorderColor(t, tObj->Sampler.BorderColor.f);
break;
case GL_TEXTURE_BASE_LEVEL:
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.c b/src/mesa/drivers/dri/nouveau/nouveau_driver.c
index 45630be7f6e..8b6aa820434 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_driver.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_driver.c
@@ -45,7 +45,7 @@ nouveau_get_string(struct gl_context *ctx, GLenum name)
case GL_RENDERER:
sprintf(hardware_name, "nv%02X", context_chipset(ctx));
- driGetRendererString(buffer, hardware_name, DRIVER_DATE, 0);
+ driGetRendererString(buffer, hardware_name, 0);
return (GLubyte *)buffer;
default:
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.h b/src/mesa/drivers/dri/nouveau/nouveau_driver.h
index 158aec820aa..0018eec021f 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_driver.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_driver.h
@@ -48,7 +48,6 @@
#include "nouveau_surface.h"
#include "nv04_pushbuf.h"
-#define DRIVER_DATE "20091015"
#define DRIVER_AUTHOR "Nouveau"
struct nouveau_driver {
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
index 1a1e10e0b3a..36e68c99181 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
@@ -270,8 +270,8 @@ get_last_level(struct gl_texture_object *t)
{
struct gl_texture_image *base = t->Image[0][t->BaseLevel];
- if (t->MinFilter == GL_NEAREST ||
- t->MinFilter == GL_LINEAR || !base)
+ if (t->Sampler.MinFilter == GL_NEAREST ||
+ t->Sampler.MinFilter == GL_LINEAR || !base)
return t->BaseLevel;
else
return MIN2(t->BaseLevel + base->MaxLog2, t->MaxLevel);
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_tex.c b/src/mesa/drivers/dri/nouveau/nv04_state_tex.c
index 5ed8b147559..648d6b18cf5 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_tex.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_tex.c
@@ -80,26 +80,26 @@ nv04_emit_tex_obj(struct gl_context *ctx, int emit)
s = &to_nouveau_texture(t)->surfaces[t->BaseLevel];
- if (t->MinFilter != GL_NEAREST &&
- t->MinFilter != GL_LINEAR) {
- lod_max = CLAMP(MIN2(t->MaxLod, t->_MaxLambda),
+ if (t->Sampler.MinFilter != GL_NEAREST &&
+ t->Sampler.MinFilter != GL_LINEAR) {
+ lod_max = CLAMP(MIN2(t->Sampler.MaxLod, t->_MaxLambda),
0, 15) + 1;
lod_bias = CLAMP(ctx->Texture.Unit[i].LodBias +
- t->LodBias, -16, 15) * 8;
+ t->Sampler.LodBias, -16, 15) * 8;
}
- format |= nvgl_wrap_mode(t->WrapT) << 28 |
- nvgl_wrap_mode(t->WrapS) << 24 |
+ format |= nvgl_wrap_mode(t->Sampler.WrapT) << 28 |
+ nvgl_wrap_mode(t->Sampler.WrapS) << 24 |
ti->HeightLog2 << 20 |
ti->WidthLog2 << 16 |
lod_max << 12 |
get_tex_format(ti);
- filter |= log2i(t->MaxAnisotropy) << 31 |
- nvgl_filter_mode(t->MagFilter) << 28 |
- log2i(t->MaxAnisotropy) << 27 |
- nvgl_filter_mode(t->MinFilter) << 24 |
+ filter |= log2i(t->Sampler.MaxAnisotropy) << 31 |
+ nvgl_filter_mode(t->Sampler.MagFilter) << 28 |
+ log2i(t->Sampler.MaxAnisotropy) << 27 |
+ nvgl_filter_mode(t->Sampler.MinFilter) << 24 |
(lod_bias & 0xff) << 16;
} else {
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_tex.c b/src/mesa/drivers/dri/nouveau/nv10_state_tex.c
index fda67b15073..620a686aea0 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_tex.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_tex.c
@@ -173,17 +173,17 @@ nv10_emit_tex_obj(struct gl_context *ctx, int emit)
return;
/* Recompute the texturing registers. */
- tx_format = nvgl_wrap_mode(t->WrapT) << 28
- | nvgl_wrap_mode(t->WrapS) << 24
+ tx_format = nvgl_wrap_mode(t->Sampler.WrapT) << 28
+ | nvgl_wrap_mode(t->Sampler.WrapS) << 24
| ti->HeightLog2 << 20
| ti->WidthLog2 << 16
| 5 << 4 | 1 << 12;
- tx_filter = nvgl_filter_mode(t->MagFilter) << 28
- | nvgl_filter_mode(t->MinFilter) << 24;
+ tx_filter = nvgl_filter_mode(t->Sampler.MagFilter) << 28
+ | nvgl_filter_mode(t->Sampler.MinFilter) << 24;
tx_enable = NV10_3D_TEX_ENABLE_ENABLE
- | log2i(t->MaxAnisotropy) << 4;
+ | log2i(t->Sampler.MaxAnisotropy) << 4;
if (t->Target == GL_TEXTURE_RECTANGLE) {
BEGIN_RING(chan, celsius, NV10_3D_TEX_NPOT_PITCH(i), 1);
@@ -196,11 +196,11 @@ nv10_emit_tex_obj(struct gl_context *ctx, int emit)
tx_format |= get_tex_format_pot(ti);
}
- if (t->MinFilter != GL_NEAREST &&
- t->MinFilter != GL_LINEAR) {
- int lod_min = t->MinLod;
- int lod_max = MIN2(t->MaxLod, t->_MaxLambda);
- int lod_bias = t->LodBias
+ if (t->Sampler.MinFilter != GL_NEAREST &&
+ t->Sampler.MinFilter != GL_LINEAR) {
+ int lod_min = t->Sampler.MinLod;
+ int lod_max = MIN2(t->Sampler.MaxLod, t->_MaxLambda);
+ int lod_bias = t->Sampler.LodBias
+ ctx->Texture.Unit[i].LodBias;
lod_max = CLAMP(lod_max, 0, 15);
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_tex.c b/src/mesa/drivers/dri/nouveau/nv20_state_tex.c
index c362aca0fdb..eab74aed5c2 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_tex.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_tex.c
@@ -186,16 +186,16 @@ nv20_emit_tex_obj(struct gl_context *ctx, int emit)
| NV20_3D_TEX_FORMAT_NO_BORDER
| 1 << 16;
- tx_wrap = nvgl_wrap_mode(t->WrapR) << 16
- | nvgl_wrap_mode(t->WrapT) << 8
- | nvgl_wrap_mode(t->WrapS) << 0;
+ tx_wrap = nvgl_wrap_mode(t->Sampler.WrapR) << 16
+ | nvgl_wrap_mode(t->Sampler.WrapT) << 8
+ | nvgl_wrap_mode(t->Sampler.WrapS) << 0;
- tx_filter = nvgl_filter_mode(t->MagFilter) << 24
- | nvgl_filter_mode(t->MinFilter) << 16
+ tx_filter = nvgl_filter_mode(t->Sampler.MagFilter) << 24
+ | nvgl_filter_mode(t->Sampler.MinFilter) << 16
| 2 << 12;
tx_enable = NV20_3D_TEX_ENABLE_ENABLE
- | log2i(t->MaxAnisotropy) << 4;
+ | log2i(t->Sampler.MaxAnisotropy) << 4;
if (t->Target == GL_TEXTURE_RECTANGLE) {
BEGIN_RING(chan, kelvin, NV20_3D_TEX_NPOT_PITCH(i), 1);
@@ -208,11 +208,11 @@ nv20_emit_tex_obj(struct gl_context *ctx, int emit)
tx_format |= get_tex_format_pot(ti);
}
- if (t->MinFilter != GL_NEAREST &&
- t->MinFilter != GL_LINEAR) {
- int lod_min = t->MinLod;
- int lod_max = MIN2(t->MaxLod, t->_MaxLambda);
- int lod_bias = t->LodBias
+ if (t->Sampler.MinFilter != GL_NEAREST &&
+ t->Sampler.MinFilter != GL_LINEAR) {
+ int lod_min = t->Sampler.MinLod;
+ int lod_max = MIN2(t->Sampler.MaxLod, t->_MaxLambda);
+ int lod_bias = t->Sampler.LodBias
+ ctx->Texture.Unit[i].LodBias;
lod_max = CLAMP(lod_max, 0, 15);
diff --git a/src/mesa/drivers/dri/r128/r128_dd.c b/src/mesa/drivers/dri/r128/r128_dd.c
index 0b7005eba69..cfe2387948d 100644
--- a/src/mesa/drivers/dri/r128/r128_dd.c
+++ b/src/mesa/drivers/dri/r128/r128_dd.c
@@ -40,9 +40,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "utils.h"
-#define DRIVER_DATE "20051027"
-
-
/* Return the width and height of the current color buffer.
*/
static void r128GetBufferSize( struct gl_framebuffer *buffer,
@@ -82,8 +79,7 @@ static const GLubyte *r128GetString( struct gl_context *ctx, GLenum name )
card_name = "Rage 128 Mobility";
}
- offset = driGetRendererString( buffer, card_name, DRIVER_DATE,
- agp_mode );
+ offset = driGetRendererString( buffer, card_name, agp_mode );
return (GLubyte *)buffer;
diff --git a/src/mesa/drivers/dri/r128/r128_span.c b/src/mesa/drivers/dri/r128/r128_span.c
index 307de56ee13..04bdbe612e5 100644
--- a/src/mesa/drivers/dri/r128/r128_span.c
+++ b/src/mesa/drivers/dri/r128/r128_span.c
@@ -135,7 +135,7 @@ do { \
r128WriteDepthSpanLocked( rmesa, n, \
x + dPriv->x, \
y + dPriv->y, \
- depth, mask ); \
+ (const GLuint *) depth, mask ); \
} while (0)
#define WRITE_DEPTH_PIXELS() \
@@ -146,7 +146,7 @@ do { \
ox[i] = x[i] + dPriv->x; \
oy[i] = Y_FLIP( y[i] ) + dPriv->y; \
} \
- r128WriteDepthPixelsLocked( rmesa, n, ox, oy, depth, mask ); \
+ r128WriteDepthPixelsLocked( rmesa, n, ox, oy, (const GLuint *) depth, mask ); \
} while (0)
#define READ_DEPTH_SPAN() \
diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c
index ba3305e076e..a3f6ce8edeb 100644
--- a/src/mesa/drivers/dri/r128/r128_tex.c
+++ b/src/mesa/drivers/dri/r128/r128_tex.c
@@ -162,9 +162,9 @@ static r128TexObjPtr r128AllocTexObj( struct gl_texture_object *texObj )
make_empty_list( (driTextureObject *) t );
- r128SetTexWrap( t, texObj->WrapS, texObj->WrapT );
- r128SetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
- r128SetTexBorderColor( t, texObj->BorderColor.f );
+ r128SetTexWrap( t, texObj->Sampler.WrapS, texObj->Sampler.WrapT );
+ r128SetTexFilter( t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter );
+ r128SetTexBorderColor( t, texObj->Sampler.BorderColor.f );
}
return t;
@@ -519,18 +519,18 @@ static void r128TexParameter( struct gl_context *ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
if ( t->base.bound ) FLUSH_BATCH( rmesa );
- r128SetTexFilter( t, tObj->MinFilter, tObj->MagFilter );
+ r128SetTexFilter( t, tObj->Sampler.MinFilter, tObj->Sampler.MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
if ( t->base.bound ) FLUSH_BATCH( rmesa );
- r128SetTexWrap( t, tObj->WrapS, tObj->WrapT );
+ r128SetTexWrap( t, tObj->Sampler.WrapS, tObj->Sampler.WrapT );
break;
case GL_TEXTURE_BORDER_COLOR:
if ( t->base.bound ) FLUSH_BATCH( rmesa );
- r128SetTexBorderColor( t, tObj->BorderColor.f );
+ r128SetTexBorderColor( t, tObj->Sampler.BorderColor.f );
break;
case GL_TEXTURE_BASE_LEVEL:
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index 9c045b73acc..4e08d3431bf 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -62,13 +62,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_span.h"
#define need_GL_ARB_occlusion_query
+#define need_GL_ARB_vertex_array_object
#define need_GL_ARB_vertex_program
+#define need_GL_APPLE_vertex_array_object
#define need_GL_ATI_fragment_shader
#define need_GL_EXT_blend_minmax
#define need_GL_EXT_fog_coord
#define need_GL_EXT_secondary_color
#define need_GL_EXT_blend_equation_separate
#define need_GL_EXT_blend_func_separate
+#define need_GL_EXT_gpu_program_parameters
#define need_GL_NV_vertex_program
#define need_GL_ARB_point_parameters
#define need_GL_EXT_framebuffer_object
@@ -76,8 +79,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "main/remap_helper.h"
-#define DRIVER_DATE "20060602"
-
#include "utils.h"
#include "xmlpool.h" /* for symbolic values of enum-type options */
@@ -96,8 +97,7 @@ static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name )
return (GLubyte *)"Tungsten Graphics, Inc.";
case GL_RENDERER:
- offset = driGetRendererString( buffer, "R200", DRIVER_DATE,
- agp_mode );
+ offset = driGetRendererString( buffer, "R200", agp_mode );
sprintf( & buffer[ offset ], " %sTCL",
!(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
@@ -115,6 +115,7 @@ static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name )
*/
static const struct dri_extension card_extensions[] =
{
+ { "GL_ARB_half_float_pixel", NULL },
{ "GL_ARB_multitexture", NULL },
{ "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions},
{ "GL_ARB_texture_border_clamp", NULL },
@@ -123,6 +124,7 @@ static const struct dri_extension card_extensions[] =
{ "GL_ARB_texture_env_dot3", NULL },
{ "GL_ARB_texture_env_crossbar", NULL },
{ "GL_ARB_texture_mirrored_repeat", NULL },
+ { "GL_ARB_vertex_array_object", GL_ARB_vertex_array_object_functions},
{ "GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions },
{ "GL_EXT_blend_subtract", NULL },
{ "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
@@ -136,6 +138,7 @@ static const struct dri_extension card_extensions[] =
{ "GL_EXT_texture_lod_bias", NULL },
{ "GL_EXT_texture_mirror_clamp", NULL },
{ "GL_EXT_texture_rectangle", NULL },
+ { "GL_APPLE_vertex_array_object", GL_APPLE_vertex_array_object_functions },
{ "GL_ATI_texture_env_combine3", NULL },
{ "GL_ATI_texture_mirror_once", NULL },
{ "GL_MESA_pack_invert", NULL },
@@ -153,7 +156,9 @@ static const struct dri_extension blend_extensions[] = {
};
static const struct dri_extension ARB_vp_extension[] = {
- { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions }
+ { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions },
+ { "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions},
+ { NULL, NULL }
};
static const struct dri_extension NV_vp_extension[] = {
@@ -458,7 +463,7 @@ GLboolean r200CreateContext( gl_api api,
driInitExtensions( ctx, blend_extensions, GL_FALSE );
}
if(rmesa->radeon.radeonScreen->drmSupportsVertexProgram)
- driInitSingleExtension( ctx, ARB_vp_extension );
+ driInitExtensions( ctx, ARB_vp_extension, GL_FALSE );
if(driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program"))
driInitSingleExtension( ctx, NV_vp_extension );
diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c
index 092b7575831..d42e8f12041 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.c
+++ b/src/mesa/drivers/dri/r200/r200_tex.c
@@ -383,18 +383,18 @@ static void r200TexParameter( struct gl_context *ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r200SetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- r200SetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
+ r200SetTexMaxAnisotropy( t, texObj->Sampler.MaxAnisotropy );
+ r200SetTexFilter( t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
case GL_TEXTURE_WRAP_R:
- r200SetTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR );
+ r200SetTexWrap( t, texObj->Sampler.WrapS, texObj->Sampler.WrapT, texObj->Sampler.WrapR );
break;
case GL_TEXTURE_BORDER_COLOR:
- r200SetTexBorderColor( t, texObj->BorderColor.f );
+ r200SetTexBorderColor( t, texObj->Sampler.BorderColor.f );
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -479,13 +479,13 @@ static struct gl_texture_object *r200NewTextureObject(struct gl_context * ctx,
_mesa_lookup_enum_by_nr(target), t);
_mesa_initialize_texture_object(&t->base, name, target);
- t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
+ t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
/* Initialize hardware state */
- r200SetTexWrap( t, t->base.WrapS, t->base.WrapT, t->base.WrapR );
- r200SetTexMaxAnisotropy( t, t->base.MaxAnisotropy );
- r200SetTexFilter(t, t->base.MinFilter, t->base.MagFilter);
- r200SetTexBorderColor(t, t->base.BorderColor.f);
+ r200SetTexWrap( t, t->base.Sampler.WrapS, t->base.Sampler.WrapT, t->base.Sampler.WrapR );
+ r200SetTexMaxAnisotropy( t, t->base.Sampler.MaxAnisotropy );
+ r200SetTexFilter(t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter);
+ r200SetTexBorderColor(t, t->base.Sampler.BorderColor.f);
return &t->base;
}
diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
index 28d132a5fe3..8b73409136f 100644
--- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
@@ -34,8 +34,6 @@
* \author Ben Skeggs <[email protected]>
*
* \author Jerome Glisse <[email protected]>
- *
- * \todo FogOption
*/
#include "r300_fragprog.h"
@@ -108,6 +106,7 @@ static unsigned int translate_rgb_opcode(struct r300_fragment_program_compiler *
{
switch(opcode) {
case RC_OPCODE_CMP: return R300_ALU_OUTC_CMP;
+ case RC_OPCODE_CND: return R300_ALU_OUTC_CND;
case RC_OPCODE_DP3: return R300_ALU_OUTC_DP3;
case RC_OPCODE_DP4: return R300_ALU_OUTC_DP4;
case RC_OPCODE_FRC: return R300_ALU_OUTC_FRC;
@@ -127,6 +126,7 @@ static unsigned int translate_alpha_opcode(struct r300_fragment_program_compiler
{
switch(opcode) {
case RC_OPCODE_CMP: return R300_ALU_OUTA_CMP;
+ case RC_OPCODE_CND: return R300_ALU_OUTA_CND;
case RC_OPCODE_DP3: return R300_ALU_OUTA_DP4;
case RC_OPCODE_DP4: return R300_ALU_OUTA_DP4;
case RC_OPCODE_EX2: return R300_ALU_OUTA_EX2;
diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
index 8ad2175eadf..654f9a070d5 100644
--- a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
+++ b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
@@ -273,6 +273,7 @@ static void ei_mad(struct r300_vertex_program_code *vp,
struct rc_sub_instruction *vpi,
unsigned int * inst)
{
+ unsigned int i;
/* Remarks about hardware limitations of MAD
* (please preserve this comment, as this information is _NOT_
* in the documentation provided by AMD).
@@ -318,6 +319,23 @@ static void ei_mad(struct r300_vertex_program_code *vp,
t_dst_index(vp, &vpi->DstReg),
t_dst_mask(vpi->DstReg.WriteMask),
t_dst_class(vpi->DstReg.File));
+
+ /* Arguments with constant swizzles still count as a unique
+ * temporary, so we should make sure these arguments share a
+ * register index with one of the other arguments. */
+ for (i = 0; i < 3; i++) {
+ unsigned int j;
+ if (vpi->SrcReg[i].File != RC_FILE_NONE)
+ continue;
+
+ for (j = 0; j < 3; j++) {
+ if (i != j) {
+ vpi->SrcReg[i].Index =
+ vpi->SrcReg[j].Index;
+ break;
+ }
+ }
+ }
}
inst[1] = t_src(vp, &vpi->SrcReg[0]);
inst[2] = t_src(vp, &vpi->SrcReg[1]);
diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
index 301b4446693..c7f79bc53c7 100644
--- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
@@ -93,6 +93,7 @@ static unsigned int translate_rgb_op(struct r300_fragment_program_compiler *c, r
{
switch(opcode) {
case RC_OPCODE_CMP: return R500_ALU_RGBA_OP_CMP;
+ case RC_OPCODE_CND: return R500_ALU_RGBA_OP_CND;
case RC_OPCODE_DDX: return R500_ALU_RGBA_OP_MDH;
case RC_OPCODE_DDY: return R500_ALU_RGBA_OP_MDV;
case RC_OPCODE_DP3: return R500_ALU_RGBA_OP_DP3;
@@ -114,6 +115,7 @@ static unsigned int translate_alpha_op(struct r300_fragment_program_compiler *c,
{
switch(opcode) {
case RC_OPCODE_CMP: return R500_ALPHA_OP_CMP;
+ case RC_OPCODE_CND: return R500_ALPHA_OP_CND;
case RC_OPCODE_COS: return R500_ALPHA_OP_COS;
case RC_OPCODE_DDX: return R500_ALPHA_OP_MDH;
case RC_OPCODE_DDY: return R500_ALPHA_OP_MDV;
@@ -197,11 +199,14 @@ static void use_temporary(struct r500_fragment_program_code* code, unsigned int
static unsigned int use_source(struct r500_fragment_program_code* code, struct rc_pair_instruction_source src)
{
+ /* From docs:
+ * Note that inline constants set the MSB of ADDR0 and clear ADDR0_CONST.
+ * MSB = 1 << 7 */
if (!src.Used)
- return 0;
+ return 1 << 7;
if (src.File == RC_FILE_CONSTANT) {
- return src.Index | 0x100;
+ return src.Index | R500_RGB_ADDR0_CONST;
} else if (src.File == RC_FILE_TEMPORARY) {
use_temporary(code, src.Index);
return src.Index;
@@ -259,7 +264,8 @@ static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair
}
code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
- code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14);
+ code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11);
+ code->inst[ip].inst0 |= inst->Alpha.WriteMask ? 1 << 14 : 0;
code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18);
if (inst->Nop) {
code->inst[ip].inst0 |= R500_INST_NOP;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_code.h b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
index 35360aa70f0..67e6acf8b10 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_code.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
@@ -132,10 +132,10 @@ typedef enum {
struct r300_fragment_program_external_state {
struct {
/**
- * If the sampler is used as a shadow sampler,
- * this field contains swizzle depending on the depth texture mode.
+ * This field contains swizzle for some lowering passes
+ * (shadow comparison, unorm->snorm conversion)
*/
- unsigned depth_texture_swizzle:12;
+ unsigned texture_swizzle:12;
/**
* If the sampler is used as a shadow sampler,
@@ -172,6 +172,12 @@ struct r300_fragment_program_external_state {
* and right before texture fetch. The scaling factor is given by
* RC_STATE_R300_TEXSCALE_FACTOR. */
unsigned clamp_and_scale_before_fetch : 1;
+
+ /**
+ * Fetch RGTC1_SNORM or LATC1_SNORM as UNORM and convert UNORM -> SNORM
+ * in the shader.
+ */
+ unsigned convert_unorm_to_snorm:1;
} unit[16];
unsigned frag_clamp:1;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
index 79cd7996f78..b7936725d85 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
@@ -483,7 +483,7 @@ void rc_validate_final_shader(struct radeon_compiler *c, void *user)
{
/* Check the number of constants. */
if (c->Program.Constants.Count > c->max_constants) {
- rc_error(c, "Too many constants. Max: 256, Got: %i\n",
- c->Program.Constants.Count);
+ rc_error(c, "Too many constants. Max: %i, Got: %i\n",
+ c->max_constants, c->Program.Constants.Count);
}
}
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
index c080d5aecc6..d1a7eab50f7 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
@@ -704,9 +704,16 @@ static void get_readers_for_single_write(
&d->BranchMasks[branch_depth];
if (masks->HasElse) {
+ /* Abort on read for components that
+ * were written in the IF block. */
d->ReaderData->AbortOnRead |=
masks->IfWriteMask
& ~masks->ElseWriteMask;
+ /* Abort on read for components that
+ * were written in the ELSE block. */
+ d->ReaderData->AbortOnRead |=
+ masks->ElseWriteMask
+ & ~d->AliveWriteMask;
d->AliveWriteMask = masks->IfWriteMask
^ ((masks->IfWriteMask ^
masks->ElseWriteMask)
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index 25afd272bee..e3e498e8fb4 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -81,6 +81,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
.IsComponentwise = 1
},
{
+ .Opcode = RC_OPCODE_CND,
+ .Name = "CND",
+ .NumSrcRegs = 3,
+ .HasDstReg = 1,
+ .IsComponentwise = 1
+ },
+ {
.Opcode = RC_OPCODE_COS,
.Name = "COS",
.NumSrcRegs = 1,
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
index 7e666101276..b5868820611 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
@@ -56,6 +56,9 @@ typedef enum {
/** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
RC_OPCODE_CMP,
+ /** vec4 instruction: dst.c = src2.c > 0.5 ? src0.c : src1.c */
+ RC_OPCODE_CND,
+
/** scalar instruction: dst = cos(src0.x) */
RC_OPCODE_COS,
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
index c4e6a5e0a1f..79898e1047e 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
@@ -509,10 +509,34 @@ static int is_presub_candidate(
{
const struct rc_opcode_info * info = rc_get_opcode_info(inst->U.I.Opcode);
unsigned int i;
+ unsigned int is_constant[2] = {0, 0};
+
+ assert(inst->U.I.Opcode == RC_OPCODE_ADD);
if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE || inst->U.I.SaturateMode)
return 0;
+ /* If both sources use a constant swizzle, then we can't convert it to
+ * a presubtract operation. In fact for the ADD and SUB presubtract
+ * operations neither source can contain a constant swizzle. This
+ * specific case is checked in peephole_add_presub_add() when
+ * we make sure the swizzles for both sources are equal, so we
+ * don't need to worry about it here. */
+ for (i = 0; i < 2; i++) {
+ int chan;
+ for (chan = 0; chan < 4; chan++) {
+ rc_swizzle swz =
+ get_swz(inst->U.I.SrcReg[i].Swizzle, chan);
+ if (swz == RC_SWIZZLE_ONE
+ || swz == RC_SWIZZLE_ZERO
+ || swz == RC_SWIZZLE_HALF) {
+ is_constant[i] = 1;
+ }
+ }
+ }
+ if (is_constant[0] && is_constant[1])
+ return 0;
+
for(i = 0; i < info->NumSrcRegs; i++) {
struct rc_src_register src = inst->U.I.SrcReg[i];
if (src_reads_dst_mask(src, inst->U.I.DstReg))
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c
index 9e03eb1aca8..2dae56a2428 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c
@@ -99,6 +99,7 @@ static void classify_instruction(struct rc_sub_instruction * inst,
switch(inst->Opcode) {
case RC_OPCODE_ADD:
case RC_OPCODE_CMP:
+ case RC_OPCODE_CND:
case RC_OPCODE_DDX:
case RC_OPCODE_DDY:
case RC_OPCODE_FRC:
@@ -289,7 +290,7 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c,
}
if (needalpha) {
- pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
+ pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3);
if (pair->Alpha.WriteMask) {
pair->Alpha.DestIndex = inst->DstReg.Index;
}
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
index 6708b16d29a..d1a435fc530 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
@@ -71,7 +71,7 @@ struct rc_pair_instruction_arg {
struct rc_pair_sub_instruction {
unsigned int Opcode:8;
unsigned int DestIndex:RC_REGISTER_INDEX_BITS;
- unsigned int WriteMask:3;
+ unsigned int WriteMask:4;
unsigned int Target:2;
unsigned int OutputWriteMask:3;
unsigned int DepthWriteMask:1;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
index 1cf77d9cf73..cef448ee4e1 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
@@ -32,8 +32,8 @@
/* Series of transformations to be done on textures. */
-static struct rc_src_register shadow_ambient(struct r300_fragment_program_compiler *compiler,
- int tmu)
+static struct rc_src_register shadow_fail_value(struct r300_fragment_program_compiler *compiler,
+ int tmu)
{
struct rc_src_register reg = { 0, };
@@ -46,6 +46,20 @@ static struct rc_src_register shadow_ambient(struct r300_fragment_program_compil
reg.File = RC_FILE_NONE;
reg.Swizzle = RC_SWIZZLE_0000;
}
+
+ reg.Swizzle = combine_swizzles(reg.Swizzle,
+ compiler->state.unit[tmu].texture_swizzle);
+ return reg;
+}
+
+static struct rc_src_register shadow_pass_value(struct r300_fragment_program_compiler *compiler,
+ int tmu)
+{
+ struct rc_src_register reg = { 0, };
+
+ reg.File = RC_FILE_NONE;
+ reg.Swizzle = combine_swizzles(RC_SWIZZLE_1111,
+ compiler->state.unit[tmu].texture_swizzle);
return reg;
}
@@ -141,10 +155,9 @@ int radeonTransformTEX(
inst->U.I.Opcode = RC_OPCODE_MOV;
if (comparefunc == RC_COMPARE_FUNC_ALWAYS) {
- inst->U.I.SrcReg[0].File = RC_FILE_NONE;
- inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111;
+ inst->U.I.SrcReg[0] = shadow_pass_value(compiler, inst->U.I.TexSrcUnit);
} else {
- inst->U.I.SrcReg[0] = shadow_ambient(compiler, inst->U.I.TexSrcUnit);
+ inst->U.I.SrcReg[0] = shadow_fail_value(compiler, inst->U.I.TexSrcUnit);
}
return 1;
@@ -157,9 +170,11 @@ int radeonTransformTEX(
/* Save the output register. */
struct rc_dst_register output_reg = inst->U.I.DstReg;
+ unsigned saturate_mode = inst->U.I.SaturateMode;
/* Redirect TEX to a new temp. */
tmp_texsample = rc_find_free_temporary(c);
+ inst->U.I.SaturateMode = 0;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = tmp_texsample;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
@@ -235,15 +250,15 @@ int radeonTransformTEX(
inst_cmp = rc_insert_new_instruction(c, inst_add);
inst_cmp->U.I.Opcode = RC_OPCODE_CMP;
+ inst_cmp->U.I.SaturateMode = saturate_mode;
inst_cmp->U.I.DstReg = output_reg;
inst_cmp->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_cmp->U.I.SrcReg[0].Index = tmp_sum;
inst_cmp->U.I.SrcReg[0].Swizzle =
combine_swizzles(RC_SWIZZLE_WWWW,
- compiler->state.unit[inst->U.I.TexSrcUnit].depth_texture_swizzle);
- inst_cmp->U.I.SrcReg[pass].File = RC_FILE_NONE;
- inst_cmp->U.I.SrcReg[pass].Swizzle = RC_SWIZZLE_1111;
- inst_cmp->U.I.SrcReg[fail] = shadow_ambient(compiler, inst->U.I.TexSrcUnit);
+ compiler->state.unit[inst->U.I.TexSrcUnit].texture_swizzle);
+ inst_cmp->U.I.SrcReg[pass] = shadow_pass_value(compiler, inst->U.I.TexSrcUnit);
+ inst_cmp->U.I.SrcReg[fail] = shadow_fail_value(compiler, inst->U.I.TexSrcUnit);
assert(tmp_texsample != tmp_sum);
}
@@ -396,6 +411,7 @@ int radeonTransformTEX(
inst->U.I.SrcReg[0].Index = temp;
}
+ /* NPOT -> POT conversion for 3D textures. */
if (inst->U.I.Opcode != RC_OPCODE_KIL &&
compiler->state.unit[inst->U.I.TexSrcUnit].clamp_and_scale_before_fetch) {
struct rc_instruction *inst_mov;
@@ -425,6 +441,53 @@ int radeonTransformTEX(
scale_texcoords(compiler, inst, RC_STATE_R300_TEXSCALE_FACTOR);
}
+ /* Convert SNORM-encoded ATI1N sampled as UNORM to SNORM.
+ * Formula: dst = tex > 0.5 ? tex*2-2 : tex*2
+ */
+ if (inst->U.I.Opcode != RC_OPCODE_KIL &&
+ compiler->state.unit[inst->U.I.TexSrcUnit].convert_unorm_to_snorm) {
+ unsigned two, two_swizzle;
+ struct rc_instruction *inst_mul, *inst_mad, *inst_cnd;
+
+ two = rc_constants_add_immediate_scalar(&c->Program.Constants, 2.35, &two_swizzle);
+
+ inst_mul = rc_insert_new_instruction(c, inst);
+ inst_mul->U.I.Opcode = RC_OPCODE_MUL;
+ inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
+ inst_mul->U.I.DstReg.Index = rc_find_free_temporary(c);
+ inst_mul->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
+ inst_mul->U.I.SrcReg[0].Index = rc_find_free_temporary(c); /* redirected TEX output */
+ inst_mul->U.I.SrcReg[1].File = RC_FILE_CONSTANT; /* 2 */
+ inst_mul->U.I.SrcReg[1].Index = two;
+ inst_mul->U.I.SrcReg[1].Swizzle = two_swizzle;
+
+ inst_mad = rc_insert_new_instruction(c, inst_mul);
+ inst_mad->U.I.Opcode = RC_OPCODE_MAD;
+ inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY;
+ inst_mad->U.I.DstReg.Index = rc_find_free_temporary(c);
+ inst_mad->U.I.SrcReg[0] = inst_mul->U.I.SrcReg[0]; /* redirected TEX output */
+ inst_mad->U.I.SrcReg[1] = inst_mul->U.I.SrcReg[1]; /* 2 */
+ inst_mad->U.I.SrcReg[2] = inst_mul->U.I.SrcReg[1]; /* 2 */
+ inst_mad->U.I.SrcReg[2].Negate = RC_MASK_XYZW;
+
+ inst_cnd = rc_insert_new_instruction(c, inst_mad);
+ inst_cnd->U.I.Opcode = RC_OPCODE_CND;
+ inst_cnd->U.I.SaturateMode = inst->U.I.SaturateMode;
+ inst_cnd->U.I.DstReg = inst->U.I.DstReg;
+ inst_cnd->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
+ inst_cnd->U.I.SrcReg[0].Index = inst_mad->U.I.DstReg.Index;
+ inst_cnd->U.I.SrcReg[0].Swizzle = compiler->state.unit[inst->U.I.TexSrcUnit].texture_swizzle;
+ inst_cnd->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
+ inst_cnd->U.I.SrcReg[1].Index = inst_mul->U.I.DstReg.Index;
+ inst_cnd->U.I.SrcReg[1].Swizzle = compiler->state.unit[inst->U.I.TexSrcUnit].texture_swizzle;
+ inst_cnd->U.I.SrcReg[2] = inst_mul->U.I.SrcReg[0]; /* redirected TEX output */
+
+ inst->U.I.SaturateMode = 0;
+ inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
+ inst->U.I.DstReg.Index = inst_mul->U.I.SrcReg[0].Index;
+ inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
+ }
+
/* Cannot write texture to output registers or with saturate (all chips),
* or with masks (non-r500). */
if (inst->U.I.Opcode != RC_OPCODE_KIL &&
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 0d8bd4fc706..213d3c060a6 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -133,7 +133,6 @@ static const struct dri_extension card_extensions[] = {
{"GL_ATI_texture_mirror_once", NULL},
{"GL_MESA_pack_invert", NULL},
{"GL_MESA_ycbcr_texture", NULL},
- {"GL_MESAX_texture_float", NULL},
{"GL_NV_blend_square", NULL},
{"GL_NV_vertex_program", GL_NV_vertex_program_functions},
#if FEATURE_OES_EGL_image
diff --git a/src/mesa/drivers/dri/r300/r300_fragprog_common.c b/src/mesa/drivers/dri/r300/r300_fragprog_common.c
index a0a26f1b38d..f0d960dca54 100644
--- a/src/mesa/drivers/dri/r300/r300_fragprog_common.c
+++ b/src/mesa/drivers/dri/r300/r300_fragprog_common.c
@@ -77,8 +77,8 @@ static void build_state(
if (fp->Base.ShadowSamplers & (1 << unit)) {
struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
- state->unit[unit].depth_texture_swizzle = build_dts(tex->DepthMode);
- state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
+ state->unit[unit].texture_swizzle = build_dts(tex->Sampler.DepthMode);
+ state->unit[unit].texture_compare_func = build_func(tex->Sampler.CompareFunc);
}
}
}
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 2b9d85fae8b..8980bd3dde1 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -1906,7 +1906,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_ALU_OUTC_D2A (3 << 23)
# define R300_ALU_OUTC_MIN (4 << 23)
# define R300_ALU_OUTC_MAX (5 << 23)
-# define R300_ALU_OUTC_CMPH (7 << 23)
+# define R300_ALU_OUTC_CND (7 << 23)
# define R300_ALU_OUTC_CMP (8 << 23)
# define R300_ALU_OUTC_FRC (9 << 23)
# define R300_ALU_OUTC_REPL_ALPHA (10 << 23)
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 51989c6b224..da6c8b602e1 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1343,7 +1343,7 @@ static void r300SetupTextures(struct gl_context * ctx)
*/
r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] =
t->pp_txfilter_1 |
- translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.LodBias);
+ translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.Sampler.LodBias);
r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] =
t->pp_txsize;
r300->hw.tex.format.cmd[R300_TEX_VALUE_0 +
@@ -2014,7 +2014,7 @@ static const GLfloat *get_fragmentprogram_constant(struct gl_context *ctx, GLuin
buffer[0] =
buffer[1] =
buffer[2] =
- buffer[3] = texObj->CompareFailValue;
+ buffer[3] = texObj->Sampler.CompareFailValue;
}
return buffer;
}
diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c
index f930b4d06bf..590d9afe14a 100644
--- a/src/mesa/drivers/dri/r300/r300_tex.c
+++ b/src/mesa/drivers/dri/r300/r300_tex.c
@@ -81,13 +81,13 @@ static void r300UpdateTexWrap(radeonTexObjPtr t)
t->pp_txfilter &=
~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK);
- t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT;
+ t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapS) << R300_TX_WRAP_S_SHIFT;
if (tObj->Target != GL_TEXTURE_1D) {
- t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT;
+ t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapT) << R300_TX_WRAP_T_SHIFT;
if (tObj->Target == GL_TEXTURE_3D)
- t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT;
+ t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapR) << R300_TX_WRAP_R_SHIFT;
}
}
@@ -202,7 +202,7 @@ static void r300TexParameter(struct gl_context * ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
+ r300SetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
break;
case GL_TEXTURE_WRAP_S:
@@ -212,7 +212,7 @@ static void r300TexParameter(struct gl_context * ctx, GLenum target,
break;
case GL_TEXTURE_BORDER_COLOR:
- r300SetTexBorderColor(t, texObj->BorderColor.f);
+ r300SetTexBorderColor(t, texObj->Sampler.BorderColor.f);
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -299,12 +299,14 @@ static struct gl_texture_object *r300NewTextureObject(struct gl_context * ctx,
}
_mesa_initialize_texture_object(&t->base, name, target);
- t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
+ t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
/* Initialize hardware state */
r300UpdateTexWrap(t);
- r300SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
- r300SetTexBorderColor(t, t->base.BorderColor.f);
+ r300SetTexFilter(t, t->base.Sampler.MinFilter,
+ t->base.Sampler.MagFilter,
+ t->base.Sampler.MaxAnisotropy);
+ r300SetTexBorderColor(t, t->base.Sampler.BorderColor.f);
return &t->base;
}
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index ed9955b05d8..e24ad6f088d 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -216,7 +216,7 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj)
return;
}
- switch (tObj->DepthMode) {
+ switch (tObj->Sampler.DepthMode) {
case GL_LUMINANCE:
t->pp_txformat = format[0];
break;
diff --git a/src/mesa/drivers/dri/r600/defaultendian.h b/src/mesa/drivers/dri/r600/defaultendian.h
index 32caf32cd2e..75bd61c3cd4 100644
--- a/src/mesa/drivers/dri/r600/defaultendian.h
+++ b/src/mesa/drivers/dri/r600/defaultendian.h
@@ -29,8 +29,8 @@
#define _DEFINEENDIAN_H_
//We have to choose a reg bits orientation if there is no compile flag for it.
-#if defined(LITTLEENDIAN_CPU)
-#elif defined(BIGENDIAN_CPU)
+#ifdef MESA_BIG_ENDIAN
+#define BIGENDIAN_CPU
#else
#define LITTLEENDIAN_CPU
#endif
diff --git a/src/mesa/drivers/dri/r600/evergreen_blit.c b/src/mesa/drivers/dri/r600/evergreen_blit.c
index e07da8c15b4..0e4da5499ba 100644
--- a/src/mesa/drivers/dri/r600/evergreen_blit.c
+++ b/src/mesa/drivers/dri/r600/evergreen_blit.c
@@ -98,10 +98,11 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
uint32_t cb_color0_base, cb_color0_info = 0;
uint32_t cb_color0_pitch = 0, cb_color0_slice = 0, cb_color0_attrib = 0;
int id = 0;
- uint32_t comp_swap, format, source_format, number_type;
+ uint32_t endian, comp_swap, format, source_format, number_type;
BATCH_LOCALS(&context->radeon);
cb_color0_base = dst_offset / 256;
+ endian = ENDIAN_NONE;
/* pitch */
SETfield(cb_color0_pitch, (nPitchInPixel / 8) - 1,
@@ -119,10 +120,6 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
SETfield(cb_color0_info,
- ENDIAN_NONE,
- EG_CB_COLOR0_INFO__ENDIAN_shift,
- EG_CB_COLOR0_INFO__ENDIAN_mask);
- SETfield(cb_color0_info,
ARRAY_LINEAR_GENERAL,
EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
@@ -131,24 +128,36 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
switch(mesa_format) {
case MESA_FORMAT_RGBA8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD_REV;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_SIGNED_RGBA8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD_REV;
number_type = NUMBER_SNORM;
source_format = 1;
break;
case MESA_FORMAT_RGBA8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_SIGNED_RGBA8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD;
number_type = NUMBER_SNORM;
@@ -156,6 +165,9 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
break;
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_XRGB8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT;
number_type = NUMBER_UNORM;
@@ -163,54 +175,81 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
break;
case MESA_FORMAT_ARGB8888_REV:
case MESA_FORMAT_XRGB8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_RGB565:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_5_6_5;
comp_swap = SWAP_STD_REV;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_RGB565_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_5_6_5;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_ARGB4444:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_4_4_4_4;
comp_swap = SWAP_ALT;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_ARGB4444_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_4_4_4_4;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_ARGB1555:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_1_5_5_5;
comp_swap = SWAP_ALT;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_ARGB1555_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_1_5_5_5;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_AL88:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
source_format = 1;
break;
case MESA_FORMAT_AL88_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_STD_REV;
number_type = NUMBER_UNORM;
@@ -242,60 +281,90 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
source_format = 1;
break;
case MESA_FORMAT_RGBA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_32_32_32_FLOAT;
comp_swap = SWAP_STD;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_RGBA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_16_16_16_FLOAT;
comp_swap = SWAP_STD;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_ALPHA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_ALPHA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_LUMINANCE_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_ALT;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_LUMINANCE_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_ALT;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_32_FLOAT;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_16_FLOAT;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_STD;
number_type = NUMBER_FLOAT;
source_format = 0;
break;
case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
@@ -303,6 +372,9 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
break;
case MESA_FORMAT_X8_Z24:
case MESA_FORMAT_S8_Z24:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_24;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
@@ -313,6 +385,9 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
source_format = 0;
break;
case MESA_FORMAT_Z24_S8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_24_8;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
@@ -323,6 +398,9 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
source_format = 0;
break;
case MESA_FORMAT_Z16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
@@ -333,6 +411,9 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
source_format = 0;
break;
case MESA_FORMAT_Z32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32;
comp_swap = SWAP_STD;
number_type = NUMBER_UNORM;
@@ -343,12 +424,18 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
source_format = 0;
break;
case MESA_FORMAT_SARGB8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT;
number_type = NUMBER_SRGB;
source_format = 1;
break;
case MESA_FORMAT_SLA8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_ALT_REV;
number_type = NUMBER_SRGB;
@@ -367,6 +454,10 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
}
SETfield(cb_color0_info,
+ endian,
+ EG_CB_COLOR0_INFO__ENDIAN_shift,
+ EG_CB_COLOR0_INFO__ENDIAN_mask);
+ SETfield(cb_color0_info,
format,
EG_CB_COLOR0_INFO__FORMAT_shift,
EG_CB_COLOR0_INFO__FORMAT_mask);
@@ -441,10 +532,10 @@ static inline void eg_load_shaders(struct gl_context * ctx)
shader = context->blit_bo->ptr;
for(i=0; i<sizeof(evergreen_vs)/4; i++) {
- shader[128+i] = evergreen_vs[i];
+ shader[128+i] = CPU_TO_LE32(evergreen_vs[i]);
}
for(i=0; i<sizeof(evergreen_ps)/4; i++) {
- shader[256+i] = evergreen_ps[i];
+ shader[256+i] = CPU_TO_LE32(evergreen_ps[i]);
}
radeon_bo_unmap(context->blit_bo);
@@ -525,6 +616,7 @@ eg_set_vtx_resource(context_t *context)
{
struct radeon_bo *bo = context->blit_bo;
uint32_t sq_vtx_constant_word3 = 0;
+ uint32_t sq_vtx_constant_word2 = 0;
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -555,13 +647,19 @@ eg_set_vtx_resource(context_t *context)
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
+ sq_vtx_constant_word2 = 0
+#ifdef MESA_BIG_ENDIAN
+ | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
+#endif
+ | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
+
BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
R600_OUT_BATCH(EG_SQ_FETCH_RESOURCE_VS_OFFSET * EG_FETCH_RESOURCE_STRIDE);
R600_OUT_BATCH(0);
R600_OUT_BATCH(48 - 1);
- R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
+ R600_OUT_BATCH(sq_vtx_constant_word2);
R600_OUT_BATCH(sq_vtx_constant_word3);
R600_OUT_BATCH(0);
R600_OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h b/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h
index eb025280739..84f20f8cafb 100644
--- a/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h
+++ b/src/mesa/drivers/dri/r600/evergreen_blit_shaders.h
@@ -37,11 +37,19 @@ const uint32_t evergreen_vs[] =
0x00000000,
0x3c000000,
0x67961001,
+#ifdef MESA_BIG_ENDIAN
+ 0x000a0000,
+#else
0x00080000,
+#endif
0x00000000,
0x1c000000,
0x67961000,
+#ifdef MESA_BIG_ENDIAN
+ 0x00020008,
+#else
0x00000008,
+#endif
0x00000000,
};
diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c
index 53dacbfdf39..42566e537a5 100644
--- a/src/mesa/drivers/dri/r600/evergreen_chip.c
+++ b/src/mesa/drivers/dri/r600/evergreen_chip.c
@@ -124,7 +124,7 @@ static void evergreenSendTexState(struct gl_context *ctx, struct radeon_state_at
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_vertex_program *vp = context->selected_vp;
+ struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
struct radeon_bo *bo = NULL;
unsigned int i;
@@ -307,6 +307,16 @@ static void evergreenSetupVTXConstants(struct gl_context * ctx,
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
+
+ SETfield(uSQ_VTX_CONSTANT_WORD2_0,
+#ifdef MESA_BIG_ENDIAN
+ SQ_ENDIAN_8IN32,
+#else
+ SQ_ENDIAN_NONE,
+#endif
+ SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
+ SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
+
if(GL_TRUE == pStreamDesc->normalize)
{
SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
@@ -379,6 +389,8 @@ static void evergreenSendVTX(struct gl_context *ctx, struct radeon_state_atom *a
struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
unsigned int i, j = 0;
BATCH_LOCALS(&context->radeon);
+ (void) b_l_rmesa; /* silence unused var warning */
+
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (context->radeon.tcl.aos_count == 0)
diff --git a/src/mesa/drivers/dri/r600/evergreen_oglprog.c b/src/mesa/drivers/dri/r600/evergreen_oglprog.c
index a2a361f32e6..1fd655e85f8 100644
--- a/src/mesa/drivers/dri/r600/evergreen_oglprog.c
+++ b/src/mesa/drivers/dri/r600/evergreen_oglprog.c
@@ -42,7 +42,7 @@
static void evergreen_freeVertProgCache(struct gl_context *ctx, struct r700_vertex_program_cont *cache)
{
- struct evergreen_vertex_program *tmp, *vp = cache->progs;
+ struct evergreen_vertex_program *tmp, *vp = (struct evergreen_vertex_program *) cache->progs;
while (vp) {
tmp = vp->next;
@@ -121,7 +121,7 @@ static void evergreenDeleteProgram(struct gl_context * ctx, struct gl_program *p
{
case GL_VERTEX_STATE_PROGRAM_NV:
case GL_VERTEX_PROGRAM_ARB:
- evergreen_freeVertProgCache(ctx, vpc);
+ evergreen_freeVertProgCache(ctx, (struct r700_vertex_program_cont *) vpc);
break;
case GL_FRAGMENT_PROGRAM_NV:
case GL_FRAGMENT_PROGRAM_ARB:
@@ -154,7 +154,7 @@ evergreenProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_p
switch (target) {
case GL_VERTEX_PROGRAM_ARB:
- evergreen_freeVertProgCache(ctx, vpc);
+ evergreen_freeVertProgCache(ctx, (struct r700_vertex_program_cont *) vpc);
vpc->progs = NULL;
break;
case GL_FRAGMENT_PROGRAM_ARB:
diff --git a/src/mesa/drivers/dri/r600/evergreen_render.c b/src/mesa/drivers/dri/r600/evergreen_render.c
index 6e51832c878..4507be29d86 100644
--- a/src/mesa/drivers/dri/r600/evergreen_render.c
+++ b/src/mesa/drivers/dri/r600/evergreen_render.c
@@ -180,6 +180,15 @@ static void evergreenRunRenderPrimitive(struct gl_context * ctx, int start, int
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
+ /* 16-bit indexes are packed in a 32-bit value */
+ SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+ VGT_DMA_SWAP_32_BIT,
+#else
+ VGT_DMA_SWAP_NONE,
+#endif
+ SWAP_MODE_shift, SWAP_MODE_mask);
+
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
@@ -252,6 +261,15 @@ static void evergreenRunRenderPrimitiveImmediate(struct gl_context * ctx, int st
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
+ /* 16-bit indexes are packed in a 32-bit value */
+ SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+ VGT_DMA_SWAP_32_BIT,
+#else
+ VGT_DMA_SWAP_NONE,
+#endif
+ SWAP_MODE_shift, SWAP_MODE_mask);
+
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
@@ -620,6 +638,7 @@ static void evergreenSetupIndexBuffer(struct gl_context *ctx, const struct _mesa
}
}
+#if 0 /* unused */
static void evergreenAlignDataToDword(struct gl_context *ctx,
const struct gl_client_array *input,
int count,
@@ -661,6 +680,7 @@ static void evergreenAlignDataToDword(struct gl_context *ctx,
attr->stride = dst_stride;
}
+#endif
static void evergreenSetupStreams(struct gl_context *ctx, const struct gl_client_array *input[], int count)
{
diff --git a/src/mesa/drivers/dri/r600/evergreen_tex.c b/src/mesa/drivers/dri/r600/evergreen_tex.c
index 3b5448a0e4e..33a5f277683 100644
--- a/src/mesa/drivers/dri/r600/evergreen_tex.c
+++ b/src/mesa/drivers/dri/r600/evergreen_tex.c
@@ -97,6 +97,16 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -105,6 +115,7 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -122,6 +133,16 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -130,6 +151,7 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -146,6 +168,16 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -154,12 +186,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_XRGB8888:
SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -168,26 +211,48 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_XRGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -196,12 +261,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB888:
SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -210,12 +286,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB565:
SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -224,12 +311,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB565_REV:
SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -238,12 +336,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB4444:
SETfield(t->SQ_TEX_RESOURCE7, FMT_4_4_4_4,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -252,12 +361,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB4444_REV:
SETfield(t->SQ_TEX_RESOURCE7, FMT_4_4_4_4,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -266,12 +386,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB1555:
SETfield(t->SQ_TEX_RESOURCE7, FMT_1_5_5_5,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -280,12 +411,23 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB1555_REV:
SETfield(t->SQ_TEX_RESOURCE7, FMT_1_5_5_5,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -294,6 +436,7 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_AL88:
case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
@@ -581,7 +724,7 @@ static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format
default:
break;
};
- switch (tObj->DepthMode) {
+ switch (tObj->Sampler.DepthMode) {
case GL_LUMINANCE: /* X, X, X, ONE */
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
@@ -699,18 +842,18 @@ static void evergreenUpdateTexWrap(radeonTexObjPtr t)
{
struct gl_texture_object *tObj = &t->base;
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->WrapS),
+ SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->Sampler.WrapS),
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
if (tObj->Target != GL_TEXTURE_1D)
{
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->WrapT),
+ SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->Sampler.WrapT),
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_shift,
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_mask);
if (tObj->Target == GL_TEXTURE_3D)
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->WrapR),
+ SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->Sampler.WrapR),
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_shift,
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_mask);
}
@@ -1022,21 +1165,21 @@ static GLboolean evergreen_setup_hardware_state(struct gl_context * ctx, struct
SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
SETfield(t->SQ_TEX_SAMPLER1,
- EG_S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 8),
+ EG_S_FIXED(CLAMP(t->base.Sampler.MinLod - t->minLod, 0, 15), 8),
EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift,
EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask);
SETfield(t->SQ_TEX_SAMPLER1,
- EG_S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 8),
+ EG_S_FIXED(CLAMP(t->base.Sampler.MaxLod - t->minLod, 0, 15), 8),
EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift,
EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask);
SETfield(t->SQ_TEX_SAMPLER2,
- EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 8),
+ EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.Sampler.LodBias, -16, 16), 8),
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift,
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask);
- if(texObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
+ if(texObj->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
{
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_shadow_func(texObj->CompareFunc),
+ SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_shadow_func(texObj->Sampler.CompareFunc),
EG_SQ_TEX_SAMPLER_WORD0_0__DCF_shift,
EG_SQ_TEX_SAMPLER_WORD0_0__DCF_mask);
}
@@ -1420,12 +1563,12 @@ static struct gl_texture_object *evergreenNewTextureObject(struct gl_context * c
t, _mesa_lookup_enum_by_nr(target));
_mesa_initialize_texture_object(&t->base, name, target);
- t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
+ t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
evergreenSetTexDefaultState(t);
evergreenUpdateTexWrap(t);
- evergreenSetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
- evergreenSetTexBorderColor(t, t->base.BorderColor.f);
+ evergreenSetTexFilter(t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter, t->base.Sampler.MaxAnisotropy);
+ evergreenSetTexBorderColor(t, t->base.Sampler.BorderColor.f);
return &t->base;
}
@@ -1475,7 +1618,7 @@ static void evergreenTexParameter(struct gl_context * ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- evergreenSetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
+ evergreenSetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
break;
case GL_TEXTURE_WRAP_S:
@@ -1485,7 +1628,7 @@ static void evergreenTexParameter(struct gl_context * ctx, GLenum target,
break;
case GL_TEXTURE_BORDER_COLOR:
- evergreenSetTexBorderColor(t, texObj->BorderColor.f);
+ evergreenSetTexBorderColor(t, texObj->Sampler.BorderColor.f);
break;
case GL_TEXTURE_BASE_LEVEL:
diff --git a/src/mesa/drivers/dri/r600/evergreen_vertprog.c b/src/mesa/drivers/dri/r600/evergreen_vertprog.c
index b3371f20b19..018869b9996 100644
--- a/src/mesa/drivers/dri/r600/evergreen_vertprog.c
+++ b/src/mesa/drivers/dri/r600/evergreen_vertprog.c
@@ -405,7 +405,7 @@ void evergreenSelectVertexShader(struct gl_context *ctx)
}
if (match)
{
- context->selected_vp = vp;
+ context->selected_vp = (struct r700_vertex_program *) vp;
return;
}
}
@@ -418,7 +418,7 @@ void evergreenSelectVertexShader(struct gl_context *ctx)
}
vp->next = vpc->progs;
vpc->progs = vp;
- context->selected_vp = vp;
+ context->selected_vp = (struct r700_vertex_program *) vp;
return;
}
@@ -566,7 +566,7 @@ void evergreenSetVertexFormat(struct gl_context *ctx, const struct gl_client_arr
void * evergreenGetActiveVpShaderBo(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program *vp = context->selected_vp;;
+ struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
if (vp)
return vp->shaderbo;
@@ -577,7 +577,7 @@ void * evergreenGetActiveVpShaderBo(struct gl_context * ctx)
void * evergreenGetActiveVpShaderConstBo(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program *vp = context->selected_vp;;
+ struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
if (vp)
return vp->constbo0;
@@ -589,7 +589,7 @@ GLboolean evergreenSetupVertexProgram(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_vertex_program *vp = context->selected_vp;
+ struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
if(GL_FALSE == vp->loaded)
{
@@ -650,7 +650,7 @@ GLboolean evergreenSetupVPconstants(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_vertex_program *vp = context->selected_vp;
+ struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
struct gl_program_parameter_list *paramList;
unsigned int unNumParamData;
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 31c32d62f9a..2d47afdcbbf 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -94,17 +94,17 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
{
uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
int id = 0;
- uint32_t comp_swap, format;
+ uint32_t endian, comp_swap, format;
BATCH_LOCALS(&context->radeon);
cb_color0_base = dst_offset / 256;
+ endian = ENDIAN_NONE;
SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
- SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
@@ -112,24 +112,36 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
switch(mesa_format) {
case MESA_FORMAT_RGBA8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SIGNED_RGBA8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGBA8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SIGNED_RGBA8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -137,6 +149,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
break;
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_XRGB8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -144,54 +159,81 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
break;
case MESA_FORMAT_ARGB8888_REV:
case MESA_FORMAT_XRGB8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGB565:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
+ comp_swap = SWAP_STD_REV;
format = COLOR_5_6_5;
- comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGB565_REV:
- format = COLOR_5_6_5;
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
comp_swap = SWAP_STD;
+ format = COLOR_5_6_5;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB4444:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_4_4_4_4;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB4444_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_4_4_4_4;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB1555:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_1_5_5_5;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB1555_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_1_5_5_5;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_AL88:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_AL88_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -223,6 +265,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGBA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_32_32_32_FLOAT;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -230,12 +275,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGBA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_16_16_16_FLOAT;
comp_swap = SWAP_STD;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ALPHA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -243,12 +294,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ALPHA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_ALT_REV;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -256,12 +313,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_ALT;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_32_FLOAT;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -269,12 +332,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_16_FLOAT;
comp_swap = SWAP_ALT_REV;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -282,6 +351,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_STD;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -289,6 +361,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
break;
case MESA_FORMAT_X8_Z24:
case MESA_FORMAT_S8_Z24:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_24;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -297,6 +372,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_Z24_S8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_24_8;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -305,6 +383,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_Z16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -313,6 +394,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_Z32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -321,12 +405,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SARGB8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SLA8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -348,6 +438,7 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
+ SETfield(cb_color0_info, endian, ENDIAN_shift, ENDIAN_mask);
SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
CB_COLOR0_INFO__FORMAT_mask);
SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
@@ -426,10 +517,10 @@ static inline void load_shaders(struct gl_context * ctx)
shader = context->blit_bo->ptr;
for(i=0; i<sizeof(r6xx_vs)/4; i++) {
- shader[128+i] = r6xx_vs[i];
+ shader[128+i] = CPU_TO_LE32(r6xx_vs[i]);
}
for(i=0; i<sizeof(r6xx_ps)/4; i++) {
- shader[256+i] = r6xx_ps[i];
+ shader[256+i] = CPU_TO_LE32(r6xx_ps[i]);
}
radeon_bo_unmap(context->blit_bo);
@@ -521,6 +612,8 @@ static inline void
set_vtx_resource(context_t *context)
{
struct radeon_bo *bo = context->blit_bo;
+ uint32_t sq_vtx_constant_word2 = 0;
+
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -543,13 +636,19 @@ set_vtx_resource(context_t *context)
else
r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
+ sq_vtx_constant_word2 = 0
+#ifdef MESA_BIG_ENDIAN
+ | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
+#endif
+ | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
+
BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
R600_OUT_BATCH(0);
R600_OUT_BATCH(48 - 1);
- R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
+ R600_OUT_BATCH(sq_vtx_constant_word2);
R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
R600_OUT_BATCH(0);
R600_OUT_BATCH(0);
@@ -670,11 +769,11 @@ set_tex_resource(context_t * context,
SETfield(sq_tex_resource1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
+ SETfield(sq_tex_resource4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(sq_tex_resource4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
+ SETfield(sq_tex_resource4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(sq_tex_resource4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
diff --git a/src/mesa/drivers/dri/r600/r600_blit_shaders.h b/src/mesa/drivers/dri/r600/r600_blit_shaders.h
index 492dde96368..2124f7673d7 100644
--- a/src/mesa/drivers/dri/r600/r600_blit_shaders.h
+++ b/src/mesa/drivers/dri/r600/r600_blit_shaders.h
@@ -10,7 +10,11 @@ const uint32_t r6xx_vs[] =
0x00000000,
0x3c000000, // SQ_VTX_INST_FETCH BUFFER_ID(0) MEGA_FETCH_COUNT(16)
0x68cd1000, // DST_GPR(0) DST_SWZ: XYZW DATA_FORMAT(35) SQ_NUM_FORMAT_SCALED SQ_FORMAT_COMP_SIGNED
+#ifdef MESA_BIG_ENDIAN
+ 0x000a0000, // ENDIAN_SWAP(SQ_ENDIAN_8IN32) MEGA_FETCH(1)
+#else
0x00080000, // ENDIAN_SWAP(SQ_ENDIAN_NONE) MEGA_FETCH(1)
+#endif
0x00000000, // VTX_DWORD_PAD
};
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 00708be1993..1b9676147ee 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -145,7 +145,6 @@ static const struct dri_extension card_extensions[] = {
{"GL_ATI_texture_mirror_once", NULL},
{"GL_MESA_pack_invert", NULL},
{"GL_MESA_ycbcr_texture", NULL},
- {"GL_MESAX_texture_float", NULL},
{"GL_NV_blend_square", NULL},
{"GL_NV_vertex_program", GL_NV_vertex_program_functions},
{"GL_ARB_pixel_buffer_object", NULL},
diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c
index 53ece9a3505..c6916ed98a3 100644
--- a/src/mesa/drivers/dri/r600/r600_emit.c
+++ b/src/mesa/drivers/dri/r600/r600_emit.c
@@ -100,14 +100,17 @@ GLboolean r600EmitShaderConsts(struct gl_context * ctx,
int sizeinBYTE)
{
struct radeon_bo * pbo = (struct radeon_bo *)constbo;
- uint8_t *out;
+ uint32_t *out;
+ int i;
radeon_bo_map(pbo, 1);
- out = (uint8_t*)(pbo->ptr);
- out = (uint8_t*)ADD_POINTERS(pbo->ptr, bo_offset);
+ out = (uint32_t*)(pbo->ptr);
+ out = (uint32_t*)ADD_POINTERS(pbo->ptr, bo_offset);
- memcpy(out, data, sizeinBYTE);
+ for(i = 0; i < sizeinBYTE / 4; i++) {
+ out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
+ }
radeon_bo_unmap(pbo);
@@ -123,6 +126,7 @@ GLboolean r600EmitShader(struct gl_context * ctx,
radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
struct radeon_bo * pbo;
uint32_t *out;
+ int i;
shader_again_alloc:
pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
0,
@@ -154,7 +158,9 @@ shader_again_alloc:
out = (uint32_t*)(pbo->ptr);
- memcpy(out, data, sizeinDWORD * 4);
+ for(i = 0; i < sizeinDWORD; i++) {
+ out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
+ }
radeon_bo_unmap(pbo);
diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index fe4f0e48661..eb7ed30c7a3 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -78,15 +78,15 @@ static void r600UpdateTexWrap(radeonTexObjPtr t)
{
struct gl_texture_object *tObj = &t->base;
- SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapS),
+ SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->Sampler.WrapS),
SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
if (tObj->Target != GL_TEXTURE_1D) {
- SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapT),
+ SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->Sampler.WrapT),
CLAMP_Y_shift, CLAMP_Y_mask);
if (tObj->Target == GL_TEXTURE_3D)
- SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapR),
+ SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->Sampler.WrapR),
CLAMP_Z_shift, CLAMP_Z_mask);
}
}
@@ -292,7 +292,7 @@ static void r600TexParameter(struct gl_context * ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
+ r600SetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
break;
case GL_TEXTURE_WRAP_S:
@@ -302,7 +302,7 @@ static void r600TexParameter(struct gl_context * ctx, GLenum target,
break;
case GL_TEXTURE_BORDER_COLOR:
- r600SetTexBorderColor(t, texObj->BorderColor.f);
+ r600SetTexBorderColor(t, texObj->Sampler.BorderColor.f);
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -382,13 +382,13 @@ static struct gl_texture_object *r600NewTextureObject(struct gl_context * ctx,
t, _mesa_lookup_enum_by_nr(target));
_mesa_initialize_texture_object(&t->base, name, target);
- t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
+ t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
/* Initialize hardware state */
r600SetTexDefaultState(t);
r600UpdateTexWrap(t);
- r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
- r600SetTexBorderColor(t, t->base.BorderColor.f);
+ r600SetTexFilter(t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter, t->base.Sampler.MaxAnisotropy);
+ r600SetTexBorderColor(t, t->base.Sampler.BorderColor.f);
return &t->base;
}
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index aafa6875774..949db29c189 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -109,6 +109,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -117,6 +127,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -133,6 +144,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -141,6 +162,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -156,6 +178,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -164,11 +196,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_XRGB8888:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -177,24 +220,46 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_XRGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -203,11 +268,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB888:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -216,11 +292,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB565:
SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -229,11 +316,23 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
+
break;
case MESA_FORMAT_RGB565_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -242,11 +341,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB4444:
SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -255,11 +365,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB4444_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -268,11 +388,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB1555:
SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -281,11 +411,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB1555_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -294,6 +434,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_AL88:
case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
@@ -571,7 +712,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
default:
break;
};
- switch (tObj->DepthMode) {
+ switch (tObj->Sampler.DepthMode) {
case GL_LUMINANCE: /* X, X, X, ONE */
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
@@ -777,18 +918,18 @@ static GLboolean setup_hardware_state(struct gl_context * ctx, struct gl_texture
SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
SETfield(t->SQ_TEX_SAMPLER1,
- S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 6),
+ S_FIXED(CLAMP(t->base.Sampler.MinLod - t->minLod, 0, 15), 6),
MIN_LOD_shift, MIN_LOD_mask);
SETfield(t->SQ_TEX_SAMPLER1,
- S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 6),
+ S_FIXED(CLAMP(t->base.Sampler.MaxLod - t->minLod, 0, 15), 6),
MAX_LOD_shift, MAX_LOD_mask);
SETfield(t->SQ_TEX_SAMPLER1,
- S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 6),
+ S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.Sampler.LodBias, -16, 16), 6),
SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift, SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask);
- if(texObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
+ if(texObj->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
{
- SETfield(t->SQ_TEX_SAMPLER0, r600_translate_shadow_func(texObj->CompareFunc), DEPTH_COMPARE_FUNCTION_shift, DEPTH_COMPARE_FUNCTION_mask);
+ SETfield(t->SQ_TEX_SAMPLER0, r600_translate_shadow_func(texObj->Sampler.CompareFunc), DEPTH_COMPARE_FUNCTION_shift, DEPTH_COMPARE_FUNCTION_mask);
}
else
{
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 024853c1beb..216ff0b941c 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -259,6 +259,7 @@ GLboolean is_reduction_opcode(PVSDWORD* dest)
return GL_FALSE;
}
+#if 0 /* unused */
GLboolean EG_is_reduction_opcode(PVSDWORD* dest)
{
if (dest->dst.op3 == 0)
@@ -270,6 +271,7 @@ GLboolean EG_is_reduction_opcode(PVSDWORD* dest)
}
return GL_FALSE;
}
+#endif
GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size)
{
@@ -1186,7 +1188,12 @@ GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
EG_VTX_WORD2__OFFSET_shift,
EG_VTX_WORD2__OFFSET_mask);
- SETfield(vfetch_instruction_ptr->m_Word2.val, SQ_ENDIAN_NONE,
+ SETfield(vfetch_instruction_ptr->m_Word2.val,
+#ifdef MESA_BIG_ENDIAN
+ SQ_ENDIAN_8IN32,
+#else
+ SQ_ENDIAN_NONE,
+#endif
EG_VTX_WORD2__ENDIAN_SWAP_shift,
EG_VTX_WORD2__ENDIAN_SWAP_mask);
SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
@@ -1292,7 +1299,11 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1;
vfetch_instruction_ptr->m_Word1.f.data_format = data_format;
+#ifdef MESA_BIG_ENDIAN
+ vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_8IN32;
+#else
vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_NONE;
+#endif
if(1 == _signed)
{
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h
index c7c7ab2d4ff..8a9ccd1c4ec 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.h
+++ b/src/mesa/drivers/dri/r600/r700_assembler.h
@@ -130,6 +130,27 @@ typedef unsigned int BITS;
typedef struct PVSDSTtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS addrmode1:1; //32
+ BITS addrmode0:1; //31 //29
+
+ BITS dualop:1; // 30 //26
+
+ BITS op3:1; // 29 Represents *_OP3_* ALU opcode
+
+ BITS writew:1; //28
+ BITS writez:1;
+ BITS writey:1;
+ BITS writex:1;
+
+ BITS reg:10; //24 //20
+ BITS rtype:3;
+
+ BITS pred_inv :1; //11 //8
+ BITS predicated:1; //10 //8
+ BITS math:1;
+ BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2
+#else
BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2
BITS math:1;
BITS predicated:1; //10 //8
@@ -149,17 +170,41 @@ typedef struct PVSDSTtag
BITS addrmode0:1; //31 //29
BITS addrmode1:1; //32
+#endif
} PVSDST;
typedef struct PVSINSTtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS index_mode :3;
+ BITS SaturateMode :2;
+ BITS literal_slots :2;
+#else
BITS literal_slots :2;
BITS SaturateMode :2;
BITS index_mode :3;
+#endif
} PVSINST;
typedef struct PVSSRCtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS addrmode1:1; //32
+ //BITS addrsel:2;
+ BITS negw:1; //31
+ BITS negz:1;
+ BITS negy:1;
+ BITS negx:1;
+ BITS abs:1;
+
+ BITS swizzlew:3; //26
+ BITS swizzlez:3;
+ BITS swizzley:3;
+ BITS swizzlex:3;
+ BITS reg:10; //14 (8)
+ BITS addrmode0:1;
+ BITS rtype:3;
+#else
BITS rtype:3;
BITS addrmode0:1;
BITS reg:10; //14 (8)
@@ -175,10 +220,24 @@ typedef struct PVSSRCtag
BITS negw:1; //31
//BITS addrsel:2;
BITS addrmode1:1; //32
+#endif
} PVSSRC;
typedef struct PVSMATHtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS spare2:3;
+ BITS dstcomp:2; // select dest component
+ BITS negy:1;
+ BITS negx:1;
+ BITS opcode:4;
+ BITS dstoff:2; // 2 bits of dest offset into alt ram
+ BITS swizzley:3;
+ BITS swizzlex:3;
+ BITS reg:8;
+ BITS spare:1;
+ BITS rtype:4;
+#else
BITS rtype:4;
BITS spare:1;
BITS reg:8;
@@ -190,6 +249,7 @@ typedef struct PVSMATHtag
BITS negy:1;
BITS dstcomp:2; // select dest component
BITS spare2:3;
+#endif
} PVSMATH;
typedef union PVSDWORDtag
@@ -204,6 +264,34 @@ typedef union PVSDWORDtag
typedef struct VAP_OUT_VTX_FMT_0tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd1:12; // 20
+
+ BITS viewport_index:1; // 19
+ BITS kill_flag:1;
+ BITS rta_index:1; // shares same channel as kill_flag
+ BITS edge_flag:1;
+ BITS point_size:1; // 15
+
+ BITS depth:1; // 14
+
+ BITS normal:1;
+
+ BITS color7:1;
+ BITS color6:1;
+ BITS color5:1;
+ BITS color4:1;
+ BITS color3:1;
+ BITS color2:1;
+ BITS color1:1;
+ BITS color0:1;
+
+ BITS pos_param:1; // 4
+ BITS clip_dist1:1;
+ BITS clip_dist0:1;
+ BITS misc:1;
+ BITS pos:1; // 0
+#else
BITS pos:1; // 0
BITS misc:1;
BITS clip_dist0:1;
@@ -230,10 +318,23 @@ typedef struct VAP_OUT_VTX_FMT_0tag
BITS viewport_index:1; // 19
BITS resvd1:12; // 20
+#endif
} VAP_OUT_VTX_FMT_0;
typedef struct VAP_OUT_VTX_FMT_1tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd:8;
+
+ BITS tex7comp:3;
+ BITS tex6comp:3;
+ BITS tex5comp:3;
+ BITS tex4comp:3;
+ BITS tex3comp:3;
+ BITS tex2comp:3;
+ BITS tex1comp:3;
+ BITS tex0comp:3;
+#else
BITS tex0comp:3;
BITS tex1comp:3;
BITS tex2comp:3;
@@ -244,10 +345,23 @@ typedef struct VAP_OUT_VTX_FMT_1tag
BITS tex7comp:3;
BITS resvd:8;
+#endif
} VAP_OUT_VTX_FMT_1;
typedef struct VAP_OUT_VTX_FMT_2tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd:8;
+
+ BITS tex15comp:3;
+ BITS tex14comp:3;
+ BITS tex13comp:3;
+ BITS tex12comp:3;
+ BITS tex11comp:3;
+ BITS tex10comp:3;
+ BITS tex9comp:3;
+ BITS tex8comp:3;
+#else
BITS tex8comp :3;
BITS tex9comp :3;
BITS tex10comp:3;
@@ -258,10 +372,28 @@ typedef struct VAP_OUT_VTX_FMT_2tag
BITS tex15comp:3;
BITS resvd:8;
+#endif
} VAP_OUT_VTX_FMT_2;
typedef struct OUT_FRAGMENT_FMT_0tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd1:20;
+
+ BITS mask:1;
+ BITS coverage_to_mask:1;
+ BITS stencil_ref:1;
+ BITS depth:1;
+
+ BITS color7:1;
+ BITS color6:1;
+ BITS color5:1;
+ BITS color4:1;
+ BITS color3:1;
+ BITS color2:1;
+ BITS color1:1;
+ BITS color0:1;
+#else
BITS color0:1;
BITS color1:1;
BITS color2:1;
@@ -277,6 +409,7 @@ typedef struct OUT_FRAGMENT_FMT_0tag
BITS mask:1;
BITS resvd1:20;
+#endif
} OUT_FRAGMENT_FMT_0;
typedef enum CF_CLAUSE_TYPE
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 4ec2845ab44..10fa3f9762b 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -202,7 +202,15 @@ static void r700SetupVTXConstants(struct gl_context * ctx,
SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
-
+ SETfield(uSQ_VTX_CONSTANT_WORD2_0,
+#ifdef MESA_BIG_ENDIAN
+ SQ_ENDIAN_8IN32,
+#else
+ SQ_ENDIAN_NONE,
+#endif
+ SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
+ SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
+
if(GL_TRUE == pStreamDesc->normalize)
{
SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
@@ -249,6 +257,7 @@ static void r700SendVTXState(struct gl_context *ctx, struct radeon_state_atom *a
struct r700_vertex_program *vp = context->selected_vp;
unsigned int i, j = 0;
BATCH_LOCALS(&context->radeon);
+ (void) b_l_rmesa; /* silence unused var warning */
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
if (context->radeon.tcl.aos_count == 0)
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index bb14a239b77..2bd3b62bfdb 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -276,6 +276,16 @@ static void r700RunRenderPrimitive(struct gl_context * ctx, int start, int end,
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
+ /* 16-bit indexes are packed in a 32-bit value */
+ SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+ VGT_DMA_SWAP_32_BIT,
+#else
+ VGT_DMA_SWAP_NONE,
+#endif
+ SWAP_MODE_shift, SWAP_MODE_mask);
+
+
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
@@ -348,6 +358,15 @@ static void r700RunRenderPrimitiveImmediate(struct gl_context * ctx, int start,
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
+ /* 16-bit indexes are packed in a 32-bit value */
+ SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+ VGT_DMA_SWAP_32_BIT,
+#else
+ VGT_DMA_SWAP_NONE,
+#endif
+ SWAP_MODE_shift, SWAP_MODE_mask);
+
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
@@ -580,6 +599,7 @@ static void r700ConvertAttrib(struct gl_context *ctx, int count,
}
}
+#if 0 /* unused */
static void r700AlignDataToDword(struct gl_context *ctx,
const struct gl_client_array *input,
int count,
@@ -621,6 +641,7 @@ static void r700AlignDataToDword(struct gl_context *ctx,
attr->stride = dst_stride;
}
+#endif
static void r700SetupStreams(struct gl_context *ctx, const struct gl_client_array *input[], int count)
{
diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
index 60f10496026..607b7470d4b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
@@ -1,6 +1,10 @@
#ifndef RADEON_CS_WRAPPER_H
#define RADEON_CS_WRAPPER_H
+/* to be used to build locally in mesa with no libdrm bits */
+#include "../radeon/radeon_bo_drm.h"
+#include "../radeon/radeon_cs_drm.h"
+
#ifdef HAVE_LIBDRM_RADEON
#include "radeon_bo.h"
@@ -24,10 +28,6 @@
* when mapped - i.e. front buffer */
#endif
-/* to be used to build locally in mesa with no libdrm bits */
-#include "../radeon/radeon_bo_drm.h"
-#include "../radeon/radeon_cs_drm.h"
-
#ifndef DRM_RADEON_GEM_INFO
#define DRM_RADEON_GEM_INFO 0x1c
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index bd6f1c79504..88b68e3d191 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -443,6 +443,8 @@
#define PCI_CHIP_PALM_9803 0x9803
#define PCI_CHIP_PALM_9804 0x9804
#define PCI_CHIP_PALM_9805 0x9805
+#define PCI_CHIP_PALM_9806 0x9806
+#define PCI_CHIP_PALM_9807 0x9807
#define PCI_CHIP_BARTS_6720 0x6720
#define PCI_CHIP_BARTS_6721 0x6721
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 0d73c0e3b1b..bfc307ca987 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -966,7 +966,7 @@ static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state
fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size);
- if (radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
+ if (state->cmd && radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
if (dwords > state->cmd_size)
dwords = state->cmd_size;
for (i = 0; i < dwords;) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 405aecb19ec..5d7b3973d57 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "swrast_setup/swrast_setup.h"
#include "tnl/tnl.h"
-#define DRIVER_DATE "20090101"
-
#ifndef RADEON_DEBUG
int RADEON_DEBUG = (0);
#endif
@@ -146,8 +144,7 @@ static const GLubyte *radeonGetString(struct gl_context * ctx, GLenum name)
get_chip_family_name(radeon->radeonScreen->chip_family),
radeon->radeonScreen->device_id);
- offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE,
- agp_mode);
+ offset = driGetRendererString(buffer, hardwarename, agp_mode);
if (IS_R600_CLASS(radeon->radeonScreen)) {
sprintf(&buffer[offset], " TCL");
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index 154a8815e4a..4d41e99df5d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -70,8 +70,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define need_GL_OES_EGL_image
#include "main/remap_helper.h"
-#define DRIVER_DATE "20061018"
-
#include "utils.h"
#include "xmlpool.h" /* for symbolic values of enum-type options */
diff --git a/src/mesa/drivers/dri/radeon/radeon_debug.h b/src/mesa/drivers/dri/radeon/radeon_debug.h
index ef8b9671ac9..449c27a3fe1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_debug.h
+++ b/src/mesa/drivers/dri/radeon/radeon_debug.h
@@ -110,30 +110,30 @@ extern void _radeon_print(const radeon_debug_type_t type,
* Print out debug message if channel specified by type is enabled
* and compile time debugging level is at least as high as level parameter
*/
-#define radeon_print(type, level, message, ...) do { \
+#define radeon_print(type, level, ...) do { \
const radeon_debug_level_t _debug_level = (level); \
const radeon_debug_type_t _debug_type = (type); \
/* Compile out if level of message is too high */ \
if (radeon_is_debug_enabled(type, level)) { \
_radeon_print(_debug_type, _debug_level, \
- (message), ## __VA_ARGS__); \
+ __VA_ARGS__); \
} \
} while(0)
/**
* printf style function for writing error messages.
*/
-#define radeon_error(message, ...) do { \
+#define radeon_error(...) do { \
radeon_print(RADEON_GENERAL, RADEON_CRITICAL, \
- (message), ## __VA_ARGS__); \
+ __VA_ARGS__); \
} while(0)
/**
* printf style function for writing warnings.
*/
-#define radeon_warning(message, ...) do { \
+#define radeon_warning(...) do { \
radeon_print(RADEON_GENERAL, RADEON_IMPORTANT, \
- (message), ## __VA_ARGS__); \
+ __VA_ARGS__); \
} while(0)
extern void radeon_init_debug(void);
@@ -158,13 +158,13 @@ static inline void radeon_debug_remove_indent(void)
I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
with other compilers ... GLUE!
*/
-#define WARN_ONCE(a, ...) do { \
+#define WARN_ONCE(...) do { \
static int __warn_once=1; \
if(__warn_once){ \
radeon_warning("*********************************WARN_ONCE*********************************\n"); \
radeon_warning("File %s function %s line %d\n", \
__FILE__, __FUNCTION__, __LINE__); \
- radeon_warning( (a), ## __VA_ARGS__);\
+ radeon_warning(__VA_ARGS__);\
radeon_warning("***************************************************************************\n"); \
__warn_once=0;\
} \
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 1fadad2756b..03d9b264367 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -296,15 +296,15 @@ static void calculate_min_max_lod(struct gl_texture_object *tObj,
case GL_TEXTURE_2D:
case GL_TEXTURE_3D:
case GL_TEXTURE_CUBE_MAP:
- if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
+ if (tObj->Sampler.MinFilter == GL_NEAREST || tObj->Sampler.MinFilter == GL_LINEAR) {
/* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
*/
minLod = maxLod = tObj->BaseLevel;
} else {
- minLod = tObj->BaseLevel + (GLint)(tObj->MinLod);
+ minLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MinLod);
minLod = MAX2(minLod, tObj->BaseLevel);
minLod = MIN2(minLod, tObj->MaxLevel);
- maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
+ maxLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MaxLod + 0.5);
maxLod = MIN2(maxLod, tObj->MaxLevel);
maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod);
maxLod = MAX2(maxLod, minLod); /* need at least one level */
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 56c5959b0aa..732efe8bd85 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -401,12 +401,12 @@ static const struct __DRI2flushExtensionRec radeonFlushExtension = {
};
static __DRIimage *
-radeon_create_image_from_name(__DRIcontext *context,
+radeon_create_image_from_name(__DRIscreen *screen,
int width, int height, int format,
int name, int pitch, void *loaderPrivate)
{
__DRIimage *image;
- radeonContextPtr radeon = context->driverPrivate;
+ radeonScreenPtr radeonScreen = screen->private;
if (name == 0)
return NULL;
@@ -442,7 +442,7 @@ radeon_create_image_from_name(__DRIcontext *context,
image->pitch = pitch;
image->height = height;
- image->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ image->bo = radeon_bo_open(radeonScreen->bom,
(uint32_t)name,
image->pitch * image->height * image->cpp,
0,
@@ -1158,6 +1158,8 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
case PCI_CHIP_PALM_9803:
case PCI_CHIP_PALM_9804:
case PCI_CHIP_PALM_9805:
+ case PCI_CHIP_PALM_9806:
+ case PCI_CHIP_PALM_9807:
screen->chip_family = CHIP_FAMILY_PALM;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index caf3f253d2a..8c6f2e49a5c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -50,6 +50,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DBG 0
+#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && BYTE_ORDER == BIG_ENDIAN
+#if defined(__linux__)
+#include <byteswap.h>
+#define CPU_TO_LE16( x ) bswap_16( x )
+#define LE16_TO_CPU( x ) bswap_16( x )
+#endif /* __linux__ */
+#else
+#define CPU_TO_LE16( x ) ( x )
+#define LE16_TO_CPU( x ) ( x )
+#endif
+
static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
@@ -579,7 +590,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_RGB565
#define TAG2(x,y) radeon##x##_RGB565##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -591,7 +606,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_RGB565_REV
#define TAG2(x,y) radeon##x##_RGB565_REV##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -605,7 +624,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB1555
#define TAG2(x,y) radeon##x##_ARGB1555##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -617,7 +640,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB1555_REV
#define TAG2(x,y) radeon##x##_ARGB1555_REV##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -631,7 +658,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB4444
#define TAG2(x,y) radeon##x##_ARGB4444##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -643,7 +674,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB4444_REV
#define TAG2(x,y) radeon##x##_ARGB4444_REV##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -657,10 +692,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_xRGB8888
#define TAG2(x,y) radeon##x##_xRGB8888##y
#if defined(RADEON_R600)
-#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0xff000000))
+#define GET_VALUE(_x, _y) ((LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))) | 0xff000000))
#define PUT_VALUE(_x, _y, d) { \
GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
- *_ptr = d; \
+ *_ptr = CPU_TO_LE32(d); \
} while (0)
#else
#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0xff000000))
@@ -679,10 +714,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB8888
#define TAG2(x,y) radeon##x##_ARGB8888##y
#if defined(RADEON_R600)
-#define GET_VALUE(_x, _y) (*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)))
+#define GET_VALUE(_x, _y) (LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
#define PUT_VALUE(_x, _y, d) { \
GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
- *_ptr = d; \
+ *_ptr = CPU_TO_LE32(d); \
} while (0)
#else
#define GET_VALUE(_x, _y) (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)))
@@ -701,10 +736,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_BGRx8888
#define TAG2(x,y) radeon##x##_BGRx8888##y
#if defined(RADEON_R600)
-#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0x000000ff))
+#define GET_VALUE(_x, _y) ((LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))) | 0x000000ff))
#define PUT_VALUE(_x, _y, d) { \
GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
- *_ptr = d; \
+ *_ptr = CPU_TO_LE32(d); \
} while (0)
#else
#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0x000000ff))
@@ -723,7 +758,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_BGRA8888
#define TAG2(x,y) radeon##x##_BGRA8888##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE32(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_4byte(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -752,7 +791,7 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
*(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d
#elif defined(RADEON_R600)
#define WRITE_DEPTH( _x, _y, d ) \
- *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = d
+ *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = CPU_TO_LE16(d)
#else
#define WRITE_DEPTH( _x, _y, d ) \
*(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d
@@ -763,7 +802,7 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off)
#elif defined(RADEON_R600)
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off)
+ d = LE16_TO_CPU(*(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off))
#else
#define READ_DEPTH( d, _x, _y ) \
d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off)
@@ -792,10 +831,10 @@ do { \
#define WRITE_DEPTH( _x, _y, d ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
} while (0)
#elif defined(RADEON_R200)
#define WRITE_DEPTH( _x, _y, d ) \
@@ -825,7 +864,7 @@ do { \
#elif defined(RADEON_R600)
#define READ_DEPTH( d, _x, _y ) \
do { \
- d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off)) & 0x00ffffff); \
+ d = (LE32_TO_CPU(*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff); \
}while(0)
#elif defined(RADEON_R200)
#define READ_DEPTH( d, _x, _y ) \
@@ -858,15 +897,15 @@ do { \
#define WRITE_DEPTH( _x, _y, d ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
- tmp = *_ptr; \
+ tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xffffff00; \
tmp |= ((d) >> 24) & 0xff; \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
} while (0)
#elif defined(RADEON_R200)
#define WRITE_DEPTH( _x, _y, d ) \
@@ -891,8 +930,8 @@ do { \
#elif defined(RADEON_R600)
#define READ_DEPTH( d, _x, _y ) \
do { \
- d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; \
- d |= ((*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) << 24) & 0xff000000; \
+ d = (LE32_TO_CPU(*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff); \
+ d |= ((LE32_TO_CPU(*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) << 24) & 0xff000000); \
}while(0)
#elif defined(RADEON_R200)
#define READ_DEPTH( d, _x, _y ) \
@@ -927,10 +966,10 @@ do { \
#define WRITE_STENCIL( _x, _y, d ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xffffff00; \
tmp |= (d) & 0xff; \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
} while (0)
#elif defined(RADEON_R200)
#define WRITE_STENCIL( _x, _y, d ) \
@@ -963,7 +1002,7 @@ do { \
#define READ_STENCIL( d, _x, _y ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_stencil( rrb, _x + x_off, _y + y_off ); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
d = tmp & 0x000000ff; \
} while (0)
#elif defined(RADEON_R200)
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c
index 8a35c7d2d27..25a8ddf7b6a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.c
@@ -330,17 +330,17 @@ static void radeonTexParameter( struct gl_context *ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
+ radeonSetTexMaxAnisotropy( t, texObj->Sampler.MaxAnisotropy );
+ radeonSetTexFilter( t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter );
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
- radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
+ radeonSetTexWrap( t, texObj->Sampler.WrapS, texObj->Sampler.WrapT );
break;
case GL_TEXTURE_BORDER_COLOR:
- radeonSetTexBorderColor( t, texObj->BorderColor.f );
+ radeonSetTexBorderColor( t, texObj->Sampler.BorderColor.f );
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -416,7 +416,7 @@ radeonNewTextureObject( struct gl_context *ctx, GLuint name, GLenum target )
radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
_mesa_initialize_texture_object(&t->base, name, target);
- t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
+ t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
t->border_fallback = GL_FALSE;
@@ -424,10 +424,10 @@ radeonNewTextureObject( struct gl_context *ctx, GLuint name, GLenum target )
t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
RADEON_TXFORMAT_PERSPECTIVE_ENABLE);
- radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT );
- radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy );
- radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter );
- radeonSetTexBorderColor( t, t->base.BorderColor.f );
+ radeonSetTexWrap( t, t->base.Sampler.WrapS, t->base.Sampler.WrapT );
+ radeonSetTexMaxAnisotropy( t, t->base.Sampler.MaxAnisotropy );
+ radeonSetTexFilter( t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter );
+ radeonSetTexBorderColor( t, t->base.Sampler.BorderColor.f );
return &t->base;
}
diff --git a/src/mesa/drivers/dri/savage/savagedd.c b/src/mesa/drivers/dri/savage/savagedd.c
index 3f8d7aafb08..c7f58835054 100644
--- a/src/mesa/drivers/dri/savage/savagedd.c
+++ b/src/mesa/drivers/dri/savage/savagedd.c
@@ -38,8 +38,6 @@
#include "utils.h"
-#define DRIVER_DATE "20061110"
-
/***************************************
* Mesa's Driver Functions
***************************************/
@@ -71,7 +69,7 @@ static const GLubyte *savageDDGetString( struct gl_context *ctx, GLenum name )
case GL_VENDOR:
return (GLubyte *)"S3 Graphics Inc.";
case GL_RENDERER:
- offset = driGetRendererString( buffer, cardNames[chipset], DRIVER_DATE,
+ offset = driGetRendererString( buffer, cardNames[chipset],
screen->agpMode );
return (GLubyte *)buffer;
default:
diff --git a/src/mesa/drivers/dri/savage/savagerender.c b/src/mesa/drivers/dri/savage/savagerender.c
index 8cc448ad4f7..6687dc5f466 100644
--- a/src/mesa/drivers/dri/savage/savagerender.c
+++ b/src/mesa/drivers/dri/savage/savagerender.c
@@ -250,9 +250,9 @@ static GLboolean run_texnorm_stage( struct gl_context *ctx,
const GLbitfield reallyEnabled = ctx->Texture.Unit[i]._ReallyEnabled;
if (reallyEnabled) {
const struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
- const GLboolean normalizeS = (texObj->WrapS == GL_REPEAT);
+ const GLboolean normalizeS = (texObj->Sampler.WrapS == GL_REPEAT);
const GLboolean normalizeT = (reallyEnabled & TEXTURE_2D_BIT) &&
- (texObj->WrapT == GL_REPEAT);
+ (texObj->Sampler.WrapT == GL_REPEAT);
const GLfloat *in = (GLfloat *)VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->data;
const GLint instride = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->stride;
GLfloat (*out)[4] = store->texcoord[i].data;
@@ -332,15 +332,15 @@ static void validate_texnorm( struct gl_context *ctx,
GLuint flags = 0;
if (((ctx->Texture.Unit[0]._ReallyEnabled & (TEXTURE_1D_BIT|TEXTURE_2D_BIT)) &&
- (ctx->Texture.Unit[0]._Current->WrapS == GL_REPEAT)) ||
+ (ctx->Texture.Unit[0]._Current->Sampler.WrapS == GL_REPEAT)) ||
((ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_2D_BIT) &&
- (ctx->Texture.Unit[0]._Current->WrapT == GL_REPEAT)))
+ (ctx->Texture.Unit[0]._Current->Sampler.WrapT == GL_REPEAT)))
flags |= VERT_BIT_TEX0;
if (((ctx->Texture.Unit[1]._ReallyEnabled & (TEXTURE_1D_BIT|TEXTURE_2D_BIT)) &&
- (ctx->Texture.Unit[1]._Current->WrapS == GL_REPEAT)) ||
+ (ctx->Texture.Unit[1]._Current->Sampler.WrapS == GL_REPEAT)) ||
((ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_2D_BIT) &&
- (ctx->Texture.Unit[1]._Current->WrapT == GL_REPEAT)))
+ (ctx->Texture.Unit[1]._Current->Sampler.WrapT == GL_REPEAT)))
flags |= VERT_BIT_TEX1;
store->active = (flags != 0);
diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c
index 3aece732c99..9486c12c158 100644
--- a/src/mesa/drivers/dri/savage/savagetex.c
+++ b/src/mesa/drivers/dri/savage/savagetex.c
@@ -502,9 +502,9 @@ savageAllocTexObj( struct gl_texture_object *texObj )
make_empty_list( &t->base );
- savageSetTexWrapping(t,texObj->WrapS,texObj->WrapT);
- savageSetTexFilter(t,texObj->MinFilter,texObj->MagFilter);
- savageSetTexBorderColor(t,texObj->BorderColor.f);
+ savageSetTexWrapping(t,texObj->Sampler.WrapS,texObj->Sampler.WrapT);
+ savageSetTexFilter(t,texObj->Sampler.MinFilter,texObj->Sampler.MagFilter);
+ savageSetTexBorderColor(t,texObj->Sampler.BorderColor.f);
}
return t;
@@ -2031,16 +2031,16 @@ static void savageTexParameter( struct gl_context *ctx, GLenum target,
switch (pname) {
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
- savageSetTexFilter(t,tObj->MinFilter,tObj->MagFilter);
+ savageSetTexFilter(t,tObj->Sampler.MinFilter,tObj->Sampler.MagFilter);
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
- savageSetTexWrapping(t,tObj->WrapS,tObj->WrapT);
+ savageSetTexWrapping(t,tObj->Sampler.WrapS,tObj->Sampler.WrapT);
break;
case GL_TEXTURE_BORDER_COLOR:
- savageSetTexBorderColor(t,tObj->BorderColor.f);
+ savageSetTexBorderColor(t,tObj->Sampler.BorderColor.f);
break;
default:
diff --git a/src/mesa/drivers/dri/sis/sis_dd.c b/src/mesa/drivers/dri/sis/sis_dd.c
index 90e894b842c..bba516f8dcd 100644
--- a/src/mesa/drivers/dri/sis/sis_dd.c
+++ b/src/mesa/drivers/dri/sis/sis_dd.c
@@ -45,8 +45,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "utils.h"
-#define DRIVER_DATE "20060710"
-
/* Return the width and height of the given buffer.
*/
static void
@@ -78,7 +76,7 @@ sisGetString( struct gl_context *ctx, GLenum name )
return (GLubyte *)"Eric Anholt";
case GL_RENDERER:
- offset = driGetRendererString( buffer, "SiS", DRIVER_DATE, agp_mode );
+ offset = driGetRendererString( buffer, "SiS", agp_mode );
return (GLubyte *)buffer;
diff --git a/src/mesa/drivers/dri/sis/sis_texstate.c b/src/mesa/drivers/dri/sis/sis_texstate.c
index daec2393211..6580f155bae 100644
--- a/src/mesa/drivers/dri/sis/sis_texstate.c
+++ b/src/mesa/drivers/dri/sis/sis_texstate.c
@@ -335,7 +335,7 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
current->texture[hw_unit].hwTextureMip = 0UL;
current->texture[hw_unit].hwTextureSet = t->hwformat;
- if ((texObj->MinFilter == GL_NEAREST) || (texObj->MinFilter == GL_LINEAR)) {
+ if ((texObj->Sampler.MinFilter == GL_NEAREST) || (texObj->Sampler.MinFilter == GL_LINEAR)) {
firstLevel = lastLevel = texObj->BaseLevel;
} else {
/* Compute which mipmap levels we really want to send to the hardware.
@@ -344,9 +344,9 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
* Yes, this looks overly complicated, but it's all needed.
*/
- firstLevel = texObj->BaseLevel + (GLint)(texObj->MinLod + 0.5);
+ firstLevel = texObj->BaseLevel + (GLint)(texObj->Sampler.MinLod + 0.5);
firstLevel = MAX2(firstLevel, texObj->BaseLevel);
- lastLevel = texObj->BaseLevel + (GLint)(texObj->MaxLod + 0.5);
+ lastLevel = texObj->BaseLevel + (GLint)(texObj->Sampler.MaxLod + 0.5);
lastLevel = MAX2(lastLevel, texObj->BaseLevel);
lastLevel = MIN2(lastLevel, texObj->BaseLevel +
texObj->Image[0][texObj->BaseLevel]->MaxLog2);
@@ -356,7 +356,7 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
current->texture[hw_unit].hwTextureSet |= (lastLevel << 8);
- switch (texObj->MagFilter)
+ switch (texObj->Sampler.MagFilter)
{
case GL_NEAREST:
current->texture[hw_unit].hwTextureMip |= TEXTURE_FILTER_NEAREST;
@@ -382,7 +382,7 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
MASK_TextureMipmapLodBias);
}
- switch (texObj->MinFilter)
+ switch (texObj->Sampler.MinFilter)
{
case GL_NEAREST:
current->texture[hw_unit].hwTextureMip |= TEXTURE_FILTER_NEAREST;
@@ -408,7 +408,7 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
break;
}
- switch (texObj->WrapS)
+ switch (texObj->Sampler.WrapS)
{
case GL_REPEAT:
current->texture[hw_unit].hwTextureSet |= MASK_TextureWrapU;
@@ -431,7 +431,7 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
break;
}
- switch (texObj->WrapT)
+ switch (texObj->Sampler.WrapT)
{
case GL_REPEAT:
current->texture[hw_unit].hwTextureSet |= MASK_TextureWrapV;
@@ -456,10 +456,10 @@ sis_set_texobj_parm( struct gl_context *ctx, struct gl_texture_object *texObj,
{
GLubyte c[4];
- CLAMPED_FLOAT_TO_UBYTE(c[0], texObj->BorderColor.f[0]);
- CLAMPED_FLOAT_TO_UBYTE(c[1], texObj->BorderColor.f[1]);
- CLAMPED_FLOAT_TO_UBYTE(c[2], texObj->BorderColor.f[2]);
- CLAMPED_FLOAT_TO_UBYTE(c[3], texObj->BorderColor.f[3]);
+ CLAMPED_FLOAT_TO_UBYTE(c[0], texObj->Sampler.BorderColor.f[0]);
+ CLAMPED_FLOAT_TO_UBYTE(c[1], texObj->Sampler.BorderColor.f[1]);
+ CLAMPED_FLOAT_TO_UBYTE(c[2], texObj->Sampler.BorderColor.f[2]);
+ CLAMPED_FLOAT_TO_UBYTE(c[3], texObj->Sampler.BorderColor.f[3]);
current->texture[hw_unit].hwTextureBorderColor =
PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
diff --git a/src/mesa/drivers/dri/tdfx/tdfx_dd.c b/src/mesa/drivers/dri/tdfx/tdfx_dd.c
index d60931ad7fd..e981f9abedf 100644
--- a/src/mesa/drivers/dri/tdfx/tdfx_dd.c
+++ b/src/mesa/drivers/dri/tdfx/tdfx_dd.c
@@ -41,9 +41,6 @@
#include "main/context.h"
-#define DRIVER_DATE "20061113"
-
-
/* These are used in calls to FX_grColorMaskv() */
const GLboolean false4[4] = { GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE };
const GLboolean true4[4] = { GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE };
@@ -91,7 +88,7 @@ static const GLubyte *tdfxDDGetString( struct gl_context *ctx, GLenum name )
}
}
- (void) driGetRendererString(buffer, hardware, DRIVER_DATE, 0);
+ (void) driGetRendererString(buffer, hardware, 0);
return (const GLubyte *) buffer;
}
case GL_VENDOR:
diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c
index 4cca243d076..d74ddb24005 100644
--- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c
+++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c
@@ -327,7 +327,7 @@ static void RevalidateTexture(struct gl_context *ctx, struct gl_texture_object *
&(ti->sScale), &(ti->tScale), NULL, NULL);
}
- if (tObj->Image[0][maxl] && (tObj->MinFilter != GL_NEAREST) && (tObj->MinFilter != GL_LINEAR)) {
+ if (tObj->Image[0][maxl] && (tObj->Sampler.MinFilter != GL_NEAREST) && (tObj->Sampler.MinFilter != GL_LINEAR)) {
/* mipmapping: need to compute smallLodLog2 */
tdfxTexGetInfo(ctx, tObj->Image[0][maxl]->Width,
tObj->Image[0][maxl]->Height,
@@ -1786,12 +1786,12 @@ tdfxTestProxyTexImage(struct gl_context *ctx, GLenum target,
#endif
if (level == 0) {
/* don't use mipmap levels > 0 */
- tObj->MinFilter = tObj->MagFilter = GL_NEAREST;
+ tObj->Sampler.MinFilter = tObj->Sampler.MagFilter = GL_NEAREST;
}
else {
/* test with all mipmap levels */
- tObj->MinFilter = GL_LINEAR_MIPMAP_LINEAR;
- tObj->MagFilter = GL_NEAREST;
+ tObj->Sampler.MinFilter = GL_LINEAR_MIPMAP_LINEAR;
+ tObj->Sampler.MagFilter = GL_NEAREST;
}
RevalidateTexture(ctx, tObj);
diff --git a/src/mesa/drivers/dri/unichrome/via_context.c b/src/mesa/drivers/dri/unichrome/via_context.c
index 77d7116611a..89c2a12a9c2 100644
--- a/src/mesa/drivers/dri/unichrome/via_context.c
+++ b/src/mesa/drivers/dri/unichrome/via_context.c
@@ -65,8 +65,6 @@
#define need_GL_EXT_secondary_color
#include "main/remap_helper.h"
-#define DRIVER_DATE "20060710"
-
#include "vblank.h"
#include "utils.h"
@@ -100,7 +98,7 @@ static const GLubyte *viaGetString(struct gl_context *ctx, GLenum name)
offset = driGetRendererString( buffer,
chipset_names[(id > VIA_PM800) ? 0 : id],
- DRIVER_DATE, 0 );
+ 0 );
return (GLubyte *)buffer;
}
diff --git a/src/mesa/drivers/dri/unichrome/via_state.c b/src/mesa/drivers/dri/unichrome/via_state.c
index 774f439bfb6..3b270e02a97 100644
--- a/src/mesa/drivers/dri/unichrome/via_state.c
+++ b/src/mesa/drivers/dri/unichrome/via_state.c
@@ -877,21 +877,21 @@ static GLboolean viaChooseTextureState(struct gl_context *ctx)
if (texUnit0->_ReallyEnabled) {
struct gl_texture_object *texObj = texUnit0->_Current;
- vmesa->regHTXnTB[0] = get_minmag_filter( texObj->MinFilter,
- texObj->MagFilter );
+ vmesa->regHTXnTB[0] = get_minmag_filter( texObj->Sampler.MinFilter,
+ texObj->Sampler.MagFilter );
vmesa->regHTXnMPMD[0] &= ~(HC_HTXnMPMD_SMASK | HC_HTXnMPMD_TMASK);
- vmesa->regHTXnMPMD[0] |= get_wrap_mode( texObj->WrapS,
- texObj->WrapT );
+ vmesa->regHTXnMPMD[0] |= get_wrap_mode( texObj->Sampler.WrapS,
+ texObj->Sampler.WrapT );
vmesa->regHTXnTB[0] &= ~(HC_HTXnTB_TBC_S | HC_HTXnTB_TBC_T);
if (texObj->Image[0][texObj->BaseLevel]->Border > 0) {
vmesa->regHTXnTB[0] |= (HC_HTXnTB_TBC_S | HC_HTXnTB_TBC_T);
vmesa->regHTXnTBC[0] =
- PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->BorderColor.f[0]),
- FLOAT_TO_UBYTE(texObj->BorderColor.f[1]),
- FLOAT_TO_UBYTE(texObj->BorderColor.f[2]));
- vmesa->regHTXnTRAH[0] = FLOAT_TO_UBYTE(texObj->BorderColor.f[3]);
+ PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[0]),
+ FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[1]),
+ FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[2]));
+ vmesa->regHTXnTRAH[0] = FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[3]);
}
if (texUnit0->LodBias != 0.0f) {
@@ -911,20 +911,20 @@ static GLboolean viaChooseTextureState(struct gl_context *ctx)
if (texUnit1->_ReallyEnabled) {
struct gl_texture_object *texObj = texUnit1->_Current;
- vmesa->regHTXnTB[1] = get_minmag_filter( texObj->MinFilter,
- texObj->MagFilter );
+ vmesa->regHTXnTB[1] = get_minmag_filter( texObj->Sampler.MinFilter,
+ texObj->Sampler.MagFilter );
vmesa->regHTXnMPMD[1] &= ~(HC_HTXnMPMD_SMASK | HC_HTXnMPMD_TMASK);
- vmesa->regHTXnMPMD[1] |= get_wrap_mode( texObj->WrapS,
- texObj->WrapT );
+ vmesa->regHTXnMPMD[1] |= get_wrap_mode( texObj->Sampler.WrapS,
+ texObj->Sampler.WrapT );
vmesa->regHTXnTB[1] &= ~(HC_HTXnTB_TBC_S | HC_HTXnTB_TBC_T);
if (texObj->Image[0][texObj->BaseLevel]->Border > 0) {
vmesa->regHTXnTB[1] |= (HC_HTXnTB_TBC_S | HC_HTXnTB_TBC_T);
vmesa->regHTXnTBC[1] =
- PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->BorderColor.f[0]),
- FLOAT_TO_UBYTE(texObj->BorderColor.f[1]),
- FLOAT_TO_UBYTE(texObj->BorderColor.f[2]));
- vmesa->regHTXnTRAH[1] = FLOAT_TO_UBYTE(texObj->BorderColor.f[3]);
+ PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[0]),
+ FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[1]),
+ FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[2]));
+ vmesa->regHTXnTRAH[1] = FLOAT_TO_UBYTE(texObj->Sampler.BorderColor.f[3]);
}
diff --git a/src/mesa/drivers/dri/unichrome/via_tex.c b/src/mesa/drivers/dri/unichrome/via_tex.c
index a2fb010e142..1a0d1eaf070 100644
--- a/src/mesa/drivers/dri/unichrome/via_tex.c
+++ b/src/mesa/drivers/dri/unichrome/via_tex.c
@@ -495,13 +495,13 @@ static GLboolean viaSetTexImages(struct gl_context *ctx,
* GL_TEXTURE_MAX_LOD, GL_TEXTURE_BASE_LEVEL, and GL_TEXTURE_MAX_LEVEL.
* Yes, this looks overly complicated, but it's all needed.
*/
- if (texObj->MinFilter == GL_LINEAR || texObj->MinFilter == GL_NEAREST) {
+ if (texObj->Sampler.MinFilter == GL_LINEAR || texObj->Sampler.MinFilter == GL_NEAREST) {
firstLevel = lastLevel = texObj->BaseLevel;
}
else {
- firstLevel = texObj->BaseLevel + (GLint)(texObj->MinLod + 0.5);
+ firstLevel = texObj->BaseLevel + (GLint)(texObj->Sampler.MinLod + 0.5);
firstLevel = MAX2(firstLevel, texObj->BaseLevel);
- lastLevel = texObj->BaseLevel + (GLint)(texObj->MaxLod + 0.5);
+ lastLevel = texObj->BaseLevel + (GLint)(texObj->Sampler.MaxLod + 0.5);
lastLevel = MAX2(lastLevel, texObj->BaseLevel);
lastLevel = MIN2(lastLevel, texObj->BaseLevel + baseImage->image.MaxLog2);
lastLevel = MIN2(lastLevel, texObj->MaxLevel);
diff --git a/src/mesa/drivers/osmesa/SConscript b/src/mesa/drivers/osmesa/SConscript
new file mode 100644
index 00000000000..5ccef5f130c
--- /dev/null
+++ b/src/mesa/drivers/osmesa/SConscript
@@ -0,0 +1,36 @@
+Import('*')
+
+env = env.Clone()
+
+env.Prepend(CPPPATH = [
+ '#src/mapi',
+ '#src/mesa',
+])
+
+env.Prepend(LIBS = [
+ glapi,
+ mesa,
+ glsl,
+])
+
+sources = [
+ 'osmesa.c',
+]
+
+if env['platform'] == 'windows':
+ env.AppendUnique(CPPDEFINES = [
+ '_GDI32_', # prevent wgl* being declared __declspec(dllimport)
+ 'BUILD_GL32', # declare gl* as __declspec(dllexport) in Mesa headers
+ ])
+ if not env['gles']:
+ # prevent _glapi_* from being declared __declspec(dllimport)
+ env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
+
+ sources += ['osmesa.def']
+
+osmesa = env.SharedLibrary(
+ target ='osmesa',
+ source = sources,
+)
+
+env.Alias('osmesa', osmesa)
diff --git a/src/mesa/drivers/osmesa/osmesa.c b/src/mesa/drivers/osmesa/osmesa.c
index 98f01fe057e..68d71144642 100644
--- a/src/mesa/drivers/osmesa/osmesa.c
+++ b/src/mesa/drivers/osmesa/osmesa.c
@@ -515,11 +515,7 @@ do { \
PACK_RGBA(p, color[0], color[1], color[2], color[3]); \
} while (0)
-#ifdef WIN32
-#include "..\swrast\s_linetemp.h"
-#else
#include "swrast/s_linetemp.h"
-#endif
@@ -544,11 +540,7 @@ do { \
} \
} while (0)
-#ifdef WIN32
-#include "..\swrast\s_linetemp.h"
-#else
#include "swrast/s_linetemp.h"
-#endif
@@ -624,11 +616,7 @@ osmesa_choose_line_function( struct gl_context *ctx )
span.z += span.zStep; \
} \
}
-#ifdef WIN32
-#include "..\swrast\s_tritemp.h"
-#else
#include "swrast/s_tritemp.h"
-#endif
@@ -656,11 +644,8 @@ osmesa_choose_line_function( struct gl_context *ctx )
span.z += span.zStep; \
} \
}
-#ifdef WIN32
-#include "..\swrast\s_tritemp.h"
-#else
+
#include "swrast/s_tritemp.h"
-#endif
diff --git a/src/mesa/drivers/windows/gdi/SConscript b/src/mesa/drivers/windows/gdi/SConscript
new file mode 100644
index 00000000000..10a7eeaa19f
--- /dev/null
+++ b/src/mesa/drivers/windows/gdi/SConscript
@@ -0,0 +1,38 @@
+Import('*')
+
+env = env.Clone()
+
+env.Prepend(CPPPATH = [
+ '#src/mapi',
+ '#src/mesa',
+])
+
+env.AppendUnique(CPPDEFINES = [
+ '_GDI32_', # prevent wgl* being declared __declspec(dllimport)
+ 'BUILD_GL32', # declare gl* as __declspec(dllexport) in Mesa headers
+])
+if not env['gles']:
+ # prevent _glapi_* from being declared __declspec(dllimport)
+ env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
+
+env.Prepend(LIBS = [
+ glapi,
+ mesa,
+ glsl,
+ 'gdi32',
+ 'user32',
+ 'kernel32',
+])
+
+sources = [
+ 'mesa.def',
+ 'wgl.c',
+ 'wmesa.c',
+]
+
+mesagdi = env.SharedLibrary(
+ target = 'opengl32',
+ source = sources,
+)
+
+env.Alias('mesagdi', mesagdi)
diff --git a/src/mesa/drivers/windows/gdi/mesa.def b/src/mesa/drivers/windows/gdi/mesa.def
index b537b3460c5..d5c98801d32 100644
--- a/src/mesa/drivers/windows/gdi/mesa.def
+++ b/src/mesa/drivers/windows/gdi/mesa.def
@@ -26,9 +26,6 @@ VERSION 6.5
; be needed (for the gl* functions) since the entry
; points are compiled with dllexport declspec.
;
-; However, this file is still needed to export "internal"
-; Mesa symbols for the benefit of the OSMESA32.DLL.
-;
EXPORTS
glNewList
glEndList
@@ -857,107 +854,3 @@ EXPORTS
wglUseFontOutlinesA
wglUseFontOutlinesW
wglGetExtensionsStringARB
-;
-; Mesa internals - mostly for OSMESA
- _vbo_CreateContext
- _vbo_DestroyContext
- _vbo_InvalidateState
- _glapi_check_multithread
- _glapi_get_context
- _glapi_get_proc_address
- _mesa_add_soft_renderbuffers
- _mesa_add_renderbuffer
- _mesa_check_conditional_render
- _mesa_choose_tex_format
- _mesa_create_framebuffer
- _mesa_create_visual
- _mesa_delete_array_object
- _mesa_delete_program
- _mesa_delete_texture_object
- _mesa_destroy_framebuffer
- _mesa_destroy_visual
- _mesa_enable_1_3_extensions
- _mesa_enable_1_4_extensions
- _mesa_enable_1_5_extensions
- _mesa_enable_2_0_extensions
- _mesa_enable_2_1_extensions
- _mesa_enable_sw_extensions
- _mesa_error
- _mesa_finish_render_texture
- _mesa_framebuffer_renderbuffer
- _mesa_free_context_data
- _mesa_free_texture_image_data
- _mesa_generate_mipmap
- _mesa_get_compressed_teximage
- _mesa_get_current_context
- _mesa_get_teximage
- _mesa_init_driver_functions
- _mesa_init_glsl_driver_functions
- _mesa_init_renderbuffer
- _mesa_initialize_context
- _mesa_make_current
- _mesa_new_array_object
- _mesa_new_framebuffer
- _mesa_new_program
- _mesa_new_renderbuffer
- _mesa_new_soft_renderbuffer
- _mesa_new_texture_image
- _mesa_new_texture_object
- _mesa_problem
- _mesa_reference_renderbuffer
- _mesa_remove_renderbuffer
- _mesa_render_texture
- _mesa_ResizeBuffersMESA
- _mesa_resize_framebuffer
- _mesa_store_compressed_teximage1d
- _mesa_store_compressed_teximage2d
- _mesa_store_compressed_teximage3d
- _mesa_store_compressed_texsubimage1d
- _mesa_store_compressed_texsubimage2d
- _mesa_store_compressed_texsubimage3d
- _mesa_store_teximage1d
- _mesa_store_teximage2d
- _mesa_store_teximage3d
- _mesa_store_texsubimage1d
- _mesa_store_texsubimage2d
- _mesa_store_texsubimage3d
- _mesa_test_proxy_teximage
- _mesa_reference_framebuffer
- _mesa_update_framebuffer_visual
- _mesa_use_program
- _mesa_Viewport
- _mesa_meta_init
- _mesa_meta_free
- _mesa_meta_CopyColorSubTable
- _mesa_meta_CopyColorTable
- _mesa_meta_CopyConvolutionFilter1D
- _mesa_meta_CopyConvolutionFilter2D
- _mesa_meta_CopyTexImage1D
- _mesa_meta_CopyTexImage2D
- _mesa_meta_CopyTexSubImage1D
- _mesa_meta_CopyTexSubImage2D
- _mesa_meta_CopyTexSubImage3D
- _swrast_Accum
- _swrast_Bitmap
- _swrast_BlitFramebuffer
- _swrast_CopyPixels
- _swrast_DrawPixels
- _swrast_GetDeviceDriverReference
- _swrast_Clear
- _swrast_choose_line
- _swrast_choose_triangle
- _swrast_CreateContext
- _swrast_DestroyContext
- _swrast_exec_fragment_program
- _swrast_InvalidateState
- _swrast_ReadPixels
- _swsetup_Wakeup
- _swsetup_CreateContext
- _swsetup_DestroyContext
- _swsetup_InvalidateState
- _tnl_CreateContext
- _tnl_DestroyContext
- _tnl_InvalidateState
- _tnl_run_pipeline
- _tnl_program_string
- _tnl_RasterPos
diff --git a/src/mesa/drivers/windows/gdi/wgl.c b/src/mesa/drivers/windows/gdi/wgl.c
index 8d8087067f5..1dafe6e2952 100644
--- a/src/mesa/drivers/windows/gdi/wgl.c
+++ b/src/mesa/drivers/windows/gdi/wgl.c
@@ -54,8 +54,8 @@
#include <windows.h>
#endif
-#include "config.h"
-#include "glapi.h"
+#include "main/config.h"
+#include "glapi/glapi.h"
#include "GL/wmesa.h" /* protos for wmesa* functions */
/*
diff --git a/src/mesa/drivers/windows/gdi/wmesa.c b/src/mesa/drivers/windows/gdi/wmesa.c
index 4a8b1b283d5..e3a37eb1ace 100644
--- a/src/mesa/drivers/windows/gdi/wmesa.c
+++ b/src/mesa/drivers/windows/gdi/wmesa.c
@@ -7,10 +7,11 @@
#include "colors.h"
#include <GL/wmesa.h>
#include <winuser.h>
-#include "context.h"
-#include "extensions.h"
-#include "framebuffer.h"
-#include "renderbuffer.h"
+#include "main/context.h"
+#include "main/extensions.h"
+#include "main/framebuffer.h"
+#include "main/renderbuffer.h"
+#include "main/macros.h"
#include "drivers/common/driverfuncs.h"
#include "drivers/common/meta.h"
#include "vbo/vbo.h"
@@ -185,7 +186,7 @@ BOOL wmCreateBackingStore(WMesaFramebuffer pwfb, long lxSize, long lySize)
}
-static wmDeleteBackingStore(WMesaFramebuffer pwfb)
+static void wmDeleteBackingStore(WMesaFramebuffer pwfb)
{
if (pwfb->hbmDIB) {
SelectObject(pwfb->dib_hDC, pwfb->hOldBitmap);
diff --git a/src/mesa/drivers/windows/gdi/wmesadef.h b/src/mesa/drivers/windows/gdi/wmesadef.h
index a73609b007a..32289ebc700 100644
--- a/src/mesa/drivers/windows/gdi/wmesadef.h
+++ b/src/mesa/drivers/windows/gdi/wmesadef.h
@@ -3,7 +3,7 @@
#ifdef __MINGW32__
#include <windows.h>
#endif
-#include "context.h"
+#include "main/context.h"
/**