diff options
author | Ben Widawsky <[email protected]> | 2016-10-21 16:47:23 +0100 |
---|---|---|
committer | Lionel Landwerlin <[email protected]> | 2016-11-08 16:13:57 +0000 |
commit | 3b0c2bc41755db2f2cef487f367e697aa57dcd78 (patch) | |
tree | 0522e16a0c023c8c528dab27d51f14382ebb6268 /src/mesa/drivers | |
parent | c0f505c7ef179249673e764de51b969e07fc8194 (diff) |
i965/gen9: Add HiZ auxiliary buffer support
The original functionality this patch introduces was authored by a patch from
Ken (the commit subject was the same). Since I ended up changing so many patches
in the code before this one, I had some non-trivial decisions to make, and I
didn't feel it was appropriate to keeps Ken's name as author (mostly because he
might not like what I've done). Ken's original patch was like 2 LOC :-)
In either case, some credit needs to go to Ken, and to Jordan for a few small
other changes in that original patch.
v2: Back to a smaller diff now that ISL handles most of the actual
programming (Lionel)
Signed-off-by: Ben Widawsky <[email protected]> (v1)
Signed-off-by: Lionel Landwerlin <[email protected]> (v2)
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index bff423e19dc..4c2d11da44b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -140,17 +140,26 @@ brw_emit_surface_state(struct brw_context *brw, union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } }; + drm_intel_bo *aux_bo; struct isl_surf *aux_surf = NULL, aux_surf_s; uint64_t aux_offset = 0; enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE; - if (mt->mcs_buf && !(flags & INTEL_AUX_BUFFER_DISABLED)) { + if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) && + !(flags & INTEL_AUX_BUFFER_DISABLED)) { intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage); aux_surf = &aux_surf_s; - assert(mt->mcs_buf->offset == 0); - aux_offset = mt->mcs_buf->bo->offset64; + + if (mt->mcs_buf) { + assert(mt->mcs_buf->offset == 0); + aux_bo = mt->mcs_buf->bo; + aux_offset = mt->mcs_buf->bo->offset64; + } else { + aux_bo = mt->hiz_buf->aux_base.bo; + aux_offset = mt->hiz_buf->aux_base.bo->offset64; + } /* We only really need a clear color if we also have an auxiliary - * surfacae. Without one, it does nothing. + * surface. Without one, it does nothing. */ clear_color = intel_miptree_get_isl_clear_color(brw, mt); } @@ -181,8 +190,7 @@ brw_emit_surface_state(struct brw_context *brw, assert((aux_offset & 0xfff) == 0); drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 4 * ss_info.aux_reloc_dw, - mt->mcs_buf->bo, - dw[ss_info.aux_reloc_dw] & 0xfff, + aux_bo, dw[ss_info.aux_reloc_dw] & 0xfff, read_domains, write_domains); } } |