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authorChris Forbes <[email protected]>2013-10-27 12:09:51 +1300
committerChris Forbes <[email protected]>2013-11-06 19:29:36 +1300
commitdbcd633040939565f91eedac6ea313503ac9f0a5 (patch)
tree872a338bf8df917f2dd418273bc04b4152683f52 /src/mesa/drivers
parent39ebb72e52779b2975bfea3f08b91b7409f4a95c (diff)
i965: Gen4-5: Don't enable hardware alpha test with MRT
We have to do this in the shader instead, since these gens lack an independent RT0 alpha value in their render target write messages. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_cc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 6f85f6355cb..53466e714ec 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -187,7 +187,8 @@ static void upload_cc_unit(struct brw_context *brw)
eqA != eqRGB);
}
- if (ctx->Color.AlphaEnabled) {
+ /* _NEW_BUFFERS */
+ if (ctx->Color.AlphaEnabled && ctx->DrawBuffer->_NumColorDrawBuffers <= 1) {
cc->cc3.alpha_test = 1;
cc->cc3.alpha_test_func =
intel_translate_compare_func(ctx->Color.AlphaFunc);