diff options
| author | Lionel Landwerlin <[email protected]> | 2017-08-30 08:44:37 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2017-08-30 17:59:17 +0100 |
| commit | b83a97a65d16cd28c0763545ee3f78832939237c (patch) | |
| tree | ad02aab9670162a0a735a742a223efbafacb9a93 /src/mesa/drivers | |
| parent | de9649071a7ded45b75bd935b0f59ca13d8e642c (diff) | |
i965: drop brw->gen in favor of devinfo->gen
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
47 files changed, 506 insertions, 311 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c index d1cbf0db3bd..4bbaa5d0594 100644 --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c @@ -56,9 +56,11 @@ brw_upload_binding_table(struct brw_context *brw, const struct brw_stage_prog_data *prog_data, struct brw_stage_state *stage_state) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (prog_data->binding_table.size_bytes == 0) { /* There are no surfaces; skip making the binding table altogether. */ - if (stage_state->bind_bo_offset == 0 && brw->gen < 9) + if (stage_state->bind_bo_offset == 0 && devinfo->gen < 9) return; stage_state->bind_bo_offset = 0; @@ -82,7 +84,7 @@ brw_upload_binding_table(struct brw_context *brw, brw->ctx.NewDriverState |= BRW_NEW_BINDING_TABLE_POINTERS; - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { BEGIN_BATCH(2); OUT_BATCH(packet_name << 16 | (2 - 2)); /* Align SurfaceStateOffset[16:6] format to [15:5] PS Binding Table field diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 3ea396d726e..6ac5b6070b3 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -66,11 +66,13 @@ brw_blorp_upload_shader(struct blorp_context *blorp, void brw_blorp_init(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + blorp_init(&brw->blorp, brw, &brw->isl_dev); brw->blorp.compiler = brw->screen->compiler; - switch (brw->gen) { + switch (devinfo->gen) { case 4: if (brw->is_g4x) { brw->blorp.exec = gen45_blorp_exec; @@ -91,7 +93,7 @@ brw_blorp_init(struct brw_context *brw) brw->blorp.mocs.tex = GEN7_MOCS_L3; brw->blorp.mocs.rb = GEN7_MOCS_L3; brw->blorp.mocs.vb = GEN7_MOCS_L3; - if (brw->is_haswell) { + if (devinfo->is_haswell) { brw->blorp.exec = gen75_blorp_exec; } else { brw->blorp.exec = gen7_blorp_exec; @@ -269,6 +271,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw, GLenum filter, bool mirror_x, bool mirror_y, bool decode_srgb, bool encode_srgb) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)" "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n", __func__, @@ -293,7 +297,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw, * shouldn't affect rendering correctness, since the destination format is * R32_FLOAT, so only the contents of the red channel matters. */ - if (brw->gen == 6 && + if (devinfo->gen == 6 && src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 && src_mt->format == dst_mt->format && (dst_format == MESA_FORMAT_L_FLOAT32 || @@ -360,6 +364,8 @@ brw_blorp_copy_miptrees(struct brw_context *brw, unsigned dst_x, unsigned dst_y, unsigned src_width, unsigned src_height) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d" "to %dx %s mt %p %d %d (%d,%d)\n", __func__, @@ -380,7 +386,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw, * with a different number of components, we can't handle clear colors * until gen9. */ - src_clear_supported = brw->gen >= 9; + src_clear_supported = devinfo->gen >= 9; break; default: src_aux_usage = ISL_AUX_USAGE_NONE; @@ -397,7 +403,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw, * with a different number of components, we can't handle clear colors * until gen9. */ - dst_clear_supported = brw->gen >= 9; + dst_clear_supported = devinfo->gen >= 9; break; default: dst_aux_usage = ISL_AUX_USAGE_NONE; @@ -483,6 +489,7 @@ try_blorp_blit(struct brw_context *brw, GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1, GLenum filter, GLbitfield buffer_bit) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; /* Sync up the state of window system buffers. We need to do this before @@ -548,7 +555,7 @@ try_blorp_blit(struct brw_context *brw, /* Blorp doesn't support combined depth stencil which is all we have * prior to gen6. */ - if (brw->gen < 6) + if (devinfo->gen < 6) return false; src_irb = @@ -1142,6 +1149,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, { assert(intel_miptree_level_has_hiz(mt, level)); assert(op != BLORP_HIZ_OP_NONE); + const struct gen_device_info *devinfo = &brw->screen->devinfo; const char *opname = NULL; switch (op) { @@ -1166,7 +1174,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, * HiZ clear operations. However, they also seem to be required for * resolve operations. */ - if (brw->gen == 6) { + if (devinfo->gen == 6) { /* From the Sandy Bridge PRM, volume 2 part 1, page 313: * * "If other rendering operations have preceded this clear, a @@ -1178,7 +1186,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_CS_STALL); - } else if (brw->gen >= 7) { + } else if (devinfo->gen >= 7) { /* * From the Ivybridge PRM, volume 2, "Depth Buffer Clear": * @@ -1223,7 +1231,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, * HiZ clear operations. However, they also seem to be required for * resolve operations. */ - if (brw->gen == 6) { + if (devinfo->gen == 6) { /* From the Sandy Bridge PRM, volume 2 part 1, page 314: * * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be @@ -1236,7 +1244,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_CS_STALL); - } else if (brw->gen >= 8) { + } else if (devinfo->gen >= 8) { /* * From the Broadwell PRM, volume 7, "Depth Buffer Clear": * diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index b7bf03d8e0a..b9e087ce33b 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -107,8 +107,9 @@ brw_fast_clear_depth(struct gl_context *ctx) intel_get_renderbuffer(fb, BUFFER_DEPTH); struct intel_mipmap_tree *mt = depth_irb->mt; struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH]; + const struct gen_device_info *devinfo = &brw->screen->devinfo; - if (brw->gen < 6) + if (devinfo->gen < 6) return false; if (!intel_renderbuffer_has_hiz(depth_irb)) @@ -149,7 +150,7 @@ brw_fast_clear_depth(struct gl_context *ctx) * width of the map (LOD0) is not multiple of 16, fast clear * optimization must be disabled. */ - if (brw->gen == 6 && + if (devinfo->gen == 6 && (minify(mt->surf.phys_level0_sa.width, depth_irb->mt_level - mt->first_level) % 16) != 0) return false; @@ -264,6 +265,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) { struct brw_context *brw = brw_context(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; + const struct gen_device_info *devinfo = &brw->screen->devinfo; bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb); if (!_mesa_check_conditional_render(ctx)) @@ -298,7 +300,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) mask &= ~BUFFER_BITS_COLOR; } - if (brw->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) { + if (devinfo->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) { brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear); debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL); mask &= ~BUFFER_BITS_DEPTH_STENCIL; diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index e3023e50e9c..3a7c4829ed7 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -69,6 +69,7 @@ static void compile_clip_prog( struct brw_context *brw, void brw_upload_clip_prog(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct brw_clip_prog_key key; @@ -113,7 +114,7 @@ brw_upload_clip_prog(struct brw_context *brw) if (ctx->Transform.ClipPlanesEnabled) key.nr_userclip = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; - if (brw->gen == 5) + if (devinfo->gen == 5) key.clip_mode = BRW_CLIP_MODE_KERNEL_CLIP; else key.clip_mode = BRW_CLIP_MODE_NORMAL; diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index ed22d712a67..1bad7ac7a0c 100644 --- a/src/mesa/drivers/dri/i965/brw_compute.c +++ b/src/mesa/drivers/dri/i965/brw_compute.c @@ -37,6 +37,7 @@ static void prepare_indirect_gpgpu_walker(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; GLintptr indirect_offset = brw->compute.num_work_groups_offset; struct brw_bo *bo = brw->compute.num_work_groups_bo; @@ -44,7 +45,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw) brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4); brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8); - if (brw->gen > 7) + if (devinfo->gen > 7) return; /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */ @@ -103,6 +104,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw) static void brw_emit_gpgpu_walker(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct brw_cs_prog_data *prog_data = brw_cs_prog_data(brw->cs.base.prog_data); @@ -114,7 +116,7 @@ brw_emit_gpgpu_walker(struct brw_context *brw) } else { indirect_flag = GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE | - (brw->gen == 7 ? GEN7_GPGPU_PREDICATE_ENABLE : 0); + (devinfo->gen == 7 ? GEN7_GPGPU_PREDICATE_ENABLE : 0); prepare_indirect_gpgpu_walker(brw); } @@ -129,11 +131,11 @@ brw_emit_gpgpu_walker(struct brw_context *brw) if (right_non_aligned != 0) right_mask >>= (simd_size - right_non_aligned); - uint32_t dwords = brw->gen < 8 ? 11 : 15; + uint32_t dwords = devinfo->gen < 8 ? 11 : 15; BEGIN_BATCH(dwords); OUT_BATCH(GPGPU_WALKER << 16 | (dwords - 2) | indirect_flag); OUT_BATCH(0); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { OUT_BATCH(0); /* Indirect Data Length */ OUT_BATCH(0); /* Indirect Data Start Address */ } @@ -141,11 +143,11 @@ brw_emit_gpgpu_walker(struct brw_context *brw) OUT_BATCH(SET_FIELD(simd_size / 16, GPGPU_WALKER_SIMD_SIZE) | SET_FIELD(thread_width_max - 1, GPGPU_WALKER_THREAD_WIDTH_MAX)); OUT_BATCH(0); /* Thread Group ID Starting X */ - if (brw->gen >= 8) + if (devinfo->gen >= 8) OUT_BATCH(0); /* MBZ */ OUT_BATCH(num_groups[0]); /* Thread Group ID X Dimension */ OUT_BATCH(0); /* Thread Group ID Starting Y */ - if (brw->gen >= 8) + if (devinfo->gen >= 8) OUT_BATCH(0); /* MBZ */ OUT_BATCH(num_groups[1]); /* Thread Group ID Y Dimension */ OUT_BATCH(0); /* Thread Group ID Starting/Resume Z */ diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 2dbcc450860..b8e4be90ab3 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -261,6 +261,8 @@ static void brw_init_driver_functions(struct brw_context *brw, struct dd_function_table *functions) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + _mesa_init_driver_functions(functions); /* GLX uses DRI2 invalidate events to handle window resizing. @@ -292,9 +294,9 @@ brw_init_driver_functions(struct brw_context *brw, brwInitFragProgFuncs( functions ); brw_init_common_queryobj_functions(functions); - if (brw->gen >= 8 || brw->is_haswell) + if (devinfo->gen >= 8 || brw->is_haswell) hsw_init_queryobj_functions(functions); - else if (brw->gen >= 6) + else if (devinfo->gen >= 6) gen6_init_queryobj_functions(functions); else gen4_init_queryobj_functions(functions); @@ -310,7 +312,7 @@ brw_init_driver_functions(struct brw_context *brw, functions->EndTransformFeedback = hsw_end_transform_feedback; functions->PauseTransformFeedback = hsw_pause_transform_feedback; functions->ResumeTransformFeedback = hsw_resume_transform_feedback; - } else if (brw->gen >= 7) { + } else if (devinfo->gen >= 7) { functions->BeginTransformFeedback = gen7_begin_transform_feedback; functions->EndTransformFeedback = gen7_end_transform_feedback; functions->PauseTransformFeedback = gen7_pause_transform_feedback; @@ -326,21 +328,22 @@ brw_init_driver_functions(struct brw_context *brw, brw_get_transform_feedback_vertex_count; } - if (brw->gen >= 6) + if (devinfo->gen >= 6) functions->GetSamplePosition = gen6_get_sample_position; } static void brw_initialize_context_constants(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; const struct brw_compiler *compiler = brw->screen->compiler; const bool stage_exists[MESA_SHADER_STAGES] = { [MESA_SHADER_VERTEX] = true, - [MESA_SHADER_TESS_CTRL] = brw->gen >= 7, - [MESA_SHADER_TESS_EVAL] = brw->gen >= 7, - [MESA_SHADER_GEOMETRY] = brw->gen >= 6, + [MESA_SHADER_TESS_CTRL] = devinfo->gen >= 7, + [MESA_SHADER_TESS_EVAL] = devinfo->gen >= 7, + [MESA_SHADER_GEOMETRY] = devinfo->gen >= 6, [MESA_SHADER_FRAGMENT] = true, [MESA_SHADER_COMPUTE] = ((ctx->API == API_OPENGL_COMPAT || ctx->API == API_OPENGL_CORE) && @@ -357,7 +360,7 @@ brw_initialize_context_constants(struct brw_context *brw) } unsigned max_samplers = - brw->gen >= 8 || brw->is_haswell ? BRW_MAX_TEX_UNIT : 16; + devinfo->gen >= 8 || brw->is_haswell ? BRW_MAX_TEX_UNIT : 16; ctx->Const.MaxDualSourceDrawBuffers = 1; ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS; @@ -383,7 +386,7 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */ ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS; - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { ctx->Const.MaxRenderbufferSize = 16384; ctx->Const.MaxTextureLevels = MIN2(15 /* 16384 */, MAX_TEXTURE_LEVELS); ctx->Const.MaxCubeTextureLevels = 15; /* 16384 */ @@ -393,17 +396,17 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */ } ctx->Const.Max3DTextureLevels = 12; /* 2048 */ - ctx->Const.MaxArrayTextureLayers = brw->gen >= 7 ? 2048 : 512; + ctx->Const.MaxArrayTextureLayers = devinfo->gen >= 7 ? 2048 : 512; ctx->Const.MaxTextureMbytes = 1536; - ctx->Const.MaxTextureRectSize = brw->gen >= 7 ? 16384 : 8192; + ctx->Const.MaxTextureRectSize = devinfo->gen >= 7 ? 16384 : 8192; ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 15.0; ctx->Const.StripTextureBorder = true; - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { ctx->Const.MaxProgramTextureGatherComponents = 4; ctx->Const.MinProgramTextureGatherOffset = -32; ctx->Const.MaxProgramTextureGatherOffset = 31; - } else if (brw->gen == 6) { + } else if (devinfo->gen == 6) { ctx->Const.MaxProgramTextureGatherComponents = 1; ctx->Const.MinProgramTextureGatherOffset = -8; ctx->Const.MaxProgramTextureGatherOffset = 7; @@ -502,7 +505,7 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.MinLineWidth = 1.0; ctx->Const.MinLineWidthAA = 1.0; - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { ctx->Const.MaxLineWidth = 7.375; ctx->Const.MaxLineWidthAA = 7.375; ctx->Const.LineWidthGranularity = 0.125; @@ -525,11 +528,11 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.MaxPointSizeAA = 255.0; ctx->Const.PointSizeGranularity = 1.0; - if (brw->gen >= 5 || brw->is_g4x) + if (devinfo->gen >= 5 || brw->is_g4x) ctx->Const.MaxClipPlanes = 8; ctx->Const.GLSLTessLevelsAsInputs = true; - ctx->Const.LowerTCSPatchVerticesIn = brw->gen >= 8; + ctx->Const.LowerTCSPatchVerticesIn = devinfo->gen >= 8; ctx->Const.LowerTESPatchVerticesIn = true; ctx->Const.PrimitiveRestartForPatches = true; @@ -580,7 +583,7 @@ brw_initialize_context_constants(struct brw_context *brw) * that affect provoking vertex decision. Always use last vertex * convention for quad primitive which works as expected for now. */ - if (brw->gen >= 6) + if (devinfo->gen >= 6) ctx->Const.QuadsFollowProvokingVertexConvention = false; ctx->Const.NativeIntegers = true; @@ -629,7 +632,7 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.TextureBufferOffsetAlignment = 16; ctx->Const.MaxTextureBufferSize = 128 * 1024 * 1024; - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { ctx->Const.MaxVarying = 32; ctx->Const.Program[MESA_SHADER_VERTEX].MaxOutputComponents = 128; ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxInputComponents = 64; @@ -647,13 +650,13 @@ brw_initialize_context_constants(struct brw_context *brw) brw->screen->compiler->glsl_compiler_options[i]; } - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { ctx->Const.MaxViewportWidth = 32768; ctx->Const.MaxViewportHeight = 32768; } /* ARB_viewport_array, OES_viewport_array */ - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { ctx->Const.MaxViewports = GEN6_NUM_VIEWPORTS; ctx->Const.ViewportSubpixelBits = 0; @@ -664,7 +667,7 @@ brw_initialize_context_constants(struct brw_context *brw) } /* ARB_gpu_shader5 */ - if (brw->gen >= 7) + if (devinfo->gen >= 7) ctx->Const.MaxVertexStreams = MIN2(4, MAX_VERTEX_STREAMS); /* ARB_framebuffer_no_attachments */ @@ -689,7 +692,7 @@ brw_initialize_context_constants(struct brw_context *brw) * * [1] glsl-1.40/uniform_buffer/vs-float-array-variable-index.shader_test */ - if (brw->gen >= 7) + if (devinfo->gen >= 7) ctx->Const.UseSTD430AsDefaultPacking = true; } @@ -739,6 +742,7 @@ brw_initialize_cs_context_constants(struct brw_context *brw) static void brw_process_driconf_options(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; driOptionCache *options = &brw->optionCache; @@ -757,7 +761,7 @@ brw_process_driconf_options(struct brw_context *brw) if (INTEL_DEBUG & DEBUG_NO_HIZ) { brw->has_hiz = false; /* On gen6, you can only do separate stencil with HIZ. */ - if (brw->gen == 6) + if (devinfo->gen == 6) brw->has_separate_stencil = false; } @@ -854,7 +858,6 @@ brwCreateContext(gl_api api, brw->screen = screen; brw->bufmgr = screen->bufmgr; - brw->gen = devinfo->gen; brw->gt = devinfo->gt; brw->is_g4x = devinfo->is_g4x; brw->is_baytrail = devinfo->is_baytrail; @@ -881,11 +884,11 @@ brwCreateContext(gl_api api, brw->tes.base.stage = MESA_SHADER_TESS_EVAL; brw->gs.base.stage = MESA_SHADER_GEOMETRY; brw->wm.base.stage = MESA_SHADER_FRAGMENT; - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { brw->vtbl.emit_depth_stencil_hiz = gen8_emit_depth_stencil_hiz; - } else if (brw->gen >= 7) { + } else if (devinfo->gen >= 7) { brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz; - } else if (brw->gen >= 6) { + } else if (devinfo->gen >= 6) { brw->vtbl.emit_depth_stencil_hiz = gen6_emit_depth_stencil_hiz; } else { brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz; @@ -948,7 +951,7 @@ brwCreateContext(gl_api api, intel_batchbuffer_init(screen, &brw->batch); - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { /* Create a new hardware context. Using a hardware context means that * our GPU state will be saved/restored on context switch, allowing us * to assume that the GPU is in the same state we left it in. @@ -981,7 +984,7 @@ brwCreateContext(gl_api api, brw->urb.size = devinfo->urb.size; - if (brw->gen == 6) + if (devinfo->gen == 6) brw->urb.gs_present = false; brw->prim_restart.in_progress = false; @@ -1031,6 +1034,7 @@ intelDestroyContext(__DRIcontext * driContextPriv) struct brw_context *brw = (struct brw_context *) driContextPriv->driverPrivate; struct gl_context *ctx = &brw->ctx; + const struct gen_device_info *devinfo = &brw->screen->devinfo; _mesa_meta_free(&brw->ctx); @@ -1042,7 +1046,7 @@ intelDestroyContext(__DRIcontext * driContextPriv) brw_destroy_shader_time(brw); } - if (brw->gen >= 6) + if (devinfo->gen >= 6) blorp_finish(&brw->blorp); brw_destroy_state(brw); @@ -1209,7 +1213,9 @@ void intel_resolve_for_dri2_flush(struct brw_context *brw, __DRIdrawable *drawable) { - if (brw->gen < 6) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen < 6) { /* MSAA and fast color clear are not supported, so don't waste time * checking whether a resolve is needed. */ diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 2274fe5c80e..6ff280d3b6c 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -746,7 +746,6 @@ struct brw_context uint64_t max_gtt_map_object_size; - int gen; int gt; bool is_g4x; diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index 2500dbd0c48..2c97c381ee8 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -195,6 +195,7 @@ static const GLfloat fixed_plane[6][4] = { static void brw_upload_constant_buffer(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */ const GLuint sz = brw->curbe.total_size; @@ -323,7 +324,7 @@ emit: * * BRW_NEW_FRAGMENT_PROGRAM */ - if (brw->gen == 4 && !brw->is_g4x && + if (devinfo->gen == 4 && !brw->is_g4x && (brw->fragment_program->info.inputs_read & (1 << VARYING_SLOT_POS))) { BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); @@ -346,4 +347,3 @@ const struct brw_tracked_state brw_constant_buffer = { }, .emit = brw_upload_constant_buffer, }; - diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index a8ad2ac05a4..86f9e5bf7d8 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -158,6 +158,7 @@ brw_emit_prim(struct brw_context *brw, struct brw_transform_feedback_object *xfb_obj, unsigned stream) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; int verts_per_instance; int vertex_access_type; int indirect_flag; @@ -169,20 +170,20 @@ brw_emit_prim(struct brw_context *brw, int base_vertex_location = prim->basevertex; if (prim->indexed) { - vertex_access_type = brw->gen >= 7 ? + vertex_access_type = devinfo->gen >= 7 ? GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM : GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM; start_vertex_location += brw->ib.start_vertex_offset; base_vertex_location += brw->vb.start_vertex_bias; } else { - vertex_access_type = brw->gen >= 7 ? + vertex_access_type = devinfo->gen >= 7 ? GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL : GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL; start_vertex_location += brw->vb.start_vertex_bias; } /* We only need to trim the primitive count on pre-Gen6. */ - if (brw->gen < 6) + if (devinfo->gen < 6) verts_per_instance = trim(prim->mode, prim->count); else verts_per_instance = prim->count; @@ -250,9 +251,9 @@ brw_emit_prim(struct brw_context *brw, indirect_flag = 0; } - BEGIN_BATCH(brw->gen >= 7 ? 7 : 6); + BEGIN_BATCH(devinfo->gen >= 7 ? 7 : 6); - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { const int predicate_enable = (brw->predicate.state == BRW_PREDICATE_STATE_USE_BIT) ? GEN7_3DPRIM_PREDICATE_ENABLE : 0; @@ -280,6 +281,7 @@ static void brw_merge_inputs(struct brw_context *brw, const struct gl_vertex_array *arrays[]) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct gl_context *ctx = &brw->ctx; GLuint i; @@ -294,7 +296,7 @@ brw_merge_inputs(struct brw_context *brw, brw->vb.inputs[i].glarray = arrays[i]; } - if (brw->gen < 8 && !brw->is_haswell) { + if (devinfo->gen < 8 && !brw->is_haswell) { uint64_t mask = ctx->VertexProgram._Current->info.inputs_read; /* Prior to Haswell, the hardware can't natively support GL_FIXED or * 2_10_10_10_REV vertex formats. Set appropriate workaround flags. @@ -361,6 +363,7 @@ intel_disable_rb_aux_buffer(struct brw_context *brw, const struct brw_bo *bo) void brw_predraw_resolve_inputs(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct intel_texture_object *tex_obj; @@ -384,7 +387,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw) intel_miptree_prepare_texture(brw, tex_obj->mt, view_format, &aux_supported); - if (!aux_supported && brw->gen >= 9 && + if (!aux_supported && devinfo->gen >= 9 && intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) { perf_debug("Sampling renderbuffer with non-compressible format - " "turning off compression\n"); @@ -531,7 +534,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) if (!irb) continue; - + brw_render_cache_set_add_bo(brw, irb->mt->bo); intel_miptree_finish_render(brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count, @@ -607,6 +610,7 @@ brw_try_draw_prims(struct gl_context *ctx, struct gl_buffer_object *indirect) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; GLuint i; bool fail_next = false; @@ -753,7 +757,7 @@ brw_try_draw_prims(struct gl_context *ctx, if (i > 0 && vs_prog_data->uses_drawid) brw->ctx.NewDriverState |= BRW_NEW_VERTICES; - if (brw->gen < 6) + if (devinfo->gen < 6) brw_set_prim(brw, &prims[i]); else gen6_set_prim(brw, &prims[i]); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 5b56aaf1862..92a9be11f6b 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -252,8 +252,9 @@ brw_get_vertex_surface_type(struct brw_context *brw, const struct gl_vertex_array *glarray) { int size = glarray->Size; + const struct gen_device_info *devinfo = &brw->screen->devinfo; const bool is_ivybridge_or_older = - brw->gen <= 7 && !brw->is_baytrail && !brw->is_haswell; + devinfo->gen <= 7 && !brw->is_baytrail && !brw->is_haswell; if (unlikely(INTEL_DEBUG & DEBUG_VERTS)) fprintf(stderr, "type %s size %d normalized %d\n", @@ -295,7 +296,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, case GL_FLOAT: return float_types[size]; case GL_HALF_FLOAT: case GL_HALF_FLOAT_OES: - if (brw->gen < 6 && size == 3) + if (devinfo->gen < 6 && size == 3) return half_float_types[4]; else return half_float_types[size]; @@ -314,7 +315,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, return ubyte_types_norm[size]; } case GL_FIXED: - if (brw->gen >= 8 || brw->is_haswell) + if (devinfo->gen >= 8 || brw->is_haswell) return fixed_point_types[size]; /* This produces GL_FIXED inputs as values between INT32_MIN and @@ -328,7 +329,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, */ case GL_INT_2_10_10_10_REV: assert(size == 4); - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? ISL_FORMAT_B10G10R10A2_SNORM : ISL_FORMAT_R10G10B10A2_SNORM; @@ -336,7 +337,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, return ISL_FORMAT_R10G10B10A2_UINT; case GL_UNSIGNED_INT_2_10_10_10_REV: assert(size == 4); - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? ISL_FORMAT_B10G10R10A2_UNORM : ISL_FORMAT_R10G10B10A2_UNORM; @@ -353,7 +354,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, */ if (glarray->Type == GL_INT_2_10_10_10_REV) { assert(size == 4); - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? ISL_FORMAT_B10G10R10A2_SSCALED : ISL_FORMAT_R10G10B10A2_SSCALED; @@ -361,7 +362,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, return ISL_FORMAT_R10G10B10A2_UINT; } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) { assert(size == 4); - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { return glarray->Format == GL_BGRA ? ISL_FORMAT_B10G10R10A2_USCALED : ISL_FORMAT_R10G10B10A2_USCALED; @@ -374,7 +375,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, case GL_FLOAT: return float_types[size]; case GL_HALF_FLOAT: case GL_HALF_FLOAT_OES: - if (brw->gen < 6 && size == 3) + if (devinfo->gen < 6 && size == 3) return half_float_types[4]; else return half_float_types[size]; @@ -385,7 +386,7 @@ brw_get_vertex_surface_type(struct brw_context *brw, case GL_UNSIGNED_SHORT: return ushort_types_scale[size]; case GL_UNSIGNED_BYTE: return ubyte_types_scale[size]; case GL_FIXED: - if (brw->gen >= 8 || brw->is_haswell) + if (devinfo->gen >= 8 || brw->is_haswell) return fixed_point_types[size]; /* This produces GL_FIXED inputs as values between INT32_MIN and @@ -452,6 +453,7 @@ copy_array_to_vbo_array(struct brw_context *brw, void brw_prepare_vertices(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; /* BRW_NEW_VS_PROG_DATA */ const struct brw_vs_prog_data *vs_prog_data = @@ -474,7 +476,7 @@ brw_prepare_vertices(struct brw_context *brw) * is passed sideband through the fixed function units. So, we need to * prepare the vertex buffer for it, but it's not present in inputs_read. */ - if (brw->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL || + if (devinfo->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL || ctx->Polygon.BackMode != GL_FILL)) { vs_inputs |= VERT_BIT_EDGEFLAG; } diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.c b/src/mesa/drivers/dri/i965/brw_ff_gs.c index a3919524df1..f7f86d33874 100644 --- a/src/mesa/drivers/dri/i965/brw_ff_gs.c +++ b/src/mesa/drivers/dri/i965/brw_ff_gs.c @@ -47,6 +47,7 @@ void brw_codegen_ff_gs_prog(struct brw_context *brw, struct brw_ff_gs_prog_key *key) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct brw_ff_gs_compile c; const GLuint *program; void *mem_ctx; @@ -71,7 +72,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw, */ brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE); - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { unsigned num_verts; bool check_edge_flag; /* On Sandybridge, we use the GS for implementing transform feedback @@ -161,6 +162,7 @@ static void brw_ff_gs_populate_key(struct brw_context *brw, struct brw_ff_gs_prog_key *key) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; static const unsigned swizzle_for_offset[4] = { BRW_SWIZZLE4(0, 1, 2, 3), BRW_SWIZZLE4(1, 2, 3, 3), @@ -170,7 +172,7 @@ brw_ff_gs_populate_key(struct brw_context *brw, struct gl_context *ctx = &brw->ctx; - assert(brw->gen < 7); + assert(devinfo->gen < 7); memset(key, 0, sizeof(*key)); @@ -189,7 +191,7 @@ brw_ff_gs_populate_key(struct brw_context *brw, key->pv_first = true; } - if (brw->gen == 6) { + if (devinfo->gen == 6) { /* On Gen6, GS is used for transform feedback. */ /* BRW_NEW_TRANSFORM_FEEDBACK */ if (_mesa_is_xfb_active_and_unpaused(ctx)) { diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c b/src/mesa/drivers/dri/i965/brw_formatquery.c index 5faf91fa9e7..4f3b9e467be 100644 --- a/src/mesa/drivers/dri/i965/brw_formatquery.c +++ b/src/mesa/drivers/dri/i965/brw_formatquery.c @@ -32,11 +32,12 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum target, GLenum internalFormat, int samples[16]) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; (void) target; (void) internalFormat; - switch (brw->gen) { + switch (devinfo->gen) { case 10: case 9: samples[0] = 16; @@ -76,7 +77,7 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum target, return 1; default: - assert(brw->gen < 6); + assert(devinfo->gen < 6); samples[0] = 1; return 1; } diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index bd8f993d11b..9242504bb30 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -198,6 +198,7 @@ brw_gs_populate_key(struct brw_context *brw, void brw_upload_gs_prog(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct brw_stage_state *stage_state = &brw->gs.base; struct brw_gs_prog_key key; /* BRW_NEW_GEOMETRY_PROGRAM */ @@ -208,7 +209,7 @@ brw_upload_gs_prog(struct brw_context *brw) if (gp == NULL) { /* No geometry shader. Vertex data just passes straight through. */ - if (brw->gen == 6 && + if (devinfo->gen == 6 && (brw->ctx.NewDriverState & BRW_NEW_TRANSFORM_FEEDBACK)) { gen6_brw_upload_ff_gs_prog(brw); return; diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index e9158c596c5..a1082a7a05a 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -74,10 +74,12 @@ static void brw_lower_packing_builtins(struct brw_context *brw, exec_list *ir) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* Gens < 7 don't have instructions to convert to or from half-precision, * and Gens < 6 don't expose that functionality. */ - if (brw->gen != 6) + if (devinfo->gen != 6) return; lower_packing_builtins(ir, LOWER_PACK_HALF_2x16 | LOWER_UNPACK_HALF_2x16); @@ -88,6 +90,7 @@ process_glsl_ir(struct brw_context *brw, struct gl_shader_program *shader_prog, struct gl_linked_shader *shader) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; /* Temporary memory context for any new IR. */ @@ -108,7 +111,7 @@ process_glsl_ir(struct brw_context *brw, EXP_TO_EXP2 | LOG_TO_LOG2 | DFREXP_DLDEXP_TO_ARITH); - if (brw->gen < 7) { + if (devinfo->gen < 7) { instructions_to_lower |= BIT_COUNT_TO_MATH | EXTRACT_TO_SHIFTS | INSERT_TO_SHIFTS | @@ -120,7 +123,7 @@ process_glsl_ir(struct brw_context *brw, /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, * if-statements need to be flattened. */ - if (brw->gen < 6) + if (devinfo->gen < 6) lower_if_to_cond_assign(shader->Stage, shader->ir, 16); do_lower_texture_projection(shader->ir); diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c index 7ce1fd137f7..d292f5a8e24 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_util.c +++ b/src/mesa/drivers/dri/i965/brw_meta_util.c @@ -277,6 +277,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw, const struct intel_mipmap_tree *mt, const union gl_color_union *color) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct gl_context *ctx = &brw->ctx; /* If we're mapping the render format to a different format than the @@ -287,14 +288,14 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw, * state so the hardware probably legitimately doesn't need to support * this case. At least on Gen9 this really does seem to cause problems. */ - if (brw->gen >= 9 && + if (devinfo->gen >= 9 && brw_isl_format_for_mesa_format(mt->format) != brw->mesa_to_isl_render_format[mt->format]) return false; const mesa_format format = _mesa_get_render_format(ctx, mt->format); if (_mesa_is_format_integer_color(format)) { - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { perf_debug("Integer fast clear not enabled for (%s)", _mesa_get_format_name(format)); } @@ -306,7 +307,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw, continue; } - if (brw->gen < 9 && + if (devinfo->gen < 9 && color->f[i] != 0.0f && color->f[i] != 1.0f) { return false; } diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index bc98a583a52..4ecee7fa57c 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -54,7 +54,9 @@ static void upload_pipelined_state_pointers(struct brw_context *brw) { - if (brw->gen == 5) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen == 5) { /* Need to flush before changing clip max threads for errata. */ BEGIN_BATCH(1); OUT_BATCH(MI_FLUSH); @@ -195,6 +197,7 @@ void brw_workaround_depthstencil_alignment(struct brw_context *brw, GLbitfield clear_mask) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct gl_framebuffer *fb = ctx->DrawBuffer; struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); @@ -215,7 +218,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, /* Gen6+ doesn't require the workarounds, since we always program the * surface state at the start of the whole surface. */ - if (brw->gen >= 6) + if (devinfo->gen >= 6) return; /* Check if depth buffer is in depth/stencil format. If so, then it's only @@ -253,6 +256,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, void brw_emit_depthbuffer(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct gl_framebuffer *fb = ctx->DrawBuffer; /* _NEW_BUFFERS */ @@ -273,7 +277,7 @@ brw_emit_depthbuffer(struct brw_context *brw) separate_stencil = stencil_mt->format == MESA_FORMAT_S_UINT8; /* Gen7 supports only separate stencil */ - assert(separate_stencil || brw->gen < 7); + assert(separate_stencil || devinfo->gen < 7); } /* If there's a packed depth/stencil bound to stencil only, we need to @@ -293,14 +297,14 @@ brw_emit_depthbuffer(struct brw_context *brw) * set to the same value. Gens after 7 implicitly always set * Separate_Stencil_Enable; software cannot disable it. */ - if ((brw->gen < 7 && hiz) || brw->gen >= 7) { + if ((devinfo->gen < 7 && hiz) || devinfo->gen >= 7) { assert(!_mesa_is_format_packed_depth_stencil(depth_mt->format)); } /* Prior to Gen7, if using separate stencil, hiz must be enabled. */ - assert(brw->gen >= 7 || !separate_stencil || hiz); + assert(devinfo->gen >= 7 || !separate_stencil || hiz); - assert(brw->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0); + assert(devinfo->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0); assert(!hiz || depth_mt->surf.tiling == ISL_TILING_Y0); depthbuffer_format = brw_depthbuffer_format(brw); @@ -370,7 +374,8 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, assert(!hiz); assert(!separate_stencil); - const unsigned len = (brw->is_g4x || brw->gen == 5) ? 6 : 5; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const unsigned len = (brw->is_g4x || devinfo->gen == 5) ? 6 : 5; BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); @@ -390,12 +395,12 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, ((height + tile_y - 1) << 19)); OUT_BATCH(0); - if (brw->is_g4x || brw->gen >= 5) + if (brw->is_g4x || devinfo->gen >= 5) OUT_BATCH(tile_x | (tile_y << 16)); else assert(tile_x == 0 && tile_y == 0); - if (brw->gen >= 6) + if (devinfo->gen >= 6) OUT_BATCH(0); ADVANCE_BATCH(); @@ -413,11 +418,12 @@ const struct brw_tracked_state brw_depthbuffer = { void brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) { - const bool is_965 = brw->gen == 4 && !brw->is_g4x; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const bool is_965 = devinfo->gen == 4 && !brw->is_g4x; const uint32_t _3DSTATE_PIPELINE_SELECT = is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; - if (brw->gen >= 8 && brw->gen < 10) { + if (devinfo->gen >= 8 && devinfo->gen < 10) { /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT: * * Software must clear the COLOR_CALC_STATE Valid field in @@ -437,7 +443,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) } } - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] * PIPELINE_SELECT [DevBWR+]": * @@ -449,7 +455,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) * MI_PIPELINE_SELECT command to change the Pipeline Select Mode. */ const unsigned dc_flush = - brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; + devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | @@ -482,11 +488,11 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) /* Select the pipeline */ BEGIN_BATCH(1); OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | - (brw->gen >= 9 ? (3 << 8) : 0) | + (devinfo->gen >= 9 ? (3 << 8) : 0) | (pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0)); ADVANCE_BATCH(); - if (brw->gen == 7 && !brw->is_haswell && + if (devinfo->gen == 7 && !brw->is_haswell && pipeline == BRW_RENDER_PIPELINE) { /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction] * PIPELINE_SELECT [DevBWR+]": @@ -517,12 +523,13 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) void brw_upload_invariant_state(struct brw_context *brw) { - const bool is_965 = brw->gen == 4 && !brw->is_g4x; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const bool is_965 = devinfo->gen == 4 && !brw->is_g4x; brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); brw->last_pipeline = BRW_RENDER_PIPELINE; - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { BEGIN_BATCH(3); OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2)); OUT_BATCH(0); @@ -574,6 +581,8 @@ const struct brw_tracked_state brw_invariant_state = { void brw_upload_state_base_address(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (brw->batch.state_base_address_emitted) return; @@ -586,9 +595,9 @@ brw_upload_state_base_address(struct brw_context *brw) * maybe this isn't required for us in particular. */ - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { const unsigned dc_flush = - brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; + devinfo->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; /* Emit a render target cache flush. * @@ -617,9 +626,9 @@ brw_upload_state_base_address(struct brw_context *brw) dc_flush); } - if (brw->gen >= 8) { - uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; - int pkt_len = brw->gen >= 9 ? 19 : 16; + if (devinfo->gen >= 8) { + uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; + int pkt_len = devinfo->gen >= 9 ? 19 : 16; BEGIN_BATCH(pkt_len); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2)); @@ -645,14 +654,14 @@ brw_upload_state_base_address(struct brw_context *brw) OUT_BATCH(0xfffff001); /* Instruction access upper bound */ OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1); - if (brw->gen >= 9) { + if (devinfo->gen >= 9) { OUT_BATCH(1); OUT_BATCH(0); OUT_BATCH(0); } ADVANCE_BATCH(); - } else if (brw->gen >= 6) { - uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0; + } else if (devinfo->gen >= 6) { + uint8_t mocs = devinfo->gen == 7 ? GEN7_MOCS_L3 : 0; BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); @@ -691,7 +700,7 @@ brw_upload_state_base_address(struct brw_context *brw) OUT_BATCH(1); /* Indirect object upper bound */ OUT_BATCH(1); /* Instruction access upper bound */ ADVANCE_BATCH(); - } else if (brw->gen == 5) { + } else if (devinfo->gen == 5) { BEGIN_BATCH(8); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); OUT_BATCH(1); /* General state base address */ @@ -713,7 +722,7 @@ brw_upload_state_base_address(struct brw_context *brw) ADVANCE_BATCH(); } - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { brw_emit_pipe_control_flush(brw, PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_STATE_CACHE_INVALIDATE | diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 2a84fb8864e..a341408fe06 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -71,7 +71,9 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags) static uint32_t gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags) { - if (brw->gen == 7 && !brw->is_haswell) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen == 7 && !brw->is_haswell) { if (flags & PIPE_CONTROL_CS_STALL) { /* If we're doing a CS stall, reset the counter and carry on. */ brw->pipe_controls_since_last_cs_stall = 0; @@ -91,11 +93,13 @@ static void brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, struct brw_bo *bo, uint32_t offset, uint64_t imm) { - if (brw->gen >= 8) { - if (brw->gen == 8) + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen >= 8) { + if (devinfo->gen == 8) gen8_add_cs_stall_workaround_bits(&flags); - if (brw->gen == 9 && + if (devinfo->gen == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { /* Hardware workaround: SKL * @@ -117,8 +121,8 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, OUT_BATCH(imm); OUT_BATCH(imm >> 32); ADVANCE_BATCH(); - } else if (brw->gen >= 6) { - if (brw->gen == 6 && + } else if (devinfo->gen >= 6) { + if (devinfo->gen == 6 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) { /* Hardware workaround: SNB B-Spec says: * @@ -134,7 +138,7 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24 * on later platforms. We always use PPGTT on Gen7+. */ - unsigned gen6_gtt = brw->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0; + unsigned gen6_gtt = devinfo->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0; BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); @@ -170,7 +174,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) { - if (brw->gen >= 6 && + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen >= 6 && (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) && (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { /* A pipe control command with flush and invalidate bits set @@ -222,14 +228,16 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, void brw_emit_depth_stall_flushes(struct brw_context *brw) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); /* Starting on BDW, these pipe controls are unnecessary. * * WM HW will internally manage the draining pipe and flushing of the caches * when this command is issued. The PIPE_CONTROL restrictions are removed. */ - if (brw->gen >= 8) + if (devinfo->gen >= 8) return; brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); @@ -248,7 +256,9 @@ brw_emit_depth_stall_flushes(struct brw_context *brw) void gen7_emit_vs_workaround_flush(struct brw_context *brw) { - assert(brw->gen == 7); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen == 7); brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE | PIPE_CONTROL_DEPTH_STALL, @@ -337,12 +347,14 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw) * * SW can track the completion of the end-of-pipe-synchronization by * using "Notify Enable" and "PostSync Operation - Write Immediate - * Data" in the PIPE_CONTROL command. + * Data" in the PIPE_CONTROL command. */ void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags) { - if (brw->gen >= 6) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen >= 6) { /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory": * * "The most common action to perform upon reaching a synchronization @@ -423,7 +435,9 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags) void brw_emit_mi_flush(struct brw_context *brw) { - if (brw->batch.ring == BLT_RING && brw->gen >= 6) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) { BEGIN_BATCH_BLT(4); OUT_BATCH(MI_FLUSH_DW); OUT_BATCH(0); @@ -432,7 +446,7 @@ brw_emit_mi_flush(struct brw_context *brw) ADVANCE_BATCH(); } else { int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c b/src/mesa/drivers/dri/i965/brw_primitive_restart.c index 3dc221e1cfb..39ca5e869ae 100644 --- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c +++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c @@ -80,9 +80,10 @@ can_cut_index_handle_prims(struct gl_context *ctx, const struct _mesa_index_buffer *ib) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; /* Otherwise Haswell can do it all. */ - if (brw->gen >= 8 || brw->is_haswell) + if (devinfo->gen >= 8 || brw->is_haswell) return true; if (!can_cut_index_handle_restart_index(ctx, ib)) { diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 257a99bc946..db4da8cae2b 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -264,10 +264,11 @@ static void brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_CS_STALL); - assert(brw->gen >= 7 && brw->gen <= 10); + assert(devinfo->gen >= 7 && devinfo->gen <= 10); if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT | GL_ELEMENT_ARRAY_BARRIER_BIT | @@ -291,7 +292,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) /* Typed surface messages are handled by the render cache on IVB, so we * need to flush it too. */ - if (brw->gen == 7 && !brw->is_haswell) + if (devinfo->gen == 7 && !brw->is_haswell) bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH; brw_emit_pipe_control_flush(brw, bits); @@ -301,9 +302,10 @@ static void brw_blend_barrier(struct gl_context *ctx) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; if (!ctx->Extensions.MESA_shader_framebuffer_fetch) { - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); @@ -644,7 +646,8 @@ brw_setup_tex_for_precompile(struct brw_context *brw, struct brw_sampler_prog_key_data *tex, struct gl_program *prog) { - const bool has_shader_channel_select = brw->is_haswell || brw->gen >= 8; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const bool has_shader_channel_select = brw->is_haswell || devinfo->gen >= 8; unsigned sampler_count = util_last_bit(prog->SamplersUsed); for (unsigned i = 0; i < sampler_count; i++) { if (!has_shader_channel_select && (prog->ShadowSamplers & (1 << i))) { diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 04ce9a94cad..906a68ead1b 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -84,7 +84,9 @@ brw_raw_timestamp_delta(struct brw_context *brw, uint64_t time0, uint64_t time1) void brw_write_timestamp(struct brw_context *brw, struct brw_bo *query_bo, int idx) { - if (brw->gen == 6) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen == 6) { /* Emit Sandybridge workaround flush: */ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | @@ -93,7 +95,7 @@ brw_write_timestamp(struct brw_context *brw, struct brw_bo *query_bo, int idx) uint32_t flags = PIPE_CONTROL_WRITE_TIMESTAMP; - if (brw->gen == 9 && brw->gt == 4) + if (devinfo->gen == 9 && brw->gt == 4) flags |= PIPE_CONTROL_CS_STALL; brw_emit_pipe_control_write(brw, flags, @@ -106,12 +108,13 @@ brw_write_timestamp(struct brw_context *brw, struct brw_bo *query_bo, int idx) void brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t flags = PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_DEPTH_STALL; - if (brw->gen == 9 && brw->gt == 4) + if (devinfo->gen == 9 && brw->gt == 4) flags |= PIPE_CONTROL_CS_STALL; - if (brw->gen >= 10) { + if (devinfo->gen >= 10) { /* "Driver must program PIPE_CONTROL with only Depth Stall Enable bit set * prior to programming a PIPE_CONTROL with Write PS Depth Count Post sync * operation." @@ -131,11 +134,12 @@ brw_queryobj_get_results(struct gl_context *ctx, struct brw_query_object *query) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; int i; uint64_t *results; - assert(brw->gen < 6); + assert(devinfo->gen < 6); if (query->bo == NULL) return; @@ -257,8 +261,9 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen < 6); + assert(devinfo->gen < 6); switch (query->Base.Target) { case GL_TIME_ELAPSED_EXT: @@ -328,8 +333,9 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen < 6); + assert(devinfo->gen < 6); switch (query->Base.Target) { case GL_TIME_ELAPSED_EXT: @@ -381,8 +387,9 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q) static void brw_wait_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_query_object *query = (struct brw_query_object *)q; + const struct gen_device_info *devinfo = &brw_context(ctx)->screen->devinfo; - assert(brw_context(ctx)->gen < 6); + assert(devinfo->gen < 6); brw_queryobj_get_results(ctx, query); query->Base.Ready = true; @@ -398,8 +405,9 @@ static void brw_check_query(struct gl_context *ctx, struct gl_query_object *q) { struct brw_context *brw = brw_context(ctx); struct brw_query_object *query = (struct brw_query_object *)q; + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen < 6); + assert(devinfo->gen < 6); /* From the GL_ARB_occlusion_query spec: * @@ -427,8 +435,9 @@ static void ensure_bo_has_space(struct gl_context *ctx, struct brw_query_object *query) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen < 6); + assert(devinfo->gen < 6); if (!query->bo || query->last_index * 2 + 1 >= 4096 / sizeof(uint64_t)) { diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 9add4515b92..37ed166e35e 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -48,6 +48,8 @@ static void brw_upload_initial_gpu_state(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* On platforms with hardware contexts, we can set our initial GPU state * right away rather than doing it via state atoms. This saves a small * amount of overhead on every draw call. @@ -55,12 +57,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw) if (!brw->hw_ctx) return; - if (brw->gen == 6) + if (devinfo->gen == 6) brw_emit_post_sync_nonzero_flush(brw); brw_upload_invariant_state(brw); - if (brw->gen == 9) { + if (devinfo->gen == 9) { /* Recommended optimizations for Victim Cache eviction and floating * point blending. */ @@ -83,7 +85,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw) } } - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { gen8_emit_3dstate_sample_pattern(brw); BEGIN_BATCH(5); @@ -108,14 +110,14 @@ brw_upload_initial_gpu_state(struct brw_context *brw) * Fortunately, we can just write the registers from userspace * on Gen8+, and they're context saved/restored. */ - if (brw->gen >= 9) { + if (devinfo->gen >= 9) { BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(CS_DEBUG_MODE2); OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) | CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE); ADVANCE_BATCH(); - } else if (brw->gen == 8) { + } else if (devinfo->gen == 8) { BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(INSTPM); @@ -165,25 +167,26 @@ brw_copy_pipeline_atoms(struct brw_context *brw, void brw_init_state( struct brw_context *brw ) { struct gl_context *ctx = &brw->ctx; + const struct gen_device_info *devinfo = &brw->screen->devinfo; /* Force the first brw_select_pipeline to emit pipeline select */ brw->last_pipeline = BRW_NUM_PIPELINES; brw_init_caches(brw); - if (brw->gen >= 10) + if (devinfo->gen >= 10) gen10_init_atoms(brw); - else if (brw->gen >= 9) + else if (devinfo->gen >= 9) gen9_init_atoms(brw); - else if (brw->gen >= 8) + else if (devinfo->gen >= 8) gen8_init_atoms(brw); else if (brw->is_haswell) gen75_init_atoms(brw); - else if (brw->gen >= 7) + else if (devinfo->gen >= 7) gen7_init_atoms(brw); - else if (brw->gen >= 6) + else if (devinfo->gen >= 6) gen6_init_atoms(brw); - else if (brw->gen >= 5) + else if (devinfo->gen >= 5) gen5_init_atoms(brw); else if (brw->is_g4x) gen45_init_atoms(brw); @@ -391,12 +394,13 @@ brw_upload_programs(struct brw_context *brw, enum brw_pipeline pipeline) { struct gl_context *ctx = &brw->ctx; + const struct gen_device_info *devinfo = &brw->screen->devinfo; if (pipeline == BRW_RENDER_PIPELINE) { brw_upload_vs_prog(brw); brw_upload_tess_programs(brw); - if (brw->gen < 6) + if (devinfo->gen < 6) brw_upload_ff_gs_prog(brw); else brw_upload_gs_prog(brw); @@ -431,7 +435,7 @@ brw_upload_programs(struct brw_context *brw, brw_upload_wm_prog(brw); - if (brw->gen < 6) { + if (devinfo->gen < 6) { brw_upload_clip_prog(brw); brw_upload_sf_prog(brw); } @@ -463,6 +467,7 @@ static inline void brw_upload_pipeline_state(struct brw_context *brw, enum brw_pipeline pipeline) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; int i; static int dirty_count = 0; @@ -526,7 +531,7 @@ brw_upload_pipeline_state(struct brw_context *brw, return; /* Emit Sandybridge workaround flushes on every primitive, for safety. */ - if (brw->gen == 6) + if (devinfo->gen == 6) brw_emit_post_sync_nonzero_flush(brw); brw_upload_programs(brw, pipeline); diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index a2bc1ded6db..879cb424533 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -412,6 +412,7 @@ bool brw_render_target_supported(struct brw_context *brw, struct gl_renderbuffer *rb) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; mesa_format format = rb->Format; /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means @@ -429,10 +430,10 @@ brw_render_target_supported(struct brw_context *brw, /* Under some conditions, MSAA is not supported for formats whose width is * more than 64 bits. */ - if (brw->gen < 8 && + if (devinfo->gen < 8 && rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) { /* Gen6: MSAA on >64 bit formats is unsupported. */ - if (brw->gen <= 6) + if (devinfo->gen <= 6) return false; /* Gen7: 8x MSAA on >64 bit formats is unsupported. */ @@ -515,13 +516,15 @@ translate_tex_format(struct brw_context *brw, uint32_t brw_depth_format(struct brw_context *brw, mesa_format format) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + switch (format) { case MESA_FORMAT_Z_UNORM16: return BRW_DEPTHFORMAT_D16_UNORM; case MESA_FORMAT_Z_FLOAT32: return BRW_DEPTHFORMAT_D32_FLOAT; case MESA_FORMAT_Z24_UNORM_X8_UINT: - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; } else { /* Use D24_UNORM_S8, not D24_UNORM_X8. diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c index 1ed622eebb1..109e3fdbf55 100644 --- a/src/mesa/drivers/dri/i965/brw_tcs.c +++ b/src/mesa/drivers/dri/i965/brw_tcs.c @@ -294,6 +294,7 @@ void brw_tcs_populate_key(struct brw_context *brw, struct brw_tcs_prog_key *key) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program; struct brw_program *tep = (struct brw_program *) brw->tess_eval_program; struct gl_program *tes_prog = &tep->program; @@ -309,7 +310,7 @@ brw_tcs_populate_key(struct brw_context *brw, per_patch_slots |= prog->info.patch_outputs_written; } - if (brw->gen < 8 || !tcp) + if (devinfo->gen < 8 || !tcp) key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices; key->outputs_written = per_vertex_slots; key->patch_outputs_written = per_patch_slots; @@ -318,7 +319,7 @@ brw_tcs_populate_key(struct brw_context *brw, * based on the domain the DS is expecting to tessellate. */ key->tes_primitive_mode = tep->program.info.tess.primitive_mode; - key->quads_workaround = brw->gen < 9 && + key->quads_workaround = devinfo->gen < 9 && tep->program.info.tess.primitive_mode == GL_QUADS && tep->program.info.tess.spacing == TESS_SPACING_EQUAL; @@ -374,6 +375,7 @@ brw_tcs_precompile(struct gl_context *ctx, struct brw_program *btcp = brw_program(prog); const struct gl_linked_shader *tes = shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]; + const struct gen_device_info *devinfo = &brw->screen->devinfo; memset(&key, 0, sizeof(key)); @@ -381,14 +383,14 @@ brw_tcs_precompile(struct gl_context *ctx, brw_setup_tex_for_precompile(brw, &key.tex, prog); /* Guess that the input and output patches have the same dimensionality. */ - if (brw->gen < 8) + if (devinfo->gen < 8) key.input_vertices = prog->info.tess.tcs_vertices_out; struct brw_program *btep; if (tes) { btep = brw_program(tes->Program); key.tes_primitive_mode = tes->Program->info.tess.primitive_mode; - key.quads_workaround = brw->gen < 9 && + key.quads_workaround = devinfo->gen < 9 && tes->Program->info.tess.primitive_mode == GL_QUADS && tes->Program->info.tess.spacing == TESS_SPACING_EQUAL; } else { diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index 18daf5137bd..82debfac2cb 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -116,6 +116,8 @@ void brw_calculate_urb_fence(struct brw_context *brw, unsigned csize, unsigned vsize, unsigned sfsize) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (csize < limits[CS].min_entry_size) csize = limits[CS].min_entry_size; @@ -145,7 +147,7 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize, brw->urb.constrained = 0; - if (brw->gen == 5) { + if (devinfo->gen == 5) { brw->urb.nr_vs_entries = 128; brw->urb.nr_sf_entries = 48; if (check_urb_layout(brw)) { diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index c0a0a13f230..a2f79a66ef9 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -73,13 +73,14 @@ GLbitfield64 brw_vs_outputs_written(struct brw_context *brw, struct brw_vs_prog_key *key, GLbitfield64 user_varyings) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; GLbitfield64 outputs_written = user_varyings; if (key->copy_edgeflag) { outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE); } - if (brw->gen < 6) { + if (devinfo->gen < 6) { /* Put dummy slots into the VUE for the SF to put the replaced * point sprite coords in. We shouldn't need these dummy slots, * which take up precious URB space, but it would mean that the SF @@ -306,6 +307,7 @@ brw_vs_populate_key(struct brw_context *brw, /* BRW_NEW_VERTEX_PROGRAM */ struct brw_program *vp = (struct brw_program *)brw->vertex_program; struct gl_program *prog = (struct gl_program *) brw->vertex_program; + const struct gen_device_info *devinfo = &brw->screen->devinfo; memset(key, 0, sizeof(*key)); @@ -321,7 +323,7 @@ brw_vs_populate_key(struct brw_context *brw, _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; } - if (brw->gen < 6) { + if (devinfo->gen < 6) { /* _NEW_POLYGON */ key->copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL || ctx->Polygon.BackMode != GL_FILL); @@ -343,7 +345,7 @@ brw_vs_populate_key(struct brw_context *brw, brw_populate_sampler_prog_key_data(ctx, prog, &key->tex); /* BRW_NEW_VS_ATTRIB_WORKAROUNDS */ - if (brw->gen < 8 && !brw->is_haswell) { + if (devinfo->gen < 8 && !brw->is_haswell) { memcpy(key->gl_attrib_wa_flags, brw->vb.attrib_wa_flags, sizeof(brw->vb.attrib_wa_flags)); } diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index e1555d60c56..fdeb83fe6dd 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -307,6 +307,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, struct brw_sampler_prog_key_data *key) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; GLbitfield mask = prog->SamplersUsed; while (mask) { @@ -329,10 +330,10 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, /* Haswell handles texture swizzling as surface format overrides * (except for GL_ALPHA); all other platforms need MOVs in the shader. */ - if (alpha_depth || (brw->gen < 8 && !brw->is_haswell)) + if (alpha_depth || (devinfo->gen < 8 && !brw->is_haswell)) key->swizzles[s] = brw_get_texture_swizzle(ctx, t); - if (brw->gen < 8 && + if (devinfo->gen < 8 && sampler->MinFilter != GL_NEAREST && sampler->MagFilter != GL_NEAREST) { if (sampler->WrapS == GL_CLAMP) @@ -344,7 +345,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, } /* gather4 for RG32* is broken in multiple ways on Gen7. */ - if (brw->gen == 7 && prog->nir->info.uses_texture_gather) { + if (devinfo->gen == 7 && prog->nir->info.uses_texture_gather) { switch (img->InternalFormat) { case GL_RG32I: case GL_RG32UI: { @@ -382,7 +383,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, /* Gen6's gather4 is broken for UINT/SINT; we treat them as * UNORM/FLOAT instead and fix it in the shader. */ - if (brw->gen == 6 && prog->nir->info.uses_texture_gather) { + if (devinfo->gen == 6 && prog->nir->info.uses_texture_gather) { key->gen6_gather_wa[s] = gen6_gather_workaround(img->InternalFormat); } @@ -397,14 +398,14 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, * compressed. These don't need ld2dms sampling along with mcs fetch. */ if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) { - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); assert(intel_tex->mt->surf.samples > 1); assert(intel_tex->mt->mcs_buf); assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY); key->compressed_multisample_layout_mask |= 1 << s; if (intel_tex->mt->surf.samples >= 16) { - assert(brw->gen >= 9); + assert(devinfo->gen >= 9); key->msaa_16 |= 1 << s; } } @@ -456,6 +457,7 @@ brw_wm_state_dirty(const struct brw_context *brw) void brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; /* BRW_NEW_FRAGMENT_PROGRAM */ const struct brw_program *fp = brw_program_const(brw->fragment_program); @@ -467,7 +469,7 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) /* Build the index for table lookup */ - if (brw->gen < 6) { + if (devinfo->gen < 6) { /* _NEW_COLOR */ if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) { lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT; @@ -527,7 +529,7 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) key->high_quality_derivatives = ctx->Hint.FragmentShaderDerivative == GL_NICEST; - if (brw->gen < 6) + if (devinfo->gen < 6) key->stats_wm = brw->stats_wm; /* _NEW_LIGHT */ @@ -565,8 +567,8 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) } /* BRW_NEW_VUE_MAP_GEOM_OUT */ - if (brw->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read & - BRW_FS_VARYING_INPUT_MASK) > 16) { + if (devinfo->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read & + BRW_FS_VARYING_INPUT_MASK) > 16) { key->input_slots_valid = brw->vue_map_geom_out.slots_valid; } @@ -576,7 +578,7 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) * like GL requires. Fix that by building the alpha test into the * shader, and we'll skip enabling the fixed function alpha test. */ - if (brw->gen < 6 && ctx->DrawBuffer->_NumColorDrawBuffers > 1 && + if (devinfo->gen < 6 && ctx->DrawBuffer->_NumColorDrawBuffers > 1 && ctx->Color.AlphaEnabled) { key->alpha_test_func = ctx->Color.AlphaFunc; key->alpha_test_ref = ctx->Color.AlphaRef; @@ -615,6 +617,7 @@ bool brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct brw_wm_prog_key key; struct brw_program *bfp = brw_program(prog); @@ -623,7 +626,7 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog) uint64_t outputs_written = prog->info.outputs_written; - if (brw->gen < 6) { + if (devinfo->gen < 6) { if (prog->info.fs.uses_discard) key.iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT; @@ -635,8 +638,8 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog) key.iz_lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT; } - if (brw->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read & - BRW_FS_VARYING_INPUT_MASK) > 16) { + if (devinfo->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read & + BRW_FS_VARYING_INPUT_MASK) > 16) { key.input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS; } @@ -656,7 +659,7 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog) struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data; struct brw_vue_map vue_map; - if (brw->gen < 6) { + if (devinfo->gen < 6) { brw_compute_vue_map(&brw->screen->devinfo, &vue_map, prog->info.inputs_read | VARYING_BIT_POS, false); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 9b1cbaf747c..367bde3a0be 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -207,6 +207,7 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, unsigned unit, uint32_t surf_index) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; @@ -236,7 +237,7 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, uint32_t offset; brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, - rb_mocs[brw->gen], + rb_mocs[devinfo->gen], &offset, surf_index, RELOC_WRITE); return offset; @@ -457,6 +458,7 @@ brw_update_texture_surface(struct gl_context *ctx, uint32_t plane) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current; if (obj->Target == GL_TEXTURE_BUFFER) { @@ -503,12 +505,12 @@ brw_update_texture_surface(struct gl_context *ctx, /* Implement gen6 and gen7 gather work-around */ bool need_green_to_blue = false; if (for_gather) { - if (brw->gen == 7 && (format == ISL_FORMAT_R32G32_FLOAT || - format == ISL_FORMAT_R32G32_SINT || - format == ISL_FORMAT_R32G32_UINT)) { + if (devinfo->gen == 7 && (format == ISL_FORMAT_R32G32_FLOAT || + format == ISL_FORMAT_R32G32_SINT || + format == ISL_FORMAT_R32G32_UINT)) { format = ISL_FORMAT_R32G32_FLOAT_LD; need_green_to_blue = brw->is_haswell; - } else if (brw->gen == 6) { + } else if (devinfo->gen == 6) { /* Sandybridge's gather4 message is broken for integer formats. * To work around this, we pretend the surface is UNORM for * 8 or 16-bit formats, and emit shader instructions to recover @@ -539,14 +541,14 @@ brw_update_texture_surface(struct gl_context *ctx, } if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) { - if (brw->gen <= 7) { + if (devinfo->gen <= 7) { assert(mt->r8stencil_mt && !mt->stencil_mt->r8stencil_needs_update); mt = mt->r8stencil_mt; } else { mt = mt->stencil_mt; } format = ISL_FORMAT_R8_UINT; - } else if (brw->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) { + } else if (devinfo->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) { assert(mt->r8stencil_mt && !mt->r8stencil_needs_update); mt = mt->r8stencil_mt; format = ISL_FORMAT_R8_UINT; @@ -580,7 +582,7 @@ brw_update_texture_surface(struct gl_context *ctx, aux_usage = ISL_AUX_USAGE_NONE; brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, - tex_mocs[brw->gen], + tex_mocs[devinfo->gen], surf_offset, surf_index, 0); } @@ -596,6 +598,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw, unsigned pitch, unsigned reloc_flags) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t *dw = brw_state_batch(brw, brw->isl_dev.ss.size, brw->isl_dev.ss.align, @@ -610,7 +613,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw, .size = buffer_size, .format = surface_format, .stride = pitch, - .mocs = tex_mocs[brw->gen]); + .mocs = tex_mocs[devinfo->gen]); } void @@ -827,6 +830,7 @@ emit_null_surface_state(struct brw_context *brw, const struct gl_framebuffer *fb, uint32_t *out_offset) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t *surf = brw_state_batch(brw, brw->isl_dev.ss.size, brw->isl_dev.ss.align, @@ -837,7 +841,7 @@ emit_null_surface_state(struct brw_context *brw, const unsigned height = fb ? _mesa_geometric_height(fb) : 1; const unsigned samples = fb ? _mesa_geometric_samples(fb) : 1; - if (brw->gen != 6 || samples <= 1) { + if (devinfo->gen != 6 || samples <= 1) { isl_null_fill_state(&brw->isl_dev, surf, isl_extent3d(width, height, 1)); return; @@ -894,6 +898,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, unsigned unit, uint32_t surf_index) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; @@ -960,7 +965,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, (mt->surf.image_alignment_el.height == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); - if (brw->gen < 6) { + if (devinfo->gen < 6) { /* _NEW_COLOR */ if (!ctx->Color.ColorLogicOpEnabled && !ctx->Color._AdvancedBlendMode && (ctx->Color.BlendEnabled & (1 << unit))) @@ -988,6 +993,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, static void update_renderbuffer_surfaces(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct gl_context *ctx = &brw->ctx; /* _NEW_BUFFERS | _NEW_COLOR */ @@ -1004,7 +1010,7 @@ update_renderbuffer_surfaces(struct brw_context *brw) struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i]; if (intel_renderbuffer(rb)) { - surf_offsets[rt_start + i] = brw->gen >= 6 ? + surf_offsets[rt_start + i] = devinfo->gen >= 6 ? gen6_update_renderbuffer_surface(brw, rb, i, rt_start + i) : gen4_update_renderbuffer_surface(brw, rb, i, rt_start + i); } else { @@ -1039,6 +1045,7 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces = { static void update_renderbuffer_read_surfaces(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct gl_context *ctx = &brw->ctx; /* BRW_NEW_FS_PROG_DATA */ @@ -1094,7 +1101,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) aux_usage = ISL_AUX_USAGE_NONE; brw_emit_surface_state(brw, irb->mt, target, view, aux_usage, - tex_mocs[brw->gen], + tex_mocs[devinfo->gen], surf_offset, surf_index, 0); @@ -1158,6 +1165,8 @@ update_stage_texture_surfaces(struct brw_context *brw, static void brw_update_texture_surfaces(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* BRW_NEW_VERTEX_PROGRAM */ struct gl_program *vs = (struct gl_program *) brw->vertex_program; @@ -1181,7 +1190,7 @@ brw_update_texture_surfaces(struct brw_context *brw) /* emit alternate set of surface state for gather. this * allows the surface format to be overriden for only the * gather4 messages. */ - if (brw->gen < 8) { + if (devinfo->gen < 8) { if (vs && vs->nir->info.uses_texture_gather) update_stage_texture_surfaces(brw, vs, &brw->vs.base, true, 0); if (tcs && tcs->nir->info.uses_texture_gather) @@ -1224,6 +1233,8 @@ const struct brw_tracked_state brw_texture_surfaces = { static void brw_update_cs_texture_surfaces(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* BRW_NEW_COMPUTE_PROGRAM */ struct gl_program *cs = (struct gl_program *) brw->compute_program; @@ -1234,7 +1245,7 @@ brw_update_cs_texture_surfaces(struct brw_context *brw) * allows the surface format to be overriden for only the * gather4 messages. */ - if (brw->gen < 8) { + if (devinfo->gen < 8) { if (cs && cs->nir->info.uses_texture_gather) update_stage_texture_surfaces(brw, cs, &brw->cs.base, true, 0); } @@ -1532,6 +1543,8 @@ update_image_surface(struct brw_context *brw, uint32_t *surf_offset, struct brw_image_param *param) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (_mesa_is_image_unit_valid(&brw->ctx, u)) { struct gl_texture_object *obj = u->TexObj; const unsigned format = get_image_format(brw, u->_ActualFormat, access); @@ -1578,7 +1591,7 @@ update_image_surface(struct brw_context *brw, view.base_array_layer, view.array_len)); brw_emit_surface_state(brw, mt, mt->target, view, - ISL_AUX_USAGE_NONE, tex_mocs[brw->gen], + ISL_AUX_USAGE_NONE, tex_mocs[devinfo->gen], surf_offset, surf_index, access == GL_READ_ONLY ? 0 : RELOC_WRITE); } diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c b/src/mesa/drivers/dri/i965/gen6_constant_state.c index dd4e224aada..46813826eb6 100644 --- a/src/mesa/drivers/dri/i965/gen6_constant_state.c +++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c @@ -49,6 +49,7 @@ gen6_upload_push_constants(struct brw_context *brw, const struct brw_stage_prog_data *prog_data, struct brw_stage_state *stage_state) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; if (prog_data->nr_params == 0) { @@ -64,7 +65,7 @@ gen6_upload_push_constants(struct brw_context *brw, int i; const int size = prog_data->nr_params * sizeof(gl_constant_value); gl_constant_value *param; - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { param = intel_upload_space(brw, size, 32, &stage_state->push_const_bo, &stage_state->push_const_offset); diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index 8e639cfeef4..357f041d3f5 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -80,9 +80,11 @@ static void write_primitives_generated(struct brw_context *brw, struct brw_bo *query_bo, int stream, int idx) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + brw_emit_mi_flush(brw); - if (brw->gen >= 7 && stream > 0) { + if (devinfo->gen >= 7 && stream > 0) { brw_store_register_mem64(brw, query_bo, GEN7_SO_PRIM_STORAGE_NEEDED(stream), idx * sizeof(uint64_t)); @@ -96,9 +98,11 @@ static void write_xfb_primitives_written(struct brw_context *brw, struct brw_bo *bo, int stream, int idx) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + brw_emit_mi_flush(brw); - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream), idx * sizeof(uint64_t)); } else { @@ -113,6 +117,7 @@ write_xfb_overflow_streams(struct gl_context *ctx, int idx) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; brw_emit_mi_flush(brw); @@ -120,7 +125,7 @@ write_xfb_overflow_streams(struct gl_context *ctx, int w_idx = 4 * i + idx; int g_idx = 4 * i + idx + 2; - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream + i), g_idx * sizeof(uint64_t)); @@ -168,6 +173,8 @@ static void emit_pipeline_stat(struct brw_context *brw, struct brw_bo *bo, int stream, int target, int idx) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* One source of confusion is the tessellation shader statistics. The * hardware has no statistics specific to the TE unit. Ideally we could have * the HS primitives for TESS_CONTROL_SHADER_PATCHES_ARB, and the DS @@ -196,7 +203,7 @@ emit_pipeline_stat(struct brw_context *brw, struct brw_bo *bo, /* Gen6 GS code counts full primitives, that is, it won't count individual * triangles in a triangle strip. Use CL_INVOCATION_COUNT for that. */ - if (brw->gen == 6 && target == GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB) + if (devinfo->gen == 6 && target == GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB) reg = CL_INVOCATION_COUNT; assert(reg != 0); @@ -217,6 +224,7 @@ gen6_queryobj_get_results(struct gl_context *ctx, struct brw_query_object *query) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; if (query->bo == NULL) return; @@ -289,7 +297,7 @@ gen6_queryobj_get_results(struct gl_context *ctx, * and correctly emitted the number of pixel shader invocations, but, * whomever forgot to undo the multiply by 4. */ - if (brw->gen == 8 || brw->is_haswell) + if (devinfo->gen == 8 || brw->is_haswell) query->Base.Result /= 4; break; diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c index b4824b67e5b..d350e77dc99 100644 --- a/src/mesa/drivers/dri/i965/gen6_sol.c +++ b/src/mesa/drivers/dri/i965/gen6_sol.c @@ -280,6 +280,7 @@ void brw_save_primitives_written_counters(struct brw_context *brw, struct brw_transform_feedback_object *obj) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct gl_context *ctx = &brw->ctx; const int streams = ctx->Const.MaxVertexStreams; @@ -295,7 +296,7 @@ brw_save_primitives_written_counters(struct brw_context *brw, brw_emit_mi_flush(brw); /* Emit MI_STORE_REGISTER_MEM commands to write the values. */ - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { for (int i = 0; i < streams; i++) { int offset = (obj->prim_count_buffer_index + i) * sizeof(uint64_t); brw_store_register_mem64(brw, obj->prim_count_bo, @@ -384,6 +385,7 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, struct gl_transform_feedback_object *obj) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; const struct gl_program *prog; const struct gl_transform_feedback_info *linked_xfb_info; struct gl_transform_feedback_object *xfb_obj = @@ -391,7 +393,7 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, struct brw_transform_feedback_object *brw_obj = (struct brw_transform_feedback_object *) xfb_obj; - assert(brw->gen == 6); + assert(devinfo->gen == 6); if (ctx->_Shader->CurrentProgram[MESA_SHADER_GEOMETRY]) { /* BRW_NEW_GEOMETRY_PROGRAM */ diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 53638eb9b83..467f325076c 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -69,6 +69,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw) static void setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL]; const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] || cfg->n[GEN_L3P_ALL]; @@ -116,7 +117,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_CS_STALL); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]); BEGIN_BATCH(3); diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c index 161e03460bf..7d20c267565 100644 --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c @@ -42,8 +42,9 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, struct brw_context *brw = brw_context(ctx); struct brw_transform_feedback_object *brw_obj = (struct brw_transform_feedback_object *) obj; + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen == 7); + assert(devinfo->gen == 7); /* We're about to lose the information needed to compute the number of * vertices written during the last Begin/EndTransformFeedback section, @@ -109,11 +110,12 @@ gen7_pause_transform_feedback(struct gl_context *ctx, struct brw_context *brw = brw_context(ctx); struct brw_transform_feedback_object *brw_obj = (struct brw_transform_feedback_object *) obj; + const struct gen_device_info *devinfo = &brw->screen->devinfo; /* Flush any drawing so that the counters have the right values. */ brw_emit_mi_flush(brw); - assert(brw->gen == 7); + assert(devinfo->gen == 7); /* Save the SOL buffer offset register values. */ for (int i = 0; i < 4; i++) { @@ -139,8 +141,9 @@ gen7_resume_transform_feedback(struct gl_context *ctx, struct brw_context *brw = brw_context(ctx); struct brw_transform_feedback_object *brw_obj = (struct brw_transform_feedback_object *) obj; + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen == 7); + assert(devinfo->gen == 7); /* Reload the SOL buffer offset registers. */ for (int i = 0; i < 4; i++) { diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 06113fa572c..0373f3a3a5c 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -62,6 +62,8 @@ static void gen7_allocate_push_constants(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* BRW_NEW_GEOMETRY_PROGRAM */ bool gs_present = brw->geometry_program; @@ -70,7 +72,7 @@ gen7_allocate_push_constants(struct brw_context *brw) unsigned avail_size = 16; unsigned multiplier = - (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 2 : 1; + (devinfo->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 2 : 1; int stages = 2 + gs_present + 2 * tess_present; @@ -113,6 +115,7 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, unsigned hs_size, unsigned ds_size, unsigned gs_size, unsigned fs_size) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; unsigned offset = 0; BEGIN_BATCH(10); @@ -143,7 +146,7 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, * * No such restriction exists for Haswell or Baytrail. */ - if (brw->gen < 8 && !brw->is_haswell && !brw->is_baytrail) + if (devinfo->gen < 8 && !brw->is_haswell && !brw->is_baytrail) gen7_emit_cs_stall_flush(brw); } @@ -178,7 +181,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, { const struct gen_device_info *devinfo = &brw->screen->devinfo; const int push_size_kB = - (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16; + (devinfo->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16; /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */ struct brw_vue_prog_data *prog_data[4] = { @@ -221,12 +224,12 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, gen_get_urb_config(devinfo, 1024 * push_size_kB, 1024 * brw->urb.size, tess_present, gs_present, entry_size, entries, start); - if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail) + if (devinfo->gen == 7 && !brw->is_haswell && !brw->is_baytrail) gen7_emit_vs_workaround_flush(brw); BEGIN_BATCH(8); for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { - assert(brw->gen != 10 || entry_size[i] % 3); + assert(devinfo->gen != 10 || entry_size[i] % 3); OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2)); OUT_BATCH(entries[i] | ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) | diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index d94ca0b6bea..34e1ed15414 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -49,7 +49,8 @@ emit_depth_packets(struct brw_context *brw, uint32_t lod, uint32_t min_array_element) { - uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; /* Skip repeated NULL depth/stencil emits (think 2D rendering). */ if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) { @@ -138,6 +139,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t width, uint32_t height, uint32_t tile_x, uint32_t tile_y) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct gl_framebuffer *fb = ctx->DrawBuffer; uint32_t surftype; @@ -178,7 +180,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw, break; case GL_TEXTURE_1D_ARRAY: case GL_TEXTURE_1D: - if (brw->gen >= 9) { + if (devinfo->gen >= 9) { /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth * textures but it does allow pretending it's a 2D texture * instead. @@ -349,9 +351,10 @@ gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits) static void gen8_emit_pma_stall_workaround(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t bits = 0; - if (brw->gen >= 9) + if (devinfo->gen >= 9) return; if (pma_fix_enable(brw)) diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c index 9dc3b3de865..fde0bce7152 100644 --- a/src/mesa/drivers/dri/i965/hsw_queryobj.c +++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c @@ -273,6 +273,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query, GLenum pname, GLenum ptype) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; assert(query->bo); assert(pname != GL_QUERY_TARGET); @@ -338,7 +339,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query, * and correctly emitted the number of pixel shader invocations, but, * whomever forgot to undo the multiply by 4. */ - if (brw->gen == 8 || brw->is_haswell) + if (devinfo->gen == 8 || brw->is_haswell) shr_gpr0_by_2_bits(brw); break; case GL_TIME_ELAPSED: @@ -410,9 +411,10 @@ store_query_result_reg(struct brw_context *brw, struct brw_bo *bo, uint32_t offset, GLenum ptype, uint32_t reg, const bool pipelined) { - uint32_t cmd_size = brw->gen >= 8 ? 4 : 3; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + uint32_t cmd_size = devinfo->gen >= 8 ? 4 : 3; uint32_t dwords = (ptype == GL_INT || ptype == GL_UNSIGNED_INT) ? 1 : 2; - assert(brw->gen >= 6); + assert(devinfo->gen >= 6); BEGIN_BATCH(dwords * cmd_size); for (int i = 0; i < dwords; i++) { @@ -420,7 +422,7 @@ store_query_result_reg(struct brw_context *brw, struct brw_bo *bo, (pipelined ? MI_STORE_REGISTER_MEM_PREDICATE : 0) | (cmd_size - 2)); OUT_BATCH(reg + 4 * i); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { OUT_RELOC64(bo, RELOC_WRITE, offset + 4 * i); } else { OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, offset + 4 * i); diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c b/src/mesa/drivers/dri/i965/hsw_sol.c index 9f6952c6bfc..c14efd571d6 100644 --- a/src/mesa/drivers/dri/i965/hsw_sol.c +++ b/src/mesa/drivers/dri/i965/hsw_sol.c @@ -161,11 +161,12 @@ hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, struct brw_context *brw = brw_context(ctx); struct brw_transform_feedback_object *brw_obj = (struct brw_transform_feedback_object *) obj; + const struct gen_device_info *devinfo = &brw->screen->devinfo; brw_obj->primitive_mode = mode; /* Reset the SO buffer offsets to 0. */ - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { brw_obj->zero_offsets = true; } else { BEGIN_BATCH(1 + 2 * BRW_MAX_XFB_STREAMS); diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index dc92e6e7bb1..fddb96016b6 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -231,9 +231,11 @@ void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz, enum brw_gpu_ring ring) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* If we're switching rings, implicitly flush the batch. */ if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING && - brw->gen >= 6) { + devinfo->gen >= 6) { intel_batchbuffer_flush(brw); } @@ -290,6 +292,7 @@ decode_structs(struct brw_context *brw, struct gen_spec *spec, static void do_batch_dump(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct intel_batchbuffer *batch = &brw->batch; struct gen_spec *spec = gen_spec_load(&brw->screen->devinfo); @@ -407,10 +410,10 @@ do_batch_dump(struct brw_context *brw) gtt_offset, p[1] & ~0x3fu, 8 * 4, color); break; case _3DSTATE_CC_STATE_POINTERS: - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { decode_struct(brw, spec, "COLOR_CALC_STATE", data, gtt_offset, p[1] & ~0x3fu, color); - } else if (brw->gen == 6) { + } else if (devinfo->gen == 6) { decode_structs(brw, spec, "BLEND_STATE", data, gtt_offset, p[1] & ~0x3fu, 2 * 4, color); decode_struct(brw, spec, "DEPTH_STENCIL_STATE", data, @@ -488,6 +491,8 @@ brw_new_batch(struct brw_context *brw) static void brw_finish_batch(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* Capture the closing pipeline statistics register values necessary to * support query objects (in the non-hardware context world). */ @@ -498,7 +503,7 @@ brw_finish_batch(struct brw_context *brw) * assume that the L3 cache is configured according to the hardware * defaults. */ - if (brw->gen >= 7) + if (devinfo->gen >= 7) gen7_restore_default_l3_config(brw); if (brw->is_haswell) { @@ -624,6 +629,7 @@ execbuffer(int fd, static int do_flush_locked(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; __DRIscreen *dri_screen = brw->screen->driScrnPriv; struct intel_batchbuffer *batch = &brw->batch; int ret = 0; @@ -655,7 +661,7 @@ do_flush_locked(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) */ int flags = I915_EXEC_NO_RELOC; - if (brw->gen >= 6 && batch->ring == BLT_RING) { + if (devinfo->gen >= 6 && batch->ring == BLT_RING) { flags |= I915_EXEC_BLT; } else { flags |= I915_EXEC_RENDER; @@ -845,12 +851,13 @@ load_sized_register_mem(struct brw_context *brw, uint32_t offset, int size) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; int i; /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */ - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { BEGIN_BATCH(4 * size); for (i = 0; i < size; i++) { OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2)); @@ -894,9 +901,11 @@ void brw_store_register_mem32(struct brw_context *brw, struct brw_bo *bo, uint32_t reg, uint32_t offset) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { BEGIN_BATCH(4); OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); OUT_BATCH(reg); @@ -918,12 +927,14 @@ void brw_store_register_mem64(struct brw_context *brw, struct brw_bo *bo, uint32_t reg, uint32_t offset) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to * read a full 64-bit register, we need to do two of them. */ - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { BEGIN_BATCH(8); OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); OUT_BATCH(reg); @@ -950,7 +961,9 @@ brw_store_register_mem64(struct brw_context *brw, void brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); @@ -965,7 +978,9 @@ brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) void brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); BEGIN_BATCH(5); OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2)); @@ -982,7 +997,9 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm) void brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest) { - assert(brw->gen >= 8 || brw->is_haswell); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 8 || brw->is_haswell); BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); @@ -997,7 +1014,9 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest) void brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest) { - assert(brw->gen >= 8 || brw->is_haswell); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 8 || brw->is_haswell); BEGIN_BATCH(6); OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); @@ -1016,11 +1035,13 @@ void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo, uint32_t offset, uint32_t imm) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); BEGIN_BATCH(4); OUT_BATCH(MI_STORE_DATA_IMM | (4 - 2)); - if (brw->gen >= 8) + if (devinfo->gen >= 8) OUT_RELOC64(bo, RELOC_WRITE, offset); else { OUT_BATCH(0); /* MBZ */ @@ -1037,11 +1058,13 @@ void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo, uint32_t offset, uint64_t imm) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); BEGIN_BATCH(5); OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2)); - if (brw->gen >= 8) + if (devinfo->gen >= 8) OUT_RELOC64(bo, 0, offset); else { OUT_BATCH(0); /* MBZ */ diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 1da37ed7305..819a3da2966 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -101,7 +101,9 @@ set_blitter_tiling(struct brw_context *brw, bool dst_y_tiled, bool src_y_tiled, uint32_t *__map) { - assert(brw->gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 6); /* Idle the blitter before we update how tiling is interpreted. */ OUT_BATCH(MI_FLUSH_DW); @@ -331,7 +333,7 @@ intel_miptree_blit(struct brw_context *brw, const unsigned h0 = src_mt->surf.phys_level0_sa.height; src_y = minify(h0, src_level - src_mt->first_level) - src_y - height; } - + if (dst_flip) { const unsigned h0 = dst_mt->surf.phys_level0_sa.height; dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height; @@ -445,12 +447,14 @@ static bool alignment_valid(struct brw_context *brw, unsigned offset, enum isl_tiling tiling) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* Tiled buffers must be page-aligned (4K). */ if (tiling != ISL_TILING_LINEAR) return (offset & 4095) == 0; /* On Gen8+, linear buffers must be cacheline-aligned. */ - if (brw->gen >= 8) + if (devinfo->gen >= 8) return (offset & 63) == 0; return true; @@ -502,6 +506,7 @@ intelEmitCopyBlit(struct brw_context *brw, GLshort w, GLshort h, GLenum logic_op) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; GLuint CMD, BR13; int dst_y2 = dst_y + h; int dst_x2 = dst_x + w; @@ -510,7 +515,7 @@ intelEmitCopyBlit(struct brw_context *brw, uint32_t src_tile_w, src_tile_h; uint32_t dst_tile_w, dst_tile_h; - if ((dst_y_tiled || src_y_tiled) && brw->gen < 6) + if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6) return false; const unsigned bo_sizes = dst_buffer->size + src_buffer->size; @@ -522,7 +527,7 @@ intelEmitCopyBlit(struct brw_context *brw, if (!brw_batch_has_aperture_space(brw, bo_sizes)) return false; - unsigned length = brw->gen >= 8 ? 10 : 8; + unsigned length = devinfo->gen >= 8 ? 10 : 8; intel_batchbuffer_require_space(brw, length * 4, BLT_RING); DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", @@ -595,14 +600,14 @@ intelEmitCopyBlit(struct brw_context *brw, OUT_BATCH(BR13 | (uint16_t)dst_pitch); OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X)); OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X)); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset); } else { OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset); } OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X)); OUT_BATCH((uint16_t)src_pitch); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { OUT_RELOC64(src_buffer, 0, src_offset); } else { OUT_RELOC(src_buffer, 0, src_offset); @@ -628,6 +633,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, GLshort w, GLshort h, GLenum logic_op) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13, blit_cmd; @@ -648,7 +654,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, __func__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); - unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8; + unsigned xy_setup_blt_length = devinfo->gen >= 8 ? 10 : 8; intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) + (3 * 4) + dwords * 4, BLT_RING); @@ -672,7 +678,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset); } else { OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset); @@ -680,7 +686,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ - if (brw->gen >= 8) + if (devinfo->gen >= 8) OUT_BATCH(0); OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); @@ -764,6 +770,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, struct intel_mipmap_tree *mt, int x, int y, int width, int height) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t BR13, CMD; int pitch, cpp; @@ -787,7 +794,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, if (!brw_batch_has_aperture_space(brw, mt->bo->size)) intel_batchbuffer_flush(brw); - unsigned length = brw->gen >= 8 ? 7 : 6; + unsigned length = devinfo->gen >= 8 ? 7 : 6; const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0; /* We need to split the blit into chunks that each fit within the blitter's @@ -815,7 +822,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, SET_FIELD(x + chunk_x, BLT_X)); OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) | SET_FIELD(x + chunk_x + chunk_w, BLT_X)); - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset); } else { OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset); diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c b/src/mesa/drivers/dri/i965/intel_copy_image.c index 2ebd8d7528b..00593235d1e 100644 --- a/src/mesa/drivers/dri/i965/intel_copy_image.c +++ b/src/mesa/drivers/dri/i965/intel_copy_image.c @@ -42,7 +42,9 @@ copy_miptrees(struct brw_context *brw, int dst_x, int dst_y, int dst_z, unsigned dst_level, int src_width, int src_height) { - if (brw->gen <= 5) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen <= 5) { /* On gen4-5, try BLT first. * * Gen4-5 have a single ring for both 3D and BLT operations, so there's diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index deacd0d9dfc..918e1b6496a 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -37,8 +37,9 @@ void intelInitExtensions(struct gl_context *ctx) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; - assert(brw->gen >= 4); + assert(devinfo->gen >= 4); ctx->Extensions.ARB_arrays_of_arrays = true; ctx->Extensions.ARB_buffer_storage = true; @@ -135,13 +136,13 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.OES_texture_half_float = true; ctx->Extensions.OES_texture_half_float_linear = true; - if (brw->gen >= 8) + if (devinfo->gen >= 8) ctx->Const.GLSLVersion = 450; else if (brw->is_haswell && can_do_pipelined_register_writes(brw->screen)) ctx->Const.GLSLVersion = 450; - else if (brw->gen >= 7 && can_do_pipelined_register_writes(brw->screen)) + else if (devinfo->gen >= 7 && can_do_pipelined_register_writes(brw->screen)) ctx->Const.GLSLVersion = 420; - else if (brw->gen >= 6) + else if (devinfo->gen >= 6) ctx->Const.GLSLVersion = 330; else ctx->Const.GLSLVersion = 120; @@ -150,21 +151,21 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130; ctx->Extensions.MESA_shader_integer_functions = ctx->Const.GLSLVersion >= 130; - if (brw->is_g4x || brw->gen >= 5) { + if (brw->is_g4x || devinfo->gen >= 5) { ctx->Extensions.MESA_shader_framebuffer_fetch_non_coherent = true; ctx->Extensions.KHR_blend_equation_advanced = true; } - if (brw->gen >= 5) { + if (devinfo->gen >= 5) { ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130; ctx->Extensions.ARB_texture_query_lod = true; ctx->Extensions.EXT_timer_query = true; } - if (brw->gen == 6) + if (devinfo->gen == 6) ctx->Extensions.ARB_transform_feedback2 = true; - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended"); ctx->Extensions.ARB_conditional_render_inverted = true; @@ -206,7 +207,7 @@ intelInitExtensions(struct gl_context *ctx) brw->predicate.supported = false; - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { ctx->Extensions.ARB_conservative_depth = true; ctx->Extensions.ARB_derivative_control = true; ctx->Extensions.ARB_framebuffer_no_attachments = true; @@ -238,7 +239,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) { ctx->Extensions.ARB_compute_shader = true; ctx->Extensions.ARB_ES3_1_compatibility = - brw->gen >= 8 || brw->is_haswell; + devinfo->gen >= 8 || brw->is_haswell; } if (can_do_predicate_writes(brw->screen)) @@ -246,7 +247,7 @@ intelInitExtensions(struct gl_context *ctx) } } - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { ctx->Extensions.ARB_stencil_texturing = true; ctx->Extensions.ARB_texture_stencil8 = true; ctx->Extensions.OES_geometry_shader = true; @@ -254,7 +255,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.OES_viewport_array = true; } - if (brw->gen >= 8 || brw->is_haswell || brw->is_baytrail) { + if (devinfo->gen >= 8 || brw->is_haswell || brw->is_baytrail) { ctx->Extensions.ARB_robust_buffer_access_behavior = true; } @@ -262,7 +263,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_query_buffer_object = true; } - if (brw->gen >= 8 || brw->is_baytrail) { + if (devinfo->gen >= 8 || brw->is_baytrail) { /* For now, we only enable OES_copy_image on platforms that support * ETC2 natively in hardware. We would need more hacks to support it * elsewhere. @@ -270,13 +271,13 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.OES_copy_image = true; } - if (brw->gen >= 8) { + if (devinfo->gen >= 8) { ctx->Extensions.ARB_gpu_shader_int64 = true; ctx->Extensions.ARB_shader_ballot = true; /* requires ARB_gpu_shader_int64 */ ctx->Extensions.ARB_ES3_2_compatibility = true; } - if (brw->gen >= 9) { + if (devinfo->gen >= 9) { ctx->Extensions.ANDROID_extension_pack_es31a = true; ctx->Extensions.ARB_shader_stencil_export = true; ctx->Extensions.KHR_blend_equation_advanced_coherent = true; @@ -290,7 +291,7 @@ intelInitExtensions(struct gl_context *ctx) if (brw->is_broxton) ctx->Extensions.KHR_texture_compression_astc_hdr = true; - if (brw->gen >= 6) + if (devinfo->gen >= 6) ctx->Extensions.INTEL_performance_query = true; if (ctx->API == API_OPENGL_CORE) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index ca80b962956..048d72dad8e 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -634,6 +634,7 @@ static void intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct intel_renderbuffer *depthRb = intel_get_renderbuffer(fb, BUFFER_DEPTH); struct intel_renderbuffer *stencilRb = @@ -654,7 +655,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) } if (depth_mt && stencil_mt) { - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { const unsigned d_width = depth_mt->surf.phys_level0_sa.width; const unsigned d_height = depth_mt->surf.phys_level0_sa.height; const unsigned d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ? @@ -707,7 +708,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) "instead of S8\n", _mesa_get_format_name(stencil_mt->format)); } - if (brw->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) { + if (devinfo->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) { /* Before Gen7, separate depth and stencil buffers can be used * only if HiZ is enabled. From the Sandybridge PRM, Volume 2, * Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable: @@ -869,6 +870,7 @@ intel_blit_framebuffer(struct gl_context *ctx, GLbitfield mask, GLenum filter) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; /* Page 679 of OpenGL 4.4 spec says: * "Added BlitFramebuffer to commands affected by conditional rendering in @@ -877,7 +879,7 @@ intel_blit_framebuffer(struct gl_context *ctx, if (!_mesa_check_conditional_render(ctx)) return; - if (brw->gen < 6) { + if (devinfo->gen < 6) { /* On gen4-5, try BLT first. * * Gen4-5 have a single ring for both 3D and BLT operations, so there's @@ -907,7 +909,7 @@ intel_blit_framebuffer(struct gl_context *ctx, if (mask == 0x0) return; - if (brw->gen >= 8 && (mask & GL_STENCIL_BUFFER_BIT)) { + if (devinfo->gen >= 8 && (mask & GL_STENCIL_BUFFER_BIT)) { assert(!"Invalid blit"); } @@ -997,10 +999,12 @@ brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo) void brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (!_mesa_set_search(brw->render_cache, bo)) return; - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 3fd5af4e3b5..4af16e9fe2f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -63,12 +63,14 @@ static bool intel_miptree_supports_mcs(struct brw_context *brw, const struct intel_mipmap_tree *mt) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* MCS compression only applies to multisampled miptrees */ if (mt->surf.samples <= 1) return false; /* Prior to Gen7, all MSAA surfaces used IMS layout. */ - if (brw->gen < 7) + if (devinfo->gen < 7) return false; /* In Gen7, IMS layout is only used for depth and stencil buffers. */ @@ -89,7 +91,7 @@ intel_miptree_supports_mcs(struct brw_context *brw, * would require converting between CMS and UMS MSAA layouts on the fly, * which is expensive. */ - if (brw->gen == 7 && _mesa_get_format_datatype(mt->format) == GL_INT) { + if (devinfo->gen == 7 && _mesa_get_format_datatype(mt->format) == GL_INT) { return false; } else { return true; @@ -101,6 +103,8 @@ static bool intel_tiling_supports_ccs(const struct brw_context *brw, enum isl_tiling tiling) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render * Target(s)", beneath the "Fast Color Clear" bullet (p326): * @@ -108,9 +112,9 @@ intel_tiling_supports_ccs(const struct brw_context *brw, * * Gen9 changes the restriction to Y-tile only. */ - if (brw->gen >= 9) + if (devinfo->gen >= 9) return tiling == ISL_TILING_Y0; - else if (brw->gen >= 7) + else if (devinfo->gen >= 7) return tiling != ISL_TILING_LINEAR; else return false; @@ -141,8 +145,10 @@ static bool intel_miptree_supports_ccs(struct brw_context *brw, const struct intel_mipmap_tree *mt) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* MCS support does not exist prior to Gen7 */ - if (brw->gen < 7) + if (devinfo->gen < 7) return false; /* This function applies only to non-multisampled render targets. */ @@ -192,7 +198,7 @@ intel_miptree_supports_ccs(struct brw_context *brw, * surfaces are supported with MCS buffer layout with these alignments in * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64. */ - if (brw->gen < 8 && (mip_mapped || arrayed)) + if (devinfo->gen < 8 && (mip_mapped || arrayed)) return false; /* There's no point in using an MCS buffer if the surface isn't in a @@ -208,7 +214,9 @@ static bool intel_tiling_supports_hiz(const struct brw_context *brw, enum isl_tiling tiling) { - if (brw->gen < 6) + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen < 6) return false; return tiling == ISL_TILING_Y0; @@ -237,7 +245,9 @@ static bool intel_miptree_supports_ccs_e(struct brw_context *brw, const struct intel_mipmap_tree *mt) { - if (brw->gen < 9) + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + if (devinfo->gen < 9) return false; /* For now compression is only enabled for integer formats even though @@ -356,10 +366,12 @@ intel_miptree_choose_aux_usage(struct brw_context *brw, mesa_format intel_lower_compressed_format(struct brw_context *brw, mesa_format format) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* No need to lower ETC formats on these platforms, * they are supported natively. */ - if (brw->gen >= 8 || brw->is_baytrail) + if (devinfo->gen >= 8 || brw->is_baytrail) return format; switch (format) { @@ -495,11 +507,13 @@ static bool need_to_retile_as_x(const struct brw_context *brw, uint64_t size, enum isl_tiling tiling) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* If the BO is too large to fit in the aperture, we need to use the * BLT engine to support it. Prior to Sandybridge, the BLT paths can't * handle Y-tiling, so we need to fall back to X. */ - if (brw->gen < 6 && size >= brw->max_gtt_map_object_size && + if (devinfo->gen < 6 && size >= brw->max_gtt_map_object_size && tiling == ISL_TILING_Y0) return true; @@ -547,7 +561,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, .array_len = target == GL_TEXTURE_3D ? 1 : depth0, .samples = num_samples, .row_pitch = row_pitch, - .usage = isl_usage_flags, + .usage = isl_usage_flags, .tiling_flags = tiling_flags, }; @@ -624,7 +638,7 @@ make_separate_stencil_surface(struct brw_context *brw, if (!mt->stencil_mt) return false; - + mt->stencil_mt->r8stencil_needs_update = true; return true; @@ -642,6 +656,8 @@ miptree_create(struct brw_context *brw, GLuint num_samples, enum intel_miptree_create_flags flags) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (format == MESA_FORMAT_S_UINT8) return make_surface(brw, target, format, first_level, last_level, width0, height0, depth0, num_samples, @@ -662,7 +678,7 @@ miptree_create(struct brw_context *brw, const mesa_format depth_only_format = intel_depth_format_for_depthstencil_format(format); struct intel_mipmap_tree *mt = make_surface( - brw, target, brw->gen >= 6 ? depth_only_format : format, + brw, target, devinfo->gen >= 6 ? depth_only_format : format, first_level, last_level, width0, height0, depth0, num_samples, ISL_TILING_Y0_BIT, ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT, @@ -695,7 +711,7 @@ miptree_create(struct brw_context *brw, ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK; /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */ - if (brw->gen < 6) + if (devinfo->gen < 6) tiling_flags &= ~ISL_TILING_Y0_BIT; struct intel_mipmap_tree *mt = make_surface( @@ -760,6 +776,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, int pitch, enum intel_miptree_create_flags flags) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct intel_mipmap_tree *mt; uint32_t tiling, swizzle; const GLenum target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D; @@ -770,7 +787,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, const mesa_format depth_only_format = intel_depth_format_for_depthstencil_format(format); mt = make_surface(brw, target, - brw->gen >= 6 ? depth_only_format : format, + devinfo->gen >= 6 ? depth_only_format : format, 0, 0, width, height, depth, 1, ISL_TILING_Y0_BIT, ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT, BO_ALLOC_BUSY, pitch, bo); @@ -1675,7 +1692,9 @@ intel_miptree_alloc_mcs(struct brw_context *brw, struct intel_mipmap_tree *mt, GLuint num_samples) { - assert(brw->gen >= 7); /* MCS only used on Gen7+ */ + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 7); /* MCS only used on Gen7+ */ assert(mt->mcs_buf == NULL); assert(mt->aux_usage == ISL_AUX_USAGE_MCS); @@ -1753,7 +1772,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw, free(aux_state); return false; } - + mt->aux_state = aux_state; return true; @@ -1769,10 +1788,12 @@ intel_miptree_level_enable_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + assert(mt->hiz_buf); assert(mt->surf.size > 0); - if (brw->gen >= 8 || brw->is_haswell) { + if (devinfo->gen >= 8 || brw->is_haswell) { uint32_t width = minify(mt->surf.phys_level0_sa.width, level); uint32_t height = minify(mt->surf.phys_level0_sa.height, level); @@ -1882,10 +1903,12 @@ bool intel_miptree_sample_with_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* It's unclear how well supported sampling from the hiz buffer is on GEN8, * so keep things conservative for now and never enable it unless we're SKL+. */ - if (brw->gen < 9) { + if (devinfo->gen < 9) { return false; } @@ -1996,12 +2019,13 @@ intel_miptree_check_color_resolve(const struct brw_context *brw, const struct intel_mipmap_tree *mt, unsigned level, unsigned layer) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; if (!mt->mcs_buf) return; /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */ - assert(brw->gen >= 8 || + assert(devinfo->gen >= 8 || (level == 0 && mt->first_level == 0 && mt->last_level == 0)); /* Compression of arrayed msaa surfaces is supported. */ @@ -2009,7 +2033,7 @@ intel_miptree_check_color_resolve(const struct brw_context *brw, return; /* Fast color clear is supported for non-msaa arrays only on Gen8+. */ - assert(brw->gen >= 8 || + assert(devinfo->gen >= 8 || (layer == 0 && mt->surf.logical_level0_px.depth == 1 && mt->surf.logical_level0_px.array_len == 1)); @@ -2944,16 +2968,18 @@ void intel_update_r8stencil(struct brw_context *brw, struct intel_mipmap_tree *mt) { - assert(brw->gen >= 7); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + assert(devinfo->gen >= 7); struct intel_mipmap_tree *src = mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt; - if (!src || brw->gen >= 8 || !src->r8stencil_needs_update) + if (!src || devinfo->gen >= 8 || !src->r8stencil_needs_update) return; assert(src->surf.size > 0); if (!mt->r8stencil_mt) { - assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */ + assert(devinfo->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */ mt->r8stencil_mt = make_surface( brw, src->target, @@ -3545,6 +3571,8 @@ use_intel_mipree_map_blit(struct brw_context *brw, unsigned int level, unsigned int slice) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (brw->has_llc && /* It's probably not worth swapping to the blit ring because of * all the overhead involved. @@ -3553,9 +3581,9 @@ use_intel_mipree_map_blit(struct brw_context *brw, !mt->compressed && (mt->surf.tiling == ISL_TILING_X || /* Prior to Sandybridge, the blitter can't handle Y tiling */ - (brw->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) || + (devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) || /* Fast copy blit on skl+ supports all tiling formats. */ - brw->gen >= 9) && + devinfo->gen >= 9) && can_blit_slice(mt, level, slice)) return true; diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index cd4fbab0972..c2ffb56c77a 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -73,6 +73,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, { struct brw_context *brw = brw_context(ctx); struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorReadBuffer; + const struct gen_device_info *devinfo = &brw->screen->devinfo; /* This path supports reading from color buffers only */ if (rb == NULL) @@ -141,7 +142,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, * parts of the memory aren't swizzled at all. Userspace just can't handle * that. */ - if (brw->gen < 5 && brw->has_swizzling) + if (devinfo->gen < 5 && brw->has_swizzling) return false; /* Since we are going to read raw data to the miptree, we need to resolve diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index 94a7ad3dcbf..eda209f69d1 100644 --- a/src/mesa/drivers/dri/i965/intel_tex.c +++ b/src/mesa/drivers/dri/i965/intel_tex.c @@ -367,8 +367,9 @@ static void intel_texture_barrier(struct gl_context *ctx) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 298a2565fb0..39c1c9a454a 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -36,7 +36,7 @@ * Choose the original base level dimension when shifted dimensions agree. * Otherwise assume real resize is intended and use the new shifted value. */ -static unsigned +static unsigned get_base_dim(unsigned old_base_dim, unsigned new_level_dim, unsigned level) { const unsigned old_level_dim = old_base_dim >> level; @@ -382,6 +382,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, const struct gl_pixelstore_attrib *packing) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct intel_texture_image *image = intel_texture_image(texImage); int dst_pitch; @@ -445,7 +446,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx, * parts of the memory aren't swizzled at all. Userspace just can't handle * that. */ - if (brw->gen < 5 && brw->has_swizzling) + if (devinfo->gen < 5 && brw->has_swizzling) return false; int level = texImage->Level + texImage->TexObject->MinLevel; @@ -624,7 +625,8 @@ intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims, bool is_linear_astc = _mesa_is_astc_format(gl_format) && !_mesa_is_srgb_format(gl_format); struct brw_context *brw = (struct brw_context*) ctx; - if (brw->gen == 9 && is_linear_astc) + const struct gen_device_info *devinfo = &brw->screen->devinfo; + if (devinfo->gen == 9 && is_linear_astc) flush_astc_denorms(ctx, dims, texImage, xoffset, yoffset, zoffset, width, height, depth); diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 5953e61ec22..42f24bec667 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -80,6 +80,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, bool for_glTexImage) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct intel_texture_image *image = intel_texture_image(texImage); int src_pitch; @@ -142,7 +143,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, * parts of the memory aren't swizzled at all. Userspace just can't handle * that. */ - if (brw->gen < 5 && brw->has_swizzling) + if (devinfo->gen < 5 && brw->has_swizzling) return false; int level = texImage->Level + texImage->TexObject->MinLevel; diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 16354d2b672..2136467db0d 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -67,6 +67,7 @@ intel_update_max_level(struct intel_texture_object *intelObj, void intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); @@ -111,7 +112,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) * * FINISHME: Avoid doing this. */ - assert(!tObj->Immutable || brw->gen < 6); + assert(!tObj->Immutable || devinfo->gen < 6); firstImage = intel_texture_image(tObj->Image[0][tObj->BaseLevel]); |