i965/wm: Surface state overrides for configuring w-tiled as y-tiled

v2: Use intel_mipmap_tree::total_width in order to get correct alignment
    automatically. Also use "mt->total_height / mt->physical_depth0" as
    surface height allowing hardware to offset to correct slice.

Cc: "10.2" <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

2 files changed, 30 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index b8e85202f0e..dbcf7c7cf87 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -206,6 +206,12 @@ void gen4_init_vtable_surface_functions(struct brw_context *brw);
 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 
+void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+                           bool is_render_target,
+                           unsigned *width, unsigned *height,
+                           unsigned *pitch, uint32_t *tiling,
+                           unsigned *format);
+
 uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
 
 GLuint translate_tex_target(GLenum target);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 054467c2ef9..c9d961491ae 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -101,6 +101,30 @@ brw_get_surface_num_multisamples(unsigned num_samples)
       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 }
 
+void
+brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+                      bool is_render_target,
+                      unsigned *width, unsigned *height,
+                      unsigned *pitch, uint32_t *tiling, unsigned *format)
+{
+   static const unsigned halign_stencil = 8;
+
+   /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
+    * there are half as many rows.
+    * In addition, mip-levels are accessed manually by the program and
+    * therefore the surface is setup to cover all the mip-levels for one slice.
+    * (Hardware is still used to access individual slices).
+    */
+   *tiling = I915_TILING_Y;
+   *pitch = mt->pitch * 2;
+   *width = ALIGN(mt->total_width, halign_stencil) * 2;
+   *height = (mt->total_height / mt->physical_depth0) / 2;
+
+   if (is_render_target) {
+      *format = BRW_SURFACEFORMAT_R8_UINT;
+   }
+}
+
 
 /**
  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle