diff options
author | Eric Anholt <[email protected]> | 2011-06-17 18:20:36 -0700 |
---|---|---|
committer | Eric Anholt <[email protected]> | 2011-06-20 08:37:43 -0700 |
commit | dfada714f8db3deea2fea3583c3c166a78db1117 (patch) | |
tree | 7c192cb7f1a98c7c0fa081b8d602ec6969e5c209 /src/mesa/drivers | |
parent | 8f9e8d79c8c180e4254d01c688969d6d45386891 (diff) |
i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.
This was spectacularly unsafe. On my system, address 0 happens to be
the hardware status page for the render ring, and the first quadword
of that happens to contain nothing we ever look at, but I sure didn't
look forward to having to debug some day when, for example, the kernel
happened to bind the ringbuffer before binding the hwsp.
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_batchbuffer.c | 20 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_batchbuffer.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.h | 3 |
4 files changed, 23 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 250102efaee..9e8f8b5eefd 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -53,6 +53,22 @@ static void clear_cache( struct intel_context *intel ) } void +intel_batchbuffer_init(struct intel_context *intel) +{ + intel_batchbuffer_reset(intel); + + if (intel->gen == 6) { + /* We can't just use brw_state_batch to get a chunk of space for + * the gen6 workaround because it involves actually writing to + * the buffer, and the kernel doesn't let us write to the batch. + */ + intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr, + "gen6 workaround", + 4096, 4096); + } +} + +void intel_batchbuffer_reset(struct intel_context *intel) { if (intel->batch.last_bo != NULL) { @@ -76,6 +92,7 @@ intel_batchbuffer_free(struct intel_context *intel) { drm_intel_bo_unreference(intel->batch.last_bo); drm_intel_bo_unreference(intel->batch.bo); + drm_intel_bo_unreference(intel->batch.workaround_bo); clear_cache(intel); } @@ -282,7 +299,8 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); - OUT_BATCH(0); /* write address */ + OUT_RELOC(intel->batch.workaround_bo, + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0); OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index a0a5c9841c6..3ed88d086d3 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -9,6 +9,7 @@ #define BATCH_RESERVED 16 +void intel_batchbuffer_init(struct intel_context *intel); void intel_batchbuffer_reset(struct intel_context *intel); void intel_batchbuffer_free(struct intel_context *intel); diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 0c2ba413ad7..820688e408b 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -854,7 +854,7 @@ intelInitContext(struct intel_context *intel, if (INTEL_DEBUG & DEBUG_BUFMGR) dri_bufmgr_set_debug(intel->bufmgr, GL_TRUE); - intel_batchbuffer_reset(intel); + intel_batchbuffer_init(intel); intel_fbo_init(intel); diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 80dee4ef38e..751af459e9c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -181,7 +181,8 @@ struct intel_context drm_intel_bo *bo; /** Last BO submitted to the hardware. Used for glFinish(). */ drm_intel_bo *last_bo; - + /** BO for post-sync nonzero writes for gen6 workaround. */ + drm_intel_bo *workaround_bo; struct cached_batch_item *cached_items; uint16_t emit, total; |