radeon/r200/r300: initial attempt to convert to common context code

46 files changed, 1067 insertions, 1226 deletions

diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index a426e7ad3fa..4f0275cc875 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -64,7 +64,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa )
 {
    int i, mtu;
 
-   mtu = rmesa->glCtx->Const.MaxTextureUnits;
+   mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
 
    make_empty_list(&rmesa->hw.atomlist);
    rmesa->hw.atomlist.name = "atom-list";
@@ -127,7 +127,7 @@ static void r200SaveHwState( r200ContextPtr rmesa )
    rmesa->backup_store.cmd_used = 0;
 
    foreach( atom, &rmesa->hw.atomlist ) {
-      if ( atom->check( rmesa->glCtx, atom->idx ) ) {
+      if ( atom->check( rmesa->radeon.glCtx, atom ) ) {
 	 int size = atom->cmd_size * 4;
 	 memcpy( dest, atom->cmd, size);
 	 dest += size;
@@ -159,7 +159,7 @@ void r200EmitState( r200ContextPtr rmesa )
    if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
       return;
 
-   mtu = rmesa->glCtx->Const.MaxTextureUnits;
+   mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
 
    /* To avoid going across the entire set of states multiple times, just check
     * for enough space for the case of emitting all state, and inline the
@@ -173,7 +173,7 @@ void r200EmitState( r200ContextPtr rmesa )
    if (R200_DEBUG & DEBUG_STATE) {
       foreach( atom, &rmesa->hw.atomlist ) {
 	 if ( atom->dirty || rmesa->hw.all_dirty ) {
-	    if ( atom->check( rmesa->glCtx, atom->idx ) )
+	    if ( atom->check( rmesa->radeon.glCtx, atom ) )
 	       print_state_atom( atom );
 	    else
 	       fprintf(stderr, "skip state %s\n", atom->name);
@@ -185,7 +185,7 @@ void r200EmitState( r200ContextPtr rmesa )
       if ( rmesa->hw.all_dirty )
 	 atom->dirty = GL_TRUE;
       if ( atom->dirty ) {
-	 if ( atom->check( rmesa->glCtx, atom->idx ) ) {
+	 if ( atom->check( rmesa->radeon.glCtx, atom ) ) {
 	    int size = atom->cmd_size * 4;
 	    memcpy( dest, atom->cmd, size);
 	    dest += size;
@@ -230,8 +230,9 @@ void r200EmitVbufPrim( r200ContextPtr rmesa,
 }
 
 
-void r200FlushElts( r200ContextPtr rmesa )
+void r200FlushElts( GLcontext *ctx )
 {
+   r200ContextPtr rmesa = R200_CONTEXT(ctx);
    int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
    int dwords;
    int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
@@ -252,7 +253,7 @@ void r200FlushElts( r200ContextPtr rmesa )
 
    if (R200_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
-      r200Finish( rmesa->glCtx );
+      r200Finish( rmesa->radeon.glCtx );
    }
 }
 
@@ -289,7 +290,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 	      cmd[1].i, primitive);
 
    assert(!rmesa->dma.flush);
-   rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+   rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
    rmesa->dma.flush = r200FlushElts;
 
    rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index 6a1b9fb9fdf..9e89c1d7433 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -93,8 +93,8 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name )
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    static char buffer[128];
    unsigned   offset;
-   GLuint agp_mode = (rmesa->radeonScreen->card_type == RADEON_CARD_PCI)? 0 :
-      rmesa->radeonScreen->AGPMode;
+   GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 :
+      rmesa->radeon.radeonScreen->AGPMode;
 
    switch ( name ) {
    case GL_VENDOR:
@@ -105,7 +105,7 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name )
 				     agp_mode );
 
       sprintf( & buffer[ offset ], " %sTCL",
-	       !(rmesa->TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
+	       !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
 	       ? "" : "NO-" );
 
       return (GLubyte *)buffer;
@@ -273,12 +273,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     * Do this here so that initialMaxAnisotropy is set before we create
     * the default textures.
     */
-   driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
+   driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 			screen->driScreen->myNum, "r200");
-   rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
-                                                 "def_max_anisotropy");
+   rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
+							"def_max_anisotropy");
 
-   if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+   if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
       if ( sPriv->drm_version.minor < 13 )
 	 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 			  "disabling.\n", sPriv->drm_version.minor );
@@ -301,53 +301,53 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
 
    /* Allocate and initialize the Mesa context */
    if (sharedContextPrivate)
-      shareCtx = ((r200ContextPtr) sharedContextPrivate)->glCtx;
+      shareCtx = ((r200ContextPtr) sharedContextPrivate)->radeon.glCtx;
    else
       shareCtx = NULL;
-   rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
+   rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx,
                                        &functions, (void *) rmesa);
-   if (!rmesa->glCtx) {
+   if (!rmesa->radeon.glCtx) {
       FREE(rmesa);
       return GL_FALSE;
    }
    driContextPriv->driverPrivate = rmesa;
 
    /* Init r200 context data */
-   rmesa->dri.context = driContextPriv;
-   rmesa->dri.screen = sPriv;
-   rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */
-   rmesa->dri.hwContext = driContextPriv->hHWContext;
-   rmesa->dri.hwLock = &sPriv->pSAREA->lock;
-   rmesa->dri.fd = sPriv->fd;
-   rmesa->dri.drmMinor = sPriv->drm_version.minor;
-
-   rmesa->radeonScreen = screen;
-   rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
+   rmesa->radeon.dri.context = driContextPriv;
+   rmesa->radeon.dri.screen = sPriv;
+   rmesa->radeon.dri.drawable = NULL; /* Set by XMesaMakeCurrent */
+   rmesa->radeon.dri.hwContext = driContextPriv->hHWContext;
+   rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock;
+   rmesa->radeon.dri.fd = sPriv->fd;
+   rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor;
+
+   rmesa->radeon.radeonScreen = screen;
+   rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
 				       screen->sarea_priv_offset);
 
 
-   rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
+   rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address;
 
-   (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
-   make_empty_list( & rmesa->swapped );
+   (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
+   make_empty_list( & rmesa->radeon.swapped );
 
-   rmesa->nr_heaps = 1 /* screen->numTexHeaps */ ;
-   assert(rmesa->nr_heaps < RADEON_NR_TEX_HEAPS);
-   for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
-      rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
+   rmesa->radeon.nr_heaps = 1 /* screen->numTexHeaps */ ;
+   assert(rmesa->radeon.nr_heaps < RADEON_NR_TEX_HEAPS);
+   for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
+      rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
 	    screen->texSize[i],
 	    12,
 	    RADEON_NR_TEX_REGIONS,
-	    (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
-	    & rmesa->sarea->tex_age[i],
-	    & rmesa->swapped,
+	    (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
+	    & rmesa->radeon.sarea->tex_age[i],
+	    & rmesa->radeon.swapped,
 	    sizeof( radeonTexObj ),
 	    (destroy_texture_object_t *) r200DestroyTexObj );
    }
-   rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
+   rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
 					   "texture_depth");
-   if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
-      rmesa->texture_depth = ( screen->cpp == 4 ) ?
+   if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
+      rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ?
 	 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
    rmesa->swtcl.RenderIndex = ~0;
@@ -359,16 +359,16 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     * setting allow larger textures.
     */
 
-   ctx = rmesa->glCtx;
-   ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
+   ctx = rmesa->radeon.glCtx;
+   ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 						 "texture_units");
    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 
-   i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures");
+   i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 
-   driCalculateMaxTextureLevels( rmesa->texture_heaps,
-				 rmesa->nr_heaps,
+   driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
+				 rmesa->radeon.nr_heaps,
 				 & ctx->Const,
 				 4,
 				 11, /* max 2D texture size is 2048x2048 */
@@ -391,7 +391,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
    ctx->Const.MinPointSizeAA = 1.0;
    ctx->Const.MaxPointSizeAA = 1.0;
    ctx->Const.PointSizeGranularity = 0.0625;
-   if (rmesa->radeonScreen->drmSupportsPointSprites)
+   if (rmesa->radeon.radeonScreen->drmSupportsPointSprites)
       ctx->Const.MaxPointSize = 2047.0;
    else
       ctx->Const.MaxPointSize = 1.0;
@@ -445,32 +445,32 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
    _math_matrix_set_identity( &rmesa->tmpmat );
 
    driInitExtensions( ctx, card_extensions, GL_TRUE );
-   if (!(rmesa->radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
+   if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
      /* yuv textures don't work with some chips - R200 / rv280 okay so far
 	others get the bit ordering right but don't actually do YUV-RGB conversion */
       _mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" );
    }
-   if (rmesa->glCtx->Mesa_DXTn) {
+   if (rmesa->radeon.glCtx->Mesa_DXTn) {
       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
    }
-   else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
+   else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
    }
 
-   if (rmesa->radeonScreen->drmSupportsCubeMapsR200)
+   if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200)
       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
-   if (rmesa->radeonScreen->drmSupportsBlendColor) {
+   if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
        driInitExtensions( ctx, blend_extensions, GL_FALSE );
    }
-   if(rmesa->radeonScreen->drmSupportsVertexProgram)
+   if(rmesa->radeon.radeonScreen->drmSupportsVertexProgram)
       driInitSingleExtension( ctx, ARB_vp_extension );
-   if(driQueryOptionb(&rmesa->optionCache, "nv_vertex_program"))
+   if(driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program"))
       driInitSingleExtension( ctx, NV_vp_extension );
 
-   if ((ctx->Const.MaxTextureUnits == 6) && rmesa->radeonScreen->drmSupportsFragShader)
+   if ((ctx->Const.MaxTextureUnits == 6) && rmesa->radeon.radeonScreen->drmSupportsFragShader)
       driInitSingleExtension( ctx, ATI_fs_extension );
-   if (rmesa->radeonScreen->drmSupportsPointSprites)
+   if (rmesa->radeon.radeonScreen->drmSupportsPointSprites)
       driInitExtensions( ctx, point_extensions, GL_FALSE );
 #if 0
    r200InitDriverFuncs( ctx );
@@ -486,25 +486,25 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
    r200InitState( rmesa );
    r200InitSwtcl( ctx );
 
-   fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
-   rmesa->iw.irq_seq = -1;
-   rmesa->irqsEmitted = 0;
-   rmesa->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
-		     rmesa->radeonScreen->irq);
+   fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
+   rmesa->radeon.iw.irq_seq = -1;
+   rmesa->radeon.irqsEmitted = 0;
+   rmesa->radeon.do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
+		     rmesa->radeon.radeonScreen->irq);
 
-   rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
+   rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 
-   if (!rmesa->do_irqs)
+   if (!rmesa->radeon.do_irqs)
       fprintf(stderr,
 	      "IRQ's not enabled, falling back to %s: %d %d\n",
-	      rmesa->do_usleeps ? "usleeps" : "busy waits",
+	      rmesa->radeon.do_usleeps ? "usleeps" : "busy waits",
 	      fthrottle_mode,
-	      rmesa->radeonScreen->irq);
+	      rmesa->radeon.radeonScreen->irq);
 
    rmesa->prefer_gart_client_texturing = 
       (getenv("R200_GART_CLIENT_TEXTURES") != 0);
 
-   (*sPriv->systemTime->getUST)( & rmesa->swap_ust );
+   (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
 
 
 #if DO_DEBUG
@@ -514,18 +514,18 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
 				      debug_control );
 #endif
 
-   tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
-   if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
+   tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
+   if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
       fprintf(stderr, "disabling 3D acceleration\n");
       FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
    }
    else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
-	    !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
-      if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
-	 rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
+	    !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
+      if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
+	 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 	 fprintf(stderr, "Disabling HW TCL support\n");
       }
-      TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
+      TCL_FALLBACK(rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
    }
 
    return GL_TRUE;
@@ -554,14 +554,14 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
       GLboolean   release_texture_heaps;
 
 
-      release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
-      _swsetup_DestroyContext( rmesa->glCtx );
-      _tnl_DestroyContext( rmesa->glCtx );
-      _vbo_DestroyContext( rmesa->glCtx );
-      _swrast_DestroyContext( rmesa->glCtx );
+      release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
+      _swsetup_DestroyContext( rmesa->radeon.glCtx );
+      _tnl_DestroyContext( rmesa->radeon.glCtx );
+      _vbo_DestroyContext( rmesa->radeon.glCtx );
+      _swrast_DestroyContext( rmesa->radeon.glCtx );
 
-      r200DestroySwtcl( rmesa->glCtx );
-      r200ReleaseArrays( rmesa->glCtx, ~0 );
+      r200DestroySwtcl( rmesa->radeon.glCtx );
+      r200ReleaseArrays( rmesa->radeon.glCtx, ~0 );
 
       if (rmesa->dma.current.buf) {
 	 r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
@@ -579,20 +579,20 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
           */
          int i;
 
-         for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
-	    driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
-	    rmesa->texture_heaps[ i ] = NULL;
+         for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
+	    driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
+	    rmesa->radeon.texture_heaps[ i ] = NULL;
          }
 
-	 assert( is_empty_list( & rmesa->swapped ) );
+	 assert( is_empty_list( & rmesa->radeon.swapped ) );
       }
 
       /* free the Mesa context */
-      rmesa->glCtx->DriverCtx = NULL;
-      _mesa_destroy_context( rmesa->glCtx );
+      rmesa->radeon.glCtx->DriverCtx = NULL;
+      _mesa_destroy_context( rmesa->radeon.glCtx );
 
       /* free the option cache */
-      driDestroyOptionCache (&rmesa->optionCache);
+      driDestroyOptionCache (&rmesa->radeon.optionCache);
 
       FREE( rmesa );
    }
@@ -608,10 +608,10 @@ r200SwapBuffers( __DRIdrawablePrivate *dPriv )
       r200ContextPtr rmesa;
       GLcontext *ctx;
       rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate;
-      ctx = rmesa->glCtx;
+      ctx = rmesa->radeon.glCtx;
       if (ctx->Visual.doubleBufferMode) {
          _mesa_notifySwapBuffers( ctx );  /* flush pending rendering comands */
-         if ( rmesa->doPageFlip ) {
+         if ( rmesa->radeon.doPageFlip ) {
             r200PageFlip( dPriv );
          }
          else {
@@ -633,7 +633,7 @@ r200CopySubBuffer( __DRIdrawablePrivate *dPriv,
       r200ContextPtr rmesa;
       GLcontext *ctx;
       rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate;
-      ctx = rmesa->glCtx;
+      ctx = rmesa->radeon.glCtx;
       if (ctx->Visual.doubleBufferMode) {
 	 drm_clip_rect_t rect;
 	 rect.x1 = x + dPriv->x;
@@ -663,32 +663,32 @@ r200MakeCurrent( __DRIcontextPrivate *driContextPriv,
 	 (r200ContextPtr) driContextPriv->driverPrivate;
 
       if (R200_DEBUG & DEBUG_DRI)
-	 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->glCtx);
+	 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->radeon.glCtx);
 
-      newCtx->dri.readable = driReadPriv;
+      newCtx->radeon.dri.readable = driReadPriv;
 
-      if ( newCtx->dri.drawable != driDrawPriv ||
-           newCtx->lastStamp != driDrawPriv->lastStamp ) {
+      if ( newCtx->radeon.dri.drawable != driDrawPriv ||
+           newCtx->radeon.lastStamp != driDrawPriv->lastStamp ) {
 	 if (driDrawPriv->swap_interval == (unsigned)-1) {
-	    driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0)
-	       ? driGetDefaultVBlankFlags(&newCtx->optionCache)
+	    driDrawPriv->vblFlags = (newCtx->radeon.radeonScreen->irq != 0)
+	       ? driGetDefaultVBlankFlags(&newCtx->radeon.optionCache)
 	       : VBLANK_FLAG_NO_IRQ;
 
 	    driDrawableInitVBlank( driDrawPriv );
 	 }
 
-	 newCtx->dri.drawable = driDrawPriv;
+	 newCtx->radeon.dri.drawable = driDrawPriv;
 
 	 r200SetCliprects(newCtx);
-	 r200UpdateViewportOffset( newCtx->glCtx );
+	 r200UpdateViewportOffset( newCtx->radeon.glCtx );
       }
 
-      _mesa_make_current( newCtx->glCtx,
+      _mesa_make_current( newCtx->radeon.glCtx,
 			  (GLframebuffer *) driDrawPriv->driverPrivate,
 			  (GLframebuffer *) driReadPriv->driverPrivate );
 
-      _mesa_update_state( newCtx->glCtx );
-      r200ValidateState( newCtx->glCtx );
+      _mesa_update_state( newCtx->radeon.glCtx );
+      r200ValidateState( newCtx->radeon.glCtx );
 
    } else {
       if (R200_DEBUG & DEBUG_DRI)
@@ -709,7 +709,7 @@ r200UnbindContext( __DRIcontextPrivate *driContextPriv )
    r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
 
    if (R200_DEBUG & DEBUG_DRI)
-      fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->glCtx);
+      fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx);
 
    return GL_TRUE;
 }
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index 64f773826c4..9ee6c15bf4e 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -53,6 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #error This driver requires a newer libdrm to compile
 #endif
 
+#include "radeon_screen.h"
 #include "common_context.h"
 
 struct r200_context;
@@ -60,21 +61,8 @@ typedef struct r200_context r200ContextRec;
 typedef struct r200_context *r200ContextPtr;
 
 #include "r200_lock.h"
-#include "radeon_screen.h"
-#include "main/mm.h"
-
-typedef void (*r200_tri_func)( r200ContextPtr,
-				 radeonVertex *,
-				 radeonVertex *,
-				 radeonVertex * );
-
-typedef void (*r200_line_func)( r200ContextPtr,
-				  radeonVertex *,
-				  radeonVertex * );
-
-typedef void (*r200_point_func)( r200ContextPtr,
-				   radeonVertex * );
 
+#include "main/mm.h"
 
 struct r200_vertex_program {
         struct gl_vertex_program mesa_program; /* Must be first */
@@ -540,7 +528,7 @@ struct r200_state {
    GLuint envneeded;
 };
 
-#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset +		\
+#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +		\
 			(rvb)->address - rmesa->dma.buf0_address +	\
 			(rvb)->start)
 
@@ -592,9 +580,9 @@ struct r200_swtcl_info {
 
    /* Fallback rasterization functions
     */
-   r200_point_func draw_point;
-   r200_line_func draw_line;
-   r200_tri_func draw_tri;
+   radeon_point_func draw_point;
+   radeon_line_func draw_line;
+   radeon_tri_func draw_tri;
 
    GLuint hw_primitive;
    GLenum render_primitive;
@@ -636,7 +624,7 @@ struct r200_swtcl_info {
 
 
 struct r200_context {
-   GLcontext *glCtx;			/* Mesa context */
+   struct radeon_context radeon;
 
    /* Driver and hardware state management
     */
@@ -644,21 +632,6 @@ struct r200_context {
    struct r200_state state;
    struct r200_vertex_program *curr_vp_hw;
 
-   /* Texture object bookkeeping
-    */
-   unsigned              nr_heaps;
-   driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
-   driTextureObject      swapped;
-   int                   texture_depth;
-   float                 initialMaxAnisotropy;
-
-   /* Rasterization and vertex state:
-    */
-   GLuint TclFallback;
-   GLuint Fallback;
-   GLuint NewGLState;
-   DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */
-
    /* Vertex buffers
     */
    struct radeon_ioctl ioctl;
@@ -669,30 +642,11 @@ struct r200_context {
     */
    struct radeon_store backup_store;
 
-   /* Page flipping
-    */
-   GLuint doPageFlip;
-
-   /* Busy waiting
-    */
-   GLuint do_usleeps;
-   GLuint do_irqs;
-   GLuint irqsEmitted;
-   drm_radeon_irq_wait_t iw;
-
    /* Clientdata textures;
     */
    GLuint prefer_gart_client_texturing;
 
-   /* Drawable, cliprect and scissor information
-    */
-   GLuint numClipRects;			/* Cliprects for the draw buffer */
-   drm_clip_rect_t *pClipRects;
-   unsigned int lastStamp;
-   GLboolean lost_context;
    GLboolean save_on_next_emit;
-   radeonScreenPtr radeonScreen;	/* Screen private DRI data */
-   drm_radeon_sarea_t *sarea;		/* Private SAREA data */
 
    /* TCL stuff
     */
@@ -705,15 +659,6 @@ struct r200_context {
    GLuint TexGenCompSel;
    GLmatrix tmpmat;
 
-   /* buffer swap
-    */
-   int64_t swap_ust;
-   int64_t swap_missed_ust;
-
-   GLuint swap_count;
-   GLuint swap_missed_count;
-
-
    /* r200_tcl.c
     */
    struct r200_tcl_info tcl;
@@ -722,14 +667,6 @@ struct r200_context {
     */
    struct r200_swtcl_info swtcl;
 
-   /* Mirrors of some DRI state
-    */
-   struct radeon_dri_mirror dri;
-
-   /* Configuration cache
-    */
-   driOptionCache optionCache;
-
    GLboolean using_hyperz;
    GLboolean texmicrotile;
 
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index da9a293241c..16776abd027 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -74,7 +74,7 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa )
    if (R200_DEBUG & DEBUG_STATE)
       fprintf(stderr, "Emitting backup state on lost context\n");
 
-   rmesa->lost_context = GL_FALSE;
+   rmesa->radeon.lost_context = GL_FALSE;
 
    nr_released_bufs = rmesa->dma.nr_released_bufs;
    saved_store = rmesa->store;
@@ -90,7 +90,7 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
    int ret, i;
    drm_radeon_cmd_buffer_t cmd;
 
-   if (rmesa->lost_context)
+   if (rmesa->radeon.lost_context)
       r200BackUpAndEmitLostStateLocked( rmesa );
 
    if (R200_DEBUG & DEBUG_IOCTL) {
@@ -114,8 +114,8 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
 				    rmesa->state.scissor.pClipRects);
       else
 	 ret = r200SanityCmdBuffer( rmesa, 
-				    rmesa->numClipRects,
-				    rmesa->pClipRects);
+				    rmesa->radeon.numClipRects,
+				    rmesa->radeon.pClipRects);
       if (ret) {
 	 fprintf(stderr, "drmSanityCommandWrite: %d\n", ret);	 
 	 goto out;
@@ -124,8 +124,8 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
 
 
    if (R200_DEBUG & DEBUG_MEMORY) {
-      if (! driValidateTextureHeaps( rmesa->texture_heaps, rmesa->nr_heaps,
-				     & rmesa->swapped ) ) {
+      if (! driValidateTextureHeaps( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
+				     & rmesa->radeon.swapped ) ) {
 	 fprintf( stderr, "%s: texture memory is inconsistent - expect "
 		  "mangled textures\n", __FUNCTION__ );
       }
@@ -139,11 +139,11 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
       cmd.nbox = rmesa->state.scissor.numClipRects;
       cmd.boxes = (drm_clip_rect_t *)rmesa->state.scissor.pClipRects;
    } else {
-      cmd.nbox = rmesa->numClipRects;
-      cmd.boxes = (drm_clip_rect_t *)rmesa->pClipRects;
+      cmd.nbox = rmesa->radeon.numClipRects;
+      cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects;
    }
 
-   ret = drmCommandWrite( rmesa->dri.fd,
+   ret = drmCommandWrite( rmesa->radeon.dri.fd,
 			  DRM_RADEON_CMDBUF,
 			  &cmd, sizeof(cmd) );
 
@@ -195,7 +195,7 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller )
 void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
 {
    struct radeon_dma_buffer *dmabuf;
-   int fd = rmesa->dri.fd;
+   int fd = rmesa->radeon.dri.fd;
    int index = 0;
    int size = 0;
    drmDMAReq dma;
@@ -205,7 +205,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
       fprintf(stderr, "%s\n", __FUNCTION__);  
 
    if (rmesa->dma.flush) {
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
    }
 
    if (rmesa->dma.current.buf)
@@ -214,7 +214,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
    if (rmesa->dma.nr_released_bufs > 4)
       r200FlushCmdBuf( rmesa, __FUNCTION__ );
 
-   dma.context = rmesa->dri.hwContext;
+   dma.context = rmesa->radeon.dri.hwContext;
    dma.send_count = 0;
    dma.send_list = NULL;
    dma.send_sizes = NULL;
@@ -236,7 +236,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
 	 r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
       }
 
-      if (rmesa->do_usleeps) {
+      if (rmesa->radeon.do_usleeps) {
 	 UNLOCK_HARDWARE( rmesa );
 	 DO_USLEEP( 1 );
 	 LOCK_HARDWARE( rmesa );
@@ -249,7 +249,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
       fprintf(stderr, "Allocated buffer %d\n", index);
 
    dmabuf = CALLOC_STRUCT( radeon_dma_buffer );
-   dmabuf->buf = &rmesa->radeonScreen->buffers->list[index];
+   dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index];
    dmabuf->refcount = 1;
 
    rmesa->dma.current.buf = dmabuf;
@@ -270,7 +270,7 @@ void r200ReleaseDmaRegion( r200ContextPtr rmesa,
       return;
 
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
 
    if (--region->buf->refcount == 0) {
       drm_radeon_cmd_header_t *cmd;
@@ -303,7 +303,7 @@ void r200AllocDmaRegion( r200ContextPtr rmesa,
       fprintf(stderr, "%s %d\n", __FUNCTION__, bytes);
 
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
 
    if (region->buf)
       r200ReleaseDmaRegion( rmesa, region, __FUNCTION__ );
@@ -341,7 +341,7 @@ static uint32_t r200GetLastFrame(r200ContextPtr rmesa)
 
    gp.param = RADEON_PARAM_LAST_FRAME;
    gp.value = (int *)&frame;
-   ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM,
+   ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM,
 			      &gp, sizeof(gp) );
    if ( ret ) {
       fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
@@ -356,8 +356,8 @@ static void r200EmitIrqLocked( r200ContextPtr rmesa )
    drm_radeon_irq_emit_t ie;
    int ret;
 
-   ie.irq_seq = &rmesa->iw.irq_seq;
-   ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT, 
+   ie.irq_seq = &rmesa->radeon.iw.irq_seq;
+   ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_EMIT, 
 			      &ie, sizeof(ie) );
    if ( ret ) {
       fprintf( stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, ret );
@@ -371,8 +371,8 @@ static void r200WaitIrq( r200ContextPtr rmesa )
    int ret;
 
    do {
-      ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_IRQ_WAIT,
-			     &rmesa->iw, sizeof(rmesa->iw) );
+      ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_WAIT,
+			     &rmesa->radeon.iw, sizeof(rmesa->radeon.iw) );
    } while (ret && (errno == EINTR || errno == EBUSY));
 
    if ( ret ) {
@@ -384,11 +384,11 @@ static void r200WaitIrq( r200ContextPtr rmesa )
 
 static void r200WaitForFrameCompletion( r200ContextPtr rmesa )
 {
-   drm_radeon_sarea_t *sarea = rmesa->sarea;
+   drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
 
-   if (rmesa->do_irqs) {
+   if (rmesa->radeon.do_irqs) {
       if (r200GetLastFrame(rmesa) < sarea->last_frame) {
-	 if (!rmesa->irqsEmitted) {
+	 if (!rmesa->radeon.irqsEmitted) {
 	    while (r200GetLastFrame (rmesa) < sarea->last_frame)
 	       ;
 	 }
@@ -397,18 +397,18 @@ static void r200WaitForFrameCompletion( r200ContextPtr rmesa )
 	    r200WaitIrq( rmesa );	
 	    LOCK_HARDWARE( rmesa ); 
 	 }
-	 rmesa->irqsEmitted = 10;
+	 rmesa->radeon.irqsEmitted = 10;
       }
 
-      if (rmesa->irqsEmitted) {
+      if (rmesa->radeon.irqsEmitted) {
 	 r200EmitIrqLocked( rmesa );
-	 rmesa->irqsEmitted--;
+	 rmesa->radeon.irqsEmitted--;
       }
    } 
    else {
       while (r200GetLastFrame (rmesa) < sarea->last_frame) {
 	 UNLOCK_HARDWARE( rmesa ); 
-	 if (rmesa->do_usleeps) 
+	 if (rmesa->radeon.do_usleeps) 
 	    DO_USLEEP( 1 );
 	 LOCK_HARDWARE( rmesa ); 
       }
@@ -435,7 +435,7 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv,
    rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate;
 
    if ( R200_DEBUG & DEBUG_IOCTL ) {
-      fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)rmesa->glCtx );
+      fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)rmesa->radeon.glCtx );
    }
 
    R200_FIREVERTICES( rmesa );
@@ -459,7 +459,7 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv,
    for ( i = 0 ; i < nbox ; ) {
       GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
       drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t *b = rmesa->sarea->boxes;
+      drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
       GLint n = 0;
 
       for ( ; i < nr ; i++ ) {
@@ -484,12 +484,12 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv,
 	  b++;
 	  n++;
       }
-      rmesa->sarea->nbox = n;
+      rmesa->radeon.sarea->nbox = n;
 
       if (!n)
 	 continue;
 
-      ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
+      ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_SWAP );
 
       if ( ret ) {
 	 fprintf( stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret );
@@ -503,14 +503,14 @@ void r200CopyBuffer( __DRIdrawablePrivate *dPriv,
    {
        rmesa->hw.all_dirty = GL_TRUE;
 
-       rmesa->swap_count++;
+       rmesa->radeon.swap_count++;
        (*psp->systemTime->getUST)( & ust );
        if ( missed_target ) {
-	   rmesa->swap_missed_count++;
-	   rmesa->swap_missed_ust = ust - rmesa->swap_ust;
+	   rmesa->radeon.swap_missed_count++;
+	   rmesa->radeon.swap_missed_ust = ust - rmesa->radeon.swap_ust;
        }
 
-       rmesa->swap_ust = ust;
+       rmesa->radeon.swap_ust = ust;
 
        sched_yield();
    }
@@ -531,7 +531,7 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv )
 
    if ( R200_DEBUG & DEBUG_IOCTL ) {
       fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
-	      rmesa->sarea->pfCurrentPage);
+	      rmesa->radeon.sarea->pfCurrentPage);
    }
 
    R200_FIREVERTICES( rmesa );
@@ -547,9 +547,9 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv )
     */
    {
       drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t *b = rmesa->sarea->boxes;
+      drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
       b[0] = box[0];
-      rmesa->sarea->nbox = 1;
+      rmesa->radeon.sarea->nbox = 1;
    }
 
    /* Throttle the frame rate -- only allow a few pending swap buffers
@@ -559,12 +559,12 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv )
    UNLOCK_HARDWARE( rmesa );
    driWaitForVBlank( dPriv, & missed_target );
    if ( missed_target ) {
-      rmesa->swap_missed_count++;
-      (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust );
+      rmesa->radeon.swap_missed_count++;
+      (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust );
    }
    LOCK_HARDWARE( rmesa );
 
-   ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP );
+   ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP );
 
    UNLOCK_HARDWARE( rmesa );
 
@@ -573,34 +573,34 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv )
       exit( 1 );
    }
 
-   rmesa->swap_count++;
-   (void) (*psp->systemTime->getUST)( & rmesa->swap_ust );
+   rmesa->radeon.swap_count++;
+   (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_ust );
 
 #if 000
-   if ( rmesa->sarea->pfCurrentPage == 1 ) {
-	 rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
-	 rmesa->state.color.drawPitch  = rmesa->radeonScreen->frontPitch;
+   if ( rmesa->radeon.sarea->pfCurrentPage == 1 ) {
+	 rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
+	 rmesa->state.color.drawPitch  = rmesa->radeon.radeonScreen->frontPitch;
    } else {
-	 rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
-	 rmesa->state.color.drawPitch  = rmesa->radeonScreen->backPitch;
+	 rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
+	 rmesa->state.color.drawPitch  = rmesa->radeon.radeonScreen->backPitch;
    }
 
    R200_STATECHANGE( rmesa, ctx );
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
-					   + rmesa->radeonScreen->fbLocation;
+					   + rmesa->radeon.radeonScreen->fbLocation;
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH]  = rmesa->state.color.drawPitch;
-   if (rmesa->sarea->tiling_enabled) {
+   if (rmesa->radeon.sarea->tiling_enabled) {
       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
    }
 #else
    /* Get ready for drawing next frame.  Update the renderbuffers'
     * flippedOffset/Pitch fields so we draw into the right place.
     */
-   driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
-                        rmesa->sarea->pfCurrentPage);
+   driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer,
+                        rmesa->radeon.sarea->pfCurrentPage);
 
 
-   r200UpdateDrawBuffer(rmesa->glCtx);
+   r200UpdateDrawBuffer(rmesa->radeon.glCtx);
 #endif
 }
 
@@ -611,7 +611,7 @@ void r200PageFlip( __DRIdrawablePrivate *dPriv )
 static void r200Clear( GLcontext *ctx, GLbitfield mask )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    GLuint flags = 0;
    GLuint color_mask = 0;
    GLint ret, i;
@@ -663,7 +663,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
 
    if (rmesa->using_hyperz) {
       flags |= RADEON_USE_COMP_ZBUF;
-/*      if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200)
+/*      if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
 	 flags |= RADEON_USE_HIERZ; */
       if (!(rmesa->state.stencil.hwBuffer) ||
 	 ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
@@ -693,7 +693,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
 
       gp.param = RADEON_PARAM_LAST_CLEAR;
       gp.value = (int *)&clear;
-      ret = drmCommandWriteRead( rmesa->dri.fd,
+      ret = drmCommandWriteRead( rmesa->radeon.dri.fd,
 		      DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
 
       if ( ret ) {
@@ -703,11 +703,11 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
 
       /* Clear throttling needs more thought.
        */
-      if ( rmesa->sarea->last_clear - clear <= 25 ) {
+      if ( rmesa->radeon.sarea->last_clear - clear <= 25 ) {
 	 break;
       }
       
-      if (rmesa->do_usleeps) {
+      if (rmesa->radeon.do_usleeps) {
 	 UNLOCK_HARDWARE( rmesa );
 	 DO_USLEEP( 1 );
 	 LOCK_HARDWARE( rmesa );
@@ -720,7 +720,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
    for ( i = 0 ; i < dPriv->numClipRects ; ) {
       GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
       drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t *b = rmesa->sarea->boxes;
+      drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
       drm_radeon_clear_t clear;
       drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
       GLint n = 0;
@@ -755,7 +755,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
 	 }
       }
 
-      rmesa->sarea->nbox = n;
+      rmesa->radeon.sarea->nbox = n;
 
       clear.flags       = flags;
       clear.clear_color = rmesa->state.color.clear;
@@ -765,7 +765,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
       clear.depth_boxes = depth_boxes;
 
       n--;
-      b = rmesa->sarea->boxes;
+      b = rmesa->radeon.sarea->boxes;
       for ( ; n >= 0 ; n-- ) {
 	 depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
 	 depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
@@ -774,7 +774,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
 	 depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear;
       }
 
-      ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
+      ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR,
 			     &clear, sizeof(clear));
 
 
@@ -796,7 +796,7 @@ void r200WaitForIdleLocked( r200ContextPtr rmesa )
     int i = 0;
     
     do {
-       ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_CP_IDLE);
+       ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_CP_IDLE);
        if (ret) 
 	  DO_USLEEP( 1 );
     } while (ret && ++i < 100);
@@ -825,7 +825,7 @@ void r200Flush( GLcontext *ctx )
       fprintf(stderr, "%s\n", __FUNCTION__);
 
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( ctx );
 
    r200EmitState( rmesa );
    
@@ -841,7 +841,7 @@ void r200Finish( GLcontext *ctx )
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    r200Flush( ctx );
 
-   if (rmesa->do_irqs) {
+   if (rmesa->radeon.do_irqs) {
       LOCK_HARDWARE( rmesa );
       r200EmitIrqLocked( rmesa );
       UNLOCK_HARDWARE( rmesa );
@@ -875,7 +875,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
       fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, 
 	      writefreq, priority);
 
-   if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeonScreen->gartTextures.map)
+   if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeon.radeonScreen->gartTextures.map)
       return NULL;
 
    if (getenv("R200_NO_ALLOC"))
@@ -886,7 +886,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
    alloc.size = size;
    alloc.region_offset = &region_offset;
 
-   ret = drmCommandWriteRead( rmesa->radeonScreen->driScreen->fd,
+   ret = drmCommandWriteRead( rmesa->radeon.radeonScreen->driScreen->fd,
 			      DRM_RADEON_ALLOC,
 			      &alloc, sizeof(alloc));
    
@@ -896,7 +896,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
    }
    
    {
-      char *region_start = (char *)rmesa->radeonScreen->gartTextures.map;
+      char *region_start = (char *)rmesa->radeon.radeonScreen->gartTextures.map;
       return (void *)(region_start + region_offset);
    }
 }
@@ -914,24 +914,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer)
    if (R200_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s %p\n", __FUNCTION__, pointer);
 
-   if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeonScreen->gartTextures.map) {
+   if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeon.radeonScreen->gartTextures.map) {
       fprintf(stderr, "%s: no context\n", __FUNCTION__);
       return;
    }
 
-   region_offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map;
+   region_offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map;
 
    if (region_offset < 0 || 
-       region_offset > rmesa->radeonScreen->gartTextures.size) {
+       region_offset > rmesa->radeon.radeonScreen->gartTextures.size) {
       fprintf(stderr, "offset %d outside range 0..%d\n", region_offset,
-	      rmesa->radeonScreen->gartTextures.size);
+	      rmesa->radeon.radeonScreen->gartTextures.size);
       return;
    }
 
    memfree.region = RADEON_MEM_REGION_GART;
    memfree.region_offset = region_offset;
    
-   ret = drmCommandWrite( rmesa->radeonScreen->driScreen->fd,
+   ret = drmCommandWrite( rmesa->radeon.radeonScreen->driScreen->fd,
 			  DRM_RADEON_FREE,
 			  &memfree, sizeof(memfree));
    
@@ -956,16 +956,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer)
 
    card_offset = r200GartOffsetFromVirtual( rmesa, pointer );
 
-   return card_offset - rmesa->radeonScreen->gart_base;
+   return card_offset - rmesa->radeon.radeonScreen->gart_base;
 }
 
 GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
 			   GLint size )
 {
-   ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map;
+   ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map;
    int valid = (size >= 0 &&
 		offset >= 0 &&
-		offset + size < rmesa->radeonScreen->gartTextures.size);
+		offset + size < rmesa->radeon.radeonScreen->gartTextures.size);
 
    if (R200_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid );
@@ -976,12 +976,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
 
 GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer )
 {
-   ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeonScreen->gartTextures.map;
+   ptrdiff_t offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map;
 
-   if (offset < 0 || offset > rmesa->radeonScreen->gartTextures.size)
+   if (offset < 0 || offset > rmesa->radeon.radeonScreen->gartTextures.size)
       return ~0;
    else
-      return rmesa->radeonScreen->gart_texture_offset + offset;
+      return rmesa->radeon.radeonScreen->gart_texture_offset + offset;
 }
 
 
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h
index d37efddaef7..f52d2a7419d 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.h
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.h
@@ -52,7 +52,7 @@ extern void r200EmitVbufPrim( r200ContextPtr rmesa,
 				GLuint primitive,
 				GLuint vertex_nr );
 
-extern void r200FlushElts( r200ContextPtr rmesa );
+extern void r200FlushElts(GLcontext *ctx);
 
 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
 					   GLuint primitive,
@@ -120,7 +120,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa );
 #define R200_NEWPRIM( rmesa )			\
 do {						\
    if ( rmesa->dma.flush )			\
-      rmesa->dma.flush( rmesa );	\
+      rmesa->dma.flush( rmesa->radeon.glCtx );	\
 } while (0)
 
 /* Can accomodate several state changes and primitive changes without
@@ -142,7 +142,7 @@ static INLINE int R200_DB_STATECHANGE(
    struct radeon_state_atom *atom )
 {
    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
-      int *tmp;
+      GLuint *tmp;
       R200_NEWPRIM( rmesa );
       atom->dirty = GL_TRUE;
       rmesa->hw.is_dirty = GL_TRUE;
@@ -161,7 +161,7 @@ static INLINE int R200_DB_STATECHANGE(
 #define R200_FIREVERTICES( rmesa )			\
 do {							\
    if ( rmesa->store.cmd_used || rmesa->dma.flush ) {	\
-      r200Flush( rmesa->glCtx );			\
+      r200Flush( rmesa->radeon.glCtx );			\
    }							\
 } while (0)
 
diff --git a/src/mesa/drivers/dri/r200/r200_lock.c b/src/mesa/drivers/dri/r200/r200_lock.c
index 99661a4bfb4..c79603cdd5a 100644
--- a/src/mesa/drivers/dri/r200/r200_lock.c
+++ b/src/mesa/drivers/dri/r200/r200_lock.c
@@ -51,10 +51,10 @@ int prevLockLine = 0;
 static void
 r200UpdatePageFlipping( r200ContextPtr rmesa )
 {
-   rmesa->doPageFlip = rmesa->sarea->pfState;
-   if (rmesa->glCtx->WinSysDrawBuffer) {
-      driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
-                           rmesa->sarea->pfCurrentPage);
+   rmesa->radeon.doPageFlip = rmesa->radeon.sarea->pfState;
+   if (rmesa->radeon.glCtx->WinSysDrawBuffer) {
+      driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer,
+                           rmesa->radeon.sarea->pfCurrentPage);
    }
 }
 
@@ -70,13 +70,13 @@ r200UpdatePageFlipping( r200ContextPtr rmesa )
  */
 void r200GetLock( r200ContextPtr rmesa, GLuint flags )
 {
-   __DRIdrawablePrivate *drawable = rmesa->dri.drawable;
-   __DRIdrawablePrivate *readable = rmesa->dri.readable;
-   __DRIscreenPrivate *sPriv = rmesa->dri.screen;
-   drm_radeon_sarea_t *sarea = rmesa->sarea;
+   __DRIdrawablePrivate *drawable = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *readable = rmesa->radeon.dri.readable;
+   __DRIscreenPrivate *sPriv = rmesa->radeon.dri.screen;
+   drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
    int i;
 
-   drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags );
+   drmGetLock( rmesa->radeon.dri.fd, rmesa->radeon.dri.hwContext, flags );
 
    /* The window might have moved, so we might need to get new clip
     * rects.
@@ -91,26 +91,26 @@ void r200GetLock( r200ContextPtr rmesa, GLuint flags )
       DRI_VALIDATE_DRAWABLE_INFO( sPriv, readable );
    }
 
-   if ( rmesa->lastStamp != drawable->lastStamp ) {
+   if ( rmesa->radeon.lastStamp != drawable->lastStamp ) {
       r200UpdatePageFlipping( rmesa );
       r200SetCliprects( rmesa );
-      r200UpdateViewportOffset( rmesa->glCtx );
-      driUpdateFramebufferSize(rmesa->glCtx, drawable);
+      r200UpdateViewportOffset( rmesa->radeon.glCtx );
+      driUpdateFramebufferSize(rmesa->radeon.glCtx, drawable);
    }
 
    R200_STATECHANGE( rmesa, ctx );
-   if (rmesa->sarea->tiling_enabled) {
+   if (rmesa->radeon.sarea->tiling_enabled) {
       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
    }
    else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE;
 
-   if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
-      sarea->ctx_owner = rmesa->dri.hwContext;
+   if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) {
+      sarea->ctx_owner = rmesa->radeon.dri.hwContext;
    }
 
-   for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
-      DRI_AGE_TEXTURES( rmesa->texture_heaps[ i ] );
+   for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
+      DRI_AGE_TEXTURES( rmesa->radeon.texture_heaps[ i ] );
    }
 
-   rmesa->lost_context = GL_TRUE;
+   rmesa->radeon.lost_context = GL_TRUE;
 }
diff --git a/src/mesa/drivers/dri/r200/r200_lock.h b/src/mesa/drivers/dri/r200/r200_lock.h
index 4ff98907fbf..f1cb624d8fe 100644
--- a/src/mesa/drivers/dri/r200/r200_lock.h
+++ b/src/mesa/drivers/dri/r200/r200_lock.h
@@ -88,8 +88,8 @@ extern int prevLockLine;
    do {								\
       char __ret = 0;						\
       DEBUG_CHECK_LOCK();					\
-      DRM_CAS( rmesa->dri.hwLock, rmesa->dri.hwContext,		\
-	       (DRM_LOCK_HELD | rmesa->dri.hwContext), __ret );	\
+      DRM_CAS( rmesa->radeon.dri.hwLock, rmesa->radeon.dri.hwContext,		\
+	       (DRM_LOCK_HELD | rmesa->radeon.dri.hwContext), __ret );	\
       if ( __ret )						\
 	 r200GetLock( rmesa, 0 );				\
       DEBUG_LOCK();						\
@@ -97,9 +97,9 @@ extern int prevLockLine;
 
 #define UNLOCK_HARDWARE( rmesa )					\
    do {									\
-      DRM_UNLOCK( rmesa->dri.fd,					\
-		  rmesa->dri.hwLock,					\
-		  rmesa->dri.hwContext );				\
+      DRM_UNLOCK( rmesa->radeon.dri.fd,					\
+		  rmesa->radeon.dri.hwLock,					\
+		  rmesa->radeon.dri.hwContext );				\
       DEBUG_RESET();							\
    } while (0)
 
diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c
index 77506c5532e..1b28a83d70a 100644
--- a/src/mesa/drivers/dri/r200/r200_pixel.c
+++ b/src/mesa/drivers/dri/r200/r200_pixel.c
@@ -51,7 +51,7 @@ check_color( const GLcontext *ctx, GLenum type, GLenum format,
 	     const void *pixels, GLint sz, GLint pitch )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLuint cpp = rmesa->radeonScreen->cpp;
+   GLuint cpp = rmesa->radeon.radeonScreen->cpp;
 
    if (R200_DEBUG & DEBUG_PIXEL)
       fprintf(stderr, "%s\n", __FUNCTION__);
@@ -137,8 +137,8 @@ clip_pixelrect( const GLcontext *ctx,
    if (*height <= 0)
       return GL_FALSE;
 
-   *size = ((*y + *height - 1) * rmesa->radeonScreen->frontPitch +
-	    (*x + *width - 1) * rmesa->radeonScreen->cpp);
+   *size = ((*y + *height - 1) * rmesa->radeon.radeonScreen->frontPitch +
+	    (*x + *width - 1) * rmesa->radeon.radeonScreen->cpp);
 
    return GL_TRUE;
 }
@@ -153,7 +153,7 @@ r200TryReadPixels( GLcontext *ctx,
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    GLint pitch = pack->RowLength ? pack->RowLength : width;
    GLint blit_format;
-   GLuint cpp = rmesa->radeonScreen->cpp;
+   GLuint cpp = rmesa->radeon.radeonScreen->cpp;
    GLint size = width * height * cpp;
 
    if (R200_DEBUG & DEBUG_PIXEL)
@@ -162,7 +162,7 @@ r200TryReadPixels( GLcontext *ctx,
    /* Only accelerate reading to GART buffers.
     */
    if ( !r200IsGartMemory(rmesa, pixels, 
-			 pitch * height * rmesa->radeonScreen->cpp ) ) {
+			 pitch * height * rmesa->radeon.radeonScreen->cpp ) ) {
       if (R200_DEBUG & DEBUG_PIXEL)
 	 fprintf(stderr, "%s: dest not GART\n", __FUNCTION__);
       return GL_FALSE;
@@ -180,7 +180,7 @@ r200TryReadPixels( GLcontext *ctx,
    if (!check_color(ctx, type, format, pack, pixels, size, pitch))
       return GL_FALSE;
 
-   switch ( rmesa->radeonScreen->cpp ) {
+   switch ( rmesa->radeon.radeonScreen->cpp ) {
    case 4:
       blit_format = R200_CP_COLOR_FORMAT_ARGB8888;
       break;
@@ -212,14 +212,14 @@ r200TryReadPixels( GLcontext *ctx,
    }
 
    {
-      __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+      __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
       driRenderbuffer *drb = (driRenderbuffer *) ctx->ReadBuffer->_ColorReadBuffer;
       int nbox = dPriv->numClipRects;
       int src_offset = drb->offset
-		     + rmesa->radeonScreen->fbLocation;
+		     + rmesa->radeon.radeonScreen->fbLocation;
       int src_pitch = drb->pitch * drb->cpp;
       int dst_offset = r200GartOffsetFromVirtual( rmesa, pixels );
-      int dst_pitch = pitch * rmesa->radeonScreen->cpp;
+      int dst_pitch = pitch * rmesa->radeon.radeonScreen->cpp;
       drm_clip_rect_t *box = dPriv->pClipRects;
       int i;
 
@@ -292,7 +292,7 @@ static void do_draw_pix( GLcontext *ctx,
 			 GLuint planemask)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    drm_clip_rect_t *box = dPriv->pClipRects;
    struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorDrawBuffers[0];
    driRenderbuffer *drb = (driRenderbuffer *) rb;
@@ -301,12 +301,12 @@ static void do_draw_pix( GLcontext *ctx,
    int blit_format;
    int size;
    int src_offset = r200GartOffsetFromVirtual( rmesa, pixels );
-   int src_pitch = pitch * rmesa->radeonScreen->cpp;
+   int src_pitch = pitch * rmesa->radeon.radeonScreen->cpp;
 
    if (R200_DEBUG & DEBUG_PIXEL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
-   switch ( rmesa->radeonScreen->cpp ) {
+   switch ( rmesa->radeon.radeonScreen->cpp ) {
    case 2:
       blit_format = R200_CP_COLOR_FORMAT_RGB565;
       break;
@@ -357,7 +357,7 @@ static void do_draw_pix( GLcontext *ctx,
 		    blit_format,
 		    src_pitch, src_offset,
 		    drb->pitch * drb->cpp,
-		    drb->offset + rmesa->radeonScreen->fbLocation,
+		    drb->offset + rmesa->radeon.radeonScreen->fbLocation,
 		    bx - x, by - y,
 		    bx, by,
 		    bw, bh );
@@ -381,7 +381,7 @@ r200TryDrawPixels( GLcontext *ctx,
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    GLint pitch = unpack->RowLength ? unpack->RowLength : width;
    GLuint planemask;
-   GLuint cpp = rmesa->radeonScreen->cpp;
+   GLuint cpp = rmesa->radeon.radeonScreen->cpp;
    GLint size = height * pitch * cpp;
 
    if (R200_DEBUG & DEBUG_PIXEL)
@@ -395,7 +395,7 @@ r200TryDrawPixels( GLcontext *ctx,
    case GL_RGB:
    case GL_RGBA:
    case GL_BGRA:
-      planemask = r200PackColor(cpp,
+      planemask = radeonPackColor(cpp,
 				ctx->Color.ColorMask[RCOMP],
 				ctx->Color.ColorMask[GCOMP],
 				ctx->Color.ColorMask[BCOMP],
@@ -471,7 +471,7 @@ r200Bitmap( GLcontext *ctx, GLint px, GLint py,
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 
-   if (rmesa->Fallback)
+   if (rmesa->radeon.Fallback)
       _swrast_Bitmap( ctx, px, py, width, height, unpack, bitmap );
    else
       r200PointsBitmap( ctx, px, py, width, height, unpack, bitmap );
diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c
index 9783678028a..361f0fde266 100644
--- a/src/mesa/drivers/dri/r200/r200_span.c
+++ b/src/mesa/drivers/dri/r200/r200_span.c
@@ -259,7 +259,7 @@ static void r200SpanRenderStart( GLcontext *ctx )
       driRenderbuffer *drb =
 	 (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0];
       volatile int *buf =
-	 (volatile int *)(rmesa->dri.screen->pFB + drb->offset);
+	 (volatile int *)(rmesa->radeon.dri.screen->pFB + drb->offset);
       p = *buf;
       *buf = p;
    }
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 8e9f2562a18..4cd87bd1b9d 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -114,7 +114,7 @@ static void r200BlendColor( GLcontext *ctx, const GLfloat cf[4] )
    CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
    CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
    CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
-   if (rmesa->radeonScreen->drmSupportsBlendColor)
+   if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
       rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] );
 }
 
@@ -213,7 +213,7 @@ static void r200_set_blend_state( GLcontext * ctx )
 
    R200_STATECHANGE( rmesa, ctx );
 
-   if (rmesa->radeonScreen->drmSupportsBlendColor) {
+   if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
       if (ctx->Color.ColorLogicOpEnabled) {
          rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] =  cntl | R200_ROP_ENABLE;
          rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
@@ -278,7 +278,7 @@ static void r200_set_blend_state( GLcontext * ctx )
       return;
    }
 
-   if (!rmesa->radeonScreen->drmSupportsBlendColor) {
+   if (!rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
       rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = eqn | func;
       return;
    }
@@ -549,8 +549,8 @@ void r200RecalcScissorRects( r200ContextPtr rmesa )
 
    /* Grow cliprect store?
     */
-   if (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
-      while (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
+   if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
+      while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
 	 rmesa->state.scissor.numAllocedClipRects += 1;	/* zero case */
 	 rmesa->state.scissor.numAllocedClipRects *= 2;
       }
@@ -571,9 +571,9 @@ void r200RecalcScissorRects( r200ContextPtr rmesa )
    out = rmesa->state.scissor.pClipRects;
    rmesa->state.scissor.numClipRects = 0;
 
-   for ( i = 0 ; i < rmesa->numClipRects ;  i++ ) {
+   for ( i = 0 ; i < rmesa->radeon.numClipRects ;  i++ ) {
       if ( intersect_rect( out, 
-			   &rmesa->pClipRects[i], 
+			   &rmesa->radeon.pClipRects[i], 
 			   &rmesa->state.scissor.rect ) ) {
 	 rmesa->state.scissor.numClipRects++;
 	 out++;
@@ -586,8 +586,8 @@ static void r200UpdateScissor( GLcontext *ctx )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 
-   if ( rmesa->dri.drawable ) {
-      __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   if ( rmesa->radeon.dri.drawable ) {
+      __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
 
       int x = ctx->Scissor.X;
       int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
@@ -803,7 +803,7 @@ static void r200ColorMask( GLcontext *ctx,
 			   GLboolean b, GLboolean a )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp,
+   GLuint mask = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
 				ctx->Color.ColorMask[RCOMP],
 				ctx->Color.ColorMask[GCOMP],
 				ctx->Color.ColorMask[BCOMP],
@@ -867,7 +867,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask )
    /* FIXME: Use window x,y offsets into stipple RAM.
     */
    stipple.mask = rmesa->state.stipple.mask;
-   drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE, 
+   drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, 
                     &stipple, sizeof(stipple) );
    UNLOCK_HARDWARE( rmesa );
 }
@@ -881,7 +881,7 @@ static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
     * cases work. 
     */
    TCL_FALLBACK( ctx, R200_TCL_FALLBACK_UNFILLED, flag);
-   if (rmesa->TclFallback) {
+   if (rmesa->radeon.TclFallback) {
       r200ChooseRenderState( ctx );
       r200ChooseVertexState( ctx );
    }
@@ -958,7 +958,7 @@ static void r200UpdateSpecular( GLcontext *ctx )
 
    /* Update vertex/render formats
     */
-   if (rmesa->TclFallback) { 
+   if (rmesa->radeon.TclFallback) { 
       r200ChooseRenderState( ctx );
       r200ChooseVertexState( ctx );
    }
@@ -1430,7 +1430,7 @@ static void r200LightModelfv( GLcontext *ctx, GLenum pname,
 	    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHT_TWOSIDE;
 	 else
 	    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~(R200_LIGHT_TWOSIDE);
-	 if (rmesa->TclFallback) {
+	 if (rmesa->radeon.TclFallback) {
 	    r200ChooseRenderState( ctx );
 	    r200ChooseVertexState( ctx );
 	 }
@@ -1700,7 +1700,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s )
 void r200UpdateWindow( GLcontext *ctx )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    GLfloat xoffset = (GLfloat)dPriv->x;
    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1744,7 +1744,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval,
 void r200UpdateViewportOffset( GLcontext *ctx )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    GLfloat xoffset = (GLfloat)dPriv->x;
    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1774,8 +1774,8 @@ void r200UpdateViewportOffset( GLcontext *ctx )
                 R200_STIPPLE_Y_OFFSET_MASK);
 
          /* add magic offsets, then invert */
-         stx = 31 - ((rmesa->dri.drawable->x - 1) & R200_STIPPLE_COORD_MASK);
-         sty = 31 - ((rmesa->dri.drawable->y + rmesa->dri.drawable->h - 1)
+         stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & R200_STIPPLE_COORD_MASK);
+         sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1)
                      & R200_STIPPLE_COORD_MASK);
 
          m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) |
@@ -1805,7 +1805,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] )
    CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]);
    CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]);
    CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]);
-   rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp,
+   rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
                                              color[0], color[1],
                                              color[2], color[3] );
 }
@@ -1854,31 +1854,31 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode )
  */
 void r200SetCliprects( r200ContextPtr rmesa )
 {
-   __DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
-   __DRIdrawablePrivate *const readable = rmesa->dri.readable;
+   __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable;
    GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate;
    GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate;
 
    if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BIT_BACK_LEFT) {
       /* Can't ignore 2d windows if we are page flipping.
        */
-      if ( drawable->numBackClipRects == 0 || rmesa->doPageFlip ) {
-         rmesa->numClipRects = drawable->numClipRects;
-         rmesa->pClipRects = drawable->pClipRects;
+      if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) {
+         rmesa->radeon.numClipRects = drawable->numClipRects;
+         rmesa->radeon.pClipRects = drawable->pClipRects;
       }
       else {
-         rmesa->numClipRects = drawable->numBackClipRects;
-         rmesa->pClipRects = drawable->pBackClipRects;
+         rmesa->radeon.numClipRects = drawable->numBackClipRects;
+         rmesa->radeon.pClipRects = drawable->pBackClipRects;
       }
    }
    else {
      /* front buffer (or none, or multiple buffers) */
-     rmesa->numClipRects = drawable->numClipRects;
-     rmesa->pClipRects = drawable->pClipRects;
+     rmesa->radeon.numClipRects = drawable->numClipRects;
+     rmesa->radeon.pClipRects = drawable->pClipRects;
   }
 
    if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) {
-      _mesa_resize_framebuffer(rmesa->glCtx, draw_fb,
+      _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb,
 			       drawable->w, drawable->h);
       draw_fb->Initialized = GL_TRUE;
    }
@@ -1886,7 +1886,7 @@ void r200SetCliprects( r200ContextPtr rmesa )
    if (drawable != readable) {
       if ((read_fb->Width != readable->w) ||
 	  (read_fb->Height != readable->h)) {
-	 _mesa_resize_framebuffer(rmesa->glCtx, read_fb,
+	 _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb,
 				  readable->w, readable->h);
 	 read_fb->Initialized = GL_TRUE;
       }
@@ -1895,7 +1895,7 @@ void r200SetCliprects( r200ContextPtr rmesa )
    if (rmesa->state.scissor.enabled)
       r200RecalcScissorRects( rmesa );
 
-   rmesa->lastStamp = drawable->lastStamp;
+   rmesa->radeon.lastStamp = drawable->lastStamp;
 }
 
 
@@ -2031,7 +2031,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
 	 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
       }
       r200UpdateSpecular( ctx ); /* for PK_SPEC */
-      if (rmesa->TclFallback) 
+      if (rmesa->radeon.TclFallback) 
 	 r200ChooseVertexState( ctx );
       _mesa_allow_light_in_model( ctx, !state );
       break;
@@ -2068,7 +2068,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_LIGHTING:
       r200UpdateSpecular(ctx);
       /* for reflection map fixup - might set recheck_texgen for all units too */
-      rmesa->NewGLState |= _NEW_TEXTURE;
+      rmesa->radeon.NewGLState |= _NEW_TEXTURE;
       break;
 
    case GL_LINE_SMOOTH:
@@ -2465,10 +2465,10 @@ r200UpdateDrawBuffer(GLcontext *ctx)
 
    /* Note: we used the (possibly) page-flipped values */
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
-     = ((drb->flippedOffset + rmesa->radeonScreen->fbLocation)
+     = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation)
 	& R200_COLOROFFSET_MASK);
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
-   if (rmesa->sarea->tiling_enabled) {
+   if (rmesa->radeon.sarea->tiling_enabled) {
       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
    }
 }
@@ -2478,7 +2478,7 @@ r200UpdateDrawBuffer(GLcontext *ctx)
 void r200ValidateState( GLcontext *ctx )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLuint new_state = rmesa->NewGLState;
+   GLuint new_state = rmesa->radeon.NewGLState;
 
    if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
      r200UpdateDrawBuffer(ctx);
@@ -2486,7 +2486,7 @@ void r200ValidateState( GLcontext *ctx )
 
    if (new_state & (_NEW_TEXTURE | _NEW_PROGRAM)) {
       r200UpdateTextureState( ctx );
-      new_state |= rmesa->NewGLState; /* may add TEXTURE_MATRIX */
+      new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */
       r200UpdateLocalViewer( ctx );
    }
 
@@ -2533,7 +2533,7 @@ void r200ValidateState( GLcontext *ctx )
       else TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, 0);
    }
 
-   rmesa->NewGLState = 0;
+   rmesa->radeon.NewGLState = 0;
 }
 
 
@@ -2544,7 +2544,7 @@ static void r200InvalidateState( GLcontext *ctx, GLuint new_state )
    _vbo_InvalidateState( ctx, new_state );
    _tnl_InvalidateState( ctx, new_state );
    _ae_invalidate_state( ctx, new_state );
-   R200_CONTEXT(ctx)->NewGLState |= new_state;
+   R200_CONTEXT(ctx)->radeon.NewGLState |= new_state;
 }
 
 /* A hack.  The r200 can actually cope just fine with materials
@@ -2573,11 +2573,11 @@ static void r200WrapRunPipeline( GLcontext *ctx )
    GLboolean has_material;
 
    if (0)
-      fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->NewGLState);
+      fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->radeon.NewGLState);
 
    /* Validate state:
     */
-   if (rmesa->NewGLState)
+   if (rmesa->radeon.NewGLState)
       r200ValidateState( ctx );
 
    has_material = !ctx->VertexProgram._Enabled && ctx->Light.Enabled && check_material( ctx );
diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h
index a917163a00a..5d7347af311 100644
--- a/src/mesa/drivers/dri/r200/r200_state.h
+++ b/src/mesa/drivers/dri/r200/r200_state.h
@@ -59,7 +59,7 @@ extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode );
 #define FALLBACK( rmesa, bit, mode ) do {				\
    if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n",		\
 		     __FUNCTION__, bit, mode );				\
-   r200Fallback( rmesa->glCtx, bit, mode );				\
+   r200Fallback( rmesa->radeon.glCtx, bit, mode );				\
 } while (0)
 
 extern void r200LightingSpaceChange( GLcontext *ctx );
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 724c224c5e8..f03a47ef464 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -127,36 +127,36 @@ static int cmdscl2( int offset, int stride, int count )
 }
 
 #define CHECK( NM, FLAG )				\
-static GLboolean check_##NM( GLcontext *ctx, int idx )	\
+static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
 {							\
    r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
-   (void) idx;						\
+   (void) atom;						\
    (void) rmesa;					\
    return FLAG;						\
 }
 
 #define TCL_CHECK( NM, FLAG )				\
-static GLboolean check_##NM( GLcontext *ctx, int idx )	\
-{							\
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
-   (void) idx;						\
-   return !rmesa->TclFallback && !ctx->VertexProgram._Enabled && (FLAG);	\
+static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
+{									\
+   r200ContextPtr rmesa = R200_CONTEXT(ctx);				\
+   (void) atom;						\
+   return !rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG);	\
 }
 
 #define TCL_OR_VP_CHECK( NM, FLAG )			\
-static GLboolean check_##NM( GLcontext *ctx, int idx )	\
+static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
 {							\
    r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
-   (void) idx;						\
-   return !rmesa->TclFallback && (FLAG);		\
+   (void) atom;						\
+   return !rmesa->radeon.TclFallback && (FLAG);		\
 }
 
 #define VP_CHECK( NM, FLAG )				\
-static GLboolean check_##NM( GLcontext *ctx, int idx )	\
-{							\
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
-   (void) idx;						\
-   return !rmesa->TclFallback && ctx->VertexProgram._Enabled && (FLAG);		\
+static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
+{									\
+   r200ContextPtr rmesa = R200_CONTEXT(ctx);				\
+   (void) atom;								\
+   return !rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG);	\
 }
 
 
@@ -164,19 +164,19 @@ CHECK( always, GL_TRUE )
 CHECK( never, GL_FALSE )
 CHECK( tex_any, ctx->Texture._EnabledUnits )
 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
-CHECK( tex_pair, (rmesa->state.texture.unit[idx].unitneeded | rmesa->state.texture.unit[idx & ~1].unitneeded) )
-CHECK( tex, rmesa->state.texture.unit[idx].unitneeded )
+CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
+CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
-CHECK( texenv, (rmesa->state.envneeded & (1 << idx) && !ctx->ATIFragmentShader._Enabled) )
+   CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
 CHECK( afs, ctx->ATIFragmentShader._Enabled )
-CHECK( tex_cube, rmesa->state.texture.unit[idx].unitneeded & TEXTURE_CUBE_BIT )
+CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
 TCL_CHECK( tcl, GL_TRUE )
-TCL_CHECK( tcl_tex, rmesa->state.texture.unit[idx].unitneeded )
+TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
-TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[idx].Enabled )
-TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << idx)) )
+TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
+TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
 VP_CHECK( tcl_vp, GL_TRUE )
 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
@@ -187,11 +187,11 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9
  */
 void r200InitState( r200ContextPtr rmesa )
 {
-   GLcontext *ctx = rmesa->glCtx;
+   GLcontext *ctx = rmesa->radeon.glCtx;
    GLuint color_fmt, depth_fmt, i;
    GLint drawPitch, drawOffset;
 
-   switch ( rmesa->radeonScreen->cpp ) {
+   switch ( rmesa->radeon.radeonScreen->cpp ) {
    case 2:
       color_fmt = R200_COLOR_FORMAT_RGB565;
       break;
@@ -228,22 +228,22 @@ void r200InitState( r200ContextPtr rmesa )
    rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
 				     ctx->Visual.depthBits == 24 );
 
-   rmesa->Fallback = 0;
+   rmesa->radeon.Fallback = 0;
 
-   if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
-      drawOffset = rmesa->radeonScreen->backOffset;
-      drawPitch  = rmesa->radeonScreen->backPitch;
+   if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
+      drawOffset = rmesa->radeon.radeonScreen->backOffset;
+      drawPitch  = rmesa->radeon.radeonScreen->backPitch;
    } else {
-      drawOffset = rmesa->radeonScreen->frontOffset;
-      drawPitch  = rmesa->radeonScreen->frontPitch;
+      drawOffset = rmesa->radeon.radeonScreen->frontOffset;
+      drawPitch  = rmesa->radeon.radeonScreen->frontPitch;
    }
 #if 000
    if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
-      rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
-      rmesa->state.color.drawPitch  = rmesa->radeonScreen->backPitch;
+      rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
+      rmesa->state.color.drawPitch  = rmesa->radeon.radeonScreen->backPitch;
    } else {
-      rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
-      rmesa->state.color.drawPitch  = rmesa->radeonScreen->frontPitch;
+      rmesa->state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
+      rmesa->state.color.drawPitch  = rmesa->radeon.radeonScreen->frontPitch;
    }
 
    rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
@@ -255,8 +255,8 @@ void r200InitState( r200ContextPtr rmesa )
 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX )				\
    do {								\
       rmesa->hw.ATOM.cmd_size = SZ;				\
-      rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int));	\
-      rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int));	\
+      rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int));	\
+      rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int));	\
       rmesa->hw.ATOM.name = NM;					\
       rmesa->hw.ATOM.idx = IDX;					\
       rmesa->hw.ATOM.check = check_##CHK;			\
@@ -267,7 +267,7 @@ void r200InitState( r200ContextPtr rmesa )
 
    /* Allocate state buffers:
     */
-   if (rmesa->radeonScreen->drmSupportsBlendColor)
+   if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
       ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
    else
       ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
@@ -282,8 +282,8 @@ void r200InitState( r200ContextPtr rmesa )
    ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
    ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
    ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
-   if (rmesa->radeonScreen->drmSupportsFragShader) {
-      if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) {
+   if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
+      if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
       /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
 	 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
 	 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
@@ -303,7 +303,7 @@ void r200InitState( r200ContextPtr rmesa )
       ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
    }
    else {
-      if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) {
+      if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
 	 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
 	 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
 	 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
@@ -321,7 +321,7 @@ void r200InitState( r200ContextPtr rmesa )
       ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
       ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
    }
-   if (rmesa->radeonScreen->drmSupportsCubeMapsR200) {
+   if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
       ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
       ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
       ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
@@ -337,7 +337,7 @@ void r200InitState( r200ContextPtr rmesa )
       ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
       ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
    }
-   if (rmesa->radeonScreen->drmSupportsVertexProgram) {
+   if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
       ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
       ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
       ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
@@ -390,13 +390,13 @@ void r200InitState( r200ContextPtr rmesa )
    ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
    ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
    ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
-   if (rmesa->radeonScreen->drmSupportsTriPerf) {
+   if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
       ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
    }
    else {
       ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
    }
-   if (rmesa->radeonScreen->drmSupportsPointSprites) {
+   if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
       ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
       ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
    }
@@ -412,7 +412,7 @@ void r200InitState( r200ContextPtr rmesa )
    rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
    rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
    rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
-   if (rmesa->radeonScreen->drmSupportsBlendColor)
+   if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
       rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR);
    rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
    rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
@@ -429,7 +429,7 @@ void r200InitState( r200ContextPtr rmesa )
    rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
    rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3);
    rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0);
-   if (rmesa->radeonScreen->drmSupportsFragShader) {
+   if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
       rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR);
       rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0);
       rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
@@ -567,7 +567,7 @@ void r200InitState( r200ContextPtr rmesa )
 				(R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
 				(R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
 
-   if (rmesa->radeonScreen->drmSupportsBlendColor) {
+   if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
       rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
       rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
 				(R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
@@ -578,10 +578,10 @@ void r200InitState( r200ContextPtr rmesa )
    }
 
    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
-      rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
+      rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
 
    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 
-      ((rmesa->radeonScreen->depthPitch &
+      ((rmesa->radeon.radeonScreen->depthPitch &
 	R200_DEPTHPITCH_MASK) |
        R200_DEPTH_ENDIAN_NO_SWAP);
    
@@ -599,7 +599,7 @@ void r200InitState( r200ContextPtr rmesa )
    if (rmesa->using_hyperz) {
       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
 						  R200_Z_DECOMPRESSION_ENABLE;
-/*      if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200)
+/*      if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
 	 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
    }
 
@@ -607,7 +607,7 @@ void r200InitState( r200ContextPtr rmesa )
  				     | R200_TEX_BLEND_0_ENABLE);
 
    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt;
-   switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
+   switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
    case DRI_CONF_DITHER_XERRORDIFFRESET:
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
       break;
@@ -615,12 +615,12 @@ void r200InitState( r200ContextPtr rmesa )
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
       break;
    }
-   if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
+   if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
 	DRI_CONF_ROUND_ROUND )
       rmesa->state.color.roundEnable = R200_ROUND_ENABLE;
    else
       rmesa->state.color.roundEnable = 0;
-   if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
+   if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
 	DRI_CONF_COLOR_REDUCTION_DITHER )
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
    else
@@ -628,7 +628,7 @@ void r200InitState( r200ContextPtr rmesa )
 
 #if 000
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
-					       rmesa->radeonScreen->fbLocation)
+					       rmesa->radeon.radeonScreen->fbLocation)
 					      & R200_COLOROFFSET_MASK);
 
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
@@ -636,7 +636,7 @@ void r200InitState( r200ContextPtr rmesa )
 					     R200_COLOR_ENDIAN_NO_SWAP);
 #else
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
-					       rmesa->radeonScreen->fbLocation)
+					       rmesa->radeon.radeonScreen->fbLocation)
 					      & R200_COLOROFFSET_MASK);
 
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
@@ -644,12 +644,12 @@ void r200InitState( r200ContextPtr rmesa )
 					     R200_COLOR_ENDIAN_NO_SWAP);
 #endif
    /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
-   if (rmesa->sarea->tiling_enabled) {
+   if (rmesa->radeon.sarea->tiling_enabled) {
       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
    }
 
    rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * 
-			driQueryOptionf (&rmesa->optionCache,"texture_blend_quality");
+			driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
    rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
 
    rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
@@ -704,7 +704,7 @@ void r200InitState( r200ContextPtr rmesa )
 						R200_VC_NO_SWAP;
 #endif
 
-   if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
+   if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
       /* Bypass TCL */
       rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
    }
@@ -743,28 +743,28 @@ void r200InitState( r200ContextPtr rmesa )
       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
          (/* R200_TEXCOORD_PROJ | */
           0x100000);	/* Small default bias */
-      if (rmesa->radeonScreen->drmSupportsFragShader) {
+      if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
 	 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
-	     rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	     rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 	 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
 	 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
       }
       else {
 	  rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
-	     rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	     rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
      }
 
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
-         rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+         rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
-         rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+         rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
-         rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+         rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
-         rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+         rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
-         rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+         rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 
       rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
          (R200_TXC_ARG_A_ZERO |
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index 104c4945629..d5cba26ddd9 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -55,7 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_tcl.h"
 
 
-static void flush_last_swtcl_prim( r200ContextPtr rmesa  );
+static void flush_last_swtcl_prim( GLcontext *ctx  );
 
 
 /***********************************************************************
@@ -185,7 +185,7 @@ static void r200SetVertexFormat( GLcontext *ctx )
       rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_SPEC_ALPHA;
    }
 
-   if (!RENDERINPUTS_EQUAL( rmesa->tnl_index_bitset, index_bitset ) ||
+   if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 	(rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) ||
 	(rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) {
       R200_NEWPRIM(rmesa);
@@ -199,7 +199,7 @@ static void r200SetVertexFormat( GLcontext *ctx )
 			      rmesa->swtcl.vertex_attr_count,
 			      NULL, 0 );
       rmesa->swtcl.vertex_size /= 4;
-      RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset );
+      RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
    }
 }
 
@@ -212,7 +212,7 @@ static void r200RenderStart( GLcontext *ctx )
 
    if (rmesa->dma.flush != 0 && 
        rmesa->dma.flush != flush_last_swtcl_prim)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( ctx );
 }
 
 
@@ -232,7 +232,7 @@ void r200ChooseVertexState( GLcontext *ctx )
     * rasterization fallback.  As this function will be called again when we
     * leave a rasterization fallback, we can just skip it for now.
     */
-   if (rmesa->Fallback != 0)
+   if (rmesa->radeon.Fallback != 0)
       return;
 
    vte = rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL];
@@ -276,8 +276,9 @@ void r200ChooseVertexState( GLcontext *ctx )
 
 /* Flush vertices in the current dma region.
  */
-static void flush_last_swtcl_prim( r200ContextPtr rmesa  )
+static void flush_last_swtcl_prim(GLcontext *ctx)
 {
+   r200ContextPtr rmesa = R200_CONTEXT(ctx);
    if (R200_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
@@ -285,7 +286,7 @@ static void flush_last_swtcl_prim( r200ContextPtr rmesa  )
 
    if (rmesa->dma.current.buf) {
       struct radeon_dma_region *current = &rmesa->dma.current;
-      GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset +
+      GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset +
 			       current->buf->buf->idx * RADEON_BUFFER_SIZE + 
 			       current->start);
 
@@ -324,7 +325,7 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize )
       r200RefillCurrentDmaRegion( rmesa );
 
    if (!rmesa->dma.flush) {
-      rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+      rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
       rmesa->dma.flush = flush_last_swtcl_prim;
    }
 
@@ -599,7 +600,7 @@ void r200ChooseRenderState( GLcontext *ctx )
    GLuint index = 0;
    GLuint flags = ctx->_TriangleCaps;
 
-   if (!rmesa->TclFallback || rmesa->Fallback) 
+   if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) 
       return;
 
    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R200_TWOSIDE_BIT;
@@ -701,10 +702,10 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
-   GLuint oldfallback = rmesa->Fallback;
+   GLuint oldfallback = rmesa->radeon.Fallback;
 
    if (mode) {
-      rmesa->Fallback |= bit;
+      rmesa->radeon.Fallback |= bit;
       if (oldfallback == 0) {
 	 R200_FIREVERTICES( rmesa );
 	 TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE );
@@ -717,7 +718,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode )
       }
    }
    else {
-      rmesa->Fallback &= ~bit;
+      rmesa->radeon.Fallback &= ~bit;
       if (oldfallback == bit) {
 
 	 _swrast_flush( ctx );
@@ -731,14 +732,14 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 
 	 tnl->Driver.Render.ResetLineStipple = r200ResetLineStipple;
 	 TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_FALSE );
-	 if (rmesa->TclFallback) {
-	    /* These are already done if rmesa->TclFallback goes to
+	 if (rmesa->radeon.TclFallback) {
+	    /* These are already done if rmesa->radeon.TclFallback goes to
 	     * zero above. But not if it doesn't (R200_NO_TCL for
 	     * example?)
 	     */
 	    _tnl_invalidate_vertex_state( ctx, ~0 );
 	    _tnl_invalidate_vertices( ctx, ~0 );
-	    RENDERINPUTS_ZERO( rmesa->tnl_index_bitset );
+	    RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 	    r200ChooseVertexState( ctx );
 	    r200ChooseRenderState( ctx );
 	 }
@@ -873,8 +874,8 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py,
     */
    LOCK_HARDWARE( rmesa );
    UNLOCK_HARDWARE( rmesa );
-   h = rmesa->dri.drawable->h + rmesa->dri.drawable->y;
-   px += rmesa->dri.drawable->x;
+   h = rmesa->radeon.dri.drawable->h + rmesa->radeon.dri.drawable->y;
+   px += rmesa->radeon.dri.drawable->x;
 
    /* Clipping handled by existing mechansims in r200_ioctl.c?
     */
@@ -929,7 +930,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py,
 
    /* Need to restore vertexformat?
     */
-   if (rmesa->TclFallback)
+   if (rmesa->radeon.TclFallback)
       r200ChooseVertexState( ctx );
 }
 
diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c
index 99aecfe1e90..d14564c29bf 100644
--- a/src/mesa/drivers/dri/r200/r200_tcl.c
+++ b/src/mesa/drivers/dri/r200/r200_tcl.c
@@ -154,7 +154,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
    }
    else {
       if (rmesa->dma.flush)
-	 rmesa->dma.flush( rmesa );
+	 rmesa->dma.flush( rmesa->radeon.glCtx );
 
       r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
 			     rmesa->hw.max_state_size + ELTS_BUFSZ(nr) );
@@ -394,7 +394,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx,
 
    /* TODO: separate this from the swtnl pipeline 
     */
-   if (rmesa->TclFallback)
+   if (rmesa->radeon.TclFallback)
       return GL_TRUE;	/* fallback to software t&l */
 
    if (R200_DEBUG & DEBUG_PRIMS)
@@ -405,7 +405,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx,
 
    /* Validate state:
     */
-   if (rmesa->NewGLState)
+   if (rmesa->radeon.NewGLState)
       r200ValidateState( ctx );
 
    if (!ctx->VertexProgram._Enabled) {
@@ -566,7 +566,7 @@ static void transition_to_hwtnl( GLcontext *ctx )
    tnl->Driver.NotifyMaterialChange = r200UpdateMaterial;
 
    if ( rmesa->dma.flush )			
-      rmesa->dma.flush( rmesa );	
+      rmesa->dma.flush( rmesa->radeon.glCtx );	
 
    rmesa->dma.flush = NULL;
    
@@ -631,10 +631,10 @@ static char *getFallbackString(GLuint bit)
 void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLuint oldfallback = rmesa->TclFallback;
+   GLuint oldfallback = rmesa->radeon.TclFallback;
 
    if (mode) {
-      rmesa->TclFallback |= bit;
+      rmesa->radeon.TclFallback |= bit;
       if (oldfallback == 0) {
 	 if (R200_DEBUG & DEBUG_FALLBACKS) 
 	    fprintf(stderr, "R200 begin tcl fallback %s\n",
@@ -643,7 +643,7 @@ void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
       }
    }
    else {
-      rmesa->TclFallback &= ~bit;
+      rmesa->radeon.TclFallback &= ~bit;
       if (oldfallback == bit) {
 	 if (R200_DEBUG & DEBUG_FALLBACKS) 
 	    fprintf(stderr, "R200 end tcl fallback %s\n",
diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c
index 0cd93253664..525a9de4a0f 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.c
+++ b/src/mesa/drivers/dri/r200/r200_tex.c
@@ -335,9 +335,9 @@ r200ChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    const GLboolean do32bpt =
-       ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32 );
+       ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_32 );
    const GLboolean force16bpt =
-       ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 );
+       ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 );
    (void) format;
 
    switch ( internalFormat ) {
@@ -997,7 +997,7 @@ static void r200TexEnv( GLcontext *ctx, GLenum target,
        * NOTE: Add a small bias to the bias for conform mipsel.c test.
        */
       bias = *param + .01;
-      min = driQueryOptionb (&rmesa->optionCache, "no_neg_lod_bias") ?
+      min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ?
 	  0.0 : -16.0;
       bias = CLAMP( bias, min, 16.0 );
       b = (int)(bias * fixed_one) & R200_LOD_BIAS_MASK;
@@ -1162,7 +1162,7 @@ r200NewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
    obj = _mesa_new_texture_object(ctx, name, target);
    if (!obj)
       return NULL;
-   obj->MaxAnisotropy = rmesa->initialMaxAnisotropy;
+   obj->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
    r200AllocTexObj( obj );
    return obj;
 }
diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c
index 3a700def050..93ae3260cca 100644
--- a/src/mesa/drivers/dri/r200/r200_texmem.c
+++ b/src/mesa/drivers/dri/r200/r200_texmem.c
@@ -66,7 +66,7 @@ r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t )
       unsigned   i;
 
 
-      for ( i = 0 ; i < rmesa->glCtx->Const.MaxTextureUnits ; i++ ) {
+      for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
 	 if ( t == rmesa->state.texture.unit[i].texobj ) {
 	    rmesa->state.texture.unit[i].texobj = NULL;
 	    rmesa->hw.tex[i].dirty = GL_FALSE;
@@ -424,7 +424,7 @@ static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t,
 
    LOCK_HARDWARE( rmesa );
    do {
-      ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
+      ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
                                  &tex, sizeof(drm_radeon_texture_t) );
       if (ret) {
 	 if (R200_DEBUG & DEBUG_IOCTL)
@@ -464,7 +464,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
 
    if ( R200_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
       fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__,
-	       (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize,
+	       (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize,
 	       t->base.firstLevel, t->base.lastLevel );
    }
 
@@ -473,7 +473,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
 
    if (R200_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
-      r200Finish( rmesa->glCtx );
+      r200Finish( rmesa->radeon.glCtx );
    }
 
    LOCK_HARDWARE( rmesa );
@@ -481,7 +481,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
    if ( t->base.memBlock == NULL ) {
       int heap;
 
-      heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps,
+      heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
 				 (driTextureObject *) t );
       if ( heap == -1 ) {
 	 UNLOCK_HARDWARE( rmesa );
@@ -489,7 +489,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
       }
 
       /* Set the base offset of the texture image */
-      t->bufAddr = rmesa->radeonScreen->texOffset[heap] 
+      t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] 
 	   + t->base.memBlock->ofs;
       t->pp_txoffset = t->bufAddr;
        
@@ -523,7 +523,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
 
    if (R200_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
-      r200Finish( rmesa->glCtx );
+      r200Finish( rmesa->radeon.glCtx );
    }
 
    return 0;
diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index b5dfe304247..02f79bf3f80 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -981,7 +981,7 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 {
 	r200ContextPtr rmesa = pDRICtx->driverPrivate;
 	struct gl_texture_object *tObj =
-	    _mesa_lookup_texture(rmesa->glCtx, texname);
+	    _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
 	radeonTexObjPtr t;
 
 	if (!tObj)
@@ -1212,7 +1212,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
 				  radeonTexObjPtr texobj )
 {
 /* do not use RADEON_DB_STATE to avoid stale texture caches */
-   int *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
+   GLuint *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
 
    R200_STATECHANGE( rmesa, tex[unit] );
 
@@ -1225,7 +1225,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
    cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */
    cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */
    cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
-   if (rmesa->radeonScreen->drmSupportsFragShader) {
+   if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
       cmd[TEX_PP_TXOFFSET_NEWDRM] = texobj->pp_txoffset;
    }
    else {
@@ -1233,13 +1233,13 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
    }
 
    if (texobj->base.tObj->Target == GL_TEXTURE_CUBE_MAP) {
-      int *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
+      GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
       GLuint bytesPerFace = texobj->base.totalSize / 6;
       ASSERT(texobj->base.totalSize % 6 == 0);
 
       R200_STATECHANGE( rmesa, cube[unit] );
       cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
-      if (rmesa->radeonScreen->drmSupportsFragShader) {
+      if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
 	 /* that value is submitted twice. could change cube atom
 	    to not include that command when new drm is used */
 	 cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
@@ -1535,7 +1535,7 @@ static void disable_tex( GLcontext *ctx, int unit )
       R200_STATECHANGE( rmesa, vtx );
       rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3));
 	 
-      if (rmesa->TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<<unit)) {
+      if (rmesa->radeon.TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<<unit)) {
 	 TCL_FALLBACK( ctx, (R200_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE);
       }
 
@@ -1553,7 +1553,7 @@ static void disable_tex( GLcontext *ctx, int unit )
 
 	 if (tmp != rmesa->TexGenEnabled) {
 	    rmesa->recheck_texgen[unit] = GL_TRUE;
-	    rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+	    rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
 	 }
       }
    }
@@ -1767,7 +1767,7 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit )
       GLboolean fallback = !r200_validate_texgen( ctx, unit );
       TCL_FALLBACK( ctx, (R200_TCL_FALLBACK_TEXGEN_0<<unit), fallback);
       rmesa->recheck_texgen[unit] = 0;
-      rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+      rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
    }
 
    FALLBACK( rmesa, R200_FALLBACK_BORDER_MODE, t->border_fallback );
@@ -1846,11 +1846,11 @@ void r200UpdateTextureState( GLcontext *ctx )
 
    FALLBACK( rmesa, R200_FALLBACK_TEXTURE, !ok );
 
-   if (rmesa->TclFallback)
+   if (rmesa->radeon.TclFallback)
       r200ChooseVertexState( ctx );
 
 
-   if (rmesa->radeonScreen->chip_family == CHIP_FAMILY_R200) {
+   if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
 
       /*
        * T0 hang workaround -------------
diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c
index 4a25031e039..888f91db73d 100644
--- a/src/mesa/drivers/dri/r200/r200_vertprog.c
+++ b/src/mesa/drivers/dri/r200/r200_vertprog.c
@@ -1110,9 +1110,9 @@ void r200SetupVertexProg( GLcontext *ctx ) {
    }
    /* could optimize setting up vertex progs away for non-tcl hw */
    fallback = !(vp->native && r200VertexProgUpdateParams(ctx, vp) &&
-      rmesa->radeonScreen->drmSupportsVertexProgram);
+      rmesa->radeon.radeonScreen->drmSupportsVertexProgram);
    TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, fallback);
-   if (rmesa->TclFallback) return;
+   if (rmesa->radeon.TclFallback) return;
 
    R200_STATECHANGE( rmesa, vap );
    /* FIXME: fglrx sets R200_VAP_SINGLE_BUF_STATE_ENABLE too. Do we need it?
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile
index 3d7122fce2d..7357cf74c98 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -77,7 +77,8 @@ COMMON_SYMLINKS = \
 	radeon_bo_legacy.c \
 	radeon_cs_legacy.c \
 	radeon_bo_legacy.h \
-	radeon_cs_legacy.h
+	radeon_cs_legacy.h \
+	common_context.h
 
 DRI_LIB_DEPS += -ldrm_radeon
 
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 4eac5183b2f..bd9d25d2f0d 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -136,10 +136,10 @@ void r300BeginBatch(r300ContextPtr r300, int n,
 }
 
 static void r300PrintStateAtom(r300ContextPtr r300,
-                               struct r300_state_atom *state)
+                               struct radeon_state_atom *state)
 {
 	int i;
-	int dwords = (*state->check) (r300, state);
+	int dwords = (*state->check) (r300->radeon.glCtx, state);
 
 	fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
 
@@ -160,7 +160,7 @@ static void r300PrintStateAtom(r300ContextPtr r300,
 static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
 {
 	BATCH_LOCALS(r300);
-	struct r300_state_atom *atom;
+	struct radeon_state_atom *atom;
 	int dwords;
 
     cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
@@ -173,13 +173,13 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
 	/* Emit actual atoms */
 	foreach(atom, &r300->hw.atomlist) {
 		if ((atom->dirty || r300->hw.all_dirty) == dirty) {
-			dwords = (*atom->check) (r300, atom);
+			dwords = (*atom->check) (r300->radeon.glCtx, atom);
 			if (dwords) {
 				if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 					r300PrintStateAtom(r300, atom);
 				}
 				if (atom->emit) {
-					(*atom->emit)(r300, atom);
+					(*atom->emit)(r300->radeon.glCtx, atom);
 				} else {
 					BEGIN_BATCH_NO_AUTOSTATE(dwords);
 					OUT_BATCH_TABLE(atom->cmd, dwords);
@@ -246,15 +246,16 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
 
-void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom)
+void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
 {
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	BATCH_LOCALS(r300);
 	drm_r300_cmd_header_t cmd;
     uint32_t addr, ndw, i;
 
     if (!r300->radeon.radeonScreen->kernel_mm) {
         uint32_t dwords;
-    	dwords = (*atom->check) (r300, atom);
+    	dwords = (*atom->check) (ctx, atom);
         BEGIN_BATCH_NO_AUTOSTATE(dwords);
         OUT_BATCH_TABLE(atom->cmd, dwords);
         END_BATCH();
@@ -284,8 +285,9 @@ void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom)
     }
 }
 
-void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom)
+void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 {
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	BATCH_LOCALS(r300);
 	drm_r300_cmd_header_t cmd;
 	uint32_t addr, ndw, i, sz;
@@ -293,7 +295,7 @@ void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom)
 
 	if (!r300->radeon.radeonScreen->kernel_mm) {
 		uint32_t dwords;
-		dwords = (*atom->check) (r300, atom);
+		dwords = (*atom->check) (ctx, atom);
 		BEGIN_BATCH_NO_AUTOSTATE(dwords);
 		OUT_BATCH_TABLE(atom->cmd, dwords);
 		END_BATCH();
@@ -323,8 +325,9 @@ void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom)
 	}
 }
 
-static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
+static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 {
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	BATCH_LOCALS(r300);
 	int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 
@@ -353,8 +356,9 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
 	}
 }
 
-static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
+static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 {
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	BATCH_LOCALS(r300);
 	struct radeon_renderbuffer *rrb;
 	uint32_t cbpitch;
@@ -362,7 +366,7 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
 
 	rrb = r300->radeon.state.color.rrb;
 	if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
-		rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+		rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 	}
 	if (!rrb || !rrb->bo) {
 		fprintf(stderr, "no rrb\n");
@@ -386,8 +390,9 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
 	END_BATCH();
 }
 
-static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
+static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 {
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	BATCH_LOCALS(r300);
 	struct radeon_renderbuffer *rrb;
 	uint32_t zbpitch;
@@ -411,22 +416,23 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
 	END_BATCH();
 }
 
-static int check_always(r300ContextPtr r300, struct r300_state_atom *atom)
+static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 {
 	return atom->cmd_size;
 }
 
-static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom)
+static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 {
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	int cnt;
-    if (atom->cmd[0] == CP_PACKET2) {
-        return 0;
-    }
+	if (atom->cmd[0] == CP_PACKET2) {
+		return 0;
+	}
 	cnt = packet0_count(r300, atom->cmd);
 	return cnt ? cnt + 1 : 0;
 }
 
-int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
+int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 {
 	int cnt;
 
@@ -434,7 +440,7 @@ int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
 	return cnt ? (cnt * 4) + 1 : 0;
 }
 
-int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
+int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 {
 	int cnt;
 
@@ -442,7 +448,7 @@ int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
 	return cnt ? (cnt * 6) + 1 : 0;
 }
 
-int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
+int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 {
 	int cnt;
 
@@ -774,7 +780,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	if (size > 64 * 256)
 		size = 64 * 256;
 
-    size = 64 * 1024 / 4;
+	size = 64 * 1024 / 4;
 	if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) {
 		fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n",
 			sizeof(drm_r300_cmd_header_t));
@@ -805,7 +811,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
  */
 void r300DestroyCmdBuf(r300ContextPtr r300)
 {
-	struct r300_state_atom *atom;
+	struct radeon_state_atom *atom;
 
     radeon_cs_destroy(r300->cmdbuf.cs);
 	foreach(atom, &r300->hw.atomlist) {
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index bb7e0bf2960..f4cc5d3bb12 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -127,11 +127,11 @@ void r300BeginBatch(r300ContextPtr r300,
 	do { \
 	} while(0)
 
-void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom);
-int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom);
+void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom);
+int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom);
 
-void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom);
-int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom);
-int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom);
+void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom);
+int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom);
+int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom);
 
 #endif				/* __R300_CMDBUF_H__ */
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 30229ed4fbc..e631e810079 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -55,7 +55,7 @@ typedef struct r300_context *r300ContextPtr;
 #include "radeon_lock.h"
 #include "main/mm.h"
 
-/* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
+/* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
    with other compilers ... GLUE!
 */
@@ -194,24 +194,6 @@ struct r300_texture_state {
 	int tc_count;		/* number of incoming texture coordinates from VAP */
 };
 
-/**
- * A block of hardware state.
- *
- * When check returns non-zero, the returned number of dwords must be
- * copied verbatim into the command buffer in order to update a state atom
- * when it is dirty.
- */
-struct r300_state_atom {
-	struct r300_state_atom *next, *prev;
-	const char *name;	/* for debug */
-	int cmd_size;		/* maximum size in dwords */
-	GLuint idx;		/* index in an array (e.g. textures) */
-	uint32_t *cmd;
-	GLboolean dirty;
-
-	int (*check) (r300ContextPtr, struct r300_state_atom * atom);
-	void (*emit) (r300ContextPtr, struct r300_state_atom * atom);
-};
 
 #define R300_VPT_CMD_0		0
 #define R300_VPT_XSCALE		1
@@ -428,96 +410,96 @@ struct r300_state_atom {
  * Cache for hardware register state.
  */
 struct r300_hw_state {
-	struct r300_state_atom atomlist;
+	struct radeon_state_atom atomlist;
 
 	GLboolean is_dirty;
 	GLboolean all_dirty;
 	int max_state_size;	/* in dwords */
 
-	struct r300_state_atom vpt;	/* viewport (1D98) */
-	struct r300_state_atom vap_cntl;
-        struct r300_state_atom vap_index_offset; /* 0x208c r5xx only */
-	struct r300_state_atom vof;	/* VAP output format register 0x2090 */
-	struct r300_state_atom vte;	/* (20B0) */
-	struct r300_state_atom vap_vf_max_vtx_indx;	/* Maximum Vertex Indx Clamp (2134) */
-	struct r300_state_atom vap_cntl_status;
-	struct r300_state_atom vir[2];	/* vap input route (2150/21E0) */
-	struct r300_state_atom vic;	/* vap input control (2180) */
-	struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
-	struct r300_state_atom vap_clip_cntl;
-	struct r300_state_atom vap_clip;
-	struct r300_state_atom vap_pvs_vtx_timeout_reg;	/* Vertex timeout register (2288) */
-	struct r300_state_atom pvs;	/* pvs_cntl (22D0) */
-	struct r300_state_atom gb_enable;	/* (4008) */
-	struct r300_state_atom gb_misc;	/* Multisampling position shifts ? (4010) */
-	struct r300_state_atom ga_point_s0;	/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
-	struct r300_state_atom ga_triangle_stipple;	/* (4214) */
-	struct r300_state_atom ps;	/* pointsize (421C) */
-	struct r300_state_atom ga_point_minmax;	/* (4230) */
-	struct r300_state_atom lcntl;	/* line control */
-	struct r300_state_atom ga_line_stipple;	/* (4260) */
-	struct r300_state_atom shade;
-	struct r300_state_atom polygon_mode;
-	struct r300_state_atom fogp;	/* fog parameters (4294) */
-	struct r300_state_atom ga_soft_reset;	/* (429C) */
-	struct r300_state_atom zbias_cntl;
-	struct r300_state_atom zbs;	/* zbias (42A4) */
-	struct r300_state_atom occlusion_cntl;
-	struct r300_state_atom cul;	/* cull cntl (42B8) */
-	struct r300_state_atom su_depth_scale;	/* (42C0) */
-	struct r300_state_atom rc;	/* rs control (4300) */
-	struct r300_state_atom ri;	/* rs interpolators (4310) */
-	struct r300_state_atom rr;	/* rs route (4330) */
-	struct r300_state_atom sc_hyperz;	/* (43A4) */
-	struct r300_state_atom sc_screendoor;	/* (43E8) */
-	struct r300_state_atom fp;	/* fragment program cntl + nodes (4600) */
-	struct r300_state_atom fpt;	/* texi - (4620) */
-	struct r300_state_atom us_out_fmt;	/* (46A4) */
-	struct r300_state_atom r500fp;	/* r500 fp instructions */
-	struct r300_state_atom r500fp_const;	/* r500 fp constants */
-	struct r300_state_atom fpi[4];	/* fp instructions (46C0/47C0/48C0/49C0) */
-	struct r300_state_atom fogs;	/* fog state (4BC0) */
-	struct r300_state_atom fogc;	/* fog color (4BC8) */
-	struct r300_state_atom at;	/* alpha test (4BD4) */
-	struct r300_state_atom fg_depth_src;	/* (4BD8) */
-	struct r300_state_atom fpp;	/* 0x4C00 and following */
-	struct r300_state_atom rb3d_cctl;	/* (4E00) */
-	struct r300_state_atom bld;	/* blending (4E04) */
-	struct r300_state_atom cmk;	/* colormask (4E0C) */
-	struct r300_state_atom blend_color;	/* constant blend color */
-	struct r300_state_atom rop;	/* ropcntl */
-	struct r300_state_atom cb;	/* colorbuffer (4E28) */
-	struct r300_state_atom rb3d_dither_ctl;	/* (4E50) */
-	struct r300_state_atom rb3d_aaresolve_ctl;	/* (4E88) */
-	struct r300_state_atom rb3d_discard_src_pixel_lte_threshold;	/* (4E88) I saw it only written on RV350 hardware..  */
-	struct r300_state_atom zs;	/* zstencil control (4F00) */
-	struct r300_state_atom zstencil_format;
-	struct r300_state_atom zb;	/* z buffer (4F20) */
-	struct r300_state_atom zb_depthclearvalue;	/* (4F28) */
-	struct r300_state_atom unk4F30;	/* (4F30) */
-	struct r300_state_atom zb_hiz_offset;	/* (4F44) */
-	struct r300_state_atom zb_hiz_pitch;	/* (4F54) */
-
-	struct r300_state_atom vpi;	/* vp instructions */
-	struct r300_state_atom vpp;	/* vp parameters */
-	struct r300_state_atom vps;	/* vertex point size (?) */
-	struct r300_state_atom vpucp[6];	/* vp user clip plane - 6 */
+	struct radeon_state_atom vpt;	/* viewport (1D98) */
+	struct radeon_state_atom vap_cntl;
+        struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
+	struct radeon_state_atom vof;	/* VAP output format register 0x2090 */
+	struct radeon_state_atom vte;	/* (20B0) */
+	struct radeon_state_atom vap_vf_max_vtx_indx;	/* Maximum Vertex Indx Clamp (2134) */
+	struct radeon_state_atom vap_cntl_status;
+	struct radeon_state_atom vir[2];	/* vap input route (2150/21E0) */
+	struct radeon_state_atom vic;	/* vap input control (2180) */
+	struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
+	struct radeon_state_atom vap_clip_cntl;
+	struct radeon_state_atom vap_clip;
+	struct radeon_state_atom vap_pvs_vtx_timeout_reg;	/* Vertex timeout register (2288) */
+	struct radeon_state_atom pvs;	/* pvs_cntl (22D0) */
+	struct radeon_state_atom gb_enable;	/* (4008) */
+	struct radeon_state_atom gb_misc;	/* Multisampling position shifts ? (4010) */
+	struct radeon_state_atom ga_point_s0;	/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
+	struct radeon_state_atom ga_triangle_stipple;	/* (4214) */
+	struct radeon_state_atom ps;	/* pointsize (421C) */
+	struct radeon_state_atom ga_point_minmax;	/* (4230) */
+	struct radeon_state_atom lcntl;	/* line control */
+	struct radeon_state_atom ga_line_stipple;	/* (4260) */
+	struct radeon_state_atom shade;
+	struct radeon_state_atom polygon_mode;
+	struct radeon_state_atom fogp;	/* fog parameters (4294) */
+	struct radeon_state_atom ga_soft_reset;	/* (429C) */
+	struct radeon_state_atom zbias_cntl;
+	struct radeon_state_atom zbs;	/* zbias (42A4) */
+	struct radeon_state_atom occlusion_cntl;
+	struct radeon_state_atom cul;	/* cull cntl (42B8) */
+	struct radeon_state_atom su_depth_scale;	/* (42C0) */
+	struct radeon_state_atom rc;	/* rs control (4300) */
+	struct radeon_state_atom ri;	/* rs interpolators (4310) */
+	struct radeon_state_atom rr;	/* rs route (4330) */
+	struct radeon_state_atom sc_hyperz;	/* (43A4) */
+	struct radeon_state_atom sc_screendoor;	/* (43E8) */
+	struct radeon_state_atom fp;	/* fragment program cntl + nodes (4600) */
+	struct radeon_state_atom fpt;	/* texi - (4620) */
+	struct radeon_state_atom us_out_fmt;	/* (46A4) */
+	struct radeon_state_atom r500fp;	/* r500 fp instructions */
+	struct radeon_state_atom r500fp_const;	/* r500 fp constants */
+	struct radeon_state_atom fpi[4];	/* fp instructions (46C0/47C0/48C0/49C0) */
+	struct radeon_state_atom fogs;	/* fog state (4BC0) */
+	struct radeon_state_atom fogc;	/* fog color (4BC8) */
+	struct radeon_state_atom at;	/* alpha test (4BD4) */
+	struct radeon_state_atom fg_depth_src;	/* (4BD8) */
+	struct radeon_state_atom fpp;	/* 0x4C00 and following */
+	struct radeon_state_atom rb3d_cctl;	/* (4E00) */
+	struct radeon_state_atom bld;	/* blending (4E04) */
+	struct radeon_state_atom cmk;	/* colormask (4E0C) */
+	struct radeon_state_atom blend_color;	/* constant blend color */
+	struct radeon_state_atom rop;	/* ropcntl */
+	struct radeon_state_atom cb;	/* colorbuffer (4E28) */
+	struct radeon_state_atom rb3d_dither_ctl;	/* (4E50) */
+	struct radeon_state_atom rb3d_aaresolve_ctl;	/* (4E88) */
+	struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;	/* (4E88) I saw it only written on RV350 hardware..  */
+	struct radeon_state_atom zs;	/* zstencil control (4F00) */
+	struct radeon_state_atom zstencil_format;
+	struct radeon_state_atom zb;	/* z buffer (4F20) */
+	struct radeon_state_atom zb_depthclearvalue;	/* (4F28) */
+	struct radeon_state_atom unk4F30;	/* (4F30) */
+	struct radeon_state_atom zb_hiz_offset;	/* (4F44) */
+	struct radeon_state_atom zb_hiz_pitch;	/* (4F54) */
+
+	struct radeon_state_atom vpi;	/* vp instructions */
+	struct radeon_state_atom vpp;	/* vp parameters */
+	struct radeon_state_atom vps;	/* vertex point size (?) */
+	struct radeon_state_atom vpucp[6];	/* vp user clip plane - 6 */
 	/* 8 texture units */
 	/* the state is grouped by function and not by
 	   texture unit. This makes single unit updates
 	   really awkward - we are much better off
 	   updating the whole thing at once */
 	struct {
-		struct r300_state_atom filter;
-		struct r300_state_atom filter_1;
-		struct r300_state_atom size;
-		struct r300_state_atom format;
-		struct r300_state_atom pitch;
-		struct r300_state_atom offset;
-		struct r300_state_atom chroma_key;
-		struct r300_state_atom border_color;
+		struct radeon_state_atom filter;
+		struct radeon_state_atom filter_1;
+		struct radeon_state_atom size;
+		struct radeon_state_atom format;
+		struct radeon_state_atom pitch;
+		struct radeon_state_atom offset;
+		struct radeon_state_atom chroma_key;
+		struct radeon_state_atom border_color;
 	} tex;
-	struct r300_state_atom txe;	/* tex enable (4104) */
+	struct radeon_state_atom txe;	/* tex enable (4104) */
 
 	r300TexObj *textures[R300_MAX_TEXTURE_UNITS];
 };
@@ -841,10 +823,6 @@ struct r300_swtcl_info {
 
    /* Fallback rasterization functions
     */
-  //   r200_point_func draw_point;
-  //   r200_line_func draw_line;
-  //   r200_tri_func draw_tri;
-
    GLuint hw_primitive;
    GLenum render_primitive;
    GLuint numverts;
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 6d7b191b24d..064732d4583 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -387,7 +387,7 @@ static void r300EmitClearState(GLcontext * ctx)
 			FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
 		END_BATCH();
 	} else {
-		struct r300_state_atom r500fp;
+		struct radeon_state_atom r500fp;
 		uint32_t _cmd[10];
 
 		R300_STATECHANGE(r300, fp);
@@ -443,7 +443,7 @@ static void r300EmitClearState(GLcontext * ctx)
 			R500_ALU_RGBA_A_SWIZ_0;
 		
 		r500fp.cmd[7] = 0;
-		emit_r500fp(r300, &r500fp);
+		emit_r500fp(ctx, &r500fp);
 	}
 
 	BEGIN_BATCH(2);
@@ -484,7 +484,7 @@ static void r300EmitClearState(GLcontext * ctx)
 	END_BATCH();
 
 	if (has_tcl) {
-        struct r300_state_atom vpu;
+        struct radeon_state_atom vpu;
         uint32_t _cmd[10];
 		R300_STATECHANGE(r300, pvs);
 		R300_STATECHANGE(r300, vpi);
@@ -528,7 +528,7 @@ static void r300EmitClearState(GLcontext * ctx)
                                       PVS_SRC_SELECT_FORCE_0,
                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 		vpu.cmd[8] = 0x0;
-		emit_vpu(r300, &vpu);
+		emit_vpu(ctx, &vpu);
 	}
 }
 
diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h
index d5bbf2928df..7dfc3b3b914 100644
--- a/src/mesa/drivers/dri/r300/radeon_context.h
+++ b/src/mesa/drivers/dri/r300/radeon_context.h
@@ -49,20 +49,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drm.h"
 #include "dri_util.h"
 
-struct radeon_context;
-typedef struct radeon_context radeonContextRec;
-typedef struct radeon_context *radeonContextPtr;
-
-/* Rasterizing fallbacks */
-/* See correponding strings in r200_swtcl.c */
-#define RADEON_FALLBACK_TEXTURE		0x0001
-#define RADEON_FALLBACK_DRAW_BUFFER	0x0002
-#define RADEON_FALLBACK_STENCIL		0x0004
-#define RADEON_FALLBACK_RENDER_MODE	0x0008
-#define RADEON_FALLBACK_BLEND_EQ	0x0010
-#define RADEON_FALLBACK_BLEND_FUNC	0x0020
-#define RADEON_FALLBACK_DISABLE		0x0040
-#define RADEON_FALLBACK_BORDER_MODE	0x0080
+#include "radeon_screen.h"
+#include "common_context.h"
 
 #if R200_MERGED
 extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
@@ -99,96 +87,6 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
 #define TCL_FALLBACK( ctx, bit, mode )	;
 #endif
 
-struct radeon_dri_mirror {
-	__DRIcontextPrivate *context;	/* DRI context */
-	__DRIscreenPrivate *screen;	/* DRI screen */
-	/**
-	 * DRI drawable bound to this context for drawing.
-	 */
-	__DRIdrawablePrivate *drawable;
-
-	/**
-	 * DRI drawable bound to this context for reading.
-	 */
-	__DRIdrawablePrivate *readable;
-
-	drm_context_t hwContext;
-	drm_hw_lock_t *hwLock;
-	int fd;
-	int drmMinor;
-};
-
-/**
- * Derived state for internal purposes.
- */
-struct radeon_scissor_state {
-	drm_clip_rect_t rect;
-	GLboolean enabled;
-
-	GLuint numClipRects;	/* Cliprects active */
-	GLuint numAllocedClipRects;	/* Cliprects available */
-	drm_clip_rect_t *pClipRects;
-};
-
-struct radeon_colorbuffer_state {
-	GLuint clear;
-	struct radeon_renderbuffer *rrb;
-};
-
-struct radeon_state {
-	struct radeon_colorbuffer_state color;
-	struct radeon_scissor_state scissor;
-	struct radeon_renderbuffer *depth_buffer;
-};
-
-/**
- * Common per-context variables shared by R200 and R300.
- * R200- and R300-specific code "derive" their own context from this
- * structure.
- */
-struct radeon_context {
-	GLcontext *glCtx;	/* Mesa context */
-	radeonScreenPtr radeonScreen;	/* Screen private DRI data */
-
-	/* Fallback state */
-	GLuint Fallback;
-	GLuint TclFallback;
-
-	/* Page flipping */
-	GLuint doPageFlip;
-
-	/* Drawable, cliprect and scissor information */
-	GLuint numClipRects;	/* Cliprects for the draw buffer */
-	drm_clip_rect_t *pClipRects;
-	unsigned int lastStamp;
-	GLboolean lost_context;
-	drm_radeon_sarea_t *sarea;	/* Private SAREA data */
-
-	/* Mirrors of some DRI state */
-	struct radeon_dri_mirror dri;
-
-	/* Busy waiting */
-	GLuint do_usleeps;
-	GLuint do_irqs;
-	GLuint irqsEmitted;
-	drm_radeon_irq_wait_t iw;
-
-	/* buffer swap */
-	int64_t swap_ust;
-	int64_t swap_missed_ust;
-
-	GLuint swap_count;
-	GLuint swap_missed_count;
-
-	/* Derived state */
-	struct radeon_state state;
-
-	/* Configuration cache
-	 */
-	driOptionCache optionCache;
-};
-
-#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 
 extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv);
 extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
@@ -216,18 +114,6 @@ extern int RADEON_DEBUG;
 #define RADEON_DEBUG		0
 #endif
 
-#define DEBUG_TEXTURE	0x0001
-#define DEBUG_STATE	0x0002
-#define DEBUG_IOCTL	0x0004
-#define DEBUG_PRIMS	0x0008
-#define DEBUG_VERTS	0x0010
-#define DEBUG_FALLBACKS	0x0020
-#define DEBUG_VFMT	0x0040
-#define DEBUG_CODEGEN	0x0080
-#define DEBUG_VERBOSE	0x0100
-#define DEBUG_DRI       0x0200
-#define DEBUG_DMA       0x0400
-#define DEBUG_SANITY    0x0800
 #define DEBUG_SYNC      0x1000
 #define DEBUG_PIXEL     0x2000
 #define DEBUG_MEMORY    0x4000
diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h
index 471763d4180..5778adf9fb9 100644
--- a/src/mesa/drivers/dri/radeon/common_context.h
+++ b/src/mesa/drivers/dri/radeon/common_context.h
@@ -1,9 +1,18 @@
+
+#ifndef COMMON_CONTEXT_H
+#define COMMON_CONTEXT_H
 /* This union is used to avoid warnings/miscompilation
    with float to uint32_t casts due to strict-aliasing */
 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
 
+struct radeon_context;
+typedef struct radeon_context radeonContextRec;
+typedef struct radeon_context *radeonContextPtr;
+
 #include "main/mm.h"
 #include "math/m_vector.h"
+#include "texmem.h"
+#include "tnl/t_context.h"
 
 
 #define TEX_0   0x1
@@ -45,11 +54,13 @@ typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
 struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
+	struct radeon_renderbuffer *rrb;
 };
 
 struct radeon_depthbuffer_state {
 	GLuint clear;
 	GLfloat scale;
+	struct radeon_renderbuffer *rrb;
 };
 
 struct radeon_scissor_state {
@@ -76,16 +87,18 @@ struct radeon_state_atom {
 	int cmd_size;		/* size in bytes */
         GLuint idx;
 	GLuint is_tcl;
-	int *cmd;		/* one or more cmd's */
-	int *lastcmd;		/* one or more cmd's */
+        GLuint *cmd;		/* one or more cmd's */
+	GLuint *lastcmd;		/* one or more cmd's */
 	GLboolean dirty;	/* dirty-mark in emit_state_list */
-        GLboolean(*check) (GLcontext *, int idx);	/* is this state active? */
+        int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
+        void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 };
 
 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 
 /* Texture object in locally shared texture space.
  */
+#ifndef RADEON_COMMON_FOR_R300
 struct radeon_tex_obj {
 	driTextureObject base;
 
@@ -118,6 +131,7 @@ struct radeon_tex_obj {
 
 	GLuint tile_bits;	/* hw texture tile bits used on this texture */
 };
+#endif
 
 /* Need refcounting on dma buffers:
  */
@@ -145,7 +159,7 @@ struct radeon_dma {
     */
    struct radeon_dma_region current;
    
-   void (*flush)( void * );
+   void (*flush)( GLcontext *ctx );
 
    char *buf0_address;		/* start of buf[0], for index calcs */
    GLuint nr_released_bufs;	/* flush after so many buffers released */
@@ -224,3 +238,77 @@ struct radeon_dri_mirror {
 #define DEBUG_PIXEL     0x2000
 #define DEBUG_MEMORY    0x4000
 
+
+
+typedef void (*radeon_tri_func) (radeonContextPtr,
+				 radeonVertex *,
+				 radeonVertex *, radeonVertex *);
+
+typedef void (*radeon_line_func) (radeonContextPtr,
+				  radeonVertex *, radeonVertex *);
+
+typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
+
+struct r300_radeon_state {
+	struct radeon_colorbuffer_state color;
+	struct radeon_scissor_state scissor;
+	struct radeon_renderbuffer *depth_buffer;
+};
+
+struct radeon_context {
+   GLcontext *glCtx;
+   radeonScreenPtr radeonScreen;	/* Screen private DRI data */
+  
+   /* Texture object bookkeeping
+    */
+   unsigned              nr_heaps;
+   driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
+   driTextureObject      swapped;
+   int                   texture_depth;
+   float                 initialMaxAnisotropy;
+
+   /* Rasterization and vertex state:
+    */
+   GLuint TclFallback;
+   GLuint Fallback;
+   GLuint NewGLState;
+   DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */
+
+   /* Page flipping */
+   GLuint doPageFlip;
+
+   /* Drawable, cliprect and scissor information */
+   GLuint numClipRects;	/* Cliprects for the draw buffer */
+   drm_clip_rect_t *pClipRects;
+   unsigned int lastStamp;
+   GLboolean lost_context;
+   drm_radeon_sarea_t *sarea;	/* Private SAREA data */
+
+   /* Mirrors of some DRI state */
+   struct radeon_dri_mirror dri;
+
+   /* Busy waiting */
+   GLuint do_usleeps;
+   GLuint do_irqs;
+   GLuint irqsEmitted;
+   drm_radeon_irq_wait_t iw;
+
+   /* buffer swap */
+   int64_t swap_ust;
+   int64_t swap_missed_ust;
+
+   GLuint swap_count;
+   GLuint swap_missed_count;
+
+   /* Derived state - for r300 only */
+   struct r300_radeon_state state;
+
+   /* Configuration cache
+    */
+   driOptionCache optionCache;
+
+};
+
+#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index 3aa1d869f10..e3474f791bb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -40,12 +40,13 @@
 #include <sys/mman.h>
 #include <sys/ioctl.h>
 #include "xf86drm.h"
+#include "texmem.h"
 #include "drm.h"
 #include "radeon_drm.h"
 #include "radeon_bo.h"
 #include "radeon_bo_legacy.h"
 #include "radeon_ioctl.h"
-#include "texmem.h"
+
 
 struct bo_legacy {
     struct radeon_bo    base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index 1e992c0b3d6..e2b2323a65e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -84,11 +84,11 @@ int RADEON_DEBUG = (0);
  */
 static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    static char buffer[128];
    unsigned   offset;
-   GLuint agp_mode = (rmesa->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
-      rmesa->radeonScreen->AGPMode;
+   GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
+      rmesa->radeon.radeonScreen->AGPMode;
 
    switch ( name ) {
    case GL_VENDOR:
@@ -99,7 +99,7 @@ static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
 				     agp_mode );
 
       sprintf( & buffer[ offset ], " %sTCL",
-	       !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
+	       !(rmesa->radeon.TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
 	       ? "" : "NO-" );
 
       return (GLubyte *)buffer;
@@ -205,7 +205,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
    struct dd_function_table functions;
-   radeonContextPtr rmesa;
+   r100ContextPtr rmesa;
    GLcontext *ctx, *shareCtx;
    int i;
    int tcl_mode, fthrottle_mode;
@@ -215,7 +215,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    assert(screen);
 
    /* Allocate the Radeon context */
-   rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
+   rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
    if ( !rmesa )
       return GL_FALSE;
 
@@ -226,12 +226,12 @@ radeonCreateContext( const __GLcontextModes *glVisual,
     * Do this here so that initialMaxAnisotropy is set before we create
     * the default textures.
     */
-   driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
+   driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 			screen->driScreen->myNum, "radeon");
-   rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
+   rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
                                                  "def_max_anisotropy");
 
-   if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+   if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
       if ( sPriv->drm_version.minor < 13 )
 	 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 			  "disabling.\n", sPriv->drm_version.minor );
@@ -254,53 +254,53 @@ radeonCreateContext( const __GLcontextModes *glVisual,
       shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
    else
       shareCtx = NULL;
-   rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
-                                       &functions, (void *) rmesa);
-   if (!rmesa->glCtx) {
+   rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx,
+					      &functions, (void *) rmesa);
+   if (!rmesa->radeon.glCtx) {
       FREE(rmesa);
       return GL_FALSE;
    }
    driContextPriv->driverPrivate = rmesa;
 
    /* Init radeon context data */
-   rmesa->dri.context = driContextPriv;
-   rmesa->dri.screen = sPriv;
-   rmesa->dri.drawable = NULL;
-   rmesa->dri.readable = NULL;
-   rmesa->dri.hwContext = driContextPriv->hHWContext;
-   rmesa->dri.hwLock = &sPriv->pSAREA->lock;
-   rmesa->dri.fd = sPriv->fd;
-   rmesa->dri.drmMinor = sPriv->drm_version.minor;
-
-   rmesa->radeonScreen = screen;
-   rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
+   rmesa->radeon.dri.context = driContextPriv;
+   rmesa->radeon.dri.screen = sPriv;
+   rmesa->radeon.dri.drawable = NULL;
+   rmesa->radeon.dri.readable = NULL;
+   rmesa->radeon.dri.hwContext = driContextPriv->hHWContext;
+   rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock;
+   rmesa->radeon.dri.fd = sPriv->fd;
+   rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor;
+
+   rmesa->radeon.radeonScreen = screen;
+   rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
 				       screen->sarea_priv_offset);
 
 
-   rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
+   rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address;
 
-   (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
-   make_empty_list( & rmesa->swapped );
+   (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
+   make_empty_list( & rmesa->radeon.swapped );
 
-   rmesa->nr_heaps = screen->numTexHeaps;
-   for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
-      rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
+   rmesa->radeon.nr_heaps = screen->numTexHeaps;
+   for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
+      rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
 	    screen->texSize[i],
 	    12,
 	    RADEON_NR_TEX_REGIONS,
-	    (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
-	    & rmesa->sarea->tex_age[i],
-	    & rmesa->swapped,
+	    (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
+	    & rmesa->radeon.sarea->tex_age[i],
+	    & rmesa->radeon.swapped,
 	    sizeof( radeonTexObj ),
 	    (destroy_texture_object_t *) radeonDestroyTexObj );
 
-      driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
+      driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i],
 					& rmesa->c_textureSwaps );
    }
-   rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
+   rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
 					   "texture_depth");
-   if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
-      rmesa->texture_depth = ( screen->cpp == 4 ) ?
+   if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
+      rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ?
 	 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
    rmesa->swtcl.RenderIndex = ~0;
@@ -312,16 +312,16 @@ radeonCreateContext( const __GLcontextModes *glVisual,
     * setting allow larger textures.
     */
 
-   ctx = rmesa->glCtx;
-   ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
+   ctx = rmesa->radeon.glCtx;
+   ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 						 "texture_units");
    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 
-   i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures");
+   i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 
-   driCalculateMaxTextureLevels( rmesa->texture_heaps,
-				 rmesa->nr_heaps,
+   driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
+				 rmesa->radeon.nr_heaps,
 				 & ctx->Const,
 				 4,
 				 11, /* max 2D texture size is 2048x2048 */
@@ -392,17 +392,17 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    }
 
    driInitExtensions( ctx, card_extensions, GL_TRUE );
-   if (rmesa->radeonScreen->drmSupportsCubeMapsR100)
+   if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
-   if (rmesa->glCtx->Mesa_DXTn) {
+   if (rmesa->radeon.glCtx->Mesa_DXTn) {
       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
    }
-   else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
+   else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
    }
 
-   if (rmesa->dri.drmMinor >= 9)
+   if (rmesa->radeon.dri.drmMinor >= 9)
       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 
    /* XXX these should really go right after _mesa_init_driver_functions() */
@@ -415,15 +415,15 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, 
 			 ctx->Const.MaxArrayLockSize, 32 );
 
-   fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
-   rmesa->iw.irq_seq = -1;
-   rmesa->irqsEmitted = 0;
-   rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
-		     fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
+   fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
+   rmesa->radeon.iw.irq_seq = -1;
+   rmesa->radeon.irqsEmitted = 0;
+   rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
+			    fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 
-   rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
+   rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 
-   (*sPriv->systemTime->getUST)( & rmesa->swap_ust );
+   (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
 
 
 #if DO_DEBUG
@@ -431,20 +431,20 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 				       debug_control );
 #endif
 
-   tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
-   if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
+   tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
+   if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
       fprintf(stderr, "disabling 3D acceleration\n");
       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
    } else if (tcl_mode == DRI_CONF_TCL_SW ||
-	      !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
-      if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
-	 rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
+	      !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
+      if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
+	 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 	 fprintf(stderr, "Disabling HW TCL support\n");
       }
-      TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
+      TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
    }
 
-   if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
+   if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
    }
    return GL_TRUE;
@@ -458,8 +458,8 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
 {
    GET_CURRENT_CONTEXT(ctx);
-   radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
-   radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
+   r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
+   r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL;
 
    /* check if we're deleting the currently bound context */
    if (rmesa == current) {
@@ -473,14 +473,14 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
       GLboolean   release_texture_heaps;
 
 
-      release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
-      _swsetup_DestroyContext( rmesa->glCtx );
-      _tnl_DestroyContext( rmesa->glCtx );
-      _vbo_DestroyContext( rmesa->glCtx );
-      _swrast_DestroyContext( rmesa->glCtx );
+      release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
+      _swsetup_DestroyContext( rmesa->radeon.glCtx );
+      _tnl_DestroyContext( rmesa->radeon.glCtx );
+      _vbo_DestroyContext( rmesa->radeon.glCtx );
+      _swrast_DestroyContext( rmesa->radeon.glCtx );
 
-      radeonDestroySwtcl( rmesa->glCtx );
-      radeonReleaseArrays( rmesa->glCtx, ~0 );
+      radeonDestroySwtcl( rmesa->radeon.glCtx );
+      radeonReleaseArrays( rmesa->radeon.glCtx, ~0 );
       if (rmesa->dma.current.buf) {
 	 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
 	 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
@@ -499,20 +499,20 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
           */
          int i;
 
-         for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
-	    driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
-	    rmesa->texture_heaps[ i ] = NULL;
+         for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
+	    driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
+	    rmesa->radeon.texture_heaps[ i ] = NULL;
          }
 
-	 assert( is_empty_list( & rmesa->swapped ) );
+	 assert( is_empty_list( & rmesa->radeon.swapped ) );
       }
 
       /* free the Mesa context */
-      rmesa->glCtx->DriverCtx = NULL;
-      _mesa_destroy_context( rmesa->glCtx );
+      rmesa->radeon.glCtx->DriverCtx = NULL;
+      _mesa_destroy_context( rmesa->radeon.glCtx );
 
       /* free the option cache */
-      driDestroyOptionCache (&rmesa->optionCache);
+      driDestroyOptionCache (&rmesa->radeon.optionCache);
 
       FREE( rmesa );
    }
@@ -526,14 +526,14 @@ radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
 {
 
    if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
-      radeonContextPtr rmesa;
+      r100ContextPtr rmesa;
       GLcontext *ctx;
-      rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-      ctx = rmesa->glCtx;
+      rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate;
+      ctx = rmesa->radeon.glCtx;
       if (ctx->Visual.doubleBufferMode) {
          _mesa_notifySwapBuffers( ctx );  /* flush pending rendering comands */
 
-         if ( rmesa->doPageFlip ) {
+         if ( rmesa->radeon.doPageFlip ) {
             radeonPageFlip( dPriv );
          }
          else {
@@ -627,10 +627,10 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
 GLboolean
 radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
 {
-   radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
+   r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
 
    if (RADEON_DEBUG & DEBUG_DRI)
-      fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
+      fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx);
 
    return GL_TRUE;
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 167f7de6187..fb2b6eac765 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -48,32 +48,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drm.h"
 #include "radeon_drm.h"
 #include "texmem.h"
-
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/colormac.h"
-
-struct radeon_context;
-typedef struct radeon_context radeonContextRec;
-typedef struct radeon_context *radeonContextPtr;
-
-#include "radeon_lock.h"
 #include "radeon_screen.h"
 
 #include "common_context.h"
 
-#define R100_TEX_ALL 0x7
 
-typedef void (*radeon_tri_func) (radeonContextPtr,
-				 radeonVertex *,
-				 radeonVertex *, radeonVertex *);
+struct r100_context;
+typedef struct r100_context r100ContextRec;
+typedef struct r100_context *r100ContextPtr;
 
-typedef void (*radeon_line_func) (radeonContextPtr,
-				  radeonVertex *, radeonVertex *);
+#include "radeon_lock.h"
 
-typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 
 
+#define R100_TEX_ALL 0x7
 
 /* used for both tcl_vtx and vc_frmt tex bits (they are identical) */
 #define RADEON_ST_BIT(unit) \
@@ -336,9 +327,8 @@ struct radeon_hw_state {
 	GLboolean is_dirty, all_dirty;
 };
 
+
 struct radeon_state {
-	/* Derived state for internal purposes:
-	 */
 	struct radeon_colorbuffer_state color;
 	struct radeon_depthbuffer_state depth;
 	struct radeon_scissor_state scissor;
@@ -347,7 +337,7 @@ struct radeon_state {
 	struct radeon_texture_state texture;
 };
 
-#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset +			\
+#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +			\
 			(rvb)->address - rmesa->dma.buf0_address +	\
 			(rvb)->start)
 
@@ -427,29 +417,14 @@ struct radeon_swtcl_info {
  */
 #define RADEON_MAX_VERTEX_SIZE 20
 
-struct radeon_context {
-	GLcontext *glCtx;	/* Mesa context */
+struct r100_context {
+        struct radeon_context radeon;
 
 	/* Driver and hardware state management
 	 */
 	struct radeon_hw_state hw;
 	struct radeon_state state;
 
-	/* Texture object bookkeeping
-	 */
-	unsigned nr_heaps;
-	driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
-	driTextureObject swapped;
-	int texture_depth;
-	float initialMaxAnisotropy;
-
-	/* Rasterization and vertex state:
-	 */
-	GLuint TclFallback;
-	GLuint Fallback;
-	GLuint NewGLState;
-	 DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */
-
 	/* Vertex buffers
 	 */
 	struct radeon_ioctl ioctl;
@@ -460,27 +435,6 @@ struct radeon_context {
 	 */
 	struct radeon_store backup_store;
 
-	/* Page flipping
-	 */
-	GLuint doPageFlip;
-
-	/* Busy waiting
-	 */
-	GLuint do_usleeps;
-	GLuint do_irqs;
-	GLuint irqsEmitted;
-	drm_radeon_irq_wait_t iw;
-
-	/* Drawable, cliprect and scissor information
-	 */
-	GLuint numClipRects;	/* Cliprects for the draw buffer */
-	drm_clip_rect_t *pClipRects;
-	unsigned int lastStamp;
-	GLboolean lost_context;
-	GLboolean save_on_next_emit;
-	radeonScreenPtr radeonScreen;	/* Screen private DRI data */
-	drm_radeon_sarea_t *sarea;	/* Private SAREA data */
-
 	/* TCL stuff
 	 */
 	GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS];
@@ -492,14 +446,6 @@ struct radeon_context {
 	GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
 	GLuint last_ReallyEnabled;
 
-	/* VBI
-	 */
-	int64_t swap_ust;
-	int64_t swap_missed_ust;
-
-	GLuint swap_count;
-	GLuint swap_missed_count;
-
 	/* radeon_tcl.c
 	 */
 	struct radeon_tcl_info tcl;
@@ -508,14 +454,6 @@ struct radeon_context {
 	 */
 	struct radeon_swtcl_info swtcl;
 
-	/* Mirrors of some DRI state
-	 */
-	struct radeon_dri_mirror dri;
-
-	/* Configuration cache
-	 */
-	driOptionCache optionCache;
-
 	GLboolean using_hyperz;
 	GLboolean texmicrotile;
 
@@ -528,9 +466,11 @@ struct radeon_context {
 	GLuint c_textureSwaps;
 	GLuint c_textureBytes;
 	GLuint c_vertexBuffers;
+
+	GLboolean save_on_next_emit;
 };
 
-#define RADEON_CONTEXT(ctx)		((radeonContextPtr)(ctx->DriverCtx))
+#define R100_CONTEXT(ctx)		((r100ContextPtr)(ctx->DriverCtx))
 
 
 #define RADEON_OLD_PACKETS 1
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 9858dacc136..5e2b9867133 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -58,8 +58,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define RADEON_IDLE_RETRY           16
 
 
-static void radeonWaitForIdle( radeonContextPtr rmesa );
-static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, 
+static void radeonWaitForIdle( r100ContextPtr rmesa );
+static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, 
 				    const char * caller );
 
 static void print_state_atom( struct radeon_state_atom *state )
@@ -74,7 +74,7 @@ static void print_state_atom( struct radeon_state_atom *state )
 
 }
 
-static void radeonSaveHwState( radeonContextPtr rmesa )
+static void radeonSaveHwState( r100ContextPtr rmesa )
 {
    struct radeon_state_atom *atom;
    char * dest = rmesa->backup_store.cmd_buf;
@@ -85,7 +85,7 @@ static void radeonSaveHwState( radeonContextPtr rmesa )
    rmesa->backup_store.cmd_used = 0;
 
    foreach( atom, &rmesa->hw.atomlist ) {
-      if ( atom->check( rmesa->glCtx, 0 ) ) {
+      if ( atom->check( rmesa->radeon.glCtx, 0 ) ) {
 	 int size = atom->cmd_size * 4;
 	 memcpy( dest, atom->cmd, size);
 	 dest += size;
@@ -105,7 +105,7 @@ static void radeonSaveHwState( radeonContextPtr rmesa )
  * it, flush it, and then put the current one back.  This is so commands at the
  * start of a cmdbuf can rely on the state being kept from the previous one.
  */
-static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa )
+static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa )
 {
    GLuint nr_released_bufs;
    struct radeon_store saved_store;
@@ -116,7 +116,7 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa )
    if (RADEON_DEBUG & DEBUG_STATE)
       fprintf(stderr, "Emitting backup state on lost context\n");
 
-   rmesa->lost_context = GL_FALSE;
+   rmesa->radeon.lost_context = GL_FALSE;
 
    nr_released_bufs = rmesa->dma.nr_released_bufs;
    saved_store = rmesa->store;
@@ -134,9 +134,9 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa )
 /* The state atoms will be emitted in the order they appear in the atom list,
  * so this step is important.
  */
-void radeonSetUpAtomList( radeonContextPtr rmesa )
+void radeonSetUpAtomList( r100ContextPtr rmesa )
 {
-   int i, mtu = rmesa->glCtx->Const.MaxTextureUnits;
+   int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
 
    make_empty_list(&rmesa->hw.atomlist);
    rmesa->hw.atomlist.name = "atom-list";
@@ -167,7 +167,7 @@ void radeonSetUpAtomList( radeonContextPtr rmesa )
    insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt);
 }
 
-void radeonEmitState( radeonContextPtr rmesa )
+void radeonEmitState( r100ContextPtr rmesa )
 {
    struct radeon_state_atom *atom;
    char *dest;
@@ -198,7 +198,7 @@ void radeonEmitState( radeonContextPtr rmesa )
    if (RADEON_DEBUG & DEBUG_STATE) {
       foreach(atom, &rmesa->hw.atomlist) {
 	 if (atom->dirty || rmesa->hw.all_dirty) {
-	    if (atom->check(rmesa->glCtx, 0))
+	    if (atom->check(rmesa->radeon.glCtx, 0))
 	       print_state_atom(atom);
 	    else
 	       fprintf(stderr, "skip state %s\n", atom->name);
@@ -209,11 +209,11 @@ void radeonEmitState( radeonContextPtr rmesa )
    foreach(atom, &rmesa->hw.atomlist) {
       if (rmesa->hw.all_dirty)
 	 atom->dirty = GL_TRUE;
-      if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) &&
+      if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) &&
 	   atom->is_tcl)
 	 atom->dirty = GL_FALSE;
       if (atom->dirty) {
-	if (atom->check(rmesa->glCtx, 0)) {
+	if (atom->check(rmesa->radeon.glCtx, 0)) {
 	    int size = atom->cmd_size * 4;
 	    memcpy(dest, atom->cmd, size);
 	    dest += size;
@@ -232,7 +232,7 @@ void radeonEmitState( radeonContextPtr rmesa )
 /* Fire a section of the retained (indexed_verts) buffer as a regular
  * primtive.  
  */
-extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
+extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
 				GLuint vertex_format,
 				GLuint primitive,
 				GLuint vertex_nr )
@@ -288,8 +288,9 @@ extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
 }
 
 
-void radeonFlushElts( radeonContextPtr rmesa )
+void radeonFlushElts( GLcontext *ctx )
 {
+  r100ContextPtr rmesa = R100_CONTEXT(ctx);
    int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
    int dwords;
 #if RADEON_OLD_PACKETS
@@ -319,12 +320,12 @@ void radeonFlushElts( radeonContextPtr rmesa )
 
    if (RADEON_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
-      radeonFinish( rmesa->glCtx );
+      radeonFinish( rmesa->radeon.glCtx );
    }
 }
 
 
-GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
+GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
 				    GLuint vertex_format,
 				    GLuint primitive,
 				    GLuint min_nr )
@@ -375,7 +376,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
 	      cmd[1].i, vertex_format, primitive);
 
    assert(!rmesa->dma.flush);
-   rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+   rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
    rmesa->dma.flush = radeonFlushElts;
 
    rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
@@ -385,7 +386,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
 
 
 
-void radeonEmitVertexAOS( radeonContextPtr rmesa,
+void radeonEmitVertexAOS( r100ContextPtr rmesa,
 			  GLuint vertex_size,
 			  GLuint offset )
 {
@@ -412,7 +413,7 @@ void radeonEmitVertexAOS( radeonContextPtr rmesa,
 }
 		       
 
-void radeonEmitAOS( radeonContextPtr rmesa,
+void radeonEmitAOS( r100ContextPtr rmesa,
 		    struct radeon_dma_region **component,
 		    GLuint nr,
 		    GLuint offset )
@@ -467,7 +468,7 @@ void radeonEmitAOS( radeonContextPtr rmesa,
 }
 
 /* using already shifted color_fmt! */
-void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is required? */
+void radeonEmitBlit( r100ContextPtr rmesa, /* FIXME: which drmMinor is required? */
 		   GLuint color_fmt,
 		   GLuint src_pitch,
 		   GLuint src_offset,
@@ -518,7 +519,7 @@ void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is require
 }
 
 
-void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
+void radeonEmitWait( r100ContextPtr rmesa, GLuint flags )
 {
    drm_radeon_cmd_header_t *cmd;
 
@@ -532,13 +533,13 @@ void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
 }
 
 
-static int radeonFlushCmdBufLocked( radeonContextPtr rmesa, 
+static int radeonFlushCmdBufLocked( r100ContextPtr rmesa, 
 				    const char * caller )
 {
    int ret, i;
    drm_radeon_cmd_buffer_t cmd;
 
-   if (rmesa->lost_context)
+   if (rmesa->radeon.lost_context)
       radeonBackUpAndEmitLostStateLocked(rmesa);
 
    if (RADEON_DEBUG & DEBUG_IOCTL) {
@@ -562,8 +563,8 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
 				      rmesa->state.scissor.pClipRects);
       else
 	 ret = radeonSanityCmdBuffer( rmesa, 
-				      rmesa->numClipRects,
-				      rmesa->pClipRects);
+				      rmesa->radeon.numClipRects,
+				      rmesa->radeon.pClipRects);
       if (ret) {
 	 fprintf(stderr, "drmSanityCommandWrite: %d\n", ret);	 
 	 goto out;
@@ -578,11 +579,11 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
       cmd.nbox = rmesa->state.scissor.numClipRects;
       cmd.boxes = rmesa->state.scissor.pClipRects;
    } else {
-      cmd.nbox = rmesa->numClipRects;
-      cmd.boxes = rmesa->pClipRects;
+      cmd.nbox = rmesa->radeon.numClipRects;
+      cmd.boxes = rmesa->radeon.pClipRects;
    }
 
-   ret = drmCommandWrite( rmesa->dri.fd,
+   ret = drmCommandWrite( rmesa->radeon.dri.fd,
 			  DRM_RADEON_CMDBUF,
 			  &cmd, sizeof(cmd) );
 
@@ -608,7 +609,7 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
 /* Note: does not emit any commands to avoid recursion on
  * radeonAllocCmdBuf.
  */
-void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
+void radeonFlushCmdBuf( r100ContextPtr rmesa, const char *caller )
 {
    int ret;
 
@@ -630,10 +631,10 @@ void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
  */
 
 
-void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
+void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa )
 {
    struct radeon_dma_buffer *dmabuf;
-   int fd = rmesa->dri.fd;
+   int fd = rmesa->radeon.dri.fd;
    int index = 0;
    int size = 0;
    drmDMAReq dma;
@@ -643,7 +644,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
       fprintf(stderr, "%s\n", __FUNCTION__);  
 
    if (rmesa->dma.flush) {
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
    }
 
    if (rmesa->dma.current.buf)
@@ -652,7 +653,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
    if (rmesa->dma.nr_released_bufs > 4)
       radeonFlushCmdBuf( rmesa, __FUNCTION__ );
 
-   dma.context = rmesa->dri.hwContext;
+   dma.context = rmesa->radeon.dri.hwContext;
    dma.send_count = 0;
    dma.send_list = NULL;
    dma.send_sizes = NULL;
@@ -693,7 +694,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
       fprintf(stderr, "Allocated buffer %d\n", index);
 
    dmabuf = CALLOC_STRUCT( radeon_dma_buffer );
-   dmabuf->buf = &rmesa->radeonScreen->buffers->list[index];
+   dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index];
    dmabuf->refcount = 1;
 
    rmesa->dma.current.buf = dmabuf;
@@ -705,7 +706,7 @@ void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
    rmesa->c_vertexBuffers++;
 }
 
-void radeonReleaseDmaRegion( radeonContextPtr rmesa,
+void radeonReleaseDmaRegion( r100ContextPtr rmesa,
 			     struct radeon_dma_region *region,
 			     const char *caller )
 {
@@ -716,7 +717,7 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa,
       return;
 
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
 
    if (--region->buf->refcount == 0) {
       drm_radeon_cmd_header_t *cmd;
@@ -740,7 +741,7 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa,
 /* Allocates a region from rmesa->dma.current.  If there isn't enough
  * space in current, grab a new buffer (and discard what was left of current)
  */
-void radeonAllocDmaRegion( radeonContextPtr rmesa, 
+void radeonAllocDmaRegion( r100ContextPtr rmesa, 
 			   struct radeon_dma_region *region,
 			   int bytes,
 			   int alignment )
@@ -749,7 +750,7 @@ void radeonAllocDmaRegion( radeonContextPtr rmesa,
       fprintf(stderr, "%s %d\n", __FUNCTION__, bytes);
 
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
 
    if (region->buf)
       radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ );
@@ -777,7 +778,7 @@ void radeonAllocDmaRegion( radeonContextPtr rmesa,
  * SwapBuffers with client-side throttling
  */
 
-static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) 
+static uint32_t radeonGetLastFrame (r100ContextPtr rmesa) 
 {
    drm_radeon_getparam_t gp;
    int ret;
@@ -785,7 +786,7 @@ static uint32_t radeonGetLastFrame (radeonContextPtr rmesa)
 
    gp.param = RADEON_PARAM_LAST_FRAME;
    gp.value = (int *)&frame;
-   ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM,
+   ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_GETPARAM,
 			      &gp, sizeof(gp) );
 
    if ( ret ) {
@@ -796,13 +797,13 @@ static uint32_t radeonGetLastFrame (radeonContextPtr rmesa)
    return frame;
 }
 
-static void radeonEmitIrqLocked( radeonContextPtr rmesa )
+static void radeonEmitIrqLocked( r100ContextPtr rmesa )
 {
    drm_radeon_irq_emit_t ie;
    int ret;
 
-   ie.irq_seq = &rmesa->iw.irq_seq;
-   ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT, 
+   ie.irq_seq = &rmesa->radeon.iw.irq_seq;
+   ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_EMIT, 
 			      &ie, sizeof(ie) );
    if ( ret ) {
       fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret );
@@ -811,13 +812,13 @@ static void radeonEmitIrqLocked( radeonContextPtr rmesa )
 }
 
 
-static void radeonWaitIrq( radeonContextPtr rmesa )
+static void radeonWaitIrq( r100ContextPtr rmesa )
 {
    int ret;
 
    do {
-      ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_IRQ_WAIT,
-			     &rmesa->iw, sizeof(rmesa->iw) );
+      ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_IRQ_WAIT,
+			     &rmesa->radeon.iw, sizeof(rmesa->radeon.iw) );
    } while (ret && (errno == EINTR || errno == EBUSY));
 
    if ( ret ) {
@@ -827,13 +828,13 @@ static void radeonWaitIrq( radeonContextPtr rmesa )
 }
 
 
-static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
+static void radeonWaitForFrameCompletion( r100ContextPtr rmesa )
 {
-   drm_radeon_sarea_t *sarea = rmesa->sarea;
+   drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
 
-   if (rmesa->do_irqs) {
+   if (rmesa->radeon.do_irqs) {
       if (radeonGetLastFrame(rmesa) < sarea->last_frame) {
-	 if (!rmesa->irqsEmitted) {
+	 if (!rmesa->radeon.irqsEmitted) {
 	    while (radeonGetLastFrame (rmesa) < sarea->last_frame)
 	       ;
 	 }
@@ -842,18 +843,18 @@ static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
 	    radeonWaitIrq( rmesa );	
 	    LOCK_HARDWARE( rmesa ); 
 	 }
-	 rmesa->irqsEmitted = 10;
+	 rmesa->radeon.irqsEmitted = 10;
       }
 
-      if (rmesa->irqsEmitted) {
+      if (rmesa->radeon.irqsEmitted) {
 	 radeonEmitIrqLocked( rmesa );
-	 rmesa->irqsEmitted--;
+	 rmesa->radeon.irqsEmitted--;
       }
    } 
    else {
       while (radeonGetLastFrame (rmesa) < sarea->last_frame) {
 	 UNLOCK_HARDWARE( rmesa ); 
-	 if (rmesa->do_usleeps) 
+	 if (rmesa->radeon.do_usleeps) 
 	    DO_USLEEP( 1 );
 	 LOCK_HARDWARE( rmesa ); 
       }
@@ -865,7 +866,7 @@ static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
 void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 		       const drm_clip_rect_t	  *rect)
 {
-   radeonContextPtr rmesa;
+   r100ContextPtr rmesa;
    GLint nbox, i, ret;
    GLboolean   missed_target;
    int64_t ust;
@@ -875,10 +876,10 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
    assert(dPriv->driContextPriv);
    assert(dPriv->driContextPriv->driverPrivate);
 
-   rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
+   rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate;
 
    if ( RADEON_DEBUG & DEBUG_IOCTL ) {
-      fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx );
+      fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->radeon.glCtx );
    }
 
    RADEON_FIREVERTICES( rmesa );
@@ -900,7 +901,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
    for ( i = 0 ; i < nbox ; ) {
       GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
       drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t *b = rmesa->sarea->boxes;
+      drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
       GLint n = 0;
 
       for ( ; i < nr ; i++ ) {
@@ -925,12 +926,12 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 	  b++;
 	  n++;
       }
-      rmesa->sarea->nbox = n;
+      rmesa->radeon.sarea->nbox = n;
 
       if (!n)
 	 continue;
 
-      ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
+      ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_SWAP );
 
       if ( ret ) {
 	 fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret );
@@ -943,21 +944,21 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
    if (!rect)
    {
        psp = dPriv->driScreenPriv;
-       rmesa->swap_count++;
+       rmesa->radeon.swap_count++;
        (*psp->systemTime->getUST)( & ust );
        if ( missed_target ) {
-	   rmesa->swap_missed_count++;
-	   rmesa->swap_missed_ust = ust - rmesa->swap_ust;
+	   rmesa->radeon.swap_missed_count++;
+	   rmesa->radeon.swap_missed_ust = ust - rmesa->radeon.swap_ust;
        }
 
-       rmesa->swap_ust = ust;
+       rmesa->radeon.swap_ust = ust;
        rmesa->hw.all_dirty = GL_TRUE;
    }
 }
 
 void radeonPageFlip( __DRIdrawablePrivate *dPriv )
 {
-   radeonContextPtr rmesa;
+   r100ContextPtr rmesa;
    GLint ret;
    GLboolean   missed_target;
    __DRIscreenPrivate *psp;
@@ -966,12 +967,12 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
    assert(dPriv->driContextPriv);
    assert(dPriv->driContextPriv->driverPrivate);
 
-   rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
+   rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate;
    psp = dPriv->driScreenPriv;
 
    if ( RADEON_DEBUG & DEBUG_IOCTL ) {
       fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
-	      rmesa->sarea->pfCurrentPage);
+	      rmesa->radeon.sarea->pfCurrentPage);
    }
 
    RADEON_FIREVERTICES( rmesa );
@@ -982,9 +983,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
    if (dPriv->numClipRects)
    {
       drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t *b = rmesa->sarea->boxes;
+      drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
       b[0] = box[0];
-      rmesa->sarea->nbox = 1;
+      rmesa->radeon.sarea->nbox = 1;
    }
 
    /* Throttle the frame rate -- only allow a few pending swap buffers
@@ -994,12 +995,12 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
    UNLOCK_HARDWARE( rmesa );
    driWaitForVBlank( dPriv, & missed_target );
    if ( missed_target ) {
-      rmesa->swap_missed_count++;
-      (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust );
+      rmesa->radeon.swap_missed_count++;
+      (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_missed_ust );
    }
    LOCK_HARDWARE( rmesa );
 
-   ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP );
+   ret = drmCommandNone( rmesa->radeon.dri.fd, DRM_RADEON_FLIP );
 
    UNLOCK_HARDWARE( rmesa );
 
@@ -1008,16 +1009,16 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
       exit( 1 );
    }
 
-   rmesa->swap_count++;
-   (void) (*psp->systemTime->getUST)( & rmesa->swap_ust );
+   rmesa->radeon.swap_count++;
+   (void) (*psp->systemTime->getUST)( & rmesa->radeon.swap_ust );
 
    /* Get ready for drawing next frame.  Update the renderbuffers'
     * flippedOffset/Pitch fields so we draw into the right place.
     */
-   driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
-                        rmesa->sarea->pfCurrentPage);
+   driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer,
+                        rmesa->radeon.sarea->pfCurrentPage);
 
-   radeonUpdateDrawBuffer(rmesa->glCtx);
+   radeonUpdateDrawBuffer(rmesa->radeon.glCtx);
 }
 
 
@@ -1028,9 +1029,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
 
 static void radeonClear( GLcontext *ctx, GLbitfield mask )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
-   drm_radeon_sarea_t *sarea = rmesa->sarea;
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
    uint32_t clear;
    GLuint flags = 0;
    GLuint color_mask = 0;
@@ -1083,7 +1084,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 
    if (rmesa->using_hyperz) {
       flags |= RADEON_USE_COMP_ZBUF;
-/*      if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) 
+/*      if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) 
          flags |= RADEON_USE_HIERZ; */
       if (!(rmesa->state.stencil.hwBuffer) ||
 	 ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
@@ -1112,7 +1113,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 
       gp.param = RADEON_PARAM_LAST_CLEAR;
       gp.value = (int *)&clear;
-      ret = drmCommandWriteRead( rmesa->dri.fd,
+      ret = drmCommandWriteRead( rmesa->radeon.dri.fd,
 				 DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
 
       if ( ret ) {
@@ -1124,7 +1125,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 	 break;
       }
 
-      if ( rmesa->do_usleeps ) {
+      if ( rmesa->radeon.do_usleeps ) {
 	 UNLOCK_HARDWARE( rmesa );
 	 DO_USLEEP( 1 );
 	 LOCK_HARDWARE( rmesa );
@@ -1137,7 +1138,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
    for ( i = 0 ; i < dPriv->numClipRects ; ) {
       GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
       drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t *b = rmesa->sarea->boxes;
+      drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
       drm_radeon_clear_t clear;
       drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
       GLint n = 0;
@@ -1172,7 +1173,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 	 }
       }
 
-      rmesa->sarea->nbox = n;
+      rmesa->radeon.sarea->nbox = n;
 
       clear.flags       = flags;
       clear.clear_color = rmesa->state.color.clear;
@@ -1182,7 +1183,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
       clear.depth_boxes = depth_boxes;
 
       n--;
-      b = rmesa->sarea->boxes;
+      b = rmesa->radeon.sarea->boxes;
       for ( ; n >= 0 ; n-- ) {
 	 depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
 	 depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
@@ -1192,7 +1193,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 	    (float)rmesa->state.depth.clear;
       }
 
-      ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
+      ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR,
 			     &clear, sizeof(drm_radeon_clear_t));
 
       if ( ret ) {
@@ -1207,9 +1208,9 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
 }
 
 
-void radeonWaitForIdleLocked( radeonContextPtr rmesa )
+void radeonWaitForIdleLocked( r100ContextPtr rmesa )
 {
-    int fd = rmesa->dri.fd;
+    int fd = rmesa->radeon.dri.fd;
     int to = 0;
     int ret, i = 0;
 
@@ -1229,7 +1230,7 @@ void radeonWaitForIdleLocked( radeonContextPtr rmesa )
 }
 
 
-static void radeonWaitForIdle( radeonContextPtr rmesa )
+static void radeonWaitForIdle( r100ContextPtr rmesa )
 {
    LOCK_HARDWARE(rmesa);
    radeonWaitForIdleLocked( rmesa );
@@ -1239,13 +1240,13 @@ static void radeonWaitForIdle( radeonContextPtr rmesa )
 
 void radeonFlush( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
 
    if (RADEON_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
 
    radeonEmitState( rmesa );
    
@@ -1258,10 +1259,10 @@ void radeonFlush( GLcontext *ctx )
  */
 void radeonFinish( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    radeonFlush( ctx );
 
-   if (rmesa->do_irqs) {
+   if (rmesa->radeon.do_irqs) {
       LOCK_HARDWARE( rmesa );
       radeonEmitIrqLocked( rmesa );
       UNLOCK_HARDWARE( rmesa );
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
index 4e3a44df075..c97f41d9a1f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
@@ -40,29 +40,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_lock.h"
 
 
-extern void radeonEmitState( radeonContextPtr rmesa );
-extern void radeonEmitVertexAOS( radeonContextPtr rmesa,
+extern void radeonEmitState( r100ContextPtr rmesa );
+extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
 				 GLuint vertex_size,
 				 GLuint offset );
 
-extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
+extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
 				GLuint vertex_format,
 				GLuint primitive,
 				GLuint vertex_nr );
 
-extern void radeonFlushElts( radeonContextPtr rmesa );
+extern void radeonFlushElts( GLcontext *ctx );
+			    
 
-extern GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
+extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
 					   GLuint vertex_format,
 					   GLuint primitive,
 					   GLuint min_nr );
 
-extern void radeonEmitAOS( radeonContextPtr rmesa,
+extern void radeonEmitAOS( r100ContextPtr rmesa,
 			   struct radeon_dma_region **regions,
 			   GLuint n,
 			   GLuint offset );
 
-extern void radeonEmitBlit( radeonContextPtr rmesa,
+extern void radeonEmitBlit( r100ContextPtr rmesa,
 			    GLuint color_fmt,
 			    GLuint src_pitch,
 			    GLuint src_offset,
@@ -72,17 +73,17 @@ extern void radeonEmitBlit( radeonContextPtr rmesa,
 			    GLint dstx, GLint dsty,
 			    GLuint w, GLuint h );
 
-extern void radeonEmitWait( radeonContextPtr rmesa, GLuint flags );
+extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags );
 
-extern void radeonFlushCmdBuf( radeonContextPtr rmesa, const char * );
-extern void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa );
+extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * );
+extern void radeonRefillCurrentDmaRegion( r100ContextPtr rmesa );
 
-extern void radeonAllocDmaRegion( radeonContextPtr rmesa,
+extern void radeonAllocDmaRegion( r100ContextPtr rmesa,
 				  struct radeon_dma_region *region,
 				  int bytes, 
 				  int alignment );
 
-extern void radeonReleaseDmaRegion( radeonContextPtr rmesa,
+extern void radeonReleaseDmaRegion( r100ContextPtr rmesa,
 				    struct radeon_dma_region *region,
 				    const char *caller );
 
@@ -91,11 +92,11 @@ extern void radeonCopyBuffer( __DRIdrawablePrivate *drawable,
 extern void radeonPageFlip( __DRIdrawablePrivate *drawable );
 extern void radeonFlush( GLcontext *ctx );
 extern void radeonFinish( GLcontext *ctx );
-extern void radeonWaitForIdleLocked( radeonContextPtr rmesa );
-extern void radeonWaitForVBlank( radeonContextPtr rmesa );
+extern void radeonWaitForIdleLocked( r100ContextPtr rmesa );
+extern void radeonWaitForVBlank( r100ContextPtr rmesa );
 extern void radeonInitIoctlFuncs( GLcontext *ctx );
-extern void radeonGetAllParams( radeonContextPtr rmesa );
-extern void radeonSetUpAtomList( radeonContextPtr rmesa );
+extern void radeonGetAllParams( r100ContextPtr rmesa );
+extern void radeonSetUpAtomList( r100ContextPtr rmesa );
 
 /* ================================================================
  * Helper macros:
@@ -106,7 +107,7 @@ extern void radeonSetUpAtomList( radeonContextPtr rmesa );
 #define RADEON_NEWPRIM( rmesa )			\
 do {						\
    if ( rmesa->dma.flush )			\
-      rmesa->dma.flush( rmesa );	\
+      rmesa->dma.flush( rmesa->radeon.glCtx );	\
 } while (0)
 
 /* Can accomodate several state changes and primitive changes without
@@ -124,11 +125,11 @@ do {								\
 	   rmesa->hw.ATOM.cmd_size * 4)
 
 static INLINE int RADEON_DB_STATECHANGE( 
-   radeonContextPtr rmesa,
+   r100ContextPtr rmesa,
    struct radeon_state_atom *atom )
 {
    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
-      int *tmp;
+      GLuint *tmp;
       RADEON_NEWPRIM( rmesa );
       atom->dirty = GL_TRUE;
       rmesa->hw.is_dirty = GL_TRUE;
@@ -147,7 +148,7 @@ static INLINE int RADEON_DB_STATECHANGE(
 #define RADEON_FIREVERTICES( rmesa )			\
 do {							\
    if ( rmesa->store.cmd_used || rmesa->dma.flush ) {	\
-      radeonFlush( rmesa->glCtx );			\
+      radeonFlush( rmesa->radeon.glCtx );			\
    }							\
 } while (0)
 
@@ -176,7 +177,7 @@ do {							\
  * and hang on to the lock until the critical section is finished and we flush
  * the buffer again and unlock.
  */
-static INLINE void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
+static INLINE void radeonEnsureCmdBufSpace( r100ContextPtr rmesa,
 					      int bytes )
 {
    if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
@@ -186,7 +187,7 @@ static INLINE void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
 
 /* Alloc space in the command buffer
  */
-static INLINE char *radeonAllocCmdBuf( radeonContextPtr rmesa,
+static INLINE char *radeonAllocCmdBuf( r100ContextPtr rmesa,
 					 int bytes, const char *where )
 {
    if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index 64bb3ca103f..0cf5574ba6e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -56,12 +56,12 @@ int prevLockLine = 0;
 
 /* Turn on/off page flipping according to the flags in the sarea:
  */
-static void radeonUpdatePageFlipping(radeonContextPtr rmesa)
+static void radeonUpdatePageFlipping(r100ContextPtr rmesa)
 {
-	rmesa->doPageFlip = rmesa->sarea->pfState;
-	if (rmesa->glCtx->WinSysDrawBuffer) {
-		driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
-				     rmesa->sarea->pfCurrentPage);
+	rmesa->radeon.doPageFlip = rmesa->radeon.sarea->pfState;
+	if (rmesa->radeon.glCtx->WinSysDrawBuffer) {
+		driFlipRenderbuffers(rmesa->radeon.glCtx->WinSysDrawBuffer,
+				     rmesa->radeon.sarea->pfCurrentPage);
 	}
 }
 
@@ -73,14 +73,14 @@ static void radeonUpdatePageFlipping(radeonContextPtr rmesa)
  * the hardware lock when it changes the window state, this routine will
  * automatically be called after such a change.
  */
-void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
+void radeonGetLock(r100ContextPtr rmesa, GLuint flags)
 {
-	__DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
-	__DRIdrawablePrivate *const readable = rmesa->dri.readable;
-	__DRIscreenPrivate *sPriv = rmesa->dri.screen;
-	drm_radeon_sarea_t *sarea = rmesa->sarea;
+	__DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable;
+	__DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable;
+	__DRIscreenPrivate *sPriv = rmesa->radeon.dri.screen;
+	drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
 
-	drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags);
+	drmGetLock(rmesa->radeon.dri.fd, rmesa->radeon.dri.hwContext, flags);
 
 	/* The window might have moved, so we might need to get new clip
 	 * rects.
@@ -95,15 +95,15 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 		DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable);
 	}
 
-	if (rmesa->lastStamp != drawable->lastStamp) {
+	if (rmesa->radeon.lastStamp != drawable->lastStamp) {
 		radeonUpdatePageFlipping(rmesa);
 		radeonSetCliprects(rmesa);
-		radeonUpdateViewportOffset(rmesa->glCtx);
-		driUpdateFramebufferSize(rmesa->glCtx, drawable);
+		radeonUpdateViewportOffset(rmesa->radeon.glCtx);
+		driUpdateFramebufferSize(rmesa->radeon.glCtx, drawable);
 	}
 
 	RADEON_STATECHANGE(rmesa, ctx);
-	if (rmesa->sarea->tiling_enabled) {
+	if (rmesa->radeon.sarea->tiling_enabled) {
 		rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 		    RADEON_COLOR_TILE_ENABLE;
 	} else {
@@ -111,14 +111,14 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 		    ~RADEON_COLOR_TILE_ENABLE;
 	}
 
-	if (sarea->ctx_owner != rmesa->dri.hwContext) {
+	if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 		int i;
-		sarea->ctx_owner = rmesa->dri.hwContext;
+		sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 
-		for (i = 0; i < rmesa->nr_heaps; i++) {
-			DRI_AGE_TEXTURES(rmesa->texture_heaps[i]);
+		for (i = 0; i < rmesa->radeon.nr_heaps; i++) {
+			DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]);
 		}
 	}
 
-	rmesa->lost_context = GL_TRUE;
+	rmesa->radeon.lost_context = GL_TRUE;
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h
index 86e96aa7d2c..e4bfa1b9d67 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.h
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.h
@@ -42,7 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef __RADEON_LOCK_H__
 #define __RADEON_LOCK_H__
 
-extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags);
+extern void radeonGetLock(r100ContextPtr rmesa, GLuint flags);
 
 /* Turn DEBUG_LOCKING on to find locking conflicts.
  */
@@ -94,8 +94,8 @@ extern int prevLockLine;
    do {								\
       char __ret = 0;						\
       DEBUG_CHECK_LOCK();					\
-      DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext,		\
-	       (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret );	\
+      DRM_CAS( (rmesa)->radeon.dri.hwLock, (rmesa)->radeon.dri.hwContext,		\
+	       (DRM_LOCK_HELD | (rmesa)->radeon.dri.hwContext), __ret );	\
       if ( __ret )						\
 	 radeonGetLock( (rmesa), 0 );				\
       DEBUG_LOCK();						\
@@ -103,9 +103,9 @@ extern int prevLockLine;
 
 #define UNLOCK_HARDWARE( rmesa )					\
    do {									\
-      DRM_UNLOCK( (rmesa)->dri.fd,					\
-		  (rmesa)->dri.hwLock,					\
-		  (rmesa)->dri.hwContext );				\
+      DRM_UNLOCK( (rmesa)->radeon.dri.fd,					\
+		  (rmesa)->radeon.dri.hwLock,					\
+		  (rmesa)->radeon.dri.hwContext );				\
       DEBUG_RESET();							\
    } while (0)
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
index 126d0727c63..2abf644ef2d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
@@ -310,7 +310,7 @@ static void init_tcl_verts( void )
 
 void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
    GLuint req = 0;
    GLuint unit;
@@ -437,7 +437,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 
 void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
 
 #if 0
    if (RADEON_DEBUG & DEBUG_VERTS) 
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index 6613757fcea..bbed838b592 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -973,7 +973,7 @@ static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
 }
 
 
-int radeonSanityCmdBuffer( radeonContextPtr rmesa,
+int radeonSanityCmdBuffer( r100ContextPtr rmesa,
 			   int nbox,
 			   drm_clip_rect_t *boxes )
 {
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.h b/src/mesa/drivers/dri/radeon/radeon_sanity.h
index 1ec06bc586b..f30eb1c4f15 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.h
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.h
@@ -1,7 +1,7 @@
 #ifndef RADEON_SANITY_H
 #define RADEON_SANITY_H
 
-extern int radeonSanityCmdBuffer( radeonContextPtr rmesa,
+extern int radeonSanityCmdBuffer( r100ContextPtr rmesa,
 				  int nbox,
 				  drm_clip_rect_t *boxes );
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 080fbfe5f41..0b64d6f4ac5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1572,11 +1572,7 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
 static int
 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 {
-#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
    radeonContextPtr  rmesa;
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
-   r200ContextPtr  rmesa;
-#endif
 
    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
 	|| (dPriv->driContextPriv->driverPrivate == NULL)
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 12051ff1c81..9733025fa9f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -282,16 +282,19 @@ static void radeonSpanRenderStart(GLcontext * ctx)
 #ifdef COMPILE_R300
 	r300ContextPtr r300 = (r300ContextPtr) rmesa;
 	R300_FIREVERTICES(r300);
+	LOCK_HARDWARE(rmesa);
 #else
-	RADEON_FIREVERTICES(rmesa);
+	r100ContextPtr r100 = (r100ContextPtr) rmesa;
+	RADEON_FIREVERTICES(r100);
+	LOCK_HARDWARE(r100);
 #endif
-	LOCK_HARDWARE(rmesa);
+
 	radeonWaitForIdleLocked(rmesa);
 }
 
 static void radeonSpanRenderFinish(GLcontext * ctx)
 {
-	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+	r100ContextPtr rmesa = R100_CONTEXT(ctx);
 	_swrast_flush(ctx);
 	UNLOCK_HARDWARE(rmesa);
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 32bcff33602..7e5306073f6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -62,7 +62,7 @@ static void radeonUpdateSpecular( GLcontext *ctx );
 
 static void radeonAlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
    GLubyte refByte;
 
@@ -106,7 +106,7 @@ static void radeonAlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref )
 static void radeonBlendEquationSeparate( GLcontext *ctx,
 					 GLenum modeRGB, GLenum modeA )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK;
    GLboolean fallback = GL_FALSE;
 
@@ -147,7 +147,7 @@ static void radeonBlendFuncSeparate( GLcontext *ctx,
 				     GLenum sfactorRGB, GLenum dfactorRGB,
 				     GLenum sfactorA, GLenum dfactorA )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & 
       ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK);
    GLboolean fallback = GL_FALSE;
@@ -257,7 +257,7 @@ static void radeonBlendFuncSeparate( GLcontext *ctx,
 
 static void radeonDepthFunc( GLcontext *ctx, GLenum func )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    RADEON_STATECHANGE( rmesa, ctx );
    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK;
@@ -293,7 +293,7 @@ static void radeonDepthFunc( GLcontext *ctx, GLenum func )
 
 static void radeonDepthMask( GLcontext *ctx, GLboolean flag )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    RADEON_STATECHANGE( rmesa, ctx );
 
    if ( ctx->Depth.Mask ) {
@@ -305,7 +305,7 @@ static void radeonDepthMask( GLcontext *ctx, GLboolean flag )
 
 static void radeonClearDepth( GLcontext *ctx, GLclampd d )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint format = (rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &
 		    RADEON_DEPTH_FORMAT_MASK);
 
@@ -327,7 +327,7 @@ static void radeonClearDepth( GLcontext *ctx, GLclampd d )
 
 static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    union { int i; float f; } c, d;
    GLchan col[4];
 
@@ -427,15 +427,15 @@ static GLboolean intersect_rect( drm_clip_rect_t *out,
 }
 
 
-void radeonRecalcScissorRects( radeonContextPtr rmesa )
+void radeonRecalcScissorRects( r100ContextPtr rmesa )
 {
    drm_clip_rect_t *out;
    int i;
 
    /* Grow cliprect store?
     */
-   if (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
-      while (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
+   if (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
+      while (rmesa->state.scissor.numAllocedClipRects < rmesa->radeon.numClipRects) {
 	 rmesa->state.scissor.numAllocedClipRects += 1;	/* zero case */
 	 rmesa->state.scissor.numAllocedClipRects *= 2;
       }
@@ -456,9 +456,9 @@ void radeonRecalcScissorRects( radeonContextPtr rmesa )
    out = rmesa->state.scissor.pClipRects;
    rmesa->state.scissor.numClipRects = 0;
 
-   for ( i = 0 ; i < rmesa->numClipRects ;  i++ ) {
+   for ( i = 0 ; i < rmesa->radeon.numClipRects ;  i++ ) {
       if ( intersect_rect( out, 
-			   &rmesa->pClipRects[i], 
+			   &rmesa->radeon.pClipRects[i], 
 			   &rmesa->state.scissor.rect ) ) {
 	 rmesa->state.scissor.numClipRects++;
 	 out++;
@@ -469,10 +469,10 @@ void radeonRecalcScissorRects( radeonContextPtr rmesa )
 
 static void radeonUpdateScissor( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
-   if ( rmesa->dri.drawable ) {
-      __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   if ( rmesa->radeon.dri.drawable ) {
+      __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
 
       int x = ctx->Scissor.X;
       int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
@@ -492,7 +492,7 @@ static void radeonUpdateScissor( GLcontext *ctx )
 static void radeonScissor( GLcontext *ctx,
 			   GLint x, GLint y, GLsizei w, GLsizei h )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    if ( ctx->Scissor.Enabled ) {
       RADEON_FIREVERTICES( rmesa );	/* don't pipeline cliprect changes */
@@ -508,7 +508,7 @@ static void radeonScissor( GLcontext *ctx,
 
 static void radeonCullFace( GLcontext *ctx, GLenum unused )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
    GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
 
@@ -545,7 +545,7 @@ static void radeonCullFace( GLcontext *ctx, GLenum unused )
 
 static void radeonFrontFace( GLcontext *ctx, GLenum mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    RADEON_STATECHANGE( rmesa, set );
    rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_FFACE_CULL_DIR_MASK;
@@ -570,7 +570,7 @@ static void radeonFrontFace( GLcontext *ctx, GLenum mode )
  */
 static void radeonLineWidth( GLcontext *ctx, GLfloat widthf )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    RADEON_STATECHANGE( rmesa, lin );
    RADEON_STATECHANGE( rmesa, set );
@@ -587,7 +587,7 @@ static void radeonLineWidth( GLcontext *ctx, GLfloat widthf )
 
 static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    RADEON_STATECHANGE( rmesa, lin );
    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = 
@@ -602,8 +602,8 @@ static void radeonColorMask( GLcontext *ctx,
 			     GLboolean r, GLboolean g,
 			     GLboolean b, GLboolean a )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp,
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   GLuint mask = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
 				  ctx->Color.ColorMask[RCOMP],
 				  ctx->Color.ColorMask[GCOMP],
 				  ctx->Color.ColorMask[BCOMP],
@@ -623,7 +623,7 @@ static void radeonColorMask( GLcontext *ctx,
 static void radeonPolygonOffset( GLcontext *ctx,
 				 GLfloat factor, GLfloat units )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    float_ui32_type constant =  { units * rmesa->state.depth.scale };
    float_ui32_type factoru = { factor };
 
@@ -634,7 +634,7 @@ static void radeonPolygonOffset( GLcontext *ctx,
 
 static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint i;
    drm_radeon_stipple_t stipple;
 
@@ -652,21 +652,21 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
    /* FIXME: Use window x,y offsets into stipple RAM.
     */
    stipple.mask = rmesa->state.stipple.mask;
-   drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE, 
+   drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, 
                     &stipple, sizeof(drm_radeon_stipple_t) );
    UNLOCK_HARDWARE( rmesa );
 }
 
 static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0;
 
    /* Can't generally do unfilled via tcl, but some good special
     * cases work. 
     */
    TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, flag);
-   if (rmesa->TclFallback) {
+   if (rmesa->radeon.TclFallback) {
       radeonChooseRenderState( ctx );
       radeonChooseVertexState( ctx );
    }
@@ -686,7 +686,7 @@ static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
  */
 static void radeonUpdateSpecular( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
    GLuint flag = 0;
 
@@ -757,7 +757,7 @@ static void radeonUpdateSpecular( GLcontext *ctx )
 
    /* Update vertex/render formats
     */
-   if (rmesa->TclFallback) { 
+   if (rmesa->radeon.TclFallback) { 
       radeonChooseRenderState( ctx );
       radeonChooseVertexState( ctx );
    }
@@ -774,7 +774,7 @@ static void radeonUpdateSpecular( GLcontext *ctx )
  */
 static void update_global_ambient( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    float *fcmd = (float *)RADEON_DB_STATE( glt );
 
    /* Need to do more if both emmissive & ambient are PREMULT:
@@ -809,7 +809,7 @@ static void update_light_colors( GLcontext *ctx, GLuint p )
 /*     fprintf(stderr, "%s\n", __FUNCTION__); */
 
    if (l->Enabled) {
-      radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+      r100ContextPtr rmesa = R100_CONTEXT(ctx);
       float *fcmd = (float *)RADEON_DB_STATE( lit[p] );
 
       COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );	 
@@ -849,7 +849,7 @@ static void check_twoside_fallback( GLcontext *ctx )
 
 static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 {
-      radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+      r100ContextPtr rmesa = R100_CONTEXT(ctx);
       GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
 
       light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
@@ -913,7 +913,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 
 void radeonUpdateMaterial( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLfloat (*mat)[4] = ctx->Light.Material.Attrib;
    GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl );
    GLuint mask = ~0;
@@ -978,7 +978,7 @@ void radeonUpdateMaterial( GLcontext *ctx )
  */
 static void update_light( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    /* Have to check these, or have an automatic shortcircuit mechanism
     * to remove noop statechanges. (Or just do a better job on the
@@ -1043,7 +1043,7 @@ static void update_light( GLcontext *ctx )
 static void radeonLightfv( GLcontext *ctx, GLenum light,
 			   GLenum pname, const GLfloat *params )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLint p = light - GL_LIGHT0;
    struct gl_light *l = &ctx->Light.Light[p];
    GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
@@ -1164,7 +1164,7 @@ static void radeonLightfv( GLcontext *ctx, GLenum light,
 static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
 				const GLfloat *param )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    switch (pname) {
       case GL_LIGHT_MODEL_AMBIENT: 
@@ -1188,7 +1188,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
 
 	 check_twoside_fallback( ctx );
 
-	 if (rmesa->TclFallback) {
+	 if (rmesa->radeon.TclFallback) {
 	    radeonChooseRenderState( ctx );
 	    radeonChooseVertexState( ctx );
 	 }
@@ -1205,7 +1205,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
 
 static void radeonShadeModel( GLcontext *ctx, GLenum mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
 
    s &= ~(RADEON_DIFFUSE_SHADE_MASK |
@@ -1244,7 +1244,7 @@ static void radeonShadeModel( GLcontext *ctx, GLenum mode )
 static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
 {
    GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
 
    RADEON_STATECHANGE( rmesa, ucp[p] );
@@ -1256,7 +1256,7 @@ static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
 
 static void radeonUpdateClipPlanes( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint p;
 
    for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
@@ -1281,7 +1281,7 @@ static void
 radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func,
                            GLint ref, GLuint mask )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint refmask = (((ctx->Stencil.Ref[0] & 0xff) << RADEON_STENCIL_REF_SHIFT) |
 		     ((ctx->Stencil.ValueMask[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT));
 
@@ -1325,7 +1325,7 @@ radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func,
 static void
 radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    RADEON_STATECHANGE( rmesa, msk );
    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~RADEON_STENCIL_WRITE_MASK;
@@ -1336,7 +1336,7 @@ radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask )
 static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
                                      GLenum zfail, GLenum zpass )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
       and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
@@ -1349,7 +1349,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
    GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
    GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
    
-   if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) {
+   if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) {
       tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
       tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
       tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC;
@@ -1455,7 +1455,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
 
 static void radeonClearStencil( GLcontext *ctx, GLint s )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    rmesa->state.stencil.clear = 
       ((GLuint) (ctx->Stencil.Clear & 0xff) |
@@ -1481,8 +1481,8 @@ static void radeonClearStencil( GLcontext *ctx, GLint s )
  */
 void radeonUpdateWindow( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    GLfloat xoffset = (GLfloat)dPriv->x;
    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1524,8 +1524,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval,
 
 void radeonUpdateViewportOffset( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    GLfloat xoffset = (GLfloat)dPriv->x;
    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1555,8 +1555,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx )
                 RADEON_STIPPLE_Y_OFFSET_MASK);
 
          /* add magic offsets, then invert */
-         stx = 31 - ((rmesa->dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK);
-         sty = 31 - ((rmesa->dri.drawable->y + rmesa->dri.drawable->h - 1)
+         stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK);
+         sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1)
                      & RADEON_STIPPLE_COORD_MASK);
 
          m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) |
@@ -1580,20 +1580,20 @@ void radeonUpdateViewportOffset( GLcontext *ctx )
 
 static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLubyte c[4];
    CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
    CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
    CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
    CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
-   rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp,
+   rmesa->state.color.clear = radeonPackColor( rmesa->radeon.radeonScreen->cpp,
 					       c[0], c[1], c[2], c[3] );
 }
 
 
 static void radeonRenderMode( GLcontext *ctx, GLenum mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) );
 }
 
@@ -1619,7 +1619,7 @@ static GLuint radeon_rop_tab[] = {
 
 static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint rop = (GLuint)opcode - GL_CLEAR;
 
    ASSERT( rop < 16 );
@@ -1632,40 +1632,40 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode )
 /**
  * Set up the cliprects for either front or back-buffer drawing.
  */
-void radeonSetCliprects( radeonContextPtr rmesa )
+void radeonSetCliprects( r100ContextPtr rmesa )
 {
-   __DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
-   __DRIdrawablePrivate *const readable = rmesa->dri.readable;
+   __DRIdrawablePrivate *const drawable = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *const readable = rmesa->radeon.dri.readable;
    GLframebuffer *const draw_fb = (GLframebuffer*) drawable->driverPrivate;
    GLframebuffer *const read_fb = (GLframebuffer*) readable->driverPrivate;
 
    if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
       /* Can't ignore 2d windows if we are page flipping.
        */
-      if ( drawable->numBackClipRects == 0 || rmesa->doPageFlip ) {
-	 rmesa->numClipRects = drawable->numClipRects;
-	 rmesa->pClipRects = drawable->pClipRects;
+      if ( drawable->numBackClipRects == 0 || rmesa->radeon.doPageFlip ) {
+	 rmesa->radeon.numClipRects = drawable->numClipRects;
+	 rmesa->radeon.pClipRects = drawable->pClipRects;
       }
       else {
-	 rmesa->numClipRects = drawable->numBackClipRects;
-	 rmesa->pClipRects = drawable->pBackClipRects;
+	 rmesa->radeon.numClipRects = drawable->numBackClipRects;
+	 rmesa->radeon.pClipRects = drawable->pBackClipRects;
       }
    }
    else {
       /* front buffer (or none, or multiple buffers */
-      rmesa->numClipRects = drawable->numClipRects;
-      rmesa->pClipRects = drawable->pClipRects;
+      rmesa->radeon.numClipRects = drawable->numClipRects;
+      rmesa->radeon.pClipRects = drawable->pClipRects;
    }
 
    if ((draw_fb->Width != drawable->w) || (draw_fb->Height != drawable->h)) {
-      _mesa_resize_framebuffer(rmesa->glCtx, draw_fb,
+      _mesa_resize_framebuffer(rmesa->radeon.glCtx, draw_fb,
 			       drawable->w, drawable->h);
       draw_fb->Initialized = GL_TRUE;
    }
 
    if (drawable != readable) {
       if ((read_fb->Width != readable->w) || (read_fb->Height != readable->h)) {
-	 _mesa_resize_framebuffer(rmesa->glCtx, read_fb,
+	 _mesa_resize_framebuffer(rmesa->radeon.glCtx, read_fb,
 				  readable->w, readable->h);
 	 read_fb->Initialized = GL_TRUE;
       }
@@ -1674,7 +1674,7 @@ void radeonSetCliprects( radeonContextPtr rmesa )
    if (rmesa->state.scissor.enabled)
       radeonRecalcScissorRects( rmesa );
 
-   rmesa->lastStamp = drawable->lastStamp;
+   rmesa->radeon.lastStamp = drawable->lastStamp;
 }
 
 
@@ -1683,7 +1683,7 @@ void radeonSetCliprects( radeonContextPtr rmesa )
  */
 static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    if (RADEON_DEBUG & DEBUG_DRI)
       fprintf(stderr, "%s %s\n", __FUNCTION__,
@@ -1726,7 +1726,7 @@ static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
 
 static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint p, flag;
 
    if ( RADEON_DEBUG & DEBUG_STATE )
@@ -2010,7 +2010,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
 
 static void radeonLightingSpaceChange( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLboolean tmp;
    RADEON_STATECHANGE( rmesa, tcl );
 
@@ -2039,7 +2039,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx )
  */
 
 
-void radeonUploadTexMatrix( radeonContextPtr rmesa,
+void radeonUploadTexMatrix( r100ContextPtr rmesa,
 			    int unit, GLboolean swapcols )
 {
 /* Here's how this works: on r100, only 3 tex coords can be submitted, so the
@@ -2065,7 +2065,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa,
    int idx = TEXMAT_0 + unit;
    float *dest = ((float *)RADEON_DB_STATE( mat[idx] )) + MAT_ELT_0;
    int i;
-   struct gl_texture_unit tUnit = rmesa->glCtx->Texture.Unit[unit];
+   struct gl_texture_unit tUnit = rmesa->radeon.glCtx->Texture.Unit[unit];
    GLfloat *src = rmesa->tmpmat[unit].m;
 
    rmesa->TexMatColSwap &= ~(1 << unit);
@@ -2119,7 +2119,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa,
 }
 
 
-static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx )
+static void upload_matrix( r100ContextPtr rmesa, GLfloat *src, int idx )
 {
    float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
    int i;
@@ -2135,7 +2135,7 @@ static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx )
    RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
 }
 
-static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx )
+static void upload_matrix_t( r100ContextPtr rmesa, GLfloat *src, int idx )
 {
    float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
    memcpy(dest, src, 16*sizeof(float));
@@ -2145,7 +2145,7 @@ static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx )
 
 static void update_texturematrix( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
    GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL];
    GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL];
    int unit;
@@ -2217,7 +2217,7 @@ static void update_texturematrix( GLcontext *ctx )
 void
 radeonUpdateDrawBuffer(GLcontext *ctx)
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_framebuffer *fb = ctx->DrawBuffer;
    driRenderbuffer *drb;
 
@@ -2241,10 +2241,10 @@ radeonUpdateDrawBuffer(GLcontext *ctx)
 
    /* Note: we used the (possibly) page-flipped values */
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
-     = ((drb->flippedOffset + rmesa->radeonScreen->fbLocation)
+     = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation)
 	& RADEON_COLOROFFSET_MASK);
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
-   if (rmesa->sarea->tiling_enabled) {
+   if (rmesa->radeon.sarea->tiling_enabled) {
       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
    }
 }
@@ -2252,8 +2252,8 @@ radeonUpdateDrawBuffer(GLcontext *ctx)
 
 void radeonValidateState( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   GLuint new_state = rmesa->NewGLState;
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   GLuint new_state = rmesa->radeon.NewGLState;
 
    if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
      radeonUpdateDrawBuffer(ctx);
@@ -2261,7 +2261,7 @@ void radeonValidateState( GLcontext *ctx )
 
    if (new_state & _NEW_TEXTURE) {
       radeonUpdateTextureState( ctx );
-      new_state |= rmesa->NewGLState; /* may add TEXTURE_MATRIX */
+      new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */
    }
 
    /* Need an event driven matrix update?
@@ -2295,7 +2295,7 @@ void radeonValidateState( GLcontext *ctx )
    }
 
 
-   rmesa->NewGLState = 0;
+   rmesa->radeon.NewGLState = 0;
 }
 
 
@@ -2306,7 +2306,7 @@ static void radeonInvalidateState( GLcontext *ctx, GLuint new_state )
    _vbo_InvalidateState( ctx, new_state );
    _tnl_InvalidateState( ctx, new_state );
    _ae_invalidate_state( ctx, new_state );
-   RADEON_CONTEXT(ctx)->NewGLState |= new_state;
+   R100_CONTEXT(ctx)->radeon.NewGLState |= new_state;
 }
 
 
@@ -2330,15 +2330,15 @@ static GLboolean check_material( GLcontext *ctx )
 
 static void radeonWrapRunPipeline( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLboolean has_material;
 
    if (0)
-      fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->NewGLState);
+      fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->radeon.NewGLState);
 
    /* Validate state:
     */
-   if (rmesa->NewGLState)
+   if (rmesa->radeon.NewGLState)
       radeonValidateState( ctx );
 
    has_material = (ctx->Light.Enabled && check_material( ctx ));
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h
index 2171879f759..20b2d890019 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.h
+++ b/src/mesa/drivers/dri/radeon/radeon_state.h
@@ -39,22 +39,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "radeon_context.h"
 
-extern void radeonInitState( radeonContextPtr rmesa );
+extern void radeonInitState( r100ContextPtr rmesa );
 extern void radeonInitStateFuncs( GLcontext *ctx );
 
 extern void radeonUpdateMaterial( GLcontext *ctx );
 
-extern void radeonSetCliprects( radeonContextPtr rmesa );
-extern void radeonRecalcScissorRects( radeonContextPtr rmesa );
+extern void radeonSetCliprects( r100ContextPtr rmesa );
+extern void radeonRecalcScissorRects( r100ContextPtr rmesa );
 extern void radeonUpdateViewportOffset( GLcontext *ctx );
 extern void radeonUpdateWindow( GLcontext *ctx );
 extern void radeonUpdateDrawBuffer( GLcontext *ctx );
-extern void radeonUploadTexMatrix( radeonContextPtr rmesa,
+extern void radeonUploadTexMatrix( r100ContextPtr rmesa,
 				   int unit, GLboolean swapcols );
 
 extern void radeonValidateState( GLcontext *ctx );
 
-extern void radeonPrintDirty( radeonContextPtr rmesa,
+extern void radeonPrintDirty( r100ContextPtr rmesa,
 			      const char *msg );
 
 
@@ -62,7 +62,7 @@ extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode );
 #define FALLBACK( rmesa, bit, mode ) do {				\
    if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n",		\
 		     __FUNCTION__, bit, mode );				\
-   radeonFallback( rmesa->glCtx, bit, mode );				\
+   radeonFallback( rmesa->radeon.glCtx, bit, mode );				\
 } while (0)
 
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 5b1e79bad24..d5b83191b60 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -50,7 +50,7 @@
  * State initialization
  */
 
-void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
+void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
 {
    struct radeon_state_atom *l;
 
@@ -97,16 +97,16 @@ static int cmdscl( int offset, int stride, int count )
 }
 
 #define CHECK( NM, FLAG )				\
-static GLboolean check_##NM( GLcontext *ctx, int idx )	\
+static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom )	\
 {							\
    return FLAG;						\
 }
 
 #define TCL_CHECK( NM, FLAG )				\
-static GLboolean check_##NM( GLcontext *ctx, int idx )	\
+static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom )	\
 {							\
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);	\
-   return !rmesa->TclFallback && (FLAG);		\
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);	\
+   return !rmesa->radeon.TclFallback && (FLAG);		\
 }
 
 
@@ -150,13 +150,13 @@ CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT))
 
 /* Initialize the context's hardware state.
  */
-void radeonInitState( radeonContextPtr rmesa )
+void radeonInitState( r100ContextPtr rmesa )
 {
-   GLcontext *ctx = rmesa->glCtx;
+   GLcontext *ctx = rmesa->radeon.glCtx;
    GLuint color_fmt, depth_fmt, i;
    GLint drawPitch, drawOffset;
 
-   switch ( rmesa->radeonScreen->cpp ) {
+   switch ( rmesa->radeon.radeonScreen->cpp ) {
    case 2:
       color_fmt = RADEON_COLOR_FORMAT_RGB565;
       break;
@@ -193,14 +193,14 @@ void radeonInitState( radeonContextPtr rmesa )
    rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
 				     ctx->Visual.depthBits == 24 );
 
-   rmesa->Fallback = 0;
+   rmesa->radeon.Fallback = 0;
 
-   if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
-      drawOffset = rmesa->radeonScreen->backOffset;
-      drawPitch  = rmesa->radeonScreen->backPitch;
+   if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
+      drawOffset = rmesa->radeon.radeonScreen->backOffset;
+      drawPitch  = rmesa->radeon.radeonScreen->backPitch;
    } else {
-      drawOffset = rmesa->radeonScreen->frontOffset;
-      drawPitch  = rmesa->radeonScreen->frontPitch;
+      drawOffset = rmesa->radeon.radeonScreen->frontOffset;
+      drawPitch  = rmesa->radeon.radeonScreen->frontPitch;
    }
 
    rmesa->hw.max_state_size = 0;
@@ -208,8 +208,8 @@ void radeonInitState( radeonContextPtr rmesa )
 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG )				\
    do {								\
       rmesa->hw.ATOM.cmd_size = SZ;				\
-      rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int));	\
-      rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int));	\
+      rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int));	\
+      rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int));	\
       rmesa->hw.ATOM.name = NM;					\
       rmesa->hw.ATOM.is_tcl = FLAG;					\
       rmesa->hw.ATOM.check = check_##CHK;				\
@@ -236,7 +236,7 @@ void radeonInitState( radeonContextPtr rmesa )
    ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
    ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
    ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 );
-   if (rmesa->radeonScreen->drmSupportsCubeMapsR100)
+   if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
    {
       ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 );
       ALLOC_STATE( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0 );
@@ -353,10 +353,10 @@ void radeonInitState( radeonContextPtr rmesa )
 					    RADEON_DST_BLEND_GL_ZERO );
 
    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
-      rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
+      rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
 
    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 
-      ((rmesa->radeonScreen->depthPitch &
+      ((rmesa->radeon.radeonScreen->depthPitch &
 	RADEON_DEPTHPITCH_MASK) |
        RADEON_DEPTH_ENDIAN_NO_SWAP);
        
@@ -374,7 +374,7 @@ void radeonInitState( radeonContextPtr rmesa )
    if (rmesa->using_hyperz) {
        rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
 						   RADEON_Z_DECOMPRESSION_ENABLE;
-      if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
+      if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 	 /* works for q3, but slight rendering errors with glxgears ? */
 /*	 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
 	 /* need this otherwise get lots of lockups with q3 ??? */
@@ -389,7 +389,7 @@ void radeonInitState( radeonContextPtr rmesa )
 				       color_fmt |
 				       RADEON_ZBLOCK16);
 
-   switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
+   switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
    case DRI_CONF_DITHER_XERRORDIFFRESET:
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
       break;
@@ -397,19 +397,19 @@ void radeonInitState( radeonContextPtr rmesa )
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
       break;
    }
-   if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
+   if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
 	DRI_CONF_ROUND_ROUND )
       rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
    else
       rmesa->state.color.roundEnable = 0;
-   if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
+   if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
 	DRI_CONF_COLOR_REDUCTION_DITHER )
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
    else
       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
 
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
-					       rmesa->radeonScreen->fbLocation)
+					       rmesa->radeon.radeonScreen->fbLocation)
 					      & RADEON_COLOROFFSET_MASK);
 
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
@@ -418,7 +418,7 @@ void radeonInitState( radeonContextPtr rmesa )
 
 
    /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
-   if (rmesa->sarea->tiling_enabled) {
+   if (rmesa->radeon.sarea->tiling_enabled) {
       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
    }
 
@@ -444,7 +444,7 @@ void radeonInitState( radeonContextPtr rmesa )
   					    RADEON_VC_NO_SWAP;
 #endif
 
-   if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
+   if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
      rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
    }
 
@@ -492,7 +492,7 @@ void radeonInitState( radeonContextPtr rmesa )
 
       /* Initialize the texture offset to the start of the card texture heap */
       rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
-	  rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	  rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 
       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
       rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =  
@@ -513,15 +513,15 @@ void radeonInitState( radeonContextPtr rmesa )
 
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
-	  rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	  rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
-	  rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	  rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
-	  rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	  rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
-	  rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	  rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
-	  rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
+	  rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
    }
 
    /* Can only add ST1 at the time of doing some multitex but can keep
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index ebea1fecdca..ef89d73bdda 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -52,7 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_tcl.h"
 
 
-static void flush_last_swtcl_prim( radeonContextPtr rmesa  );
+static void flush_last_swtcl_prim(GLcontext *ctx);
 
 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
@@ -87,7 +87,7 @@ static GLuint radeon_cp_vc_frmts[3][2] =
 
 static void radeonSetVertexFormat( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    struct vertex_buffer *VB = &tnl->vb;
    DECLARE_RENDERINPUTS(index_bitset);
@@ -204,7 +204,7 @@ static void radeonSetVertexFormat( GLcontext *ctx )
       }
    }
 
-   if (!RENDERINPUTS_EQUAL( rmesa->tnl_index_bitset, index_bitset ) ||
+   if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 	fmt_0 != rmesa->swtcl.vertex_format) {
       RADEON_NEWPRIM(rmesa);
       rmesa->swtcl.vertex_format = fmt_0;
@@ -214,7 +214,7 @@ static void radeonSetVertexFormat( GLcontext *ctx )
 			      rmesa->swtcl.vertex_attr_count,
 			      NULL, 0 );
       rmesa->swtcl.vertex_size /= 4;
-      RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset );
+      RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
       if (RADEON_DEBUG & DEBUG_VERTS)
 	 fprintf( stderr, "%s: vertex_size= %d floats\n",
 		  __FUNCTION__, rmesa->swtcl.vertex_size);
@@ -224,13 +224,13 @@ static void radeonSetVertexFormat( GLcontext *ctx )
 
 static void radeonRenderStart( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
 
    radeonSetVertexFormat( ctx );
    
    if (rmesa->dma.flush != 0 && 
        rmesa->dma.flush != flush_last_swtcl_prim)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( ctx );
 }
 
 
@@ -241,7 +241,7 @@ static void radeonRenderStart( GLcontext *ctx )
  */
 void radeonChooseVertexState( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
    TNLcontext *tnl = TNL_CONTEXT(ctx);
 
    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
@@ -254,7 +254,7 @@ void radeonChooseVertexState( GLcontext *ctx )
     * rasterization fallback.  As this function will be called again when we
     * leave a rasterization fallback, we can just skip it for now.
     */
-   if (rmesa->Fallback != 0)
+   if (rmesa->radeon.Fallback != 0)
       return;
 
    /* HW perspective divide is a win, but tiny vertex formats are a
@@ -284,8 +284,9 @@ void radeonChooseVertexState( GLcontext *ctx )
 
 /* Flush vertices in the current dma region.
  */
-static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
+static void flush_last_swtcl_prim(GLcontext *ctx)
 {
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    if (RADEON_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
@@ -293,7 +294,7 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
 
    if (rmesa->dma.current.buf) {
       struct radeon_dma_region *current = &rmesa->dma.current;
-      GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset +
+      GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset +
 			       current->buf->buf->idx * RADEON_BUFFER_SIZE + 
 			       current->start);
 
@@ -326,7 +327,7 @@ static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
 /* Alloc space in the current dma region.
  */
 static INLINE void *
-radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
+radeonAllocDmaLowVerts( r100ContextPtr rmesa, int nverts, int vsize )
 {
    GLuint bytes = vsize * nverts;
 
@@ -334,7 +335,7 @@ radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
       radeonRefillCurrentDmaRegion( rmesa );
 
    if (!rmesa->dma.flush) {
-      rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+      rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
       rmesa->dma.flush = flush_last_swtcl_prim;
    }
 
@@ -387,14 +388,14 @@ static const GLuint hw_prim[GL_POLYGON+1] = {
 };
 
 static INLINE void
-radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim )
+radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 {
    RADEON_NEWPRIM( rmesa );
    rmesa->swtcl.hw_primitive = hw_prim[prim];
    assert(rmesa->dma.current.ptr == rmesa->dma.current.start);
 }
 
-#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
+#define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 #define GET_CURRENT_VB_MAX_VERTS() \
@@ -418,7 +419,7 @@ radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim )
 static GLboolean radeon_run_render( GLcontext *ctx,
 				    struct tnl_pipeline_stage *stage )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    struct vertex_buffer *VB = &tnl->vb;
    tnl_render_func *tab = TAG(render_tab_verts);
@@ -496,12 +497,12 @@ static void radeonResetLineStipple( GLcontext *ctx );
 
 #undef LOCAL_VARS
 #undef ALLOC_VERTS
-#define CTX_ARG radeonContextPtr rmesa
+#define CTX_ARG r100ContextPtr rmesa
 #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
 #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
 #undef LOCAL_VARS
 #define LOCAL_VARS						\
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);		\
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);		\
    const char *radeonverts = (char *)rmesa->swtcl.verts;
 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 #define VERTEX radeonVertex 
@@ -606,7 +607,7 @@ do {							\
 #undef INIT
 
 #define LOCAL_VARS(n)							\
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);			\
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);			\
    GLuint color[n], spec[n];						\
    GLuint coloroffset = rmesa->swtcl.coloroffset;	\
    GLuint specoffset = rmesa->swtcl.specoffset;			\
@@ -673,7 +674,7 @@ static void init_rast_tab( void )
 } while (0)
 #undef LOCAL_VARS
 #define LOCAL_VARS						\
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);		\
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);		\
    const GLuint vertsize = rmesa->swtcl.vertex_size;		\
    const char *radeonverts = (char *)rmesa->swtcl.verts;		\
    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;	\
@@ -700,11 +701,11 @@ static void init_rast_tab( void )
 void radeonChooseRenderState( GLcontext *ctx )
 {
    TNLcontext *tnl = TNL_CONTEXT(ctx);
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint index = 0;
    GLuint flags = ctx->_TriangleCaps;
 
-   if (!rmesa->TclFallback || rmesa->Fallback) 
+   if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) 
       return;
 
    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
@@ -739,7 +740,7 @@ void radeonChooseRenderState( GLcontext *ctx )
 
 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    if (rmesa->swtcl.hw_primitive != hwprim) {
       RADEON_NEWPRIM( rmesa );
@@ -749,7 +750,7 @@ static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 
 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    rmesa->swtcl.render_primitive = prim;
    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) 
       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
@@ -761,7 +762,7 @@ static void radeonRenderFinish( GLcontext *ctx )
 
 static void radeonResetLineStipple( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    RADEON_STATECHANGE( rmesa, lin );
 }
 
@@ -795,12 +796,12 @@ static const char *getFallbackString(GLuint bit)
 
 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
-   GLuint oldfallback = rmesa->Fallback;
+   GLuint oldfallback = rmesa->radeon.Fallback;
 
    if (mode) {
-      rmesa->Fallback |= bit;
+      rmesa->radeon.Fallback |= bit;
       if (oldfallback == 0) {
 	 RADEON_FIREVERTICES( rmesa );
 	 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
@@ -813,7 +814,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
       }
    }
    else {
-      rmesa->Fallback &= ~bit;
+      rmesa->radeon.Fallback &= ~bit;
       if (oldfallback == bit) {
 	 _swrast_flush( ctx );
 	 tnl->Driver.Render.Start = radeonRenderStart;
@@ -826,14 +827,14 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 
 	 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 	 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
-	 if (rmesa->TclFallback) {
-	    /* These are already done if rmesa->TclFallback goes to
+	 if (rmesa->radeon.TclFallback) {
+	    /* These are already done if rmesa->radeon.TclFallback goes to
 	     * zero above. But not if it doesn't (RADEON_NO_TCL for
 	     * example?)
 	     */
 	    _tnl_invalidate_vertex_state( ctx, ~0 );
 	    _tnl_invalidate_vertices( ctx, ~0 );
-	    RENDERINPUTS_ZERO( rmesa->tnl_index_bitset );
+	    RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 	    radeonChooseVertexState( ctx );
 	    radeonChooseRenderState( ctx );
 	 }
@@ -853,7 +854,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 void radeonInitSwtcl( GLcontext *ctx )
 {
    TNLcontext *tnl = TNL_CONTEXT(ctx);
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    static int firsttime = 1;
 
    if (firsttime) {
@@ -881,7 +882,7 @@ void radeonInitSwtcl( GLcontext *ctx )
 
 void radeonDestroySwtcl( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    if (rmesa->swtcl.indexed_verts.buf) 
       radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, 
diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c
index 779e9ae5df0..b59685790c1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c
@@ -104,7 +104,7 @@ static GLboolean discrete_prim[0x10] = {
 };
    
 
-#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
+#define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 #define ELT_TYPE  GLushort
 
 #define ELT_INIT(prim, hw_prim) \
@@ -143,10 +143,10 @@ static GLboolean discrete_prim[0x10] = {
 
 #define ALLOC_ELTS(nr)	radeonAllocElts( rmesa, nr )
 
-static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr ) 
+static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) 
 {
    if (rmesa->dma.flush)
-      rmesa->dma.flush( rmesa );
+      rmesa->dma.flush( rmesa->radeon.glCtx );
 
    radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
 			   rmesa->hw.max_state_size + ELTS_BUFSZ(nr));
@@ -174,7 +174,7 @@ static void radeonEmitPrim( GLcontext *ctx,
 		       GLuint start, 
 		       GLuint count)	
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+   r100ContextPtr rmesa = R100_CONTEXT( ctx );
    radeonTclPrimitive( ctx, prim, hwprim );
    
    radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
@@ -254,7 +254,7 @@ void radeonTclPrimitive( GLcontext *ctx,
 			 GLenum prim,
 			 int hw_prim )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint se_cntl;
    GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
 
@@ -371,7 +371,7 @@ radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord )
 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 					struct tnl_pipeline_stage *stage )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    struct vertex_buffer *VB = &tnl->vb;
    GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
@@ -379,7 +379,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 
    /* TODO: separate this from the swtnl pipeline 
     */
-   if (rmesa->TclFallback)
+   if (rmesa->radeon.TclFallback)
       return GL_TRUE;	/* fallback to software t&l */
 
    if (VB->Count == 0)
@@ -461,7 +461,7 @@ const struct tnl_pipeline_stage _radeon_tcl_stage =
 
 static void transition_to_swtnl( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    GLuint se_cntl;
 
@@ -490,7 +490,7 @@ static void transition_to_swtnl( GLcontext *ctx )
 
 static void transition_to_hwtnl( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 
@@ -510,7 +510,7 @@ static void transition_to_hwtnl( GLcontext *ctx )
    tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
 
    if ( rmesa->dma.flush )			
-      rmesa->dma.flush( rmesa );	
+      rmesa->dma.flush( rmesa->radeon.glCtx );	
 
    rmesa->dma.flush = NULL;
    rmesa->swtcl.vertex_format = 0;
@@ -550,11 +550,11 @@ static char *getFallbackString(GLuint bit)
 
 void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   GLuint oldfallback = rmesa->TclFallback;
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   GLuint oldfallback = rmesa->radeon.TclFallback;
 
    if (mode) {
-      rmesa->TclFallback |= bit;
+      rmesa->radeon.TclFallback |= bit;
       if (oldfallback == 0) {
 	 if (RADEON_DEBUG & DEBUG_FALLBACKS) 
 	    fprintf(stderr, "Radeon begin tcl fallback %s\n",
@@ -563,7 +563,7 @@ void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
       }
    }
    else {
-      rmesa->TclFallback &= ~bit;
+      rmesa->radeon.TclFallback &= ~bit;
       if (oldfallback == bit) {
 	 if (RADEON_DEBUG & DEBUG_FALLBACKS) 
 	    fprintf(stderr, "Radeon end tcl fallback %s\n",
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c
index 35774ab8c69..e4829aaeaba 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.c
@@ -287,11 +287,11 @@ static const struct gl_texture_format *
 radeonChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
                            GLenum format, GLenum type )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    const GLboolean do32bpt =
-       ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32 );
+       ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_32 );
    const GLboolean force16bpt =
-       ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 );
+       ( rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 );
    (void) format;
 
    switch ( internalFormat ) {
@@ -670,7 +670,7 @@ static void radeonCompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint
 static void radeonTexEnv( GLcontext *ctx, GLenum target,
 			  GLenum pname, const GLfloat *param )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint unit = ctx->Texture.CurrentUnit;
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
 
@@ -701,7 +701,7 @@ static void radeonTexEnv( GLcontext *ctx, GLenum target,
        * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
        * [0.0,4.0] to [0,127].
        */
-      min = driQueryOptionb (&rmesa->optionCache, "no_neg_lod_bias") ?
+      min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ?
 	  0.0 : -1.0;
       bias = CLAMP( *param, min, 4.0 );
       if ( bias == 0 ) {
@@ -797,7 +797,7 @@ static void radeonBindTexture( GLcontext *ctx, GLenum target,
 static void radeonDeleteTexture( GLcontext *ctx,
 				 struct gl_texture_object *texObj )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    driTextureObject * t = (driTextureObject *) texObj->DriverData;
 
    if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
@@ -832,7 +832,7 @@ static void radeonTexGen( GLcontext *ctx,
 			  GLenum pname,
 			  const GLfloat *params )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint unit = ctx->Texture.CurrentUnit;
    rmesa->recheck_texgen[unit] = GL_TRUE;
 }
@@ -846,12 +846,12 @@ static void radeonTexGen( GLcontext *ctx,
 static struct gl_texture_object *
 radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_texture_object *obj;
    obj = _mesa_new_texture_object(ctx, name, target);
    if (!obj)
       return NULL;
-   obj->MaxAnisotropy = rmesa->initialMaxAnisotropy;
+   obj->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
    radeonAllocTexObj( obj );
    return obj;
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h
index 80008808289..8c2f9be241d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.h
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.h
@@ -43,10 +43,10 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
 
 extern void radeonUpdateTextureState( GLcontext *ctx );
 
-extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t,
+extern int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t,
 				  GLuint face );
 
-extern void radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t );
+extern void radeonDestroyTexObj( r100ContextPtr rmesa, radeonTexObjPtr t );
 
 extern void radeonInitTextureFuncs( struct dd_function_table *functions );
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c
index 786373d3004..77810ef7e19 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c
@@ -53,7 +53,7 @@ SOFTWARE.
  * include NULLing out hardware state that points to the texture.
  */
 void
-radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
+radeonDestroyTexObj( r100ContextPtr rmesa, radeonTexObjPtr t )
 {
    if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
       fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj );
@@ -63,7 +63,7 @@ radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
       unsigned   i;
 
 
-      for ( i = 0 ; i < rmesa->glCtx->Const.MaxTextureUnits ; i++ ) {
+      for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
 	 if ( t == rmesa->state.texture.unit[i].texobj ) {
 	    rmesa->state.texture.unit[i].texobj = NULL;
 	 }
@@ -77,7 +77,7 @@ radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
  */
 
 
-static void radeonUploadRectSubImage( radeonContextPtr rmesa,
+static void radeonUploadRectSubImage( r100ContextPtr rmesa,
 				      radeonTexObjPtr t, 
 				      struct gl_texture_image *texImage,
 				      GLint x, GLint y, 
@@ -172,7 +172,7 @@ static void radeonUploadRectSubImage( radeonContextPtr rmesa,
  * Upload the texture image associated with texture \a t at the specified
  * level at the address relative to \a start.
  */
-static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t, 
+static void uploadSubImage( r100ContextPtr rmesa, radeonTexObjPtr t, 
 			    GLint hwlevel,
 			    GLint x, GLint y, GLint width, GLint height,
 			    GLuint face )
@@ -300,7 +300,7 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
 
    LOCK_HARDWARE( rmesa );
    do {
-      ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
+      ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
                                  &tex, sizeof(drm_radeon_texture_t) );
    } while ( ret == -EAGAIN );
 
@@ -329,7 +329,7 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
  * \param face Cube map face to be uploaded.  Zero for non-cube maps.
  */
 
-int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint face )
+int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
 {
    int numLevels;
 
@@ -338,7 +338,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
 
    if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
       fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__,
-	       (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize,
+	       (void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize,
 	       t->base.firstLevel, t->base.lastLevel );
    }
 
@@ -346,7 +346,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
 
    if (RADEON_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
-      radeonFinish( rmesa->glCtx );
+      radeonFinish( rmesa->radeon.glCtx );
    }
 
    LOCK_HARDWARE( rmesa );
@@ -354,7 +354,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
    if ( t->base.memBlock == NULL ) {
       int heap;
 
-      heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps,
+      heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
 				 (driTextureObject *) t );
       if ( heap == -1 ) {
 	 UNLOCK_HARDWARE( rmesa );
@@ -362,7 +362,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
       }
 
       /* Set the base offset of the texture image */
-      t->bufAddr = rmesa->radeonScreen->texOffset[heap] 
+      t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap] 
 	   + t->base.memBlock->ofs;
       t->pp_txoffset = t->bufAddr;
 
@@ -397,7 +397,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
 
    if (RADEON_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
-      radeonFinish( rmesa->glCtx );
+      radeonFinish( rmesa->radeon.glCtx );
    }
 
    return 0;
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 54674a7fa2a..911a0b3a0c5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -122,7 +122,7 @@ tx_table[] =
  * \param tObj GL texture object whose images are to be posted to
  *                 hardware state.
  */
-static void radeonSetTexImages( radeonContextPtr rmesa,
+static void radeonSetTexImages( r100ContextPtr rmesa,
 				struct gl_texture_object *tObj )
 {
    radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData;
@@ -503,7 +503,7 @@ do {							\
 
 static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    GLuint color_combine, alpha_combine;
    const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO
@@ -846,9 +846,9 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
 void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
                         unsigned long long offset, GLint depth, GLuint pitch)
 {
-	radeonContextPtr rmesa = pDRICtx->driverPrivate;
+	r100ContextPtr rmesa = pDRICtx->driverPrivate;
 	struct gl_texture_object *tObj =
-	    _mesa_lookup_texture(rmesa->glCtx, texname);
+	    _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
 	radeonTexObjPtr t;
 
 	if (tObj == NULL)
@@ -901,7 +901,7 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
                               RADEON_TXFORMAT_NON_POWER2)
 
 
-static void import_tex_obj_state( radeonContextPtr rmesa,
+static void import_tex_obj_state( r100ContextPtr rmesa,
 				  int unit,
 				  radeonTexObjPtr texobj )
 {
@@ -958,7 +958,7 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
 
 
 
-static void set_texgen_matrix( radeonContextPtr rmesa, 
+static void set_texgen_matrix( r100ContextPtr rmesa, 
 			       GLuint unit,
 			       const GLfloat *s_plane,
 			       const GLfloat *t_plane,
@@ -986,14 +986,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa,
    rmesa->TexGenMatrix[unit].m[15] = q_plane[3];
 
    rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit;
-   rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+   rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
 }
 
 /* Returns GL_FALSE if fallback required.
  */
 static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
    GLuint tmp = rmesa->TexGenEnabled;
@@ -1094,7 +1094,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
    }
 
    if (tmp != rmesa->TexGenEnabled) {
-      rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+      rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
    }
 
    return GL_TRUE;
@@ -1103,7 +1103,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
 
 static void disable_tex( GLcontext *ctx, int unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    if (rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<<unit)) {
       /* Texture unit disabled */
@@ -1124,7 +1124,7 @@ static void disable_tex( GLcontext *ctx, int unit )
       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) |
 						RADEON_Q_BIT(unit));
 
-      if (rmesa->TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) {
+      if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) {
 	 TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE);
 	 rmesa->recheck_texgen[unit] = GL_TRUE;
       }
@@ -1151,7 +1151,7 @@ static void disable_tex( GLcontext *ctx, int unit )
 
 	 if (tmp != rmesa->TexGenEnabled) {
 	    rmesa->recheck_texgen[unit] = GL_TRUE;
-	    rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+	    rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
 	 }
       }
    }
@@ -1159,7 +1159,7 @@ static void disable_tex( GLcontext *ctx, int unit )
 
 static GLboolean enable_tex_2d( GLcontext *ctx, int unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    struct gl_texture_object *tObj = texUnit->_Current;
    radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
@@ -1186,7 +1186,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit )
 
 static GLboolean enable_tex_cube( GLcontext *ctx, int unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    struct gl_texture_object *tObj = texUnit->_Current;
    radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
@@ -1228,7 +1228,7 @@ static GLboolean enable_tex_cube( GLcontext *ctx, int unit )
 
 static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    struct gl_texture_object *tObj = texUnit->_Current;
    radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
@@ -1257,7 +1257,7 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
 
 static GLboolean update_tex_common( GLcontext *ctx, int unit )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    struct gl_texture_object *tObj = texUnit->_Current;
    radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
@@ -1309,14 +1309,14 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit )
    if (t->dirty_state & (1<<unit)) {
       import_tex_obj_state( rmesa, unit, t );
       /* may need to update texture matrix (for texrect adjustments) */
-      rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+      rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
    }
 
    if (rmesa->recheck_texgen[unit]) {
       GLboolean fallback = !radeon_validate_texgen( ctx, unit );
       TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), fallback);
       rmesa->recheck_texgen[unit] = 0;
-      rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
+      rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
    }
 
    format = tObj->Image[0][tObj->BaseLevel]->_BaseFormat;
@@ -1362,7 +1362,7 @@ static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
 
 void radeonUpdateTextureState( GLcontext *ctx )
 {
-   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLboolean ok;
 
    ok = (radeonUpdateTextureUnit( ctx, 0 ) &&
@@ -1371,6 +1371,6 @@ void radeonUpdateTextureState( GLcontext *ctx )
 
    FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok );
 
-   if (rmesa->TclFallback)
+   if (rmesa->radeon.TclFallback)
       radeonChooseVertexState( ctx );
 }