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authorAlex Deucher <[email protected]>2009-11-09 11:36:10 -0500
committerAlex Deucher <[email protected]>2009-11-09 12:16:55 -0500
commit37676b396a8416ad35253412d3a2e06482859a4d (patch)
tree10761af3bb3a760ae15e181304866570144a05b1 /src/mesa/drivers
parenta9035f3dc313d047ce3af191d6d7ac8ada8167df (diff)
r600: don't emit htile regs
These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm.
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 47b38d2e36f..ec76fbcb6da 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -784,8 +784,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
BATCH_LOCALS(&context->radeon);
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
- BEGIN_BATCH_NO_AUTOSTATE(23);
- R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
+ BEGIN_BATCH_NO_AUTOSTATE(17);
R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
@@ -798,7 +797,6 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
- R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
END_BATCH();
@@ -1282,7 +1280,7 @@ void r600InitAtoms(context_t *context)
context->radeon.hw.atomlist.name = "atom-list";
ALLOC_STATE(sq, always, 34, r700SendSQConfig);
- ALLOC_STATE(db, always, 23, r700SendDBState);
+ ALLOC_STATE(db, always, 17, r700SendDBState);
ALLOC_STATE(stencil, always, 4, r700SendStencilState);
ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
ALLOC_STATE(sc, always, 15, r700SendSCState);