diff options
| author | Topi Pohjolainen <[email protected]> | 2017-01-10 10:13:30 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <[email protected]> | 2017-01-27 08:57:26 +0200 |
| commit | 40bf622cedda2fba54488188c98591354f16a132 (patch) | |
| tree | 980330a3ad29de66f7ca2a1e9b56b8d53b3b2ac4 /src/mesa/drivers | |
| parent | 5201d2991b0a9e6d6a24bd9b0d07182bc14221bd (diff) | |
i965/blorp/gen6: Simplify hiz surface setup
In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo
is unconditionally initialised to point to the same buffer
object as hiz_mt does. Also intel_miptree_aux_buffer::offset
is initialised to zero (calloc()).
This will make following patches significantly simpler to read.
Reviewed-by: Jason Ekstrand <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 3a7cf84db03..f21b41a4e3b 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -244,9 +244,12 @@ blorp_surf_for_miptree(struct brw_context *brw, surf->aux_addr.offset = mt->mcs_buf->offset; } else { assert(surf->aux_usage == ISL_AUX_USAGE_HIZ); + + surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo; + surf->aux_addr.offset = mt->hiz_buf->aux_base.offset; + struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt; if (hiz_mt) { - surf->aux_addr.buffer = hiz_mt->bo; if (brw->gen == 6 && hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) { /* gen6 requires the HiZ buffer to be manually offset to the @@ -255,13 +258,8 @@ blorp_surf_for_miptree(struct brw_context *brw, */ apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level, &surf->aux_addr.offset); - } else { - surf->aux_addr.offset = 0; } assert(hiz_mt->pitch == aux_surf->row_pitch); - } else { - surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo; - surf->aux_addr.offset = mt->hiz_buf->aux_base.offset; } } } else { |