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authorPaul Berry <[email protected]>2013-08-31 20:23:49 -0700
committerPaul Berry <[email protected]>2013-09-05 09:52:47 -0700
commit588ec545acc930470c605005292c8ef10adf4919 (patch)
treeeab7ffc66da90f8106ec7fe4c98e02c4d36d496d /src/mesa/drivers/windows/gdi/wmesadef.h
parentae79e3332eca5c8024c894c7c7689bfbf3311038 (diff)
i965/gen7.5: Fix lower bound on number of VS URB entries.
Haswell GT2 and GT3 require the number of vertex shader URB entries to be at least 64, not 32. At the moment, we always meet this requirement automatically, because in the absence of a geometry shader, we assign all available URB space to the vertex shader. But when we turn on support for geometry shaders, this lower limit will become important. Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/windows/gdi/wmesadef.h')
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