diff options
| author | Dylan Baker <[email protected]> | 2018-09-14 12:57:32 -0700 |
|---|---|---|
| committer | Dylan Baker <[email protected]> | 2020-04-21 11:09:04 -0700 |
| commit | 8e3696137f2cb7b4f5a3824f26186ecbb06f9282 (patch) | |
| tree | 4494df8d138aaf2bab2feafa832f68e9fdf9bfb1 /src/mesa/drivers/dri | |
| parent | 289f02d1d5990e052e21eb250f6d40b47d6eb12f (diff) | |
remove final imports.h and imports.c bits
This moves the fi_types to a new mesa_private.h and removes the
imports.c file. The vast majority of this patch is just removing
pound includes of imports.h and fixing up the recursive includes.
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Kristian H. Kristensen <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
Diffstat (limited to 'src/mesa/drivers/dri')
52 files changed, 359 insertions, 399 deletions
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c index 865a3809c66..e8ce5adfd51 100644 --- a/src/mesa/drivers/dri/i915/i830_context.c +++ b/src/mesa/drivers/dri/i915/i830_context.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,13 +22,12 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ #include "i830_context.h" #include "main/api_exec.h" #include "main/extensions.h" -#include "util/imports.h" #include "main/version.h" #include "main/vtxfmt.h" #include "tnl/tnl.h" diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index d8db4ab42a3..394a6180f58 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,14 +22,13 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ #include "i915_context.h" #include "main/api_exec.h" #include "main/framebuffer.h" #include "main/extensions.h" -#include "util/imports.h" #include "main/macros.h" #include "main/version.h" #include "main/vtxfmt.h" diff --git a/src/mesa/drivers/dri/i915/i915_debug_fp.c b/src/mesa/drivers/dri/i915/i915_debug_fp.c index 474394e0df7..3e32bffdf66 100644 --- a/src/mesa/drivers/dri/i915/i915_debug_fp.c +++ b/src/mesa/drivers/dri/i915/i915_debug_fp.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,14 +22,16 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ #include <stdio.h> +#include <assert.h> + +#include "main/glheader.h" #include "i915_reg.h" #include "i915_debug.h" -#include "util/imports.h" #include "main/glheader.h" static const char *opcodes[0x20] = { diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 44c41bb43dc..8c0f64c2386 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,14 +22,13 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ #include "main/glheader.h" #include "main/mtypes.h" -#include "util/imports.h" #include "main/macros.h" #include "main/renderbuffer.h" #include "main/framebuffer.h" @@ -96,7 +95,7 @@ i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim) /* Pull apart the vertex format registers and figure out how large a - * vertex is supposed to be. + * vertex is supposed to be. */ static bool i915_check_vertex_size(struct intel_context *intel, GLuint expected) @@ -341,7 +340,7 @@ i915_emit_state(struct intel_context *intel) } /* work out list of buffers to emit */ - + /* Do this here as we may have flushed the batchbuffer above, * causing more state to be dirty! */ @@ -432,7 +431,7 @@ i915_emit_state(struct intel_context *intel) } /* Combine all the dirty texture state into a single command to - * avoid lockups on I915 hardware. + * avoid lockups on I915 hardware. */ if (dirty & I915_UPLOAD_TEX_ALL) { int nr = 0; @@ -820,7 +819,7 @@ i915_new_batch(struct intel_context *intel) i915->current_vertex_size = 0; } -static void +static void i915_assert_not_dirty( struct intel_context *intel ) { struct i915_context *i915 = i915_context(&intel->ctx); diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c index 2c3c488ee22..73165418dc5 100644 --- a/src/mesa/drivers/dri/i915/intel_context.c +++ b/src/mesa/drivers/dri/i915/intel_context.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,7 +22,7 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ @@ -31,7 +31,6 @@ #include "main/extensions.h" #include "main/fbobject.h" #include "main/framebuffer.h" -#include "util/imports.h" #include "main/points.h" #include "main/renderbuffer.h" @@ -111,7 +110,7 @@ intel_flush_front(struct gl_context *ctx) __DRIscreen *const screen = intel->intelScreen->driScrnPriv; if (intel->front_buffer_dirty && _mesa_is_winsys_fbo(ctx->DrawBuffer)) { - if (flushFront(screen) && + if (flushFront(screen) && driDrawable && driDrawable->loaderPrivate) { flushFront(screen)(driDrawable, driDrawable->loaderPrivate); @@ -632,7 +631,7 @@ intelMakeCurrent(__DRIcontext * driContextPriv, if (driContextPriv) { struct gl_context *ctx = &intel->ctx; struct gl_framebuffer *fb, *readFb; - + if (driDrawPriv == NULL && driReadPriv == NULL) { fb = _mesa_get_incomplete_framebuffer(); readFb = _mesa_get_incomplete_framebuffer(); diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c b/src/mesa/drivers/dri/i915/intel_fbo.c index 2e00e803b58..f914f1b2f00 100644 --- a/src/mesa/drivers/dri/i915/intel_fbo.c +++ b/src/mesa/drivers/dri/i915/intel_fbo.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2006 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,12 +22,11 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ #include "main/enums.h" -#include "util/imports.h" #include "main/macros.h" #include "main/mtypes.h" #include "main/fbobject.h" diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c index 9d90a5499fc..726fbe0d091 100644 --- a/src/mesa/drivers/dri/i915/intel_render.c +++ b/src/mesa/drivers/dri/i915/intel_render.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,7 +22,7 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ /* @@ -33,7 +33,6 @@ #include "main/glheader.h" #include "main/context.h" #include "main/macros.h" -#include "util/imports.h" #include "main/mtypes.h" #include "main/enums.h" @@ -167,7 +166,7 @@ do { \ /* Render pipeline stage */ /**********************************************************************/ -/* Heuristic to choose between the two render paths: +/* Heuristic to choose between the two render paths: */ static bool choose_render(struct intel_context *intel, struct vertex_buffer *VB) diff --git a/src/mesa/drivers/dri/i915/intel_syncobj.c b/src/mesa/drivers/dri/i915/intel_syncobj.c index b5e363872ad..7355b493c32 100644 --- a/src/mesa/drivers/dri/i915/intel_syncobj.c +++ b/src/mesa/drivers/dri/i915/intel_syncobj.c @@ -38,8 +38,6 @@ * performance bottleneck, though. */ -#include "util/imports.h" - #include "intel_context.h" #include "intel_batchbuffer.h" #include "intel_reg.h" diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c index 2450e707a2b..463918f70e3 100644 --- a/src/mesa/drivers/dri/i965/brw_conditional_render.c +++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c @@ -30,7 +30,6 @@ * (GL_NV_conditional_render, GL_ARB_conditional_render_inverted) on Gen7+. */ -#include "util/imports.h" #include "main/condrender.h" #include "brw_context.h" diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 7a359b32c48..5deff66d817 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -37,7 +37,6 @@ #include "main/fbobject.h" #include "main/extensions.h" #include "main/glthread.h" -#include "util/imports.h" #include "main/macros.h" #include "main/points.h" #include "main/version.h" diff --git a/src/mesa/drivers/dri/i965/brw_object_purgeable.c b/src/mesa/drivers/dri/i965/brw_object_purgeable.c index fd55fe27e72..7a75cfc3f97 100644 --- a/src/mesa/drivers/dri/i965/brw_object_purgeable.c +++ b/src/mesa/drivers/dri/i965/brw_object_purgeable.c @@ -27,7 +27,6 @@ * The driver implementation of the GL_APPLE_object_purgeable extension. */ -#include "util/imports.h" #include "main/mtypes.h" #include "main/macros.h" #include "main/bufferobj.h" diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c b/src/mesa/drivers/dri/i965/brw_primitive_restart.c index a780df31809..e73f32720e1 100644 --- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c +++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c @@ -25,7 +25,6 @@ * */ -#include "util/imports.h" #include "main/bufferobj.h" #include "main/varray.h" #include "vbo/vbo.h" diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 54f700b7b11..412be5ec599 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -30,7 +30,6 @@ */ #include <pthread.h> -#include "util/imports.h" #include "main/glspirv.h" #include "program/prog_parameter.h" #include "program/prog_print.h" diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c b/src/mesa/drivers/dri/i965/brw_program_cache.c index 30be02fa253..c1bdaab591c 100644 --- a/src/mesa/drivers/dri/i965/brw_program_cache.c +++ b/src/mesa/drivers/dri/i965/brw_program_cache.c @@ -44,7 +44,6 @@ * big we throw out all of the cache data and let it get regenerated. */ -#include "util/imports.h" #include "main/streaming-load-memcpy.h" #include "x86/common_x86_asm.h" #include "intel_batchbuffer.h" diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index b27a685d052..1e8316f6f6a 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -35,7 +35,6 @@ * appropriately synced with the stage of the pipeline for our extensions' * needs. */ -#include "util/imports.h" #include "main/queryobj.h" #include "brw_context.h" diff --git a/src/mesa/drivers/dri/i965/brw_sync.c b/src/mesa/drivers/dri/i965/brw_sync.c index 73764834c6c..f44c4e08ccb 100644 --- a/src/mesa/drivers/dri/i965/brw_sync.c +++ b/src/mesa/drivers/dri/i965/brw_sync.c @@ -40,8 +40,6 @@ #include <libsync.h> /* Requires Android or libdrm-2.4.72 */ -#include "util/imports.h" - #include "brw_context.h" #include "intel_batchbuffer.h" diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index 08fe90b8c02..94dd9a4b1ee 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -31,8 +31,6 @@ * GL_EXT_transform_feedback, and friends) on platforms that support * hardware contexts (Gen6+). */ -#include "util/imports.h" - #include "brw_context.h" #include "brw_defines.h" #include "brw_state.h" diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c index 4af64f029d5..f0eb3fdbbd7 100644 --- a/src/mesa/drivers/dri/i965/hsw_queryobj.c +++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c @@ -26,8 +26,6 @@ * * Support for query buffer objects (GL_ARB_query_buffer_object) on Haswell+. */ -#include "util/imports.h" - #include "brw_context.h" #include "brw_defines.h" #include "intel_batchbuffer.h" diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index c0862b5e72a..19fa253af41 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c @@ -29,7 +29,6 @@ * This provides core GL buffer object functionality. */ -#include "util/imports.h" #include "main/mtypes.h" #include "main/macros.h" #include "main/streaming-load-memcpy.h" diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index cc450baf51e..9f8fee9879c 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -24,7 +24,6 @@ */ #include "main/enums.h" -#include "util/imports.h" #include "main/macros.h" #include "main/mtypes.h" #include "main/fbobject.h" diff --git a/src/mesa/drivers/dri/i965/intel_upload.c b/src/mesa/drivers/dri/i965/intel_upload.c index 595e330f3b6..a4a353ed069 100644 --- a/src/mesa/drivers/dri/i965/intel_upload.c +++ b/src/mesa/drivers/dri/i965/intel_upload.c @@ -28,7 +28,6 @@ * Batched upload via BOs. */ -#include "util/imports.h" #include "main/macros.h" #include "brw_bufmgr.h" #include "brw_context.h" diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.h b/src/mesa/drivers/dri/nouveau/nouveau_driver.h index 3230d7e0881..d5b23edae08 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_driver.h +++ b/src/mesa/drivers/dri/nouveau/nouveau_driver.h @@ -27,7 +27,7 @@ #ifndef __NOUVEAU_DRIVER_H__ #define __NOUVEAU_DRIVER_H__ -#include "util/imports.h" + #include "main/mtypes.h" #include "main/macros.h" #include "main/formats.h" diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 3390e0a6672..4a068e0d930 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -32,7 +32,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" + #include "main/macros.h" #include "main/context.h" #include "util/simple_list.h" @@ -111,7 +111,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) } /* Fire a section of the retained (indexed_verts) buffer as a regular - * primtive. + * primtive. */ void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, @@ -120,13 +120,13 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & R200_VF_PRIM_WALK_IND)); - + radeonEmitState(&rmesa->radeon); - + radeon_print(RADEON_RENDER|RADEON_SWRENDER,RADEON_VERBOSE, "%s cmd_used/4: %d prim %x nr %d\n", __func__, rmesa->store.cmd_used/4, primitive, vertex_nr); - + BEGIN_BATCH(3); OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | @@ -142,7 +142,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) BEGIN_BATCH(8+2); OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | - R200_VF_COLOR_ORDER_RGBA | + R200_VF_COLOR_ORDER_RGBA | ((vertex_count + 0) << 16) | type); @@ -190,7 +190,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %d prim %x\n", __func__, min_nr, primitive); assert((primitive & R200_VF_PRIM_WALK_IND)); - + radeonEmitState(&rmesa->radeon); radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, @@ -199,7 +199,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; - + assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES; rmesa->radeon.dma.flush = r200FlushElts; @@ -242,7 +242,7 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) uint32_t voffset; int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; int i; - + radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: nr=%d, ofs=0x%08x\n", __func__, nr, offset); @@ -257,7 +257,7 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) (rmesa->radeon.tcl.aos[i].stride << 8) | (rmesa->radeon.tcl.aos[i + 1].components << 16) | (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - + voffset = rmesa->radeon.tcl.aos[i + 0].offset + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); @@ -265,7 +265,7 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } - + if (nr & 1) { OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 91ce34c6c42..f1c5e8f172b 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -37,7 +37,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/api_arrayelt.h" #include "main/api_exec.h" #include "main/context.h" -#include "util/imports.h" + #include "main/extensions.h" #include "main/version.h" #include "main/vtxfmt.h" @@ -103,7 +103,7 @@ static const struct tnl_pipeline_stage *r200_pipeline[] = { /* Try and go straight to t&l */ - &_r200_tcl_stage, + &_r200_tcl_stage, /* Catch any t&l fallbacks */ @@ -115,7 +115,7 @@ static const struct tnl_pipeline_stage *r200_pipeline[] = { &_tnl_texture_transform_stage, &_tnl_point_attenuation_stage, &_tnl_vertex_program_stage, - /* Try again to go to tcl? + /* Try again to go to tcl? * - no good for asymmetric-twoside (do with multipass) * - no good for asymmetric-unfilled (do with multipass) * - good for material @@ -124,7 +124,7 @@ static const struct tnl_pipeline_stage *r200_pipeline[] = { * * - worth it/not worth it? */ - + /* Else do them here. */ /* &_r200_render_stage, */ /* FIXME: bugs with ut2003 */ @@ -266,7 +266,7 @@ GLboolean r200CreateContext( gl_api api, ctx->Const.StripTextureBorder = GL_TRUE; - /* FIXME: When no memory manager is available we should set this + /* FIXME: When no memory manager is available we should set this * to some reasonable value based on texture memory pool size */ ctx->Const.MaxTextureSize = 2048; ctx->Const.Max3DTextureLevels = 9; @@ -378,7 +378,7 @@ GLboolean r200CreateContext( gl_api api, r200InitState( rmesa ); r200InitSwtcl( ctx ); - rmesa->prefer_gart_client_texturing = + rmesa->prefer_gart_client_texturing = (getenv("R200_GART_CLIENT_TEXTURES") != 0); tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode"); diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 293bec216c8..2e0285cc6a2 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -36,7 +36,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include <errno.h> #include "main/glheader.h" -#include "util/imports.h" + #include "main/macros.h" #include "main/context.h" #include "swrast/swrast.h" diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 646f8bfc973..7177488d087 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -34,7 +34,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/glheader.h" #include "main/mtypes.h" -#include "util/imports.h" + #include "main/macros.h" #include "main/state.h" @@ -71,7 +71,7 @@ do { \ #endif /* Emit any changed arrays to new GART memory, re-emit a packet to - * update the arrays. + * update the arrays. */ void r200EmitArrays( struct gl_context *ctx, GLubyte *vimap_rev ) { diff --git a/src/mesa/drivers/dri/r200/r200_sanity.c b/src/mesa/drivers/dri/r200/r200_sanity.c index ade7aaf007a..8bef63e413a 100644 --- a/src/mesa/drivers/dri/r200/r200_sanity.c +++ b/src/mesa/drivers/dri/r200/r200_sanity.c @@ -31,11 +31,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Keith Whitwell <[email protected]> * */ - -#include <errno.h> + +#include <errno.h> #include "main/glheader.h" -#include "util/imports.h" + #include "r200_context.h" #include "r200_sanity.h" @@ -57,11 +57,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. + * the tcl scalar and vector areas. */ -static struct { - int start; - int len; +static struct { + int start; + int len; const char *name; } packet[RADEON_MAX_STATE_PACKETS] = { { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, @@ -115,15 +115,15 @@ static struct { { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, - { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, - { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, - { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, - { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, - { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, - { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, - { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, - { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, - { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, + { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, + { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, + { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, + { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, + { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, + { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, + { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, + { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, + { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ @@ -598,7 +598,7 @@ static struct reg_names vector_names[] = { #define TOUCHED 4 struct reg { - int idx; + int idx; struct reg_names *closest; int flags; union fi current; @@ -681,14 +681,14 @@ static const char *get_reg_name( struct reg *reg ) { static char tmp[80]; - if (reg->idx == reg->closest->idx) + if (reg->idx == reg->closest->idx) return reg->closest->name; - + if (reg->flags & ISVEC) { if (reg->idx/4 != reg->closest->idx) - sprintf(tmp, "%s+%d[%d]", - reg->closest->name, + sprintf(tmp, "%s+%d[%d]", + reg->closest->name, (reg->idx/4) - reg->closest->idx, reg->idx%4); else @@ -708,17 +708,17 @@ static int print_int_reg_assignment( struct reg *reg, int data ) { int changed = (reg->current.i != data); int ever_seen = find_or_add_value( reg, data ); - + if (VERBOSE || (NORMAL && (changed || !ever_seen))) fprintf(stderr, " %s <-- 0x%x", get_reg_name(reg), data); - + if (NORMAL) { - if (!ever_seen) + if (!ever_seen) fprintf(stderr, " *** BRAND NEW VALUE"); - else if (changed) - fprintf(stderr, " *** CHANGED"); + else if (changed) + fprintf(stderr, " *** CHANGED"); } - + reg->current.i = data; if (VERBOSE || (NORMAL && (changed || !ever_seen))) @@ -786,19 +786,19 @@ static void dump_state( void ) { int i; - for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) + for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) print_reg( ®s[i] ); - for (i = 0 ; i < ARRAY_SIZE(scalars) ; i++) + for (i = 0 ; i < ARRAY_SIZE(scalars) ; i++) print_reg( &scalars[i] ); - for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++) + for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++) print_reg( &vectors[i] ); } -static int radeon_emit_packets( +static int radeon_emit_packets( drm_radeon_cmd_header_t header, drm_radeon_cmd_buffer_t *cmdbuf ) { @@ -806,9 +806,9 @@ static int radeon_emit_packets( int sz = packet[id].len; int *data = (int *)cmdbuf->buf; int i; - + if (sz * sizeof(int) > cmdbuf->bufsz) { - fprintf(stderr, "Packet overflows cmdbuf\n"); + fprintf(stderr, "Packet overflows cmdbuf\n"); return -EINVAL; } @@ -817,8 +817,8 @@ static int radeon_emit_packets( return -EINVAL; } - - if (VERBOSE) + + if (VERBOSE) fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz ); for ( i = 0 ; i < sz ; i++) { @@ -834,7 +834,7 @@ static int radeon_emit_packets( } -static int radeon_emit_scalars( +static int radeon_emit_scalars( drm_radeon_cmd_header_t header, drm_radeon_cmd_buffer_t *cmdbuf ) { @@ -855,14 +855,14 @@ static int radeon_emit_scalars( total_changed++; total++; } - + cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; } -static int radeon_emit_scalars2( +static int radeon_emit_scalars2( drm_radeon_cmd_header_t header, drm_radeon_cmd_buffer_t *cmdbuf ) { @@ -887,7 +887,7 @@ static int radeon_emit_scalars2( total_changed++; total++; } - + cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; @@ -896,7 +896,7 @@ static int radeon_emit_scalars2( /* Check: inf/nan/extreme-size? * Check: table start, end, nr, etc. */ -static int radeon_emit_vectors( +static int radeon_emit_vectors( drm_radeon_cmd_header_t header, drm_radeon_cmd_buffer_t *cmdbuf ) { @@ -926,14 +926,14 @@ static int radeon_emit_vectors( total_changed += 4; total += 4; } - + cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; } -static int radeon_emit_veclinear( +static int radeon_emit_veclinear( drm_radeon_cmd_header_t header, drm_radeon_cmd_buffer_t *cmdbuf ) { @@ -1019,7 +1019,7 @@ static int print_vertex_format( int vfmt ) (vfmt & R200_VTX_W1) ? "w1," : "", (vfmt & R200_VTX_N1) ? "n1," : ""); - + if (!find_or_add_value( &others[V_VTXFMT], vfmt )) fprintf(stderr, " *** NEW VALUE"); @@ -1052,7 +1052,7 @@ static char *primname[0x10] = { static int print_prim_and_flags( int prim ) { int numverts; - + if (NORMAL) fprintf(stderr, " %s(%x): %s%s%s%s%s%s\n", "prim flags", @@ -1065,7 +1065,7 @@ static int print_prim_and_flags( int prim ) (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : ""); numverts = prim>>16; - + if (NORMAL) fprintf(stderr, " prim: %s numverts %d\n", primname[prim&0xf], numverts); @@ -1123,7 +1123,7 @@ static int print_prim_and_flags( int prim ) default: fprintf(stderr, "Bad primitive\n"); return -1; - } + } return 0; } @@ -1247,7 +1247,7 @@ static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) break; case R200_CP_CMD_HOSTDATA_BLT: if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n", + fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n", cmdsz); break; case R200_CP_CMD_POLYLINE: @@ -1256,41 +1256,41 @@ static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) break; case R200_CP_CMD_POLYSCANLINES: if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n", + fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n", cmdsz); break; case R200_CP_CMD_PAINT_MULTI: if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n", + fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n", cmdsz); break; case R200_CP_CMD_BITBLT_MULTI: if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n", + fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n", cmdsz); break; case R200_CP_CMD_TRANS_BITBLT: if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n", + fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n", cmdsz); break; case R200_CP_CMD_3D_DRAW_VBUF_2: if (NORMAL) - fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n", + fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n", cmdsz); if (print_prim_and_flags(cmd[1])) return -EINVAL; break; case R200_CP_CMD_3D_DRAW_IMMD_2: if (NORMAL) - fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n", + fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n", cmdsz); if (print_prim_and_flags(cmd[1])) return -EINVAL; break; case R200_CP_CMD_3D_DRAW_INDX_2: if (NORMAL) - fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n", + fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n", cmdsz); if (print_prim_and_flags(cmd[1])) return -EINVAL; @@ -1299,7 +1299,7 @@ static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz); break; } - + cmdbuf->buf += cmdsz * 4; cmdbuf->bufsz -= cmdsz * 4; return 0; @@ -1309,7 +1309,7 @@ static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) /* Check cliprects for bounds, then pass on to above: */ static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf ) -{ +{ drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes; int i = 0; @@ -1356,13 +1356,13 @@ int r200SanityCmdBuffer( r200ContextPtr rmesa, cmdbuf.nbox = nbox; while ( cmdbuf.bufsz >= sizeof(header) ) { - + header.i = *(int *)cmdbuf.buf; cmdbuf.buf += sizeof(header); cmdbuf.bufsz -= sizeof(header); switch (header.header.cmd_type) { - case RADEON_CMD_PACKET: + case RADEON_CMD_PACKET: if (radeon_emit_packets( header, &cmdbuf )) { fprintf(stderr,"radeon_emit_packets failed\n"); return -EINVAL; @@ -1422,7 +1422,7 @@ int r200SanityCmdBuffer( r200ContextPtr rmesa, break; default: - fprintf(stderr,"bad cmd_type %d at %p\n", + fprintf(stderr,"bad cmd_type %d at %p\n", header.header.cmd_type, cmdbuf.buf - sizeof(header)); return -EINVAL; @@ -1436,7 +1436,7 @@ int r200SanityCmdBuffer( r200ContextPtr rmesa, if (n == 10) { fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n", bufs, - total, total_changed, + total, total_changed, ((float)total_changed/(float)total*100.0)); fprintf(stderr, "Total emitted per buf: %.2f\n", (float)total/(float)bufs); diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index eff71dbd051..9f2070c5939 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -34,7 +34,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" + #include "main/enums.h" #include "main/light.h" #include "main/framebuffer.h" diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 9febc20363a..3d6e6559973 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -33,7 +33,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/errors.h" #include "main/glheader.h" -#include "util/imports.h" + #include "main/enums.h" #include "main/api_arrayelt.h" #include "main/state.h" @@ -164,12 +164,12 @@ static struct { /* ============================================================= * State initialization */ -static int cmdpkt( r200ContextPtr rmesa, int id ) +static int cmdpkt( r200ContextPtr rmesa, int id ) { return CP_PACKET0(packet[id].start, packet[id].len - 1); } -static int cmdvec( int offset, int stride, int count ) +static int cmdvec( int offset, int stride, int count ) { drm_radeon_cmd_header_t h; h.i = 0; @@ -182,7 +182,7 @@ static int cmdvec( int offset, int stride, int count ) /* warning: the count here is divided by 4 compared to other cmds (so it doesn't exceed the char size)! */ -static int cmdveclinear( int offset, int count ) +static int cmdveclinear( int offset, int count ) { drm_radeon_cmd_header_t h; h.i = 0; @@ -193,7 +193,7 @@ static int cmdveclinear( int offset, int count ) return h.i; } -static int cmdscl( int offset, int stride, int count ) +static int cmdscl( int offset, int stride, int count ) { drm_radeon_cmd_header_t h; h.i = 0; @@ -204,7 +204,7 @@ static int cmdscl( int offset, int stride, int count ) return h.i; } -static int cmdscl2( int offset, int stride, int count ) +static int cmdscl2( int offset, int stride, int count ) { drm_radeon_cmd_header_t h; h.i = 0; @@ -849,9 +849,9 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ptp.emit = ptp_emit; - rmesa->hw.mtl[0].cmd[MTL_CMD_0] = + rmesa->hw.mtl[0].cmd[MTL_CMD_0] = cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); - rmesa->hw.mtl[0].cmd[MTL_CMD_1] = + rmesa->hw.mtl[0].cmd[MTL_CMD_1] = cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 ); rmesa->hw.mtl[1].cmd[MTL_CMD_0] = cmdvec( R200_VS_MAT_1_EMISS, 1, 16 ); @@ -867,43 +867,43 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.vpp[1].cmd[VPP_CMD_0] = cmdveclinear( R200_PVS_PARAM1, 96 ); - rmesa->hw.grd.cmd[GRD_CMD_0] = + rmesa->hw.grd.cmd[GRD_CMD_0] = cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); - rmesa->hw.fog.cmd[FOG_CMD_0] = + rmesa->hw.fog.cmd[FOG_CMD_0] = cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 ); - rmesa->hw.glt.cmd[GLT_CMD_0] = + rmesa->hw.glt.cmd[GLT_CMD_0] = cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); - rmesa->hw.eye.cmd[EYE_CMD_0] = + rmesa->hw.eye.cmd[EYE_CMD_0] = cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 ); - rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_0_MV, 1, 16); - rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16); - rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_2_MVP, 1, 16); - rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16); - rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16); - rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16); - rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16); - rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16); - rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] = + rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] = cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16); for (i = 0 ; i < 8; i++) { - rmesa->hw.lit[i].cmd[LIT_CMD_0] = + rmesa->hw.lit[i].cmd[LIT_CMD_0] = cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); - rmesa->hw.lit[i].cmd[LIT_CMD_1] = + rmesa->hw.lit[i].cmd[LIT_CMD_1] = cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 ); } for (i = 0 ; i < 6; i++) { - rmesa->hw.ucp[i].cmd[UCP_CMD_0] = + rmesa->hw.ucp[i].cmd[UCP_CMD_0] = cmdvec( R200_VS_UCP_ADDR + i, 1, 4 ); } @@ -937,11 +937,11 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = + rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = ((rmesa->radeon.radeonScreen->depthPitch & R200_DEPTHPITCH_MASK) | R200_DEPTH_ENDIAN_NO_SWAP); - + if (rmesa->using_hyperz) rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; @@ -959,7 +959,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ } - rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE + rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE | R200_TEX_BLEND_0_ENABLE); switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { @@ -981,7 +981,7 @@ void r200InitState( r200ContextPtr rmesa ) else rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; - rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * + rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality"); rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; @@ -1003,13 +1003,13 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); - rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = + rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = ((0 << R200_LINE_CURRENT_PTR_SHIFT) | (1 << R200_LINE_CURRENT_COUNT_SHIFT)); rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = + rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = ((0x00 << R200_STENCIL_REF_SHIFT) | (0xff << R200_STENCIL_MASK_SHIFT) | (0xff << R200_STENCIL_WRITEMASK_SHIFT)); @@ -1019,7 +1019,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tam.cmd[TAM_DEBUG3] = 0; - rmesa->hw.msc.cmd[MSC_RE_MISC] = + rmesa->hw.msc.cmd[MSC_RE_MISC] = ((0 << R200_STIPPLE_X_OFFSET_SHIFT) | (0 << R200_STIPPLE_Y_OFFSET_SHIFT) | R200_STIPPLE_BIG_BIT_ORDER); @@ -1055,7 +1055,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] = (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) | (0x0B << R200_VTX_TEX_5_ADDR__SHIFT); - + rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; @@ -1066,7 +1066,7 @@ void r200InitState( r200ContextPtr rmesa ) for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL; - rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = + rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */ (2 << R200_TXFORMAT_WIDTH_SHIFT) | (2 << R200_TXFORMAT_HEIGHT_SHIFT)); @@ -1123,11 +1123,11 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0; rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0; - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = - (R200_VAP_TCL_ENABLE | + rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = + (R200_VAP_TCL_ENABLE | (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)); - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = + rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = (R200_VPORT_X_SCALE_ENA | R200_VPORT_Y_SCALE_ENA | R200_VPORT_Z_SCALE_ENA | @@ -1135,50 +1135,50 @@ void r200InitState( r200ContextPtr rmesa ) R200_VPORT_Y_OFFSET_ENA | R200_VPORT_Z_OFFSET_ENA | /* FIXME: Turn on for tex rect only */ - R200_VTX_ST_DENORMALIZED | - R200_VTX_W0_FMT); + R200_VTX_ST_DENORMALIZED | + R200_VTX_W0_FMT); rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0; rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = ((R200_VTX_Z0 | R200_VTX_W0 | - (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT))); + (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT))); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0; rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW); rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE; - + /* Matrix selection */ - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] = + rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] = (R200_MTX_MV << R200_MODELVIEW_0_SHIFT); - - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] = + + rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] = (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT); - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] = + rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] = (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT); - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] = + rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] = ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) | (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) | (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) | (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT)); - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] = + rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] = ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) | (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT)); /* General TCL state */ - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = + rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = (R200_SPECULAR_LIGHTS | R200_DIFFUSE_SPECULAR_COMBINE | R200_LOCAL_LIGHT_VEC_GL | R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT | R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT); - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = + rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) | (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | @@ -1186,34 +1186,34 @@ void r200InitState( r200ContextPtr rmesa ) (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) | (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) | (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT)); + (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT)); rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */ rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0; rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0; rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0; - - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = + + rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = (R200_UCP_IN_CLIP_SPACE | R200_CULL_FRONT_IS_CCW); /* Texgen/Texmat state */ rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = + rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) | (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) | (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) | (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) | (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) | - (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT)); - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = + (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT)); + rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; + rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = ((0 << R200_TEXGEN_0_INPUT_SHIFT) | (1 << R200_TEXGEN_1_INPUT_SHIFT) | (2 << R200_TEXGEN_2_INPUT_SHIFT) | (3 << R200_TEXGEN_3_INPUT_SHIFT) | (4 << R200_TEXGEN_4_INPUT_SHIFT) | - (5 << R200_TEXGEN_5_INPUT_SHIFT)); + (5 << R200_TEXGEN_5_INPUT_SHIFT)); rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0; @@ -1231,14 +1231,14 @@ void r200InitState( r200ContextPtr rmesa ) ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, &l->ConstantAttenuation ); - ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, + ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, &l->LinearAttenuation ); - ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, + ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, &l->QuadraticAttenuation ); *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; } - ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, + ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, ctx->Light.Model.Ambient ); TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); @@ -1253,7 +1253,7 @@ void r200InitState( r200ContextPtr rmesa ) ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); - + rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index d951bee4fa2..eda0411da03 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -36,7 +36,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/mtypes.h" #include "main/enums.h" #include "main/image.h" -#include "util/imports.h" + #include "main/macros.h" #include "main/state.h" diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 1802711eef0..d7b2479773d 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -33,7 +33,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" + #include "main/mtypes.h" #include "main/enums.h" #include "main/light.h" @@ -99,7 +99,7 @@ static GLboolean discrete_prim[0x10] = { 0, /* e quad strip */ 0, /* f polygon */ }; - + #define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx) #define ELT_TYPE GLushort @@ -138,7 +138,7 @@ static GLboolean discrete_prim[0x10] = { #define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr ) -static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) +static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { @@ -174,21 +174,21 @@ while (0) * discrete and there are no intervening state changes. (Somewhat * duplicates changes to DrawArrays code) */ -static void r200EmitPrim( struct gl_context *ctx, - GLenum prim, - GLuint hwprim, - GLuint start, - GLuint count) +static void r200EmitPrim( struct gl_context *ctx, + GLenum prim, + GLuint hwprim, + GLuint start, + GLuint count) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - + // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count); r200EmitAOS( rmesa, rmesa->radeon.tcl.aos_count, start ); - + /* Why couldn't this packet have taken an offset param? */ r200EmitVbufPrim( rmesa, @@ -238,7 +238,7 @@ static void r200EmitPrim( struct gl_context *ctx, /* External entrypoints */ /**********************************************************************/ -void r200EmitPrimitive( struct gl_context *ctx, +void r200EmitPrimitive( struct gl_context *ctx, GLuint first, GLuint last, GLuint flags ) @@ -246,7 +246,7 @@ void r200EmitPrimitive( struct gl_context *ctx, tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); } -void r200EmitEltPrimitive( struct gl_context *ctx, +void r200EmitEltPrimitive( struct gl_context *ctx, GLuint first, GLuint last, GLuint flags ) @@ -254,7 +254,7 @@ void r200EmitEltPrimitive( struct gl_context *ctx, tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); } -void r200TclPrimitive( struct gl_context *ctx, +void r200TclPrimitive( struct gl_context *ctx, GLenum prim, int hw_prim ) { @@ -360,14 +360,14 @@ static GLboolean r200_run_tcl_render( struct gl_context *ctx, struct vertex_buffer *VB = &tnl->vb; GLuint i; GLubyte *vimap_rev; -/* use hw fixed order for simplicity, pos 0, weight 1, normal 2, fog 3, +/* use hw fixed order for simplicity, pos 0, weight 1, normal 2, fog 3, color0 - color3 4-7, texcoord0 - texcoord5 8-13, pos 1 14. Must not use more than 12 of those at the same time. */ GLubyte map_rev_fixed[15] = {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255}; - /* TODO: separate this from the swtnl pipeline + /* TODO: separate this from the swtnl pipeline */ if (rmesa->radeon.TclFallback) return GL_TRUE; /* fallback to software t&l */ @@ -485,7 +485,7 @@ static GLboolean r200_run_tcl_render( struct gl_context *ctx, -/* Initial state for tcl stage. +/* Initial state for tcl stage. */ const struct tnl_pipeline_stage _r200_tcl_stage = { @@ -519,9 +519,9 @@ static void transition_to_swtnl( struct gl_context *ctx ) r200ChooseVertexState( ctx ); r200ChooseRenderState( ctx ); - _tnl_validate_shine_tables( ctx ); + _tnl_validate_shine_tables( ctx ); - tnl->Driver.NotifyMaterialChange = + tnl->Driver.NotifyMaterialChange = _tnl_validate_shine_tables; radeonReleaseArrays( ctx, ~0 ); @@ -544,11 +544,11 @@ static void transition_to_hwtnl( struct gl_context *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; - if ( rmesa->radeon.dma.flush ) - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); + if ( rmesa->radeon.dma.flush ) + rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); rmesa->radeon.dma.flush = NULL; - + R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_FORCE_W_TO_ONE; diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index c1d0717361c..51f4495e18a 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -32,7 +32,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" + #include "main/context.h" #include "main/enums.h" #include "main/image.h" @@ -52,7 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /** * Set the texture wrap modes. - * + * * \param t Texture object whose wrap modes are to be set * \param swrap Wrap mode for the \a s texture coordinate * \param twrap Wrap mode for the \a t texture coordinate @@ -205,7 +205,7 @@ static void r200SetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max ) /** * Set the texture magnification and minification modes. - * + * * \param t Texture whose filter modes are to be set * \param minf Texture minification mode * \param magf Texture magnification mode @@ -327,7 +327,7 @@ static void r200TexEnv( struct gl_context *ctx, GLenum target, const int fixed_one = R200_LOD_BIAS_FIXED_ONE; /* The R200's LOD bias is a signed 2's complement value with a - * range of -16.0 <= bias < 16.0. + * range of -16.0 <= bias < 16.0. * * NOTE: Add a small bias to the bias for conform mipsel.c test. */ @@ -337,7 +337,7 @@ static void r200TexEnv( struct gl_context *ctx, GLenum target, bias = CLAMP( bias, min, 16.0 ); b = ((int)(bias * fixed_one) + R200_LOD_BIAS_CORRECTION) & R200_LOD_BIAS_MASK; - + if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) { R200_STATECHANGE( rmesa, tex[unit] ); rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK; @@ -426,7 +426,7 @@ static void r200DeleteTexture(struct gl_context * ctx, struct gl_texture_object rmesa->hw.tex[i].dirty = GL_FALSE; rmesa->hw.cube[i].dirty = GL_FALSE; } - } + } } radeon_miptree_unreference(&t->mt); @@ -434,13 +434,13 @@ static void r200DeleteTexture(struct gl_context * ctx, struct gl_texture_object _mesa_delete_texture_object(ctx, texObj); } -/* Need: +/* Need: * - Same GEN_MODE for all active bits * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj * - STRQ presumably all supported (matrix means incoming R values * can end up in STQ, this has implications for vertex support, * presumably ok if maos is used, though?) - * + * * Basically impossible to do this on the fly - just collect some * basic info & do the checks from ValidateState(). */ diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index f98fadf560a..f736391ca55 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -33,7 +33,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" + #include "main/context.h" #include "main/macros.h" #include "main/state.h" @@ -457,7 +457,7 @@ static GLboolean r200UpdateTextureEnv( struct gl_context *ctx, int unit, int slo break; case GL_ADD: color_combine = (R200_TXC_ARG_B_ZERO | - R200_TXC_COMP_ARG_B | + R200_TXC_COMP_ARG_B | R200_TXC_OP_MADD); R200_COLOR_ARG( 0, A ); R200_COLOR_ARG( 1, C ); @@ -472,7 +472,7 @@ static GLboolean r200UpdateTextureEnv( struct gl_context *ctx, int unit, int slo break; case GL_SUBTRACT: color_combine = (R200_TXC_ARG_B_ZERO | - R200_TXC_COMP_ARG_B | + R200_TXC_COMP_ARG_B | R200_TXC_NEG_ARG_C | R200_TXC_OP_MADD); R200_COLOR_ARG( 0, A ); @@ -798,7 +798,7 @@ static GLboolean r200UpdateAllTexEnv( struct gl_context *ctx ) continue; } currentnext = j; - + const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB; const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA; const GLboolean isdot3rgba = (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) || @@ -940,10 +940,10 @@ static GLboolean r200UpdateAllTexEnv( struct gl_context *ctx ) R200_VOLUME_FILTER_MASK) -static void disable_tex_obj_state( r200ContextPtr rmesa, +static void disable_tex_obj_state( r200ContextPtr rmesa, int unit ) { - + R200_STATECHANGE( rmesa, vtx ); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); @@ -1002,7 +1002,7 @@ static void import_tex_obj_state( r200ContextPtr rmesa, } -static void set_texgen_matrix( r200ContextPtr rmesa, +static void set_texgen_matrix( r200ContextPtr rmesa, GLuint unit, const GLfloat *s_plane, const GLfloat *t_plane, @@ -1079,10 +1079,10 @@ static GLuint r200_need_dis_texgen(const GLbitfield texGenEnabled, /* - * Returns GL_FALSE if fallback required. + * Returns GL_FALSE if fallback required. */ static GLboolean r200_validate_texgen( struct gl_context *ctx, GLuint unit ) -{ +{ r200ContextPtr rmesa = R200_CONTEXT(ctx); const struct gl_fixedfunc_texture_unit *texUnit = &ctx->Texture.FixedFuncUnit[unit]; @@ -1110,7 +1110,7 @@ static GLboolean r200_validate_texgen( struct gl_context *ctx, GLuint unit ) tgcm = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] & ~(R200_TEXGEN_COMP_MASK << (unit * 4)); - if (0) + if (0) fprintf(stderr, "%s unit %d\n", __func__, unit); if (texUnit->TexGenEnabled & S_BIT) { @@ -1179,7 +1179,7 @@ static GLboolean r200_validate_texgen( struct gl_context *ctx, GLuint unit ) } tgi |= R200_TEXGEN_INPUT_OBJ << inputshift; - set_texgen_matrix( rmesa, unit, + set_texgen_matrix( rmesa, unit, (texUnit->TexGenEnabled & S_BIT) ? texUnit->GenS.ObjectPlane : I, (texUnit->TexGenEnabled & T_BIT) ? texUnit->GenT.ObjectPlane : I + 4, (texUnit->TexGenEnabled & R_BIT) ? texUnit->GenR.ObjectPlane : I + 8, @@ -1219,7 +1219,7 @@ static GLboolean r200_validate_texgen( struct gl_context *ctx, GLuint unit ) tgi |= R200_TEXGEN_INPUT_EYE_REFLECT << inputshift; /* pretty weird, must only negate when lighting is enabled? */ if (ctx->Light.Enabled) - set_texgen_matrix( rmesa, unit, + set_texgen_matrix( rmesa, unit, (texUnit->TexGenEnabled & S_BIT) ? reflect : I, (texUnit->TexGenEnabled & T_BIT) ? reflect + 4 : I + 4, (texUnit->TexGenEnabled & R_BIT) ? reflect + 8 : I + 8, @@ -1253,7 +1253,7 @@ static GLboolean r200_validate_texgen( struct gl_context *ctx, GLuint unit ) rmesa->TexGenEnabled |= R200_TEXGEN_TEXMAT_0_ENABLE << unit; rmesa->TexGenCompSel |= R200_OUTPUT_TEX_0 << unit; - if (tgi != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] || + if (tgi != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] || tgcm != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2]) { R200_STATECHANGE(rmesa, tcg); @@ -1313,11 +1313,11 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) #else const struct tx_table *table = tx_table_be; #endif - + t->pp_txformat &= ~(R200_TXFORMAT_FORMAT_MASK | R200_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~R200_YUV_TO_RGB; - + t->pp_txformat |= table[ firstImage->TexFormat ].format; t->pp_txfilter |= table[ firstImage->TexFormat ].filter; @@ -1349,9 +1349,9 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) R200_TXFORMAT_F5_HEIGHT_MASK); t->pp_txformat |= (((log2Width + extra_size) << R200_TXFORMAT_WIDTH_SHIFT) | ((log2Height + extra_size)<< R200_TXFORMAT_HEIGHT_SHIFT)); - + t->tile_bits = 0; - + t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK | R200_MIN_MIP_LEVEL_MASK); @@ -1424,7 +1424,7 @@ static GLboolean r200_validate_texture(struct gl_context *ctx, struct gl_texture set_re_cntl_d3d( ctx, unit, GL_TRUE ); R200_STATECHANGE( rmesa, ctx ); rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; - + R200_STATECHANGE( rmesa, vtx ); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c index 8332534c814..71fe9302cf7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c +++ b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c @@ -25,7 +25,6 @@ * */ -#include "util/imports.h" #include "main/mtypes.h" #include "main/bufferobj.h" #include "util/u_memory.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index ad63ea2d240..1b734d26a57 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -43,7 +43,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include <errno.h> #include "main/glheader.h" -#include "util/imports.h" #include "main/context.h" #include "main/enums.h" #include "main/fbobject.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 5435d0f34be..e05b8ba2ff6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/api_exec.h" #include "main/context.h" #include "util/simple_list.h" -#include "util/imports.h" #include "main/extensions.h" #include "main/version.h" #include "main/vtxfmt.h" @@ -76,7 +75,7 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = { /* Try and go straight to t&l */ - &_radeon_tcl_stage, + &_radeon_tcl_stage, /* Catch any t&l fallbacks */ @@ -95,7 +94,7 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = { static void r100_vtbl_pre_emit_state(radeonContextPtr radeon) { r100ContextPtr rmesa = (r100ContextPtr)radeon; - + /* r100 always needs to emit ZBS to avoid TCL lockups */ rmesa->hw.zbs.dirty = 1; radeon->hw.is_dirty = 1; @@ -228,7 +227,7 @@ r100CreateContext( gl_api api, ctx->Const.StripTextureBorder = GL_TRUE; - /* FIXME: When no memory manager is available we should set this + /* FIXME: When no memory manager is available we should set this * to some reasonable value based on texture memory pool size */ ctx->Const.MaxTextureSize = 2048; ctx->Const.Max3DTextureLevels = 9; @@ -255,9 +254,9 @@ r100CreateContext( gl_api api, * fit in a single dma buffer for indexed rendering of quad strips, * etc. */ - ctx->Const.MaxArrayLockSize = - MIN2( ctx->Const.MaxArrayLockSize, - RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE ); + ctx->Const.MaxArrayLockSize = + MIN2( ctx->Const.MaxArrayLockSize, + RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE ); rmesa->boxes = 0; @@ -319,7 +318,7 @@ r100CreateContext( gl_api api, radeonInitState( rmesa ); radeonInitSwtcl( ctx ); - _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, + _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, ctx->Const.MaxArrayLockSize, 32 ); fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 6105a9cf916..cff0c0d6f5f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -1,8 +1,8 @@ /************************************************************************** - * + * * Copyright 2008 Red Hat Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. @@ -22,11 +22,10 @@ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ -#include "util/imports.h" #include "main/macros.h" #include "main/mtypes.h" #include "main/enums.h" @@ -177,7 +176,7 @@ radeon_map_renderbuffer_s8z24(struct gl_renderbuffer *rb, } radeon_bo_unmap(rrb->bo); - + *out_map = rrb->map_buffer; *out_stride = rrb->map_pitch; } @@ -275,7 +274,7 @@ radeon_map_renderbuffer(struct gl_context *ctx, rrb->map_bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, rrb->map_pitch * h, 4, RADEON_GEM_DOMAIN_GTT, 0); - + ok = rmesa->vtbl.blit(ctx, rrb->bo, rrb->draw_offset, rb->Format, rrb->pitch / rrb->cpp, rb->Width, rb->Height, @@ -359,7 +358,7 @@ radeon_unmap_renderbuffer_s8z24(struct gl_context *ctx, int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0; radeon_bo_map(rrb->bo, 1); - + tiled_s8z24_map = rrb->bo->ptr; for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) { @@ -392,7 +391,7 @@ radeon_unmap_renderbuffer_z16(struct gl_context *ctx, int y_bias = (rb->Name == 0) ? (rb->Height - 1) : 0; radeon_bo_map(rrb->bo, 1); - + tiled_z16_map = rrb->bo->ptr; for (uint32_t pix_y = 0; pix_y < rrb->map_h; pix_y++) { @@ -732,7 +731,7 @@ radeon_framebuffer_renderbuffer(struct gl_context * ctx, } static GLboolean -radeon_update_wrapper(struct gl_context *ctx, struct radeon_renderbuffer *rrb, +radeon_update_wrapper(struct gl_context *ctx, struct radeon_renderbuffer *rrb, struct gl_texture_image *texImage) { struct gl_renderbuffer *rb = &rrb->base.Base; @@ -881,7 +880,7 @@ void radeon_fbo_init(struct radeon_context *radeon) radeon_image_target_renderbuffer_storage; } - + void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, struct radeon_bo *bo) { diff --git a/src/mesa/drivers/dri/radeon/radeon_fog.c b/src/mesa/drivers/dri/radeon/radeon_fog.c index c4df8d28cce..107bc23295a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fog.c +++ b/src/mesa/drivers/dri/radeon/radeon_fog.c @@ -34,7 +34,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "c99_math.h" #include "main/glheader.h" -#include "util/imports.h" #include "main/context.h" #include "main/mtypes.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index f5092a414bb..90f8a6cf263 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -42,7 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "main/glheader.h" -#include "util/imports.h" #include "util/simple_list.h" #include "radeon_context.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index bdfa0a8ca1c..0ac3748da49 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -33,7 +33,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" #include "main/mtypes.h" #include "main/macros.h" @@ -139,7 +138,7 @@ static void emit_tex_vector(struct gl_context *ctx, struct radeon_aos *aos, /* Emit any changed arrays to new GART memory, re-emit a packet to - * update the arrays. + * update the arrays. */ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) { @@ -149,15 +148,15 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) GLuint vfmt = 0; GLuint count = VB->Count; GLuint vtx, unit; - + #if 0 if (RADEON_DEBUG & RADEON_VERTS) _tnl_print_vert_flags( __func__, inputs ); #endif if (1) { - if (!rmesa->tcl.obj.buf) - rcommon_emit_vector( ctx, + if (!rmesa->tcl.obj.buf) + rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[_TNL_ATTRIB_POS]->data, VB->AttribPtr[_TNL_ATTRIB_POS]->size, @@ -173,11 +172,11 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) } nr++; } - + if (inputs & VERT_BIT_NORMAL) { if (!rmesa->tcl.norm.buf) - rcommon_emit_vector( ctx, + rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[_TNL_ATTRIB_NORMAL]->data, 3, @@ -247,7 +246,7 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2)); - + for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) { if (inputs & VERT_BIT_TEX(unit)) { if (!rmesa->tcl.tex[unit].buf) diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 443068e06d9..51a85d17e45 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -33,7 +33,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" #include "main/mtypes.h" #include "main/state.h" @@ -280,7 +279,7 @@ static struct { /*********************************************************************** - * Initialization + * Initialization ***********************************************************************/ @@ -370,8 +369,8 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; } - for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++) - if ((setup_tab[i].vertex_format & req) == req) + for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++) + if ((setup_tab[i].vertex_format & req) == req) break; if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && @@ -384,12 +383,12 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) radeonAllocDmaRegion( &rmesa->radeon, &rmesa->radeon.tcl.aos[0].bo, &rmesa->radeon.tcl.aos[0].offset, - VB->Count * setup_tab[i].vertex_size * 4, + VB->Count * setup_tab[i].vertex_size * 4, 4); /* The vertex code expects Obj to be clean to element 3. To fix * this, add more vertex code (for obj-2, obj-3) or preferably move - * to maos. + * to maos. */ if (VB->AttribPtr[_TNL_ATTRIB_POS]->size < 3 || (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 3 && @@ -422,7 +421,7 @@ void radeonEmitArrays( struct gl_context *ctx, GLuint inputs ) radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1); - setup_tab[i].emit( ctx, 0, VB->Count, + setup_tab[i].emit( ctx, 0, VB->Count, rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset); radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo); // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size; diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c index 5225c99145d..ae2c721ce66 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c @@ -28,7 +28,7 @@ #include "radeon_queryobj.h" #include "radeon_debug.h" -#include "util/imports.h" + #include "main/queryobj.h" #include <inttypes.h> diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.h b/src/mesa/drivers/dri/radeon/radeon_queryobj.h index e1cda17b005..9dfeccbc4bb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.h +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.h @@ -25,7 +25,6 @@ * */ -#include "util/imports.h" #include "util/simple_list.h" #include "radeon_common_context.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index c5bd995fe9d..62e680cd6db 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -37,7 +37,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include <errno.h> #include "main/glheader.h" -#include "util/imports.h" #include "main/mtypes.h" #include "main/framebuffer.h" #include "main/renderbuffer.h" @@ -711,7 +710,7 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv, MESA_FORMAT_X8R8G8B8_UNORM; #endif else - rgbFormat = + rgbFormat = #if UTIL_ARCH_LITTLE_ENDIAN MESA_FORMAT_B8G8R8A8_UNORM; #else diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index b3873e2c0ec..59dc4708901 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -33,7 +33,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" #include "main/enums.h" #include "main/light.h" #include "main/context.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 18e0fea490e..ac387184f69 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -29,7 +29,6 @@ #include "main/errors.h" #include "main/glheader.h" -#include "util/imports.h" #include "main/api_arrayelt.h" #include "swrast/swrast.h" @@ -159,12 +158,12 @@ static struct { /* ============================================================= * State initialization */ -static int cmdpkt( r100ContextPtr rmesa, int id ) +static int cmdpkt( r100ContextPtr rmesa, int id ) { return CP_PACKET0(packet[id].start, packet[id].len - 1); } -static int cmdvec( int offset, int stride, int count ) +static int cmdvec( int offset, int stride, int count ) { drm_radeon_cmd_header_t h; h.i = 0; @@ -175,7 +174,7 @@ static int cmdvec( int offset, int stride, int count ) return h.i; } -static int cmdscl( int offset, int stride, int count ) +static int cmdscl( int offset, int stride, int count ) { drm_radeon_cmd_header_t h; h.i = 0; @@ -263,7 +262,7 @@ static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); uint32_t dwords = atom->check(ctx, atom); - + BEGIN_BATCH(dwords); OUT_SCL(atom->cmd[0], atom->cmd+1); END_BATCH(); @@ -367,7 +366,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; - + } BEGIN_BATCH(dwords); @@ -617,34 +616,34 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2); rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); - rmesa->hw.mtl.cmd[MTL_CMD_0] = + rmesa->hw.mtl.cmd[MTL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); - rmesa->hw.grd.cmd[GRD_CMD_0] = + rmesa->hw.grd.cmd[GRD_CMD_0] = cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); - rmesa->hw.fog.cmd[FOG_CMD_0] = + rmesa->hw.fog.cmd[FOG_CMD_0] = cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); - rmesa->hw.glt.cmd[GLT_CMD_0] = + rmesa->hw.glt.cmd[GLT_CMD_0] = cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); - rmesa->hw.eye.cmd[EYE_CMD_0] = + rmesa->hw.eye.cmd[EYE_CMD_0] = cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); for (i = 0 ; i < 6; i++) { - rmesa->hw.mat[i].cmd[MAT_CMD_0] = + rmesa->hw.mat[i].cmd[MAT_CMD_0] = cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); } for (i = 0 ; i < 8; i++) { - rmesa->hw.lit[i].cmd[LIT_CMD_0] = + rmesa->hw.lit[i].cmd[LIT_CMD_0] = cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); - rmesa->hw.lit[i].cmd[LIT_CMD_1] = + rmesa->hw.lit[i].cmd[LIT_CMD_1] = cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); } for (i = 0 ; i < 6; i++) { - rmesa->hw.ucp[i].cmd[UCP_CMD_0] = + rmesa->hw.ucp[i].cmd[UCP_CMD_0] = cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); } @@ -699,7 +698,7 @@ void radeonInitState( r100ContextPtr rmesa ) /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ /* need this otherwise get lots of lockups with q3 ??? */ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; - } + } } rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | @@ -761,13 +760,13 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); - rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = + rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = + rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = ((0x00 << RADEON_STENCIL_REF_SHIFT) | (0xff << RADEON_STENCIL_MASK_SHIFT) | (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); @@ -775,7 +774,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; - rmesa->hw.msc.cmd[MSC_RE_MISC] = + rmesa->hw.msc.cmd[MSC_RE_MISC] = ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | RADEON_STIPPLE_BIG_BIT_ORDER); @@ -789,7 +788,7 @@ void radeonInitState( r100ContextPtr rmesa ) for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; - rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = + rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = (RADEON_TXFORMAT_ENDIAN_NO_SWAP | RADEON_TXFORMAT_PERSPECTIVE_ENABLE | (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ @@ -801,14 +800,14 @@ void radeonInitState( r100ContextPtr rmesa ) // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; - rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = + rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = (RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | RADEON_COLOR_ARG_C_CURRENT_COLOR | RADEON_BLEND_CTL_ADD | RADEON_SCALE_1X | RADEON_CLAMP_TX); - rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = + rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = (RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO | RADEON_ALPHA_ARG_C_CURRENT_ALPHA | @@ -833,12 +832,12 @@ void radeonInitState( r100ContextPtr rmesa ) /* Can only add ST1 at the time of doing some multitex but can keep * it after that. Errors if DIFFUSE is missing. */ - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = (RADEON_TCL_VTX_Z0 | RADEON_TCL_VTX_W0 | RADEON_TCL_VTX_PK_DIFFUSE ); /* need to keep this uptodate */ - + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = ( RADEON_TCL_COMPUTE_XYZW | (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | @@ -847,23 +846,23 @@ void radeonInitState( r100ContextPtr rmesa ) /* XXX */ - rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = + rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = ((MODEL << RADEON_MODELVIEW_0_SHIFT) | (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); - rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = + rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = + rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = (RADEON_UCP_IN_CLIP_SPACE | RADEON_CULL_FRONT_IS_CCW); - rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; + rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = + rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = (RADEON_SPECULAR_LIGHTS | RADEON_DIFFUSE_SPECULAR_COMBINE | RADEON_LOCAL_LIGHT_VEC_GL | @@ -886,14 +885,14 @@ void radeonInitState( r100ContextPtr rmesa ) ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, &l->ConstantAttenuation ); - ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, + ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, &l->LinearAttenuation ); - ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, + ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, &l->QuadraticAttenuation ); *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; } - ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, + ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, ctx->Light.Model.Ambient ); TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); @@ -908,7 +907,7 @@ void radeonInitState( r100ContextPtr rmesa ) ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); - + rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; @@ -922,7 +921,7 @@ void radeonInitState( r100ContextPtr rmesa ) radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; - + rmesa->radeon.hw.all_dirty = GL_TRUE; rcommonInitCmdBuf(&rmesa->radeon); diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 84e216281e3..f1e55e0b68e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -35,7 +35,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/glheader.h" #include "main/mtypes.h" #include "main/enums.h" -#include "util/imports.h" #include "main/macros.h" #include "main/state.h" @@ -60,7 +59,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */ /*********************************************************************** - * Initialization + * Initialization ***********************************************************************/ #define EMIT_ATTR( ATTR, STYLE, F0 ) \ @@ -113,19 +112,19 @@ static void radeonSetVertexFormat( struct gl_context *ctx ) if ( !rmesa->swtcl.needproj || (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) { /* for projtex */ - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F, + EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F, RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 ); offset = 4; } else { - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F, + EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F, RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z ); offset = 3; } rmesa->swtcl.coloroffset = offset; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, +#if MESA_LITTLE_ENDIAN + EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, RADEON_CP_VC_FRMT_PKCOLOR ); #else EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, @@ -137,7 +136,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx ) if (index_bitset & (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) { -#if MESA_LITTLE_ENDIAN +#if MESA_LITTLE_ENDIAN if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { rmesa->swtcl.specoffset = offset; EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, @@ -220,7 +219,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx ) rmesa->swtcl.vertex_format = fmt_0; rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attrs, rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); rmesa->radeon.swtcl.vertex_size /= 4; @@ -277,7 +276,7 @@ void radeonChooseVertexState( struct gl_context *ctx ) GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL || ctx->Polygon.BackMode != GL_FILL); GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide; - + se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | RADEON_VTX_Z_PRE_MULT_1_OVER_W0 | RADEON_VTX_W0_IS_NOT_1_OVER_W0); @@ -293,7 +292,7 @@ void radeonChooseVertexState( struct gl_context *ctx ) * bigger one. */ - if ((0 == (tnl->render_inputs_bitset & + if ((0 == (tnl->render_inputs_bitset & (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX) | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)))) || twosided @@ -327,7 +326,7 @@ void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset) rmesa->radeon.swtcl.bo, current_offset); - + radeonEmitVbufPrim( rmesa, rmesa->swtcl.vertex_format, rmesa->radeon.swtcl.hw_primitive, @@ -438,7 +437,7 @@ static GLboolean radeon_run_render( struct gl_context *ctx, radeon_print(RADEON_SWRENDER, RADEON_NORMAL, "radeon_render.c: prim %s %d..%d\n", - _mesa_enum_to_string(prim & PRIM_MODE_MASK), + _mesa_enum_to_string(prim & PRIM_MODE_MASK), start, start+length); if (length) @@ -498,7 +497,7 @@ static void radeonResetLineStipple( struct gl_context *ctx ); r100ContextPtr rmesa = R100_CONTEXT(ctx); \ const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int))) -#define VERTEX radeonVertex +#define VERTEX radeonVertex #undef TAG #define TAG(x) radeon_##x #include "tnl_dd/t_dd_triemit.h" @@ -699,7 +698,7 @@ void radeonChooseRenderState( struct gl_context *ctx ) ctx->Polygon.BackMode != GL_FILL); GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide; - if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) + if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) return; if (twosided) @@ -751,7 +750,7 @@ static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim ) ctx->Polygon.BackMode != GL_FILL); rmesa->radeon.swtcl.render_primitive = prim; - if (prim < GL_TRIANGLES || !unfilled) + if (prim < GL_TRIANGLES || !unfilled) radeonRasterPrimitive( ctx, reduced_hw_prim[prim] ); } @@ -870,9 +869,9 @@ void radeonInitSwtcl( struct gl_context *ctx ) tnl->Driver.Render.CopyPV = _tnl_copy_pv; tnl->Driver.Render.Interp = _tnl_interp; - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, + _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, RADEON_MAX_TNL_VERTEX_SIZE); - + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 0a228d21aaf..4f0a127314a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -33,7 +33,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" #include "main/mtypes.h" #include "main/light.h" #include "main/enums.h" @@ -105,7 +104,7 @@ static GLboolean discrete_prim[0x10] = { 0, 0, }; - + #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx) #define ELT_TYPE GLushort @@ -146,7 +145,7 @@ static GLboolean discrete_prim[0x10] = { #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr ) -static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) +static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) { if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); @@ -166,19 +165,19 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) * discrete and there are no intervening state changes. (Somewhat * duplicates changes to DrawArrays code) */ -static void radeonEmitPrim( struct gl_context *ctx, - GLenum prim, - GLuint hwprim, - GLuint start, - GLuint count) +static void radeonEmitPrim( struct gl_context *ctx, + GLenum prim, + GLuint hwprim, + GLuint start, + GLuint count) { r100ContextPtr rmesa = R100_CONTEXT( ctx ); radeonTclPrimitive( ctx, prim, hwprim ); - + radeonEmitAOS( rmesa, rmesa->radeon.tcl.aos_count, start ); - + /* Why couldn't this packet have taken an offset param? */ radeonEmitVbufPrim( rmesa, @@ -230,7 +229,7 @@ static void radeonEmitPrim( struct gl_context *ctx, /* External entrypoints */ /**********************************************************************/ -void radeonEmitPrimitive( struct gl_context *ctx, +void radeonEmitPrimitive( struct gl_context *ctx, GLuint first, GLuint last, GLuint flags ) @@ -238,7 +237,7 @@ void radeonEmitPrimitive( struct gl_context *ctx, tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); } -void radeonEmitEltPrimitive( struct gl_context *ctx, +void radeonEmitEltPrimitive( struct gl_context *ctx, GLuint first, GLuint last, GLuint flags ) @@ -246,7 +245,7 @@ void radeonEmitEltPrimitive( struct gl_context *ctx, tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); } -void radeonTclPrimitive( struct gl_context *ctx, +void radeonTclPrimitive( struct gl_context *ctx, GLenum prim, int hw_prim ) { @@ -267,7 +266,7 @@ void radeonTclPrimitive( struct gl_context *ctx, se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL]; se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST; - if (prim == GL_POLYGON && ctx->Light.ShadeModel == GL_FLAT) + if (prim == GL_POLYGON && ctx->Light.ShadeModel == GL_FLAT) se_cntl |= RADEON_FLAT_SHADE_VTX_0; else se_cntl |= RADEON_FLAT_SHADE_VTX_LAST; @@ -363,7 +362,7 @@ static GLboolean radeon_run_tcl_render( struct gl_context *ctx, GLuint i; GLuint emit_end; - /* TODO: separate this from the swtnl pipeline + /* TODO: separate this from the swtnl pipeline */ if (rmesa->radeon.TclFallback) return GL_TRUE; /* fallback to software t&l */ @@ -427,7 +426,7 @@ static GLboolean radeon_run_tcl_render( struct gl_context *ctx, -/* Initial state for tcl stage. +/* Initial state for tcl stage. */ const struct tnl_pipeline_stage _radeon_tcl_stage = { @@ -463,16 +462,16 @@ static void transition_to_swtnl( struct gl_context *ctx ) radeonChooseVertexState( ctx ); radeonChooseRenderState( ctx ); - _tnl_validate_shine_tables( ctx ); + _tnl_validate_shine_tables( ctx ); - tnl->Driver.NotifyMaterialChange = + tnl->Driver.NotifyMaterialChange = _tnl_validate_shine_tables; radeonReleaseArrays( ctx, ~0 ); se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL]; se_cntl |= RADEON_FLAT_SHADE_VTX_LAST; - + if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) { RADEON_STATECHANGE( rmesa, set ); rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl; @@ -501,14 +500,14 @@ static void transition_to_hwtnl( struct gl_context *ctx ) tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial; - if ( rmesa->radeon.dma.flush ) - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); + if ( rmesa->radeon.dma.flush ) + rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); rmesa->radeon.dma.flush = NULL; rmesa->swtcl.vertex_format = 0; - - // if (rmesa->swtcl.indexed_verts.buf) - // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + + // if (rmesa->swtcl.indexed_verts.buf) + // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, // __func__ ); if (RADEON_DEBUG & RADEON_FALLBACKS) diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index bdae54eecad..c3d7affffab 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -32,7 +32,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" #include "main/context.h" #include "main/enums.h" #include "main/image.h" @@ -51,7 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /** * Set the texture wrap modes. - * + * * \param t Texture object whose wrap modes are to be set * \param swrap Wrap mode for the \a s texture coordinate * \param twrap Wrap mode for the \a t texture coordinate @@ -158,7 +157,7 @@ static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max ) /** * Set the texture magnification and minification modes. - * + * * \param t Texture whose filter modes are to be set * \param minf Texture minification mode * \param magf Texture magnification mode @@ -378,13 +377,13 @@ static void radeonDeleteTexture( struct gl_context *ctx, _mesa_delete_texture_object(ctx, texObj); } -/* Need: +/* Need: * - Same GEN_MODE for all active bits * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj * - STRQ presumably all supported (matrix means incoming R values * can end up in STQ, this has implications for vertex support, * presumably ok if maos is used, though?) - * + * * Basically impossible to do this on the fly - just collect some * basic info & do the checks from ValidateState(). */ @@ -418,7 +417,7 @@ radeonNewTextureObject( struct gl_context *ctx, GLuint name, GLenum target ) t->pp_txfilter = RADEON_BORDER_MODE_OGL; t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP | RADEON_TXFORMAT_PERSPECTIVE_ENABLE); - + radeonSetTexWrap( t, t->base.Sampler.WrapS, t->base.Sampler.WrapT ); radeonSetTexMaxAnisotropy( t, t->base.Sampler.MaxAnisotropy ); radeonSetTexFilter( t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter ); diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 30cdc56bf1e..79f0095f480 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -34,7 +34,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" -#include "util/imports.h" #include "main/context.h" #include "main/macros.h" #include "main/teximage.h" @@ -326,7 +325,7 @@ static GLboolean radeonUpdateTextureEnv( struct gl_context *ctx, int unit ) break; case GL_TEXTURE0: case GL_TEXTURE1: - case GL_TEXTURE2: { + case GL_TEXTURE2: { GLuint txunit = srcAi - GL_TEXTURE0; if (texture_base_format(ctx->Texture.Unit[txunit]._Current) == GL_LUMINANCE) alpha_arg[i] = radeon_zero_alpha[op+1]; @@ -670,7 +669,7 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri RADEON_TXFORMAT_NON_POWER2) -static void disable_tex_obj_state( r100ContextPtr rmesa, +static void disable_tex_obj_state( r100ContextPtr rmesa, int unit ) { RADEON_STATECHANGE( rmesa, tex[unit] ); @@ -678,7 +677,7 @@ static void disable_tex_obj_state( r100ContextPtr rmesa, RADEON_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | RADEON_Q_BIT(unit)); - + if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) { TCL_FALLBACK( &rmesa->radeon.glCtx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE); rmesa->recheck_texgen[unit] = GL_TRUE; @@ -701,7 +700,7 @@ static void disable_tex_obj_state( r100ContextPtr rmesa, rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit); rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift); rmesa->TexGenNeedNormals[unit] = 0; - rmesa->TexGenEnabled |= + rmesa->TexGenEnabled |= (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift; if (tmp != rmesa->TexGenEnabled) { @@ -758,7 +757,7 @@ static void import_tex_obj_state( r100ContextPtr rmesa, } -static void set_texgen_matrix( r100ContextPtr rmesa, +static void set_texgen_matrix( r100ContextPtr rmesa, GLuint unit, const GLfloat *s_plane, const GLfloat *t_plane, @@ -928,8 +927,8 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | RADEON_TXFORMAT_ALPHA_IN_MAP); - t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - + t->pp_txfilter &= ~RADEON_YUV_TO_RGB; + t->pp_txformat |= table[ firstImage->TexFormat ].format; t->pp_txfilter |= table[ firstImage->TexFormat ].filter; } else { @@ -941,7 +940,7 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; t->pp_txfilter |= (t->maxLod - t->minLod) << RADEON_MAX_MIP_LEVEL_SHIFT; - + t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK | RADEON_TXFORMAT_HEIGHT_MASK | RADEON_TXFORMAT_CUBIC_MAP_ENABLE | @@ -1004,7 +1003,7 @@ static GLboolean radeon_validate_texture(struct gl_context *ctx, struct gl_textu return GL_FALSE; RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= + rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; RADEON_STATECHANGE( rmesa, tcl ); rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 3bf7a0dbec3..86059c44751 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -30,7 +30,6 @@ */ #include "main/glheader.h" -#include "util/imports.h" #include "main/context.h" #include "main/enums.h" #include "main/mipmap.h" @@ -113,7 +112,7 @@ radeonAllocTextureImageBuffer(struct gl_context *ctx, return GL_FALSE; teximage_assign_miptree(rmesa, texobj, timage); - + return GL_TRUE; } @@ -182,7 +181,7 @@ radeon_map_texture_image(struct gl_context *ctx, } else if (likely(mt)) { void *base; radeon_mipmap_level *lvl = &image->mt->levels[texImage->Level]; - + radeon_bo_map(mt->bo, write); base = mt->bo->ptr + lvl->faces[image->base.Base.Face].offset; @@ -687,6 +686,6 @@ static radeon_mipmap_tree *radeon_miptree_create_for_teximage(radeonContextPtr r return radeon_miptree_create(rmesa, texObj->Target, texImage->TexFormat, firstLevel, lastLevel - firstLevel + 1, - width, height, depth, + width, height, depth, t->tile_bits); -} +} diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c index 1c1ecb66efd..a4f2985b6ab 100644 --- a/src/mesa/drivers/dri/swrast/swrast.c +++ b/src/mesa/drivers/dri/swrast/swrast.c @@ -39,7 +39,6 @@ #include "main/fbobject.h" #include "main/formats.h" #include "main/framebuffer.h" -#include "util/imports.h" #include "main/renderbuffer.h" #include "main/version.h" #include "main/vtxfmt.h" |