Merge commit 'origin/gallium-0.2' into gallium-xlib-rework

Conflicts:

	progs/glsl/Makefile

24 files changed, 574 insertions, 207 deletions

diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
index a2316e2662b..ae790554055 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -314,10 +314,28 @@ static void driReportDamage(__DRIdrawable *pdp,
 static void driSwapBuffers(__DRIdrawable *dPriv)
 {
     __DRIscreen *psp = dPriv->driScreenPriv;
+    drm_clip_rect_t *rects;
+    int i;
+    
+    if (!dPriv->numClipRects)
+        return;
 
     psp->DriverAPI.SwapBuffers(dPriv);
 
-    driReportDamage(dPriv, dPriv->pClipRects, dPriv->numClipRects);
+    rects = _mesa_malloc(sizeof(*rects) * dPriv->numClipRects);
+
+    if (!rects)
+        return;
+
+    for (i = 0; i < dPriv->numClipRects; i++) {
+        rects[i].x1 = dPriv->pClipRects[i].x1 - dPriv->x;
+        rects[i].y1 = dPriv->pClipRects[i].y1 - dPriv->y;
+        rects[i].x2 = dPriv->pClipRects[i].x2 - dPriv->x;
+        rects[i].y2 = dPriv->pClipRects[i].y2 - dPriv->y;
+    }
+
+    driReportDamage(dPriv, rects, dPriv->numClipRects);
+    _mesa_free(rects);
 }
 
 static int driDrawableGetMSC( __DRIscreen *sPriv, __DRIdrawable *dPriv,
diff --git a/src/mesa/drivers/dri/common/vblank.c b/src/mesa/drivers/dri/common/vblank.c
index d610253fe6f..12aeaa108f7 100644
--- a/src/mesa/drivers/dri/common/vblank.c
+++ b/src/mesa/drivers/dri/common/vblank.c
@@ -130,9 +130,8 @@ int driWaitForMSC32( __DRIdrawablePrivate *priv,
 
 
    if ( divisor != 0 ) {
-      unsigned int target = (unsigned int)target_msc;
-      unsigned int next = target;
-      unsigned int r;
+      int64_t next = target_msc;
+      int64_t r;
       int dont_wait = (target_msc == 0);
 
       do {
@@ -154,9 +153,9 @@ int driWaitForMSC32( __DRIdrawablePrivate *priv,
 
 	 *msc = vblank_to_msc(priv, vbl.reply.sequence);
 
-         dont_wait = 0;
-         if (target_msc != 0 && *msc == target)
+         if (!dont_wait && *msc == next)
             break;
+         dont_wait = 0;
 
          /* Assuming the wait-done test fails, the next refresh to wait for
           * will be one that satisfies (MSC % divisor) == remainder.  The
@@ -165,11 +164,12 @@ int driWaitForMSC32( __DRIdrawablePrivate *priv,
           * If this refresh has already happened, we add divisor to obtain 
           * the next refresh after the current one that will satisfy it.
           */
-         r = (*msc % (unsigned int)divisor);
-         next = (*msc - r + (unsigned int)remainder);
-         if (next <= *msc) next += (unsigned int)divisor;
+         r = ((uint64_t)*msc % divisor);
+         next = (*msc - r + remainder);
+         if (next <= *msc)
+	    next += divisor;
 
-      } while ( r != (unsigned int)remainder );
+      } while (r != remainder);
    }
    else {
       /* If the \c divisor is zero, just wait until the MSC is greater
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index e0ddc7fd613..9bff74294d8 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -55,6 +55,7 @@ static const struct dri_extension i915_extensions[] = {
    {"GL_ARB_fragment_program", NULL},
    {"GL_ARB_shadow", NULL},
    {"GL_ARB_texture_non_power_of_two", NULL},
+   {"GL_ATI_texture_env_combine3",       NULL},
    {"GL_EXT_shadow_funcs", NULL},
    {NULL, NULL}
 };
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 8bd761ec6a1..4760906a7ed 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1105,30 +1105,14 @@ i915ValidateFragmentProgram(struct i915_context *i915)
       EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
    }
 
-   if ((inputsRead & (FRAG_BIT_COL1 | FRAG_BIT_FOGC)) ||
-       i915->vertex_fog != I915_FOG_NONE) {
-
-      if (inputsRead & FRAG_BIT_COL1) {
-         intel->specoffset = offset / 4;
-         EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3);
-      }
-      else
-         EMIT_PAD(3);
-
-      if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE)
-         EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1);
-      else
-         EMIT_PAD(1);
+   if (inputsRead & FRAG_BIT_COL1) {
+       intel->specoffset = offset / 4;
+       EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_4UB_4F_BGRA, S4_VFMT_SPEC_FOG, 4);
    }
 
-   /* XXX this was disabled, but enabling this code helped fix the Glean
-    * tfragprog1 fog tests.
-    */
-#if 1
    if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE) {
       EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4);
    }
-#endif
 
    for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
       if (inputsRead & FRAG_BIT_TEX(i)) {
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 1d6ac2cea68..a415e378fff 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -32,6 +32,7 @@
 
 #include "main/imports.h"
 #include "main/api_noop.h"
+#include "main/macros.h"
 #include "main/vtxfmt.h"
 #include "main/simple_list.h"
 #include "shader/shader_api.h"
@@ -128,9 +129,10 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
 
    TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 
-   ctx->Const.MaxTextureUnits = BRW_MAX_TEX_UNIT;
    ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
-   ctx->Const.MaxTextureCoordUnits = BRW_MAX_TEX_UNIT;
+   ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
+   ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
+                                     ctx->Const.MaxTextureImageUnits);
    ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */
 
    /* Advertise the full hardware capabilities.  The new memory
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 77980109cdf..5d3f99e025e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -238,7 +238,7 @@ struct brw_vs_ouput_sizes {
 };
 
 
-#define BRW_MAX_TEX_UNIT 8
+#define BRW_MAX_TEX_UNIT 16
 #define BRW_WM_MAX_SURF BRW_MAX_TEX_UNIT + MAX_DRAW_BUFFERS
 
 enum brw_cache_id {
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 49b422ee2ff..9e2b39af9bb 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -129,17 +129,28 @@ static INLINE int type_sz( GLuint type )
    }
 }
 
+/**
+ * Construct a brw_reg.
+ * \param file  one of the BRW_x_REGISTER_FILE values
+ * \param nr  register number/index
+ * \param subnr  register sub number
+ * \param type  one of BRW_REGISTER_TYPE_x
+ * \param vstride  one of BRW_VERTICAL_STRIDE_x
+ * \param width  one of BRW_WIDTH_x
+ * \param hstride  one of BRW_HORIZONTAL_STRIDE_x
+ * \param swizzle  one of BRW_SWIZZLE_x
+ * \param writemask  WRITEMASK_X/Y/Z/W bitfield
+ */
 static INLINE struct brw_reg brw_reg( GLuint file,
-					GLuint nr,
-					GLuint subnr,
-					GLuint type,
-					GLuint vstride,
-					GLuint width,
-					GLuint hstride,
-					GLuint swizzle,
-					GLuint writemask)
-{
-      
+                                      GLuint nr,
+                                      GLuint subnr,
+                                      GLuint type,
+                                      GLuint vstride,
+                                      GLuint width,
+                                      GLuint hstride,
+                                      GLuint swizzle,
+                                      GLuint writemask )
+{
    struct brw_reg reg;
    reg.type = type;
    reg.file = file;
@@ -166,6 +177,7 @@ static INLINE struct brw_reg brw_reg( GLuint file,
    return reg;
 }
 
+/** Construct float[16] register */
 static INLINE struct brw_reg brw_vec16_reg( GLuint file,
 					      GLuint nr,
 					      GLuint subnr )
@@ -181,6 +193,7 @@ static INLINE struct brw_reg brw_vec16_reg( GLuint file,
 		  WRITEMASK_XYZW);
 }
 
+/** Construct float[8] register */
 static INLINE struct brw_reg brw_vec8_reg( GLuint file,
 					     GLuint nr,
 					     GLuint subnr )
@@ -196,7 +209,7 @@ static INLINE struct brw_reg brw_vec8_reg( GLuint file,
 		  WRITEMASK_XYZW);
 }
 
-
+/** Construct float[4] register */
 static INLINE struct brw_reg brw_vec4_reg( GLuint file,
 					      GLuint nr,
 					      GLuint subnr )
@@ -212,7 +225,7 @@ static INLINE struct brw_reg brw_vec4_reg( GLuint file,
 		  WRITEMASK_XYZW);
 }
 
-
+/** Construct float[2] register */
 static INLINE struct brw_reg brw_vec2_reg( GLuint file,
 					      GLuint nr,
 					      GLuint subnr )
@@ -228,6 +241,7 @@ static INLINE struct brw_reg brw_vec2_reg( GLuint file,
 		  WRITEMASK_XY);
 }
 
+/** Construct float[1] register */
 static INLINE struct brw_reg brw_vec1_reg( GLuint file,
 					     GLuint nr,
 					     GLuint subnr )
@@ -277,6 +291,7 @@ static INLINE struct brw_reg byte_offset( struct brw_reg reg,
 }
    
 
+/** Construct unsigned word[16] register */
 static INLINE struct brw_reg brw_uw16_reg( GLuint file,
 					     GLuint nr,
 					     GLuint subnr )
@@ -284,6 +299,7 @@ static INLINE struct brw_reg brw_uw16_reg( GLuint file,
    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 }
 
+/** Construct unsigned word[8] register */
 static INLINE struct brw_reg brw_uw8_reg( GLuint file,
 					    GLuint nr,
 					    GLuint subnr )
@@ -291,6 +307,7 @@ static INLINE struct brw_reg brw_uw8_reg( GLuint file,
    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 }
 
+/** Construct unsigned word[1] register */
 static INLINE struct brw_reg brw_uw1_reg( GLuint file,
 					    GLuint nr,
 					    GLuint subnr )
@@ -311,6 +328,7 @@ static INLINE struct brw_reg brw_imm_reg( GLuint type )
 		   0);      
 }
 
+/** Construct float immediate register */
 static INLINE struct brw_reg brw_imm_f( GLfloat f )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
@@ -318,6 +336,7 @@ static INLINE struct brw_reg brw_imm_f( GLfloat f )
    return imm;
 }
 
+/** Construct integer immediate register */
 static INLINE struct brw_reg brw_imm_d( GLint d )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
@@ -325,6 +344,7 @@ static INLINE struct brw_reg brw_imm_d( GLint d )
    return imm;
 }
 
+/** Construct uint immediate register */
 static INLINE struct brw_reg brw_imm_ud( GLuint ud )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
@@ -332,6 +352,7 @@ static INLINE struct brw_reg brw_imm_ud( GLuint ud )
    return imm;
 }
 
+/** Construct ushort immediate register */
 static INLINE struct brw_reg brw_imm_uw( GLushort uw )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
@@ -339,6 +360,7 @@ static INLINE struct brw_reg brw_imm_uw( GLushort uw )
    return imm;
 }
 
+/** Construct short immediate register */
 static INLINE struct brw_reg brw_imm_w( GLshort w )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
@@ -350,8 +372,7 @@ static INLINE struct brw_reg brw_imm_w( GLshort w )
  * numbers alias with _V and _VF below:
  */
 
-/* Vector of eight signed half-byte values: 
- */
+/** Construct vector of eight signed half-byte values */
 static INLINE struct brw_reg brw_imm_v( GLuint v )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
@@ -362,8 +383,7 @@ static INLINE struct brw_reg brw_imm_v( GLuint v )
    return imm;
 }
 
-/* Vector of four 8-bit float values:
- */
+/** Construct vector of four 8-bit float values */
 static INLINE struct brw_reg brw_imm_vf( GLuint v )
 {
    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
@@ -400,44 +420,43 @@ static INLINE struct brw_reg brw_address( struct brw_reg reg )
    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
 }
 
-
-static INLINE struct brw_reg brw_vec1_grf( GLuint nr,
-					       GLuint subnr )
+/** Construct float[1] general-purpose register */
+static INLINE struct brw_reg brw_vec1_grf( GLuint nr, GLuint subnr )
 {
    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 }
 
-static INLINE struct brw_reg brw_vec8_grf( GLuint nr,
-					     GLuint subnr )
+/** Construct float[2] general-purpose register */
+static INLINE struct brw_reg brw_vec2_grf( GLuint nr, GLuint subnr )
 {
-   return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+   return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 }
 
-static INLINE struct brw_reg brw_vec4_grf( GLuint nr,
-					     GLuint subnr )
+/** Construct float[4] general-purpose register */
+static INLINE struct brw_reg brw_vec4_grf( GLuint nr, GLuint subnr )
 {
    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 }
 
-
-static INLINE struct brw_reg brw_vec2_grf( GLuint nr,
-					     GLuint subnr )
+/** Construct float[8] general-purpose register */
+static INLINE struct brw_reg brw_vec8_grf( GLuint nr, GLuint subnr )
 {
-   return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+   return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 }
 
-static INLINE struct brw_reg brw_uw8_grf( GLuint nr,
-					    GLuint subnr )
+
+static INLINE struct brw_reg brw_uw8_grf( GLuint nr, GLuint subnr )
 {
    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 }
 
-static INLINE struct brw_reg brw_uw16_grf( GLuint nr,
-					    GLuint subnr )
+static INLINE struct brw_reg brw_uw16_grf( GLuint nr, GLuint subnr )
 {
    return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 }
 
+
+/** Construct null register (usually used for setting condition codes) */
 static INLINE struct brw_reg brw_null_reg( void )
 {
    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, 
@@ -524,13 +543,13 @@ static INLINE struct brw_reg stride( struct brw_reg reg,
 				       GLuint width,
 				       GLuint hstride )
 {
-   
    reg.vstride = cvt(vstride);
    reg.width = cvt(width) - 1;
    reg.hstride = cvt(hstride);
    return reg;
 }
 
+
 static INLINE struct brw_reg vec16( struct brw_reg reg )
 {
    return stride(reg, 16,16,1);
@@ -556,6 +575,7 @@ static INLINE struct brw_reg vec1( struct brw_reg reg )
    return stride(reg, 0,1,0);
 }
 
+
 static INLINE struct brw_reg get_element( struct brw_reg reg, GLuint elt )
 {
    return vec1(suboffset(reg, elt));
@@ -687,7 +707,7 @@ static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset
 
 static INLINE struct brw_instruction *current_insn( struct brw_compile *p)
 {
-	return &p->store[p->nr_insn];
+   return &p->store[p->nr_insn];
 }
 
 void brw_pop_insn_state( struct brw_compile *p );
@@ -733,6 +753,7 @@ ALU2(ADD)
 ALU2(MUL)
 ALU1(FRC)
 ALU1(RNDD)
+ALU1(RNDZ)
 ALU2(MAC)
 ALU2(MACH)
 ALU1(LZD)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index ce4cf46cfa6..4e099b5945c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -439,6 +439,7 @@ ALU2(ADD)
 ALU2(MUL)
 ALU1(FRC)
 ALU1(RNDD)
+ALU1(RNDZ)
 ALU2(MAC)
 ALU2(MACH)
 ALU1(LZD)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 4a9541378f7..71e2a95bfd9 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -73,8 +73,6 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 
    c->prog_data.curb_read_length = reg - 1;
 
-
-
    /* Allocate input regs:  
     */
    c->nr_inputs = 0;
@@ -84,8 +82,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 	 c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0);
 	 reg++;
       }
-   }     
-
+   }
 
    /* Allocate outputs: TODO: could organize the non-position outputs
     * to go straight into message regs.
@@ -339,6 +336,7 @@ static void emit_math1( struct brw_vs_compile *c,
    }
 }
 
+
 static void emit_math2( struct brw_vs_compile *c, 
 			GLuint function,
 			struct brw_reg dst,
@@ -370,7 +368,6 @@ static void emit_math2( struct brw_vs_compile *c,
       release_tmp(c, tmp);
    }
 }
-		     
 
 
 static void emit_exp_noalias( struct brw_vs_compile *c,
@@ -521,8 +518,6 @@ static void emit_log_noalias( struct brw_vs_compile *c,
 }
 
 
-      
-
 /* Need to unalias - consider swizzles:   r0 = DST r0.xxxx r1
  */
 static void emit_dst_noalias( struct brw_vs_compile *c, 
@@ -544,6 +539,7 @@ static void emit_dst_noalias( struct brw_vs_compile *c,
       brw_MOV(p, brw_writemask(dst, WRITEMASK_W), arg1);
 }
 
+
 static void emit_xpd( struct brw_compile *p,
 		      struct brw_reg dst,
 		      struct brw_reg t,
@@ -554,7 +550,6 @@ static void emit_xpd( struct brw_compile *p,
 }
 
 
-
 static void emit_lit_noalias( struct brw_vs_compile *c, 
 			      struct brw_reg dst,
 			      struct brw_reg arg0 )
@@ -596,7 +591,29 @@ static void emit_lit_noalias( struct brw_vs_compile *c,
 }
 
 
+/** 3 or 4-component vector normalization */
+static void emit_nrm( struct brw_vs_compile *c, 
+                      struct brw_reg dst,
+                      struct brw_reg arg0,
+                      int num_comps)
+{
+   struct brw_compile *p = &c->func;
+   struct brw_reg tmp = get_tmp(c);
 
+   /* tmp = dot(arg0, arg0) */
+   if (num_comps == 3)
+      brw_DP3(p, tmp, arg0, arg0);
+   else
+      brw_DP4(p, tmp, arg0, arg0);
+
+   /* tmp = 1 / sqrt(tmp) */
+   emit_math1(c, BRW_MATH_FUNCTION_RSQ, tmp, tmp, BRW_MATH_PRECISION_FULL);
+
+   /* dst = arg0 * tmp */
+   brw_MUL(p, dst, arg0, tmp);
+
+   release_tmp(c, tmp);
+}
 
 
 /* TODO: relative addressing!
@@ -634,7 +651,6 @@ static struct brw_reg get_reg( struct brw_vs_compile *c,
 }
 
 
-
 static struct brw_reg deref( struct brw_vs_compile *c,
 			     struct brw_reg arg,
 			     GLint offset)
@@ -728,8 +744,6 @@ static struct brw_reg get_dst( struct brw_vs_compile *c,
 }
 
 
-
-
 static void emit_swz( struct brw_vs_compile *c, 
 		      struct brw_reg dst,
 		      struct prog_src_register src )
@@ -801,8 +815,8 @@ static void emit_swz( struct brw_vs_compile *c,
 }
 
 
-
-/* Post-vertex-program processing.  Send the results to the URB.
+/**
+ * Post-vertex-program processing.  Send the results to the URB.
  */
 static void emit_vertex_write( struct brw_vs_compile *c)
 {
@@ -817,7 +831,6 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 	      get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG));
    }
 
-
    /* Build ndc coords */
    if (!c->key.know_w_is_one) {
       ndc = get_tmp(c);
@@ -848,7 +861,6 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 	 brw_AND(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8));
       }
 
-
       for (i = 0; i < c->key.nr_userclip; i++) {
 	 brw_set_conditionalmod(p, BRW_CONDITIONAL_L);
 	 brw_DP4(p, brw_null_reg(), pos, c->userplane[i]);
@@ -856,7 +868,6 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
       }
 
-
       /* i965 clipping workaround: 
        * 1) Test for -ve rhw
        * 2) If set, 
@@ -888,14 +899,12 @@ static void emit_vertex_write( struct brw_vs_compile *c)
       brw_MOV(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
    }
 
-
    /* Emit the (interleaved) headers for the two vertices - an 8-reg
     * of zeros followed by two sets of NDC coordinates:
     */
    brw_set_access_mode(p, BRW_ALIGN_1);
    brw_MOV(p, offset(m0, 2), ndc);
    brw_MOV(p, offset(m0, 3), pos);
-   
 
    brw_urb_WRITE(p, 
 		 brw_null_reg(), /* dest */
@@ -909,9 +918,9 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 		 1, 		/* writes complete */
 		 0, 		/* urb destination offset */
 		 BRW_URB_SWIZZLE_INTERLEAVE);
-
 }
 
+
 static void 
 post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst )
 {
@@ -1035,6 +1044,12 @@ void brw_vs_emit(struct brw_vs_compile *c )
       case OPCODE_DPH:
 	 brw_DPH(p, dst, args[0], args[1]);
 	 break;
+      case OPCODE_NRM3:
+	 emit_nrm(c, dst, args[0], 3);
+	 break;
+      case OPCODE_NRM4:
+	 emit_nrm(c, dst, args[0], 4);
+	 break;
       case OPCODE_DST:
 	 unalias2(c, dst, args[0], args[1], emit_dst_noalias); 
 	 break;
@@ -1102,7 +1117,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	 break;
       case OPCODE_SGT:
          emit_sgt(p, dst, args[0], args[1]);
-        break;
+         break;
       case OPCODE_SLT:
 	 emit_slt(p, dst, args[0], args[1]);
 	 break;
@@ -1118,6 +1133,10 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	  */
 	 emit_swz(c, dst, inst->SrcReg[0] );
 	 break;
+      case OPCODE_TRUNC:
+         /* round toward zero */
+	 brw_RNDZ(p, dst, args[0]);
+	 break;
       case OPCODE_XPD:
 	 emit_xpd(p, dst, args[0], args[1]);
 	 break;
@@ -1136,7 +1155,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
          brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
          brw_set_predicate_control_flag_value(p, 0xff);
-        break;
+         break;
       case OPCODE_CAL:
 	 brw_set_access_mode(p, BRW_ALIGN_1);
 	 brw_ADD(p, deref_1d(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
@@ -1145,7 +1164,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
 			 get_addr_reg(stack_index), brw_imm_d(4));
 	 inst->Data = &p->store[p->nr_insn];
 	 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
-        break;
+         break;
       case OPCODE_RET:
 	 brw_ADD(p, get_addr_reg(stack_index),
 			 get_addr_reg(stack_index), brw_imm_d(-4));
@@ -1154,17 +1173,17 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	 brw_set_access_mode(p, BRW_ALIGN_16);
       case OPCODE_END:	
          brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
-        break;
+         break;
       case OPCODE_PRINT:
       case OPCODE_BGNSUB:
       case OPCODE_ENDSUB:
+         /* no-op instructions */
 	 break;
       default:
-	 _mesa_printf("Unsupported opcode %i (%s) in vertex shader\n",
-		      inst->Opcode, inst->Opcode < MAX_OPCODE ?
+	 _mesa_problem(NULL, "Unsupported opcode %i (%s) in vertex shader",
+                       inst->Opcode, inst->Opcode < MAX_OPCODE ?
 				    _mesa_opcode_string(inst->Opcode) :
 				    "unknown");
-	 break;
       }
 
       if ((inst->DstReg.File == PROGRAM_OUTPUT)
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index bad76793af7..5b4ee20ecb5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -36,6 +36,7 @@
 #include "brw_state.h"
 
 
+/** Return number of src args for given instruction */
 GLuint brw_wm_nr_args( GLuint opcode )
 {
    switch (opcode) {
@@ -58,6 +59,8 @@ GLuint brw_wm_nr_args( GLuint opcode )
    case OPCODE_TXP:	
    case OPCODE_KIL:
    case OPCODE_LIT: 
+   case OPCODE_NRM3:
+   case OPCODE_NRM4:
    case WM_CINTERP: 
    case WM_WPOSXY: 
       return 1;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 58c78c4b2c5..b5050a3e40b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -194,7 +194,7 @@ static void emit_linterp( struct brw_compile *p,
    interp[2] = brw_vec1_grf(nr+1, 0);
    interp[3] = brw_vec1_grf(nr+1, 4);
 
-   for(i = 0; i < 4; i++ ) {
+   for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
 	 brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
 	 brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
@@ -219,42 +219,40 @@ static void emit_pinterp( struct brw_compile *p,
    interp[2] = brw_vec1_grf(nr+1, 0);
    interp[3] = brw_vec1_grf(nr+1, 4);
 
-   for(i = 0; i < 4; i++ ) {
+   for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
 	 brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
 	 brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
       }
    }
-   for(i = 0; i < 4; i++ ) {
+   for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
 	 brw_MUL(p, dst[i], dst[i], w[3]);
       }
    }
 }
 
+
 static void emit_cinterp( struct brw_compile *p, 
 			 const struct brw_reg *dst,
 			 GLuint mask,
 			 const struct brw_reg *arg0 )
 {
-	struct brw_reg interp[4];
-	GLuint nr = arg0[0].nr;
-	GLuint i;
-
-	interp[0] = brw_vec1_grf(nr, 0);
-	interp[1] = brw_vec1_grf(nr, 4);
-	interp[2] = brw_vec1_grf(nr+1, 0);
-	interp[3] = brw_vec1_grf(nr+1, 4);
-
-	for(i = 0; i < 4; i++ ) {
-		if (mask & (1<<i)) {
-			brw_MOV(p, dst[i], suboffset(interp[i],3));	/* TODO: optimize away like other moves */
-		}
-	}
-}
-
+   struct brw_reg interp[4];
+   GLuint nr = arg0[0].nr;
+   GLuint i;
 
+   interp[0] = brw_vec1_grf(nr, 0);
+   interp[1] = brw_vec1_grf(nr, 4);
+   interp[2] = brw_vec1_grf(nr+1, 0);
+   interp[3] = brw_vec1_grf(nr+1, 4);
 
+   for (i = 0; i < 4; i++) {
+      if (mask & (1<<i)) {
+         brw_MOV(p, dst[i], suboffset(interp[i],3));	/* TODO: optimize away like other moves */
+      }
+   }
+}
 
 
 static void emit_alu1( struct brw_compile *p, 
@@ -280,6 +278,7 @@ static void emit_alu1( struct brw_compile *p,
       brw_set_saturate(p, 0);
 }
 
+
 static void emit_alu2( struct brw_compile *p, 
 		       struct brw_instruction *(*func)(struct brw_compile *, 
 						       struct brw_reg, 
@@ -351,6 +350,7 @@ static void emit_lrp( struct brw_compile *p,
       }
    }
 }
+
 static void emit_sop( struct brw_compile *p, 
 		      const struct brw_reg *dst,
 		      GLuint mask,
@@ -376,7 +376,7 @@ static void emit_slt( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
-	 emit_sop(p, dst, mask, BRW_CONDITIONAL_L, arg0, arg1);
+   emit_sop(p, dst, mask, BRW_CONDITIONAL_L, arg0, arg1);
 }
 
 static void emit_sle( struct brw_compile *p, 
@@ -385,7 +385,7 @@ static void emit_sle( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
-	 emit_sop(p, dst, mask, BRW_CONDITIONAL_LE, arg0, arg1);
+   emit_sop(p, dst, mask, BRW_CONDITIONAL_LE, arg0, arg1);
 }
 
 static void emit_sgt( struct brw_compile *p, 
@@ -394,7 +394,7 @@ static void emit_sgt( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
-	 emit_sop(p, dst, mask, BRW_CONDITIONAL_G, arg0, arg1);
+   emit_sop(p, dst, mask, BRW_CONDITIONAL_G, arg0, arg1);
 }
 
 static void emit_sge( struct brw_compile *p, 
@@ -403,7 +403,7 @@ static void emit_sge( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
-	 emit_sop(p, dst, mask, BRW_CONDITIONAL_GE, arg0, arg1);
+   emit_sop(p, dst, mask, BRW_CONDITIONAL_GE, arg0, arg1);
 }
 
 static void emit_seq( struct brw_compile *p, 
@@ -412,7 +412,7 @@ static void emit_seq( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
-	 emit_sop(p, dst, mask, BRW_CONDITIONAL_EQ, arg0, arg1);
+   emit_sop(p, dst, mask, BRW_CONDITIONAL_EQ, arg0, arg1);
 }
 
 static void emit_sne( struct brw_compile *p, 
@@ -421,7 +421,7 @@ static void emit_sne( struct brw_compile *p,
 		      const struct brw_reg *arg0,
 		      const struct brw_reg *arg1 )
 {
-	 emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1);
+   emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1);
 }
 
 static void emit_cmp( struct brw_compile *p, 
@@ -505,7 +505,7 @@ static void emit_dp3( struct brw_compile *p,
 		      const struct brw_reg *arg1 )
 {
    if (!(mask & WRITEMASK_XYZW))
-      return; /* Do not emit dead code*/
+      return; /* Do not emit dead code */
 
    assert((mask & WRITEMASK_XYZW) == WRITEMASK_X);
 
@@ -525,7 +525,7 @@ static void emit_dp4( struct brw_compile *p,
 		      const struct brw_reg *arg1 )
 {
    if (!(mask & WRITEMASK_XYZW))
-      return; /* Do not emit dead code*/
+      return; /* Do not emit dead code */
 
    assert((mask & WRITEMASK_XYZW) == WRITEMASK_X);
 
@@ -546,7 +546,7 @@ static void emit_dph( struct brw_compile *p,
 		      const struct brw_reg *arg1 )
 {
    if (!(mask & WRITEMASK_XYZW))
-      return; /* Do not emit dead code*/
+      return; /* Do not emit dead code */
 
    assert((mask & WRITEMASK_XYZW) == WRITEMASK_X);
 
@@ -592,7 +592,7 @@ static void emit_math1( struct brw_compile *p,
 			const struct brw_reg *arg0 )
 {
    if (!(mask & WRITEMASK_XYZW))
-      return; /* Do not emit dead code*/
+      return; /* Do not emit dead code */
 
    //assert((mask & WRITEMASK_XYZW) == WRITEMASK_X ||
    //	  function == BRW_MATH_FUNCTION_SINCOS);
@@ -619,7 +619,7 @@ static void emit_math2( struct brw_compile *p,
 			const struct brw_reg *arg1)
 {
    if (!(mask & WRITEMASK_XYZW))
-      return; /* Do not emit dead code*/
+      return; /* Do not emit dead code */
 
    assert((mask & WRITEMASK_XYZW) == WRITEMASK_X);
 
@@ -760,7 +760,6 @@ static void emit_txb( struct brw_wm_compile *c,
    brw_MOV(p, brw_message_reg(8), arg[3]);
    msgLength = 9;
 
-
    brw_SAMPLE(p, 
 	      retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW),
 	      1,
@@ -772,7 +771,6 @@ static void emit_txb( struct brw_wm_compile *c,
 	      8,		/* responseLength */
 	      msgLength,
 	      0);	
-
 }
 
 
@@ -823,7 +821,6 @@ static void emit_kil( struct brw_wm_compile *c,
    struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
    GLuint i;
    
-
    /* XXX - usually won't need 4 compares!
     */
    for (i = 0; i < 4; i++) {
@@ -836,6 +833,7 @@ static void emit_kil( struct brw_wm_compile *c,
    }
 }
 
+
 static void fire_fb_write( struct brw_wm_compile *c,
 			   GLuint base_reg,
 			   GLuint nr,
@@ -869,6 +867,7 @@ static void fire_fb_write( struct brw_wm_compile *c,
 		eot);
 }
 
+
 static void emit_aa( struct brw_wm_compile *c,
 		     struct brw_reg *arg1,
 		     GLuint reg )
@@ -962,7 +961,6 @@ static void emit_fb_write( struct brw_wm_compile *c,
       nr += 2;
    }
 
-
    if (!c->key.runtime_check_aads_emit) {
       if (c->key.aa_dest_stencil_reg)
 	 emit_aa(c, arg1, 2);
@@ -996,8 +994,6 @@ static void emit_fb_write( struct brw_wm_compile *c,
 }
 
 
-
-
 /* Post-fragment-program processing.  Send the results to the
  * framebuffer.
  */
@@ -1022,6 +1018,7 @@ static void emit_spill( struct brw_wm_compile *c,
 		   slot);
 }
 
+
 static void emit_unspill( struct brw_wm_compile *c,
 			  struct brw_reg reg,
 			  GLuint slot )
@@ -1047,7 +1044,6 @@ static void emit_unspill( struct brw_wm_compile *c,
 }
 
 
-
 /**
  * Retrieve upto 4 GEN4 register pairs for the given wm reg:
  */
@@ -1073,6 +1069,7 @@ static void get_argument_regs( struct brw_wm_compile *c,
    }
 }
 
+
 static void spill_values( struct brw_wm_compile *c,
 			  struct brw_wm_value *values,
 			  GLuint nr )
@@ -1085,7 +1082,6 @@ static void spill_values( struct brw_wm_compile *c,
 }
 
 
-
 /* Emit the fragment program instructions here.
  */
 void brw_wm_emit( struct brw_wm_compile *c )
@@ -1176,7 +1172,7 @@ void brw_wm_emit( struct brw_wm_compile *c )
 	 emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]);
 	 break;
 
-      case OPCODE_DP3:	/*  */
+      case OPCODE_DP3:
 	 emit_dp3(p, dst, dst_flags, args[0], args[1]);
 	 break;
 
@@ -1188,7 +1184,7 @@ void brw_wm_emit( struct brw_wm_compile *c )
 	 emit_dph(p, dst, dst_flags, args[0], args[1]);
 	 break;
 
-      case OPCODE_LRP:	/*  */
+      case OPCODE_LRP:
 	 emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]);
 	 break;
 
@@ -1315,8 +1311,3 @@ void brw_wm_emit( struct brw_wm_compile *c )
 		      inst->dst[i]->spill_slot);
    }
 }
-
-
-
-
-
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index baecfdcb799..d43e326f7d1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -267,7 +267,7 @@ static void emit_trunc( struct brw_wm_compile *c,
 	    struct brw_reg src, dst;
 	    dst = get_dst_reg(c, inst, i, 1) ;
 	    src = get_src_reg(c, &inst->SrcReg[0], i, 1);
-	    brw_RNDD(p, dst, src);
+	    brw_RNDZ(p, dst, src);
 	}
     }
     brw_set_saturate(p, 0);
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index f8f009c6a30..4d036dee42e 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -181,7 +181,7 @@ intelUpdatePageFlipping(struct intel_context *intel,
    intel_fb->pf_current_page = (intel->sarea->pf_current_page >>
 				(intel_fb->pf_planes & 0x2)) & 0x3;
 
-   intel_fb->pf_num_pages = intel->intelScreen->third.handle ? 3 : 2;
+   intel_fb->pf_num_pages = 2;
 
    pf_active = pf_planes && (pf_planes & intel->sarea->pf_active) == pf_planes;
 
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 6c625b428c0..44b276a123e 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -412,6 +412,7 @@ static const struct dri_extension brw_extensions[] = {
    { "GL_EXT_shadow_funcs",               NULL },
    { "GL_EXT_texture_sRGB",		  NULL },
    { "GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions },
+   { "GL_ATI_texture_env_combine3",       NULL },
    { NULL,                                NULL }
 };
 
@@ -775,7 +776,6 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
 
       intel_region_release(&intel->front_region);
       intel_region_release(&intel->back_region);
-      intel_region_release(&intel->third_region);
       intel_region_release(&intel->depth_region);
 
       driDestroyOptionCache(&intel->optionCache);
@@ -825,12 +825,7 @@ intelMakeCurrent(__DRIcontextPrivate * driContextPriv,
 	    intel_renderbuffer_set_region(intel_fb->color_rb[1],
 					  intel->back_region);
          }
-#if 0
-         if (intel_fb->color_rb[2]) {
-	    intel_renderbuffer_set_region(intel_fb->color_rb[2],
-					  intel->third_region);
-         }
-#endif
+
          if (irbDepth) {
 	    intel_renderbuffer_set_region(irbDepth, intel->depth_region);
          }
@@ -867,7 +862,7 @@ intelMakeCurrent(__DRIcontextPrivate * driContextPriv,
 	       driDrawableInitVBlank(driDrawPriv);
 	       intel_fb->vbl_waited = driDrawPriv->vblSeq;
 
-	       for (i = 0; i < (intel->intelScreen->third.handle ? 3 : 2); i++) {
+	       for (i = 0; i < 2; i++) {
 		  if (intel_fb->color_rb[i])
 		     intel_fb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
 	       }
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index ee43ed7e833..048286c196b 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -157,6 +157,19 @@ struct intel_context
       void (*debug_batch)(struct intel_context *intel);
    } vtbl;
 
+   struct {
+      struct gl_fragment_program *bitmap_fp;
+      struct gl_vertex_program *passthrough_vp;
+
+      struct gl_fragment_program *saved_fp;
+      GLboolean saved_fp_enable;
+      struct gl_vertex_program *saved_vp;
+      GLboolean saved_vp_enable;
+
+      GLint saved_vp_x, saved_vp_y;
+      GLsizei saved_vp_width, saved_vp_height;
+   } meta;
+
    GLint refcount;
    GLuint Fallback;
    GLuint NewGLState;
@@ -166,7 +179,6 @@ struct intel_context
 
    struct intel_region *front_region;
    struct intel_region *back_region;
-   struct intel_region *third_region;
    struct intel_region *depth_region;
 
    /**
diff --git a/src/mesa/drivers/dri/intel/intel_pixel.c b/src/mesa/drivers/dri/intel/intel_pixel.c
index 5702ad9bb57..cf2f32d3845 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel.c
@@ -27,7 +27,12 @@
 
 #include "main/enums.h"
 #include "main/state.h"
+#include "main/context.h"
+#include "main/enable.h"
+#include "main/matrix.h"
 #include "swrast/swrast.h"
+#include "shader/arbprogram.h"
+#include "shader/program.h"
 
 #include "intel_context.h"
 #include "intel_pixel.h"
@@ -167,6 +172,159 @@ intel_check_blit_format(struct intel_region * region,
    return GL_FALSE;
 }
 
+void
+intel_meta_set_passthrough_transform(struct intel_context *intel)
+{
+   GLcontext *ctx = &intel->ctx;
+
+   intel->meta.saved_vp_x = ctx->Viewport.X;
+   intel->meta.saved_vp_y = ctx->Viewport.Y;
+   intel->meta.saved_vp_width = ctx->Viewport.Width;
+   intel->meta.saved_vp_height = ctx->Viewport.Height;
+
+   _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height);
+
+   _mesa_MatrixMode(GL_PROJECTION);
+   _mesa_PushMatrix();
+   _mesa_LoadIdentity();
+   _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1);
+
+   _mesa_MatrixMode(GL_MODELVIEW);
+   _mesa_PushMatrix();
+   _mesa_LoadIdentity();
+}
+
+void
+intel_meta_restore_transform(struct intel_context *intel)
+{
+   _mesa_MatrixMode(GL_PROJECTION);
+   _mesa_PopMatrix();
+   _mesa_MatrixMode(GL_MODELVIEW);
+   _mesa_PopMatrix();
+
+   _mesa_Viewport(intel->meta.saved_vp_x, intel->meta.saved_vp_y,
+		  intel->meta.saved_vp_width, intel->meta.saved_vp_height);
+}
+
+/**
+ * Set up a vertex program to pass through the position and first texcoord
+ * for pixel path.
+ */
+void
+intel_meta_set_passthrough_vertex_program(struct intel_context *intel)
+{
+   GLcontext *ctx = &intel->ctx;
+   static const char *vp =
+      "!!ARBvp1.0\n"
+      "TEMP vertexClip;\n"
+      "DP4 vertexClip.x, state.matrix.mvp.row[0], vertex.position;\n"
+      "DP4 vertexClip.y, state.matrix.mvp.row[1], vertex.position;\n"
+      "DP4 vertexClip.z, state.matrix.mvp.row[2], vertex.position;\n"
+      "DP4 vertexClip.w, state.matrix.mvp.row[3], vertex.position;\n"
+      "MOV result.position, vertexClip;\n"
+      "MOV result.texcoord[0], vertex.texcoord[0];\n"
+      "MOV result.color, vertex.color;\n"
+      "END\n";
+
+   assert(intel->meta.saved_vp == NULL);
+
+   _mesa_reference_vertprog(ctx, &intel->meta.saved_vp,
+			    ctx->VertexProgram.Current);
+   if (intel->meta.passthrough_vp == NULL) {
+      GLuint prog_name;
+      _mesa_GenPrograms(1, &prog_name);
+      _mesa_BindProgram(GL_VERTEX_PROGRAM_ARB, prog_name);
+      _mesa_ProgramStringARB(GL_VERTEX_PROGRAM_ARB,
+			     GL_PROGRAM_FORMAT_ASCII_ARB,
+			     strlen(vp), (const GLubyte *)vp);
+      _mesa_reference_vertprog(ctx, &intel->meta.passthrough_vp,
+			       ctx->VertexProgram.Current);
+      _mesa_DeletePrograms(1, &prog_name);
+   }
+
+   FLUSH_VERTICES(ctx, _NEW_PROGRAM);
+   _mesa_reference_vertprog(ctx, &ctx->VertexProgram.Current,
+			    intel->meta.passthrough_vp);
+   ctx->Driver.BindProgram(ctx, GL_VERTEX_PROGRAM_ARB,
+			   &intel->meta.passthrough_vp->Base);
+
+   intel->meta.saved_vp_enable = ctx->VertexProgram.Enabled;
+   _mesa_Enable(GL_VERTEX_PROGRAM_ARB);
+}
+
+/**
+ * Restores the previous vertex program after
+ * intel_meta_set_passthrough_vertex_program()
+ */
+void
+intel_meta_restore_vertex_program(struct intel_context *intel)
+{
+   GLcontext *ctx = &intel->ctx;
+
+   FLUSH_VERTICES(ctx, _NEW_PROGRAM);
+   _mesa_reference_vertprog(ctx, &ctx->VertexProgram.Current,
+			    intel->meta.saved_vp);
+   _mesa_reference_vertprog(ctx, &intel->meta.saved_vp, NULL);
+   ctx->Driver.BindProgram(ctx, GL_VERTEX_PROGRAM_ARB,
+			   &ctx->VertexProgram.Current->Base);
+
+   if (!intel->meta.saved_vp_enable)
+      _mesa_Disable(GL_VERTEX_PROGRAM_ARB);
+}
+
+/**
+ * Binds the given program string to GL_FRAGMENT_PROGRAM_ARB, caching the
+ * program object.
+ */
+void
+intel_meta_set_fragment_program(struct intel_context *intel,
+				struct gl_fragment_program **prog,
+				const char *prog_string)
+{
+   GLcontext *ctx = &intel->ctx;
+   assert(intel->meta.saved_fp == NULL);
+
+   _mesa_reference_fragprog(ctx, &intel->meta.saved_fp,
+			    ctx->FragmentProgram.Current);
+   if (*prog == NULL) {
+      GLuint prog_name;
+      _mesa_GenPrograms(1, &prog_name);
+      _mesa_BindProgram(GL_FRAGMENT_PROGRAM_ARB, prog_name);
+      _mesa_ProgramStringARB(GL_FRAGMENT_PROGRAM_ARB,
+			     GL_PROGRAM_FORMAT_ASCII_ARB,
+			     strlen(prog_string), (const GLubyte *)prog_string);
+      _mesa_reference_fragprog(ctx, prog, ctx->FragmentProgram.Current);
+      /* Note that DeletePrograms unbinds the program on us */
+      _mesa_DeletePrograms(1, &prog_name);
+   }
+
+   FLUSH_VERTICES(ctx, _NEW_PROGRAM);
+   _mesa_reference_fragprog(ctx, &ctx->FragmentProgram.Current, *prog);
+   ctx->Driver.BindProgram(ctx, GL_FRAGMENT_PROGRAM_ARB, &((*prog)->Base));
+
+   intel->meta.saved_fp_enable = ctx->FragmentProgram.Enabled;
+   _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB);
+}
+
+/**
+ * Restores the previous fragment program after
+ * intel_meta_set_fragment_program()
+ */
+void
+intel_meta_restore_fragment_program(struct intel_context *intel)
+{
+   GLcontext *ctx = &intel->ctx;
+
+   FLUSH_VERTICES(ctx, _NEW_PROGRAM);
+   _mesa_reference_fragprog(ctx, &ctx->FragmentProgram.Current,
+			    intel->meta.saved_fp);
+   _mesa_reference_fragprog(ctx, &intel->meta.saved_fp, NULL);
+   ctx->Driver.BindProgram(ctx, GL_FRAGMENT_PROGRAM_ARB,
+			   &ctx->FragmentProgram.Current->Base);
+
+   if (!intel->meta.saved_fp_enable)
+      _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB);
+}
 
 void
 intelInitPixelFuncs(struct dd_function_table *functions)
@@ -181,3 +339,13 @@ intelInitPixelFuncs(struct dd_function_table *functions)
 #endif
    }
 }
+
+void
+intel_free_pixel_state(struct intel_context *intel)
+{
+   GLcontext *ctx = &intel->ctx;
+
+   _mesa_reference_vertprog(ctx, &intel->meta.passthrough_vp, NULL);
+   _mesa_reference_fragprog(ctx, &intel->meta.bitmap_fp, NULL);
+}
+
diff --git a/src/mesa/drivers/dri/intel/intel_pixel.h b/src/mesa/drivers/dri/intel/intel_pixel.h
index 6fa6effe835..76b8781316b 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel.h
+++ b/src/mesa/drivers/dri/intel/intel_pixel.h
@@ -31,6 +31,15 @@
 #include "main/mtypes.h"
 
 void intelInitPixelFuncs(struct dd_function_table *functions);
+void intel_meta_set_passthrough_transform(struct intel_context *intel);
+void intel_meta_restore_transform(struct intel_context *intel);
+void intel_meta_set_passthrough_vertex_program(struct intel_context *intel);
+void intel_meta_restore_vertex_program(struct intel_context *intel);
+void intel_meta_set_fragment_program(struct intel_context *intel,
+				     struct gl_fragment_program **prog,
+				     const char *prog_string);
+void intel_meta_restore_fragment_program(struct intel_context *intel);
+void intel_free_pixel_state(struct intel_context *intel);
 
 GLboolean intel_check_blit_fragment_ops(GLcontext * ctx,
 					GLboolean src_alpha_is_one);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index fb1a051cdc8..1d7f15f10a5 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -32,7 +32,18 @@
 #include "main/mtypes.h"
 #include "main/macros.h"
 #include "main/bufferobj.h"
+#include "main/pixelstore.h"
 #include "main/state.h"
+#include "main/teximage.h"
+#include "main/texenv.h"
+#include "main/texobj.h"
+#include "main/texstate.h"
+#include "main/texparam.h"
+#include "main/varray.h"
+#include "main/attrib.h"
+#include "main/enable.h"
+#include "shader/arbprogram.h"
+#include "glapi/dispatch.h"
 #include "swrast/swrast.h"
 
 #include "intel_screen.h"
@@ -87,6 +98,11 @@ static GLboolean test_bit( const GLubyte *src,
    return (src[bit/8] & (1<<(bit % 8))) ? 1 : 0;
 }
 
+static GLboolean test_msb_bit(const GLubyte *src, GLuint bit)
+{
+   return (src[bit/8] & (1<<(7 - (bit % 8)))) ? 1 : 0;
+}
+
 static void set_bit( GLubyte *dest,
 			  GLuint bit )
 {
@@ -244,8 +260,8 @@ do_blit_bitmap( GLcontext *ctx,
 	 /* Clip to drawable cliprect */
          if (!_mesa_clip_to_region(cliprects[i].x1,
 				   cliprects[i].y1,
-				   cliprects[i].x2 - cliprects[i].x1,
-				   cliprects[i].y2 - cliprects[i].y1,
+				   cliprects[i].x2,
+				   cliprects[i].y2,
 				   &box_x, &box_y, &box_w, &box_h))
 	    continue;
 
@@ -317,9 +333,174 @@ out:
    return GL_TRUE;
 }
 
+static GLboolean
+intel_texture_bitmap(GLcontext * ctx,
+		     GLint dst_x, GLint dst_y,
+		     GLsizei width, GLsizei height,
+		     const struct gl_pixelstore_attrib *unpack,
+		     const GLubyte *bitmap)
+{
+   struct intel_context *intel = intel_context(ctx);
+   static const char *fp =
+      "!!ARBfp1.0\n"
+      "TEMP val;\n"
+      "PARAM color=program.local[0];\n"
+      "TEX val, fragment.texcoord[0], texture[0], 2D;\n"
+      "ADD val, val.wwww, {-.5, -.5, -.5, -.5};\n"
+      "KIL val;\n"
+      "MOV result.color, color;\n"
+      "END\n";
+   GLuint texname;
+   GLfloat vertices[4][4];
+   GLfloat texcoords[4][2];
+   GLint old_active_texture;
+   GLubyte *unpacked_bitmap;
+   GLubyte *a8_bitmap;
+   int x, y;
+
+   /* We need a fragment program for the KIL effect */
+   if (!ctx->Extensions.ARB_fragment_program ||
+       !ctx->Extensions.ARB_vertex_program) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr,
+		 "glBitmap fallback: No fragment/vertex program support\n");
+      return GL_FALSE;
+   }
+
+   /* We're going to mess with texturing with no regard to existing texture
+    * state, so if there is some set up we have to bail.
+    */
+   if (ctx->Texture._EnabledUnits != 0) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr, "glBitmap fallback: texturing enabled\n");
+      return GL_FALSE;
+   }
+
+   /* Can't do textured DrawPixels with a fragment program, unless we were
+    * to generate a new program that sampled our texture and put the results
+    * in the fragment color before the user's program started.
+    */
+   if (ctx->FragmentProgram.Enabled) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr, "glBitmap fallback: fragment program enabled\n");
+      return GL_FALSE;
+   }
+
+   if (ctx->VertexProgram.Enabled) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr, "glBitmap fallback: vertex program enabled\n");
+      return GL_FALSE;
+   }
+
+   /* Check that we can load in a texture this big. */
+   if (width > (1 << (ctx->Const.MaxTextureLevels - 1)) ||
+       height > (1 << (ctx->Const.MaxTextureLevels - 1))) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr, "glBitmap fallback: bitmap too large (%dx%d)\n",
+		 width, height);
+      return GL_FALSE;
+   }
 
+   /* Convert the A1 bitmap to an A8 format suitable for glTexImage */
+   if (unpack->BufferObj->Name) {
+      bitmap = map_pbo(ctx, width, height, unpack, bitmap);
+      if (bitmap == NULL)
+	 return GL_TRUE;	/* even though this is an error, we're done */
+   }
+   unpacked_bitmap = _mesa_unpack_bitmap(width, height, bitmap,
+					 unpack);
+   a8_bitmap = _mesa_calloc(width * height);
+   for (y = 0; y < height; y++) {
+      for (x = 0; x < width; x++) {
+	 if (test_msb_bit(unpacked_bitmap, ALIGN(width, 8) * y + x))
+	    a8_bitmap[y * width + x] = 0xff;
+      }
+   }
+   _mesa_free(unpacked_bitmap);
+   if (unpack->BufferObj->Name) {
+      /* done with PBO so unmap it now */
+      ctx->Driver.UnmapBuffer(ctx, GL_PIXEL_UNPACK_BUFFER_EXT,
+                              unpack->BufferObj);
+   }
 
+   /* Save GL state before we start setting up our drawing */
+   _mesa_PushAttrib(GL_ENABLE_BIT | GL_CURRENT_BIT |
+		    GL_VIEWPORT_BIT);
+   _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT |
+			  GL_CLIENT_PIXEL_STORE_BIT);
+   old_active_texture = ctx->Texture.CurrentUnit;
+
+   _mesa_Disable(GL_POLYGON_STIPPLE);
+
+   /* Upload our bitmap data to an alpha texture */
+   _mesa_ActiveTextureARB(GL_TEXTURE0_ARB);
+   _mesa_Enable(GL_TEXTURE_2D);
+   _mesa_GenTextures(1, &texname);
+   _mesa_BindTexture(GL_TEXTURE_2D, texname);
+   _mesa_TexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
+   _mesa_TexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);
+
+   _mesa_PixelStorei(GL_UNPACK_SWAP_BYTES, GL_FALSE);
+   _mesa_PixelStorei(GL_UNPACK_LSB_FIRST, GL_FALSE);
+   _mesa_PixelStorei(GL_UNPACK_ROW_LENGTH, 0);
+   _mesa_PixelStorei(GL_UNPACK_SKIP_PIXELS, 0);
+   _mesa_PixelStorei(GL_UNPACK_SKIP_ROWS, 0);
+   _mesa_PixelStorei(GL_UNPACK_ALIGNMENT, 1);
+   _mesa_TexImage2D(GL_TEXTURE_2D, 0, GL_ALPHA, width, height, 0,
+		    GL_ALPHA, GL_UNSIGNED_BYTE, a8_bitmap);
+   _mesa_free(a8_bitmap);
+
+   intel_meta_set_fragment_program(intel, &intel->meta.bitmap_fp, fp);
+   _mesa_ProgramLocalParameter4fvARB(GL_FRAGMENT_PROGRAM_ARB, 0,
+				     ctx->Current.RasterColor);
+   intel_meta_set_passthrough_vertex_program(intel);
+   intel_meta_set_passthrough_transform(intel);
+
+   vertices[0][0] = dst_x;
+   vertices[0][1] = dst_y;
+   vertices[0][2] = ctx->Current.RasterPos[2];
+   vertices[0][3] = 1.0;
+   vertices[1][0] = dst_x + width;
+   vertices[1][1] = dst_y;
+   vertices[1][2] = ctx->Current.RasterPos[2];
+   vertices[1][3] = 1.0;
+   vertices[2][0] = dst_x + width;
+   vertices[2][1] = dst_y + height;
+   vertices[2][2] = ctx->Current.RasterPos[2];
+   vertices[2][3] = 1.0;
+   vertices[3][0] = dst_x;
+   vertices[3][1] = dst_y + height;
+   vertices[3][2] = ctx->Current.RasterPos[2];
+   vertices[3][3] = 1.0;
+
+   texcoords[0][0] = 0.0;
+   texcoords[0][1] = 0.0;
+   texcoords[1][0] = 1.0;
+   texcoords[1][1] = 0.0;
+   texcoords[2][0] = 1.0;
+   texcoords[2][1] = 1.0;
+   texcoords[3][0] = 0.0;
+   texcoords[3][1] = 1.0;
+
+   _mesa_VertexPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &vertices);
+   _mesa_TexCoordPointer(2, GL_FLOAT, 2 * sizeof(GLfloat), &texcoords);
+   _mesa_Enable(GL_VERTEX_ARRAY);
+   _mesa_Enable(GL_TEXTURE_COORD_ARRAY);
+   CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
+
+   intel_meta_restore_transform(intel);
+   intel_meta_restore_fragment_program(intel);
+   intel_meta_restore_vertex_program(intel);
+
+   _mesa_PopClientAttrib();
+   _mesa_Disable(GL_TEXTURE_2D); /* asserted that it was disabled at entry */
+   _mesa_ActiveTextureARB(GL_TEXTURE0_ARB + old_active_texture);
+   _mesa_PopAttrib();
+
+   _mesa_DeleteTextures(1, &texname);
 
+   return GL_TRUE;
+}
 
 /* There are a large number of possible ways to implement bitmap on
  * this hardware, most of them have some sort of drawback.  Here are a
@@ -352,6 +533,10 @@ intelBitmap(GLcontext * ctx,
                           unpack, pixels))
       return;
 
+   if (intel_texture_bitmap(ctx, x, y, width, height,
+			    unpack, pixels))
+      return;
+
    if (INTEL_DEBUG & DEBUG_PIXEL)
       _mesa_printf("%s: fallback to swrast\n", __FUNCTION__);
 
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 8ebbc95a1d0..0d66935ad27 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -36,7 +36,6 @@
 #include "main/texobj.h"
 #include "main/texstate.h"
 #include "main/texparam.h"
-#include "main/matrix.h"
 #include "main/varray.h"
 #include "main/attrib.h"
 #include "main/enable.h"
@@ -68,6 +67,7 @@ intel_texture_drawpixels(GLcontext * ctx,
 			 const struct gl_pixelstore_attrib *unpack,
 			 const GLvoid *pixels)
 {
+   struct intel_context *intel = intel_context(ctx);
    GLuint texname;
    GLfloat vertices[4][4];
    GLfloat texcoords[4][2];
@@ -117,7 +117,7 @@ intel_texture_drawpixels(GLcontext * ctx,
       return GL_FALSE;
    }
 
-   _mesa_PushAttrib(GL_ENABLE_BIT | GL_TRANSFORM_BIT | GL_TEXTURE_BIT |
+   _mesa_PushAttrib(GL_ENABLE_BIT | GL_TEXTURE_BIT |
 		    GL_CURRENT_BIT);
    _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
 
@@ -138,14 +138,7 @@ intel_texture_drawpixels(GLcontext * ctx,
    _mesa_TexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, width, height, 0, format,
 		    type, pixels);
 
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
-   _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1);
-
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
+   intel_meta_set_passthrough_transform(intel);
 
    /* Create the vertex buffer based on the current raster pos.  The x and y
     * we're handed are ctx->Current.RasterPos[0,1] rounded to integers.
@@ -184,10 +177,7 @@ intel_texture_drawpixels(GLcontext * ctx,
    _mesa_Enable(GL_TEXTURE_COORD_ARRAY);
    CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
 
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PopMatrix();
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PopMatrix();
+   intel_meta_restore_transform(intel);
    _mesa_PopClientAttrib();
    _mesa_PopAttrib();
 
@@ -205,6 +195,7 @@ intel_stencil_drawpixels(GLcontext * ctx,
 			 const struct gl_pixelstore_attrib *unpack,
 			 const GLvoid *pixels)
 {
+   struct intel_context *intel = intel_context(ctx);
    GLuint texname, rb_name, fb_name, old_fb_name;
    GLfloat vertices[4][2];
    GLfloat texcoords[4][2];
@@ -267,7 +258,7 @@ intel_stencil_drawpixels(GLcontext * ctx,
       return GL_FALSE;
    }
 
-   _mesa_PushAttrib(GL_ENABLE_BIT | GL_TRANSFORM_BIT | GL_TEXTURE_BIT |
+   _mesa_PushAttrib(GL_ENABLE_BIT | GL_TEXTURE_BIT |
 		    GL_CURRENT_BIT | GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
    _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
    old_fb_name = ctx->DrawBuffer->Name;
@@ -335,14 +326,7 @@ intel_stencil_drawpixels(GLcontext * ctx,
    ctx->Unpack = old_unpack;
    _mesa_free(stencil_pixels);
 
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
-   _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1);
-
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
+   intel_meta_set_passthrough_transform(intel);
 
    vertices[0][0] = x;
    vertices[0][1] = y;
@@ -368,12 +352,10 @@ intel_stencil_drawpixels(GLcontext * ctx,
    _mesa_Enable(GL_TEXTURE_COORD_ARRAY);
    CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
 
+   intel_meta_restore_transform(intel);
+
    _mesa_BindFramebufferEXT(GL_FRAMEBUFFER_EXT, old_fb_name);
 
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PopMatrix();
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PopMatrix();
    _mesa_PopClientAttrib();
    _mesa_PopAttrib();
 
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 8dbcc3050ee..51ce32a9679 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -550,15 +550,6 @@ intel_recreate_static_regions(struct intel_context *intel)
 			    intel->back_region,
 			    &intelScreen->back);
 
-#ifdef I915
-   if (intelScreen->third.handle) {
-      intel->third_region =
-	 intel_recreate_static(intel, "third",
-			       intel->third_region,
-			       &intelScreen->third);
-   }
-#endif /* I915 */
-
    /* Still assumes front.cpp == depth.cpp.  We can kill this when we move to
     * private buffers.
     */
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 61b55b97b51..fc4e82b56c9 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -177,13 +177,6 @@ intelUpdateScreenFromSAREA(intelScreenPrivate * intelScreen,
    intelScreen->back.size = sarea->back_size;
    intelScreen->back.tiled = sarea->back_tiled;
 
-   if (intelScreen->driScrnPriv->ddx_version.minor >= 8) {
-      intelScreen->third.offset = sarea->third_offset;
-      intelScreen->third.handle = sarea->third_handle;
-      intelScreen->third.size = sarea->third_size;
-      intelScreen->third.tiled = sarea->third_tiled;
-   }
-
    intelScreen->depth.offset = sarea->depth_offset;
    intelScreen->depth.handle = sarea->depth_handle;
    intelScreen->depth.size = sarea->depth_size;
@@ -192,12 +185,10 @@ intelUpdateScreenFromSAREA(intelScreenPrivate * intelScreen,
    if (intelScreen->driScrnPriv->ddx_version.minor >= 9) {
       intelScreen->front.bo_handle = sarea->front_bo_handle;
       intelScreen->back.bo_handle = sarea->back_bo_handle;
-      intelScreen->third.bo_handle = sarea->third_bo_handle;
       intelScreen->depth.bo_handle = sarea->depth_bo_handle;
    } else {
       intelScreen->front.bo_handle = -1;
       intelScreen->back.bo_handle = -1;
-      intelScreen->third.bo_handle = -1;
       intelScreen->depth.bo_handle = -1;
    }
 
@@ -353,12 +344,6 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
          _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
 				&intel_fb->color_rb[1]->Base);
 
-	 if (screen->third.handle) {
-	    struct gl_renderbuffer *tmp_rb = NULL;
-
-	    intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat);
-	    _mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
-	 }
       }
 
       if (mesaVis->depthBits == 24) {
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 91f0d6d1ae8..cf5359baaeb 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -56,7 +56,6 @@ typedef struct
 {
    intelRegion front;
    intelRegion back;
-   intelRegion third;
    intelRegion depth;
    intelRegion tex;
 
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 778db96cc1f..7c6485ef60b 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -64,7 +64,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R300_SE_VPORT_ZSCALE                0x1DA8
 #define R300_SE_VPORT_ZOFFSET               0x1DAC
 
-
+#define R300_VAP_PORT_IDX0		    0x2040
 /*
  * Vertex Array Processing (VAP) Control
  */
@@ -3201,9 +3201,9 @@ enum {
 #define R300_PACKET3_3D_LOAD_VBPNTR         0x00002F00
 
 #define R300_PACKET3_INDX_BUFFER            0x00003300
-#    define R300_EB_UNK1_SHIFT                      24
-#    define R300_EB_UNK1                    (0x80<<24)
-#    define R300_EB_UNK2                        0x0810
+#    define R300_INDX_BUFFER_DST_SHIFT          0
+#    define R300_INDX_BUFFER_SKIP_SHIFT         16
+#    define R300_INDX_BUFFER_ONE_REG_WR		(1<<31)
 
 /* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */
 #define R300_PACKET3_3D_DRAW_VBUF_2         0x00003400
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index 292f87a2b1b..f9266e44c13 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -208,7 +208,8 @@ static void r300FireEB(r300ContextPtr rmesa, unsigned long addr,
 	e32(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (vertex_count << 16) | type | R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
 
 	start_packet3(CP_PACKET3(R300_PACKET3_INDX_BUFFER, 2), 2);
-	e32(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2);
+	e32(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
+	    (R300_VAP_PORT_IDX0 >> 2));
 	e32(addr);
 	e32(vertex_count);
 }