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authorGiuseppe Bilotta <[email protected]>2016-06-23 19:20:18 +0200
committerChad Versace <[email protected]>2016-06-23 13:55:03 -0700
commit60a27ad122128145d28be37e9c0b0bc86a8e5181 (patch)
treebdd03c1cb36b1fa784f025dc29bbb0596708ad75 /src/mesa/drivers/dri
parent5d0799831725e67a224ef3cbb4ead39e2cebc7e6 (diff)
Remove wrongly repeated words in comments
Clean up misrepetitions ('if if', 'the the' etc) found throughout the comments. This has been done manually, after grepping case-insensitively for duplicate if, is, the, then, do, for, an, plus a few other typos corrected in fly-by v2: * proper commit message and non-joke title; * replace two 'as is' followed by 'is' to 'as-is'. v3: * 'a integer' => 'an integer' and similar (originally spotted by Jason Ekstrand, I fixed a few other similar ones while at it) Signed-off-by: Giuseppe Bilotta <[email protected]> Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_device_info.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_performance_monitor.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h b/src/mesa/drivers/dri/i965/brw_device_info.h
index 4e7f3135960..0869063df32 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.h
+++ b/src/mesa/drivers/dri/i965/brw_device_info.h
@@ -73,7 +73,7 @@ struct brw_device_info
* In general, you can find shader thread maximums by looking at the "Maximum
* Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
* 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
- * limits come from the "Number of URB Entries" field in the the
+ * limits come from the "Number of URB Entries" field in the
* 3DSTATE_URB_VS command and friends.
*
* These fields are used to calculate the scratch space to allocate. The
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 17673f8947c..51f163418ce 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1180,7 +1180,7 @@ fs_visitor::emit_general_interpolation(fs_reg *attr, const char *name,
/* Data starts at suboffet 3 in 32-bit units (12 bytes), so it is not
* 64-bit aligned and the current implementation fails to read the
- * data properly. Instead, when there is is a double input varying,
+ * data properly. Instead, when there is a double input varying,
* read it as vector of floats with twice the number of components.
*/
if (attr->type == BRW_REGISTER_TYPE_DF) {
diff --git a/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c b/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c
index 86fcdd4789a..14a9a0faca2 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c
+++ b/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c
@@ -113,7 +113,7 @@ get_mul_for_src(nir_alu_src *src, int num_components,
break;
case nir_op_fmul:
- /* Only absorb a fmul into a ffma if the fmul is is only used in fadd
+ /* Only absorb a fmul into a ffma if the fmul is only used in fadd
* operations. This prevents us from being too aggressive with our
* fusing which can actually lead to more instructions.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
index a91c6e2047a..cb1ab4c5d40 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -1016,7 +1016,7 @@ wrap_bookend_bo(struct brw_context *brw)
}
/* This is fairly arbitrary; the trade off is memory usage vs. extra overhead
- * from wrapping. On Gen7, 32768 should be enough for for 128 snapshots before
+ * from wrapping. On Gen7, 32768 should be enough for 128 snapshots before
* wrapping (since each is 256 bytes).
*/
#define BOOKEND_BO_SIZE_BYTES 32768