i965: Drop use of intel_region from miptrees.

Note: region->width/height used to reflect the total_width/height padding
of separate stencil, though mt->total_width didn't.  region->width/height
was being used in EGL images, where the padded value would have been the
wrong one, so I converted them to use rb->Width/Height.

v2: Drop debug printf that slipped in (caught by Ken)

Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chad Versace <[email protected]>

20 files changed, 242 insertions, 256 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 0b13bf1331b..b6bb4b3ed11 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -223,7 +223,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
     *      accessing tiled memory.  Using this Message Type to access linear
     *      (untiled) memory is UNDEFINED."
     */
-   if (irb->mt->region->tiling == I915_TILING_NONE)
+   if (irb->mt->tiling == I915_TILING_NONE)
       wm_prog_key.use_simd16_replicated_data = false;
 
    /* Constant color writes ignore everyting in blend and color calculator
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 3ce9ff6f187..8ffacc8f1a5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1265,7 +1265,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
 	* name, then drm_intel_bo_flink() is a low-cost getter.  It does not
 	* create a new name.
 	*/
-      drm_intel_bo_flink(last_mt->region->bo, &old_name);
+      drm_intel_bo_flink(last_mt->bo, &old_name);
    }
 
    if (old_name == buffer->name)
@@ -1346,7 +1346,7 @@ intel_update_image_buffer(struct brw_context *intel,
    else
       last_mt = rb->singlesample_mt;
 
-   if (last_mt && last_mt->region->bo == buffer->bo)
+   if (last_mt && last_mt->bo == buffer->bo)
       return;
 
    intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 671a5941889..d16106c4049 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -324,7 +324,7 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
 	 continue;
       intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
       intel_miptree_resolve_color(brw, tex_obj->mt);
-      brw_render_cache_set_check_flush(brw, tex_obj->mt->region->bo);
+      brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
    }
 }
 
@@ -360,12 +360,12 @@ static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
       back_irb->need_downsample = true;
    if (depth_irb && ctx->Depth.Mask) {
       intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
-      brw_render_cache_set_add_bo(brw, depth_irb->mt->region->bo);
+      brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
    }
 
    if (ctx->Extensions.ARB_stencil_texturing &&
        stencil_irb && ctx->Stencil._WriteEnabled) {
-      brw_render_cache_set_add_bo(brw, stencil_irb->mt->region->bo);
+      brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
    }
 
    for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
@@ -373,7 +373,7 @@ static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
          intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
       if (irb)
-         brw_render_cache_set_add_bo(brw, irb->mt->region->bo);
+         brw_render_cache_set_add_bo(brw, irb->mt->bo);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 87564280a80..ebe77882c5c 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -468,7 +468,7 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
           * that the region is untiled even though it's W tiled.
           */
          brw->depthstencil.stencil_offset =
-            (stencil_draw_y & ~tile_mask_y) * stencil_mt->region->pitch +
+            (stencil_draw_y & ~tile_mask_y) * stencil_mt->pitch +
             (stencil_draw_x & ~tile_mask_x) * 64;
       }
    }
@@ -524,8 +524,8 @@ brw_emit_depthbuffer(struct brw_context *brw)
       /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
       assert(brw->gen >= 7 || !separate_stencil || hiz);
 
-      assert(brw->gen < 6 || depth_mt->region->tiling == I915_TILING_Y);
-      assert(!hiz || depth_mt->region->tiling == I915_TILING_Y);
+      assert(brw->gen < 6 || depth_mt->tiling == I915_TILING_Y);
+      assert(!hiz || depth_mt->tiling == I915_TILING_Y);
 
       depthbuffer_format = brw_depthbuffer_format(brw);
       depth_surface_type = BRW_SURFACE_2D;
@@ -552,9 +552,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
    }
 
    if (depth_mt)
-      brw_render_cache_set_check_flush(brw, depth_mt->region->bo);
+      brw_render_cache_set_check_flush(brw, depth_mt->bo);
    if (stencil_mt)
-      brw_render_cache_set_check_flush(brw, stencil_mt->region->bo);
+      brw_render_cache_set_check_flush(brw, stencil_mt->bo);
 
    brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
                                     depthbuffer_format, depth_surface_type,
@@ -602,17 +602,17 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
 
    BEGIN_BATCH(len);
    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
-   OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
              ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
              (BRW_TILEWALK_YMAJOR << 26) |
-             ((depth_mt ? depth_mt->region->tiling != I915_TILING_NONE : 1)
+             ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
               << 27) |
              (depth_surface_type << 29));
 
    if (depth_mt) {
-      OUT_RELOC(depth_mt->region->bo,
+      OUT_RELOC(depth_mt->bo,
 		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		depth_offset);
    } else {
@@ -647,8 +647,8 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
          struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(hiz_mt->region->pitch - 1);
-	 OUT_RELOC(hiz_mt->region->bo,
+	 OUT_BATCH(hiz_mt->pitch - 1);
+	 OUT_RELOC(hiz_mt->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		   brw->depthstencil.hiz_offset);
 	 ADVANCE_BATCH();
@@ -662,8 +662,6 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
 
       /* Emit stencil buffer. */
       if (separate_stencil) {
-	 struct intel_region *region = stencil_mt->region;
-
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
          /* The stencil buffer has quirky pitch requirements.  From Vol 2a,
@@ -671,8 +669,8 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
           *    The pitch must be set to 2x the value computed based on width, as
           *    the stencil buffer is stored with two rows interleaved.
           */
-	 OUT_BATCH(2 * region->pitch - 1);
-	 OUT_RELOC(region->bo,
+	 OUT_BATCH(2 * stencil_mt->pitch - 1);
+	 OUT_RELOC(stencil_mt->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		   brw->depthstencil.stencil_offset);
 	 ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_object_purgeable.c b/src/mesa/drivers/dri/i965/brw_object_purgeable.c
index 2567de75900..20f66f229c3 100644
--- a/src/mesa/drivers/dri/i965/brw_object_purgeable.c
+++ b/src/mesa/drivers/dri/i965/brw_object_purgeable.c
@@ -77,10 +77,10 @@ intel_texture_object_purgeable(struct gl_context * ctx,
    (void) option;
 
    intel = intel_texture_object(obj);
-   if (intel->mt == NULL || intel->mt->region == NULL)
+   if (intel->mt == NULL || intel->mt->bo == NULL)
       return GL_RELEASED_APPLE;
 
-   return intel_buffer_purgeable(intel->mt->region->bo);
+   return intel_buffer_purgeable(intel->mt->bo);
 }
 
 static GLenum
@@ -97,7 +97,7 @@ intel_render_object_purgeable(struct gl_context * ctx,
    if (intel->mt == NULL)
       return GL_RELEASED_APPLE;
 
-   return intel_buffer_purgeable(intel->mt->region->bo);
+   return intel_buffer_purgeable(intel->mt->bo);
 }
 
 static GLenum
@@ -134,10 +134,10 @@ intel_texture_object_unpurgeable(struct gl_context * ctx,
    (void) option;
 
    intel = intel_texture_object(obj);
-   if (intel->mt == NULL || intel->mt->region == NULL)
+   if (intel->mt == NULL || intel->mt->bo == NULL)
       return GL_UNDEFINED_APPLE;
 
-   return intel_buffer_unpurgeable(intel->mt->region->bo);
+   return intel_buffer_unpurgeable(intel->mt->bo);
 }
 
 static GLenum
@@ -154,7 +154,7 @@ intel_render_object_unpurgeable(struct gl_context * ctx,
    if (intel->mt == NULL)
       return GL_UNDEFINED_APPLE;
 
-   return intel_buffer_unpurgeable(intel->mt->region->bo);
+   return intel_buffer_unpurgeable(intel->mt->bo);
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e93a33ea336..054467c2ef9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -319,16 +319,15 @@ brw_update_texture_surface(struct gl_context *ctx,
 	      BRW_SURFACE_CUBEFACE_ENABLES |
 	      tex_format << BRW_SURFACE_FORMAT_SHIFT);
 
-   surf[1] = mt->region->bo->offset64 + mt->offset; /* reloc */
+   surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
 
    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 	      (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
 	      (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 
-   surf[3] = (brw_get_surface_tiling_bits(mt->region->tiling) |
+   surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
 	      (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
-	      (mt->region->pitch - 1) <<
-	      BRW_SURFACE_PITCH_SHIFT);
+	      (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
 
    surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
               SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
@@ -338,8 +337,8 @@ brw_update_texture_surface(struct gl_context *ctx,
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            *surf_offset + 4,
-                           mt->region->bo,
-                           surf[1] - mt->region->bo->offset64,
+                           mt->bo,
+                           surf[1] - mt->bo->offset64,
                            I915_GEM_DOMAIN_SAMPLER, 0);
 }
 
@@ -613,7 +612,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
-   struct intel_region *region;
    uint32_t *surf;
    uint32_t tile_x, tile_y;
    uint32_t format = 0;
@@ -641,8 +639,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 
    intel_miptree_used_for_rendering(irb->mt);
 
-   region = irb->mt->region;
-
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
                           &brw->wm.base.surf_offset[surf_index]);
 
@@ -657,13 +653,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 
    /* reloc */
    surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
-	      region->bo->offset64);
+	      mt->bo->offset64);
 
    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 	      (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 
-   surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
-	      (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+   surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
+	      (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
 
    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
 
@@ -701,8 +697,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
 			   brw->wm.base.surf_offset[surf_index] + 4,
-			   region->bo,
-			   surf[1] - region->bo->offset64,
+			   mt->bo,
+			   surf[1] - mt->bo->offset64,
 			   I915_GEM_DOMAIN_RENDER,
 			   I915_GEM_DOMAIN_RENDER);
 }
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 903cb7899f3..fe065e2079c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -367,7 +367,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
       width /= 2;
       height /= 2;
    }
-   struct intel_region *region = surface->mt->region;
+   struct intel_mipmap_tree *mt = surface->mt;
    uint32_t tile_x, tile_y;
 
    uint32_t *surf = (uint32_t *)
@@ -381,7 +381,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
 
    /* reloc */
    surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
-              region->bo->offset64);
+              mt->bo->offset64);
 
    surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -389,8 +389,8 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
 
    uint32_t tiling = surface->map_stencil_as_y_tiled
       ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y
-      : brw_get_surface_tiling_bits(region->tiling);
-   uint32_t pitch_bytes = region->pitch;
+      : brw_get_surface_tiling_bits(mt->tiling);
+   uint32_t pitch_bytes = mt->pitch;
    if (surface->map_stencil_as_y_tiled)
       pitch_bytes *= 2;
    surf[3] = (tiling |
@@ -412,8 +412,8 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            wm_surf_offset + 4,
-                           region->bo,
-                           surf[1] - region->bo->offset64,
+                           mt->bo,
+                           surf[1] - mt->bo->offset64,
                            read_domains, write_domain);
 
    return wm_surf_offset;
@@ -834,14 +834,14 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
       BEGIN_BATCH(7);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
-      OUT_BATCH((params->depth.mt->region->pitch - 1) |
+      OUT_BATCH((params->depth.mt->pitch - 1) |
                 params->depth_format << 18 |
                 1 << 21 | /* separate stencil enable */
                 1 << 22 | /* hiz enable */
                 BRW_TILEWALK_YMAJOR << 26 |
                 1 << 27 | /* y-tiled */
                 BRW_SURFACE_2D << 29);
-      OUT_RELOC(params->depth.mt->region->bo,
+      OUT_RELOC(params->depth.mt->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                 offset);
       OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 |
@@ -864,8 +864,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
       BEGIN_BATCH(3);
       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-      OUT_BATCH(hiz_mt->region->pitch - 1);
-      OUT_RELOC(hiz_mt->region->bo,
+      OUT_BATCH(hiz_mt->pitch - 1);
+      OUT_RELOC(hiz_mt->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                 hiz_offset);
       ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 4bf93964a82..448b5050314 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -149,12 +149,12 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
     * to divide them by 2 as we do for Gen6 (see
     * gen6_blorp_emit_surface_state).
     */
-   struct intel_region *region = surface->mt->region;
+   struct intel_mipmap_tree *mt = surface->mt;
    uint32_t tile_x, tile_y;
    const uint8_t mocs = GEN7_MOCS_L3;
 
    uint32_t tiling = surface->map_stencil_as_y_tiled
-      ? I915_TILING_Y : region->tiling;
+      ? I915_TILING_Y : mt->tiling;
 
    uint32_t *surf = (uint32_t *)
       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
@@ -176,7 +176,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
 
    /* reloc */
    surf[1] =
-      surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64;
+      surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
 
    /* Note that the low bits of these fields are missing, so
     * there's the possibility of getting in trouble.
@@ -190,7 +190,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 
-   uint32_t pitch_bytes = region->pitch;
+   uint32_t pitch_bytes = mt->pitch;
    if (surface->map_stencil_as_y_tiled)
       pitch_bytes *= 2;
    surf[3] = pitch_bytes - 1;
@@ -213,8 +213,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            wm_surf_offset + 4,
-                           region->bo,
-                           surf[1] - region->bo->offset64,
+                           mt->bo,
+                           surf[1] - mt->bo->offset64,
                            read_domains, write_domain);
 
    gen7_check_surface_setup(surf, is_render_target);
@@ -732,12 +732,12 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
       BEGIN_BATCH(7);
       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
-      OUT_BATCH((params->depth.mt->region->pitch - 1) |
+      OUT_BATCH((params->depth.mt->pitch - 1) |
                 params->depth_format << 18 |
                 1 << 22 | /* hiz enable */
                 1 << 28 | /* depth write */
                 surftype << 29);
-      OUT_RELOC(params->depth.mt->region->bo,
+      OUT_RELOC(params->depth.mt->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                 0);
       OUT_BATCH((surfwidth - 1) << 4 |
@@ -753,13 +753,13 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
+      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
 
       BEGIN_BATCH(3);
       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_region->pitch - 1));
-      OUT_RELOC(hiz_region->bo,
+                (hiz_mt->pitch - 1));
+      OUT_RELOC(hiz_mt->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                 0);
       ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 328b01e69df..731325e2f35 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -109,7 +109,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
    /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((hiz ? 1 : 0) << 22) |
              ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
@@ -118,7 +118,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
 
    /* 3DSTATE_DEPTH_BUFFER dw2 */
    if (depth_mt) {
-      OUT_RELOC(depth_mt->region->bo,
+      OUT_RELOC(depth_mt->bo,
 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 	        0);
    } else {
@@ -153,8 +153,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_mt->region->pitch - 1));
-      OUT_RELOC(hiz_mt->region->bo,
+                (hiz_mt->pitch - 1));
+      OUT_RELOC(hiz_mt->bo,
                 I915_GEM_DOMAIN_RENDER,
                 I915_GEM_DOMAIN_RENDER,
                 0);
@@ -184,8 +184,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
        */
       OUT_BATCH(enabled |
                 mocs << 25 |
-	        (2 * stencil_mt->region->pitch - 1));
-      OUT_RELOC(stencil_mt->region->bo,
+	        (2 * stencil_mt->pitch - 1));
+      OUT_RELOC(stencil_mt->bo,
 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		0);
       ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 1303555f835..d71a1d15656 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -107,12 +107,12 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
     *
     *     "The MCS surface must be stored as Tile Y."
     */
-   assert(mcs_mt->region->tiling == I915_TILING_Y);
+   assert(mcs_mt->tiling == I915_TILING_Y);
 
    /* Compute the pitch in units of tiles.  To do this we need to divide the
     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
     */
-   unsigned pitch_tiles = mcs_mt->region->pitch / 128;
+   unsigned pitch_tiles = mcs_mt->pitch / 128;
 
    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
     * GPU address of the MCS buffer; the lower 12 bits contain other control
@@ -120,15 +120,15 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
     * the necessary address translation.
     */
-   assert ((mcs_mt->region->bo->offset64 & 0xfff) == 0);
+   assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
 
    surf[6] = GEN7_SURFACE_MCS_ENABLE |
              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
-             mcs_mt->region->bo->offset64;
+             mcs_mt->bo->offset64;
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            surf_offset + 6 * 4,
-                           mcs_mt->region->bo,
+                           mcs_mt->bo,
                            surf[6] & 0xfff,
                            is_render_target ? I915_GEM_DOMAIN_RENDER
                            : I915_GEM_DOMAIN_SAMPLER,
@@ -296,7 +296,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
 
    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
              tex_format << BRW_SURFACE_FORMAT_SHIFT |
-             gen7_surface_tiling_mode(mt->region->tiling);
+             gen7_surface_tiling_mode(mt->tiling);
 
    /* mask of faces present in cube map; for other surfaces MBZ. */
    if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
@@ -319,13 +319,13 @@ gen7_update_texture_surface(struct gl_context *ctx,
    if (mt->array_spacing_lod0)
       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 
-   surf[1] = mt->region->bo->offset64 + mt->offset; /* reloc */
+   surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
 
    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 
    surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) |
-             (mt->region->pitch - 1);
+             (mt->pitch - 1);
 
    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
              SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
@@ -366,8 +366,8 @@ gen7_update_texture_surface(struct gl_context *ctx,
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            *surf_offset + 4,
-                           mt->region->bo,
-                           surf[1] - mt->region->bo->offset64,
+                           mt->bo,
+                           surf[1] - mt->bo->offset64,
                            I915_GEM_DOMAIN_SAMPLER, 0);
 
    gen7_check_surface_setup(surf, false /* is_render_target */);
@@ -448,7 +448,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 {
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   struct intel_region *region = irb->mt->region;
+   struct intel_mipmap_tree *mt = irb->mt;
    uint32_t format;
    /* _NEW_BUFFERS */
    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
@@ -504,7 +504,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
              format << BRW_SURFACE_FORMAT_SHIFT |
              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
                                           : GEN7_SURFACE_ARYSPC_FULL) |
-             gen7_surface_tiling_mode(region->tiling);
+             gen7_surface_tiling_mode(mt->tiling);
 
    if (irb->mt->align_h == 4)
       surf[0] |= GEN7_SURFACE_VALIGN_4;
@@ -515,7 +515,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
       surf[0] |= GEN7_SURFACE_IS_ARRAY;
    }
 
-   surf[1] = region->bo->offset64;
+   surf[1] = mt->bo->offset64;
 
    assert(brw->has_surface_tile_offset);
 
@@ -526,7 +526,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 
    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
-             (region->pitch - 1);
+             (mt->pitch - 1);
 
    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
@@ -548,8 +548,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
 			   brw->wm.base.surf_offset[surf_index] + 4,
-			   region->bo,
-			   surf[1] - region->bo->offset64,
+			   mt->bo,
+			   surf[1] - mt->bo->offset64,
 			   I915_GEM_DOMAIN_RENDER,
 			   I915_GEM_DOMAIN_RENDER);
 
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 05c37239543..2de30eea637 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -65,9 +65,9 @@ emit_depth_packets(struct brw_context *brw,
              (stencil_mt != NULL && stencil_writable) << 27 |
              (hiz ? 1 : 0) << 22 |
              depthbuffer_format << 18 |
-             (depth_mt ? depth_mt->region->pitch - 1 : 0));
+             (depth_mt ? depth_mt->pitch - 1 : 0));
    if (depth_mt) {
-      OUT_RELOC64(depth_mt->region->bo,
+      OUT_RELOC64(depth_mt->bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
    } else {
       OUT_BATCH(0);
@@ -90,8 +90,8 @@ emit_depth_packets(struct brw_context *brw,
    } else {
       BEGIN_BATCH(5);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
-      OUT_BATCH((depth_mt->hiz_mt->region->pitch - 1) | BDW_MOCS_WB << 25);
-      OUT_RELOC64(depth_mt->hiz_mt->region->bo,
+      OUT_BATCH((depth_mt->hiz_mt->pitch - 1) | BDW_MOCS_WB << 25);
+      OUT_RELOC64(depth_mt->hiz_mt->bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
       OUT_BATCH(depth_mt->hiz_mt->qpitch >> 2);
       ADVANCE_BATCH();
@@ -123,8 +123,8 @@ emit_depth_packets(struct brw_context *brw,
        * indicate that it does.
        */
       OUT_BATCH(HSW_STENCIL_ENABLED | BDW_MOCS_WB << 22 |
-                (2 * stencil_mt->region->pitch - 1));
-      OUT_RELOC64(stencil_mt->region->bo,
+                (2 * stencil_mt->pitch - 1));
+      OUT_RELOC64(stencil_mt->bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                   stencil_offset);
       OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
@@ -308,7 +308,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
    ADVANCE_BATCH();
 
    /* Mark this buffer as needing a TC flush, as we've rendered to it. */
-   brw_render_cache_set_add_bo(brw, mt->region->bo);
+   brw_render_cache_set_add_bo(brw, mt->bo);
 
    /* We've clobbered all of the depth packets, and the drawing rectangle,
     * so we need to ensure those packets are re-emitted before the next
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 4db53597684..564d275fb9e 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -146,10 +146,10 @@ gen8_update_texture_surface(struct gl_context *ctx,
    unsigned tiling_mode, pitch;
    if (mt->format == MESA_FORMAT_S_UINT8) {
       tiling_mode = GEN8_SURFACE_TILING_W;
-      pitch = 2 * mt->region->pitch;
+      pitch = 2 * mt->pitch;
    } else {
-      tiling_mode = surface_tiling_mode(mt->region->tiling);
-      pitch = mt->region->pitch;
+      tiling_mode = surface_tiling_mode(mt->tiling);
+      pitch = mt->pitch;
    }
 
    uint32_t tex_format = translate_tex_format(brw,
@@ -203,7 +203,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), false), GEN7_SURFACE_SCS_B) |
       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), false), GEN7_SURFACE_SCS_A);
 
-   *((uint64_t *) &surf[8]) = mt->region->bo->offset64 + mt->offset; /* reloc */
+   *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 
    surf[10] = 0;
    surf[11] = 0;
@@ -212,7 +212,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            *surf_offset + 8 * 4,
-                           mt->region->bo,
+                           mt->bo,
                            mt->offset,
                            I915_GEM_DOMAIN_SAMPLER, 0);
 }
@@ -272,7 +272,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
-   struct intel_region *region = mt->region;
    uint32_t format = 0;
    uint32_t surf_type;
    bool is_array = false;
@@ -328,7 +327,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              (format << BRW_SURFACE_FORMAT_SHIFT) |
              vertical_alignment(mt) |
              horizontal_alignment(mt) |
-             surface_tiling_mode(region->tiling);
+             surface_tiling_mode(mt->tiling);
 
    surf[1] = SET_FIELD(BDW_MOCS_WT, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 
@@ -336,7 +335,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 
    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
-             (region->pitch - 1); /* Surface Pitch */
+             (mt->pitch - 1); /* Surface Pitch */
 
    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
@@ -352,7 +351,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 
-   *((uint64_t *) &surf[8]) = region->bo->offset64; /* reloc */
+   *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
 
    /* Nothing of relevance. */
    surf[10] = 0;
@@ -361,7 +360,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            brw->wm.base.surf_offset[surf_index] + 8 * 4,
-                           region->bo,
+                           mt->bo,
                            0,
                            I915_GEM_DOMAIN_RENDER,
                            I915_GEM_DOMAIN_RENDER);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index d4822727874..2ebaf73768f 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -202,10 +202,10 @@ intel_miptree_blit(struct brw_context *brw,
     * pitches < 32k.
     *
     * As a result of these two limitations, we can only use the blitter to do
-    * this copy when the region's pitch is less than 32k.
+    * this copy when the miptree's pitch is less than 32k.
     */
-   if (src_mt->region->pitch >= 32768 ||
-       dst_mt->region->pitch >= 32768) {
+   if (src_mt->pitch >= 32768 ||
+       dst_mt->pitch >= 32768) {
       perf_debug("Falling back due to >=32k pitch\n");
       return false;
    }
@@ -224,7 +224,7 @@ intel_miptree_blit(struct brw_context *brw,
    if (dst_flip)
       dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
 
-   int src_pitch = src_mt->region->pitch;
+   int src_pitch = src_mt->pitch;
    if (src_flip != dst_flip)
       src_pitch = -src_pitch;
 
@@ -263,11 +263,11 @@ intel_miptree_blit(struct brw_context *brw,
    if (!intelEmitCopyBlit(brw,
                           src_mt->cpp,
                           src_pitch,
-                          src_mt->region->bo, src_mt->offset,
-                          src_mt->region->tiling,
-                          dst_mt->region->pitch,
-                          dst_mt->region->bo, dst_mt->offset,
-                          dst_mt->region->tiling,
+                          src_mt->bo, src_mt->offset,
+                          src_mt->tiling,
+                          dst_mt->pitch,
+                          dst_mt->bo, dst_mt->offset,
+                          dst_mt->tiling,
                           src_x, src_y,
                           dst_x, dst_y,
                           width, height,
@@ -583,22 +583,21 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
                               struct intel_mipmap_tree *mt,
                               int x, int y, int width, int height)
 {
-   struct intel_region *region = mt->region;
    uint32_t BR13, CMD;
    int pitch, cpp;
    drm_intel_bo *aper_array[2];
 
-   pitch = region->pitch;
-   cpp = region->cpp;
+   pitch = mt->pitch;
+   cpp = mt->cpp;
 
    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
-       __FUNCTION__, region->bo, pitch, x, y, width, height);
+       __FUNCTION__, mt->bo, pitch, x, y, width, height);
 
    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
    CMD = XY_COLOR_BLT_CMD;
    CMD |= XY_BLT_WRITE_ALPHA;
 
-   if (region->tiling != I915_TILING_NONE) {
+   if (mt->tiling != I915_TILING_NONE) {
       CMD |= XY_DST_TILED;
       pitch /= 4;
    }
@@ -606,7 +605,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
 
    /* do space check before going any further */
    aper_array[0] = brw->batch.bo;
-   aper_array[1] = region->bo;
+   aper_array[1] = mt->bo;
 
    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 					     ARRAY_SIZE(aper_array)) != 0) {
@@ -614,7 +613,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
    }
 
    unsigned length = brw->gen >= 8 ? 7 : 6;
-   bool dst_y_tiled = region->tiling == I915_TILING_Y;
+   bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 
    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
    OUT_BATCH(CMD | (length - 2));
@@ -622,11 +621,11 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
    if (brw->gen >= 8) {
-      OUT_RELOC64(region->bo,
+      OUT_RELOC64(mt->bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                   0);
    } else {
-      OUT_RELOC(region->bo,
+      OUT_RELOC(mt->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                 0);
    }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d573033e7f7..5f241eff034 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -144,7 +144,7 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
                                  struct intel_mipmap_tree *mt,
                                  unsigned *width_px, unsigned *height)
 {
-   switch (mt->region->tiling) {
+   switch (mt->tiling) {
    default:
       assert(!"Non-MSRT MCS requires X or Y tiling");
       /* In release builds, fall through */
@@ -190,8 +190,8 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
       return false;
    }
 
-   if (mt->region->tiling != I915_TILING_X &&
-       mt->region->tiling != I915_TILING_Y)
+   if (mt->tiling != I915_TILING_X &&
+       mt->tiling != I915_TILING_Y)
       return false;
    if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
       return false;
@@ -583,36 +583,45 @@ intel_miptree_create(struct brw_context *brw,
    uint32_t tiling = intel_miptree_choose_tiling(brw, format, width0,
                                                  num_samples, requested_tiling,
                                                  mt);
-   bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X);
+   bool y_or_x = false;
 
+   if (tiling == (I915_TILING_Y | I915_TILING_X)) {
+      y_or_x = true;
+      mt->tiling = I915_TILING_Y;
+   } else {
+      mt->tiling = tiling;
+   }
+
+   unsigned long pitch;
    mt->etc_format = etc_format;
-   mt->region = intel_region_alloc(brw->intelScreen,
-				   y_or_x ? I915_TILING_Y : tiling,
-				   mt->cpp,
-				   total_width,
-				   total_height,
-				   expect_accelerated_upload);
-
-   /* If the region is too large to fit in the aperture, we need to use the
+   mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+                                     total_width, total_height, mt->cpp,
+                                     &mt->tiling, &pitch,
+                                     (expect_accelerated_upload ?
+                                      BO_ALLOC_FOR_RENDER : 0));
+   mt->pitch = pitch;
+
+   /* If the BO is too large to fit in the aperture, we need to use the
     * BLT engine to support it.  The BLT paths can't currently handle Y-tiling,
     * so we need to fall back to X.
     */
-   if (y_or_x && mt->region->bo->size >= brw->max_gtt_map_object_size) {
+   if (y_or_x && mt->bo->size >= brw->max_gtt_map_object_size) {
       perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
                  mt->total_width, mt->total_height);
-      intel_region_release(&mt->region);
-
-      mt->region = intel_region_alloc(brw->intelScreen,
-                                      I915_TILING_X,
-                                      mt->cpp,
-                                      total_width,
-                                      total_height,
-                                      expect_accelerated_upload);
+
+      mt->tiling = I915_TILING_X;
+      drm_intel_bo_unreference(mt->bo);
+      mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+                                        total_width, total_height, mt->cpp,
+                                        &mt->tiling, &pitch,
+                                        (expect_accelerated_upload ?
+                                         BO_ALLOC_FOR_RENDER : 0));
+      mt->pitch = pitch;
    }
 
    mt->offset = 0;
 
-   if (!mt->region) {
+   if (!mt->bo) {
        intel_miptree_release(&mt);
        return NULL;
    }
@@ -648,10 +657,6 @@ intel_miptree_create_for_bo(struct brw_context *brw,
    struct intel_mipmap_tree *mt;
    uint32_t tiling, swizzle;
 
-   struct intel_region *region = calloc(1, sizeof(*region));
-   if (!region)
-      return NULL;
-
    drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
 
    /* Nothing will be able to use this miptree with the BO if the offset isn't
@@ -670,21 +675,15 @@ intel_miptree_create_for_bo(struct brw_context *brw,
                                     width, height, 1,
                                     true, 0 /* num_samples */);
    if (!mt) {
-      free(region);
+      free(mt);
       return mt;
    }
 
-   region->cpp = mt->cpp;
-   region->width = width;
-   region->height = height;
-   region->pitch = pitch;
-   region->refcount = 1;
    drm_intel_bo_reference(bo);
-   region->bo = bo;
-   region->tiling = tiling;
-
-   mt->region = region;
+   mt->bo = bo;
+   mt->pitch = pitch;
    mt->offset = offset;
+   mt->tiling = tiling;
 
    return mt;
 }
@@ -830,7 +829,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
 
       DBG("%s deleting %p\n", __FUNCTION__, *mt);
 
-      intel_region_release(&((*mt)->region));
+      drm_intel_bo_unreference((*mt)->bo);
       intel_miptree_release(&(*mt)->stencil_mt);
       intel_miptree_release(&(*mt)->hiz_mt);
       intel_miptree_release(&(*mt)->mcs_mt);
@@ -989,8 +988,8 @@ intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
                              uint32_t *mask_x, uint32_t *mask_y,
                              bool map_stencil_as_y_tiled)
 {
-   int cpp = mt->region->cpp;
-   uint32_t tiling = mt->region->tiling;
+   int cpp = mt->cpp;
+   uint32_t tiling = mt->tiling;
 
    if (map_stencil_as_y_tiled)
       tiling = I915_TILING_Y;
@@ -1022,9 +1021,9 @@ intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
                                  uint32_t x, uint32_t y,
                                  bool map_stencil_as_y_tiled)
 {
-   int cpp = mt->region->cpp;
-   uint32_t pitch = mt->region->pitch;
-   uint32_t tiling = mt->region->tiling;
+   int cpp = mt->cpp;
+   uint32_t pitch = mt->pitch;
+   uint32_t tiling = mt->tiling;
 
    if (map_stencil_as_y_tiled) {
       tiling = I915_TILING_Y;
@@ -1190,9 +1189,9 @@ intel_miptree_copy_slice(struct brw_context *brw,
 
    DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
        _mesa_get_format_name(src_mt->format),
-       src_mt, src_x, src_y, src_mt->region->pitch,
+       src_mt, src_x, src_y, src_mt->pitch,
        _mesa_get_format_name(dst_mt->format),
-       dst_mt, dst_x, dst_y, dst_mt->region->pitch,
+       dst_mt, dst_x, dst_y, dst_mt->pitch,
        width, height);
 
    if (!intel_miptree_blit(brw,
@@ -1297,7 +1296,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
     * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
     */
    void *data = intel_miptree_map_raw(brw, mt->mcs_mt);
-   memset(data, 0xff, mt->mcs_mt->region->height * mt->mcs_mt->region->pitch);
+   memset(data, 0xff, mt->mcs_mt->total_height * mt->mcs_mt->pitch);
    intel_miptree_unmap_raw(brw, mt->mcs_mt);
    mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
 
@@ -1569,7 +1568,7 @@ intel_miptree_resolve_color(struct brw_context *brw,
 
 
 /**
- * Make it possible to share the region backing the given miptree with another
+ * Make it possible to share the BO backing the given miptree with another
  * process or another miptree.
  *
  * Fast color clears are unsafe with shared buffers, so we need to resolve and
@@ -1690,12 +1689,12 @@ intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt)
     */
    intel_miptree_resolve_color(brw, mt);
 
-   drm_intel_bo *bo = mt->region->bo;
+   drm_intel_bo *bo = mt->bo;
 
    if (drm_intel_bo_references(brw->batch.bo, bo))
       intel_batchbuffer_flush(brw);
 
-   if (mt->region->tiling != I915_TILING_NONE)
+   if (mt->tiling != I915_TILING_NONE)
       brw_bo_map_gtt(brw, bo, "miptree");
    else
       brw_bo_map(brw, bo, true, "miptree");
@@ -1707,7 +1706,7 @@ void
 intel_miptree_unmap_raw(struct brw_context *brw,
                         struct intel_mipmap_tree *mt)
 {
-   drm_intel_bo_unmap(mt->region->bo);
+   drm_intel_bo_unmap(mt->bo);
 }
 
 static void
@@ -1742,7 +1741,7 @@ intel_miptree_map_gtt(struct brw_context *brw,
       x += image_x;
       y += image_y;
 
-      map->stride = mt->region->pitch;
+      map->stride = mt->pitch;
       map->ptr = base + y * map->stride + x * mt->cpp;
    }
 
@@ -1777,7 +1776,7 @@ intel_miptree_map_blit(struct brw_context *brw,
       fprintf(stderr, "Failed to allocate blit temporary\n");
       goto fail;
    }
-   map->stride = map->mt->region->pitch;
+   map->stride = map->mt->pitch;
 
    if (!intel_miptree_blit(brw,
                            mt, level, slice,
@@ -1856,15 +1855,15 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
    void *src = intel_miptree_map_raw(brw, mt);
    if (!src)
       return;
-   src += image_y * mt->region->pitch;
-   src += image_x * mt->region->cpp;
+   src += image_y * mt->pitch;
+   src += image_x * mt->cpp;
 
    /* Due to the pixel offsets for the particular image being mapped, our
     * src pointer may not be 16-byte aligned.  However, if the pitch is
     * divisible by 16, then the amount by which it's misaligned will remain
     * consistent from row to row.
     */
-   assert((mt->region->pitch % 16) == 0);
+   assert((mt->pitch % 16) == 0);
    const int misalignment = ((uintptr_t) src) & 15;
 
    /* Create an untiled temporary buffer for the mapping. */
@@ -1880,7 +1879,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
 
    for (uint32_t y = 0; y < map->h; y++) {
       void *dst_ptr = map->ptr + y * map->stride;
-      void *src_ptr = src + y * mt->region->pitch;
+      void *src_ptr = src + y * mt->pitch;
 
       _mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes);
    }
@@ -1926,7 +1925,7 @@ intel_miptree_map_s8(struct brw_context *brw,
 
       for (uint32_t y = 0; y < map->h; y++) {
 	 for (uint32_t x = 0; x < map->w; x++) {
-	    ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
+	    ptrdiff_t offset = intel_offset_S8(mt->pitch,
 	                                       x + image_x + map->x,
 	                                       y + image_y + map->y,
 					       brw->has_swizzling);
@@ -1962,7 +1961,7 @@ intel_miptree_unmap_s8(struct brw_context *brw,
 
       for (uint32_t y = 0; y < map->h; y++) {
 	 for (uint32_t x = 0; x < map->w; x++) {
-	    ptrdiff_t offset = intel_offset_S8(mt->region->pitch,
+	    ptrdiff_t offset = intel_offset_S8(mt->pitch,
 	                                       x + map->x,
 	                                       y + map->y,
 					       brw->has_swizzling);
@@ -2012,15 +2011,15 @@ intel_miptree_unmap_etc(struct brw_context *brw,
    image_y += map->y;
 
    uint8_t *dst = intel_miptree_map_raw(brw, mt)
-                + image_y * mt->region->pitch
-                + image_x * mt->region->cpp;
+                + image_y * mt->pitch
+                + image_x * mt->cpp;
 
    if (mt->etc_format == MESA_FORMAT_ETC1_RGB8)
-      _mesa_etc1_unpack_rgba8888(dst, mt->region->pitch,
+      _mesa_etc1_unpack_rgba8888(dst, mt->pitch,
                                  map->ptr, map->stride,
                                  map->w, map->h);
    else
-      _mesa_unpack_etc2_format(dst, mt->region->pitch,
+      _mesa_unpack_etc2_format(dst, mt->pitch,
                                map->ptr, map->stride,
                                map->w, map->h, mt->etc_format);
 
@@ -2075,12 +2074,12 @@ intel_miptree_map_depthstencil(struct brw_context *brw,
       for (uint32_t y = 0; y < map->h; y++) {
 	 for (uint32_t x = 0; x < map->w; x++) {
 	    int map_x = map->x + x, map_y = map->y + y;
-	    ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
+	    ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch,
 						 map_x + s_image_x,
 						 map_y + s_image_y,
 						 brw->has_swizzling);
 	    ptrdiff_t z_offset = ((map_y + z_image_y) *
-                                  (z_mt->region->pitch / 4) +
+                                  (z_mt->pitch / 4) +
 				  (map_x + z_image_x));
 	    uint8_t s = s_map[s_offset];
 	    uint32_t z = z_map[z_offset];
@@ -2135,12 +2134,12 @@ intel_miptree_unmap_depthstencil(struct brw_context *brw,
 
       for (uint32_t y = 0; y < map->h; y++) {
 	 for (uint32_t x = 0; x < map->w; x++) {
-	    ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch,
+	    ptrdiff_t s_offset = intel_offset_S8(s_mt->pitch,
 						 x + s_image_x + map->x,
 						 y + s_image_y + map->y,
 						 brw->has_swizzling);
 	    ptrdiff_t z_offset = ((y + z_image_y) *
-                                  (z_mt->region->pitch / 4) +
+                                  (z_mt->pitch / 4) +
 				  (x + z_image_x));
 
 	    if (map_z32f_x24s8) {
@@ -2225,7 +2224,7 @@ can_blit_slice(struct intel_mipmap_tree *mt,
    if (image_x >= 32768 || image_y >= 32768)
       return false;
 
-   if (mt->region->pitch >= 32768)
+   if (mt->pitch >= 32768)
       return false;
 
    return true;
@@ -2272,12 +2271,12 @@ intel_miptree_map(struct brw_context *brw,
    else if (brw->has_llc &&
             !(mode & GL_MAP_WRITE_BIT) &&
             !mt->compressed &&
-            (mt->region->tiling == I915_TILING_X ||
-             (brw->gen >= 6 && mt->region->tiling == I915_TILING_Y)) &&
+            (mt->tiling == I915_TILING_X ||
+             (brw->gen >= 6 && mt->tiling == I915_TILING_Y)) &&
             can_blit_slice(mt, level, slice)) {
       intel_miptree_map_blit(brw, mt, map, level, slice);
-   } else if (mt->region->tiling != I915_TILING_NONE &&
-              mt->region->bo->size >= brw->max_gtt_map_object_size) {
+   } else if (mt->tiling != I915_TILING_NONE &&
+              mt->bo->size >= brw->max_gtt_map_object_size) {
       assert(can_blit_slice(mt, level, slice));
       intel_miptree_map_blit(brw, mt, map, level, slice);
 #ifdef __SSE4_1__
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index d9b7d8b2529..502a9bf4218 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -25,6 +25,24 @@
  *
  **************************************************************************/
 
+/** @file intel_mipmap_tree.h
+ *
+ * This file defines the structure that wraps a BO and describes how the
+ * mipmap levels and slices of a texture are laid out.
+ *
+ * The hardware has a fixed layout of a texture depending on parameters such
+ * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
+ * mipmap levels.  The individual level/layer slices are each 2D rectangles of
+ * pixels at some x/y offset from the start of the drm_intel_bo.
+ *
+ * Original OpenGL allowed texture miplevels to be specified in arbitrary
+ * order, and a texture may change size over time.  Thus, each
+ * intel_texture_image has a reference to a miptree that contains the pixel
+ * data sized appropriately for it, which will later be referenced by/copied
+ * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
+ * that there's a single miptree for the complete texture.
+ */
+
 #ifndef INTEL_MIPMAP_TREE_H
 #define INTEL_MIPMAP_TREE_H
 
@@ -40,32 +58,6 @@ extern "C" {
 
 struct intel_renderbuffer;
 
-/* A layer on top of the intel_regions code which adds:
- *
- * - Code to size and layout a region to hold a set of mipmaps.
- * - Query to determine if a new image fits in an existing tree.
- * - More refcounting
- *     - maybe able to remove refcounting from intel_region?
- * - ?
- *
- * The fixed mipmap layout of intel hardware where one offset
- * specifies the position of all images in a mipmap hierachy
- * complicates the implementation of GL texture image commands,
- * compared to hardware where each image is specified with an
- * independent offset.
- *
- * In an ideal world, each texture object would be associated with a
- * single bufmgr buffer or 2d intel_region, and all the images within
- * the texture object would slot into the tree as they arrive.  The
- * reality can be a little messier, as images can arrive from the user
- * with sizes that don't fit in the existing tree, or in an order
- * where the tree layout cannot be guessed immediately.
- *
- * This structure encodes an idealized mipmap tree.  The GL image
- * commands build these where possible, otherwise store the images in
- * temporary system buffers.
- */
-
 struct intel_resolve_map;
 struct intel_texture_image;
 
@@ -96,7 +88,7 @@ struct intel_miptree_map {
 };
 
 /**
- * Describes the location of each texture image within a texture region.
+ * Describes the location of each texture image within a miptree.
  */
 struct intel_mipmap_level
 {
@@ -263,6 +255,13 @@ enum intel_fast_clear_state
 
 struct intel_mipmap_tree
 {
+   /** Buffer object containing the pixel data. */
+   drm_intel_bo *bo;
+
+   uint32_t pitch; /**< pitch in bytes. */
+
+   uint32_t tiling; /**< One of the I915_TILING_* flags */
+
    /* Effectively the key:
     */
    GLenum target;
@@ -306,13 +305,13 @@ struct intel_mipmap_tree
     */
    GLuint physical_width0, physical_height0, physical_depth0;
 
-   GLuint cpp;
+   GLuint cpp; /**< bytes per pixel */
    GLuint num_samples;
    bool compressed;
 
    /**
     * Level zero image dimensions.  These dimensions correspond to the
-    * logical width, height, and depth of the region as seen by client code.
+    * logical width, height, and depth of the texture as seen by client code.
     * Accordingly, they do not account for the extra width, height, and/or
     * depth that must be allocated in order to accommodate multisample
     * formats, nor do they account for the extra factor of 6 in depth that
@@ -356,11 +355,7 @@ struct intel_mipmap_tree
     */
    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 
-   /* The data is held here:
-    */
-   struct intel_region *region;
-
-   /* Offset into region bo where miptree starts:
+   /* Offset into bo where miptree starts:
     */
    uint32_t offset;
 
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index 29c2d28aaba..1d9193a739b 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -296,10 +296,10 @@ do_blit_bitmap( struct gl_context *ctx,
 						(GLubyte *)stipple,
 						sz,
 						color,
-						irb->mt->region->pitch,
-						irb->mt->region->bo,
+						irb->mt->pitch,
+						irb->mt->bo,
 						0,
-						irb->mt->region->tiling,
+						irb->mt->tiling,
 						dstx + px,
 						dsty + py,
 						w, h,
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index da96540a736..30321242f43 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -140,14 +140,14 @@ aub_dump_bmp(struct gl_context *ctx)
 	    continue;
 	 }
 
-         assert(irb->mt->region->pitch % irb->mt->region->cpp == 0);
-	 drm_intel_gem_bo_aub_dump_bmp(irb->mt->region->bo,
+         assert(irb->mt->pitch % irb->mt->cpp == 0);
+         drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo,
 				       irb->draw_x,
 				       irb->draw_y,
 				       irb->Base.Base.Width,
 				       irb->Base.Base.Height,
 				       format,
-				       irb->mt->region->pitch,
+				       irb->mt->pitch,
 				       0);
       }
    }
@@ -338,15 +338,15 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
 
    image->width = minify(mt->physical_width0, level - mt->first_level);
    image->height = minify(mt->physical_height0, level - mt->first_level);
-   image->pitch = mt->region->pitch;
+   image->pitch = mt->pitch;
 
    image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
                                                   &image->tile_x,
                                                   &image->tile_y);
 
    drm_intel_bo_unreference(image->bo);
-   image->bo = mt->region->bo;
-   drm_intel_bo_reference(mt->region->bo);
+   image->bo = mt->bo;
+   drm_intel_bo_reference(mt->bo);
 }
 
 static __DRIimage *
@@ -407,11 +407,11 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
    image->offset = 0;
    image->data = loaderPrivate;
    drm_intel_bo_unreference(image->bo);
-   image->bo = irb->mt->region->bo;
-   drm_intel_bo_reference(irb->mt->region->bo);
-   image->width = irb->mt->region->width;
-   image->height = irb->mt->region->height;
-   image->pitch = irb->mt->region->pitch;
+   image->bo = irb->mt->bo;
+   drm_intel_bo_reference(irb->mt->bo);
+   image->width = rb->Width;
+   image->height = rb->Height;
+   image->pitch = irb->mt->pitch;
    image->dri_format = driGLFormatToImageFormat(image->format);
    image->has_depthstencil = irb->mt->stencil_mt? true : false;
 
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 9e8b36ef8f0..bbb66026f23 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -254,8 +254,8 @@ intel_set_texture_image_bo(struct gl_context *ctx,
    intel_texobj->needs_validate = true;
 
    intel_image->mt->offset = offset;
-   assert(pitch % intel_image->mt->region->cpp == 0);
-   intel_image->base.RowStride = pitch / intel_image->mt->region->cpp;
+   assert(pitch % intel_image->mt->cpp == 0);
+   intel_image->base.RowStride = pitch / intel_image->mt->cpp;
 
    /* Immediately validate the image to the object. */
    intel_miptree_reference(&intel_texobj->mt, intel_image->mt);
@@ -285,8 +285,8 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
       intel_update_renderbuffers(pDRICtx, dPriv);
 
    rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
-   /* If the region isn't set, then intel_update_renderbuffers was unable
-    * to get the buffers for the drawable.
+   /* If the miptree isn't set, then intel_update_renderbuffers was unable
+    * to get the BO for the drawable from the window system.
     */
    if (!rb || !rb->mt)
       return;
@@ -308,11 +308,11 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
    _mesa_lock_texture(&brw->ctx, texObj);
    texImage = _mesa_get_tex_image(ctx, texObj, target, level);
    intel_miptree_make_shareable(brw, rb->mt);
-   intel_set_texture_image_bo(ctx, texImage, rb->mt->region->bo, target,
+   intel_set_texture_image_bo(ctx, texImage, rb->mt->bo, target,
                               internalFormat, texFormat, 0,
-                              rb->mt->region->width,
-                              rb->mt->region->height,
-                              rb->mt->region->pitch,
+                              rb->Base.Base.Width,
+                              rb->Base.Base.Height,
+                              rb->mt->pitch,
                               0, 0);
    _mesa_unlock_texture(&brw->ctx, texObj);
 }
diff --git a/src/mesa/drivers/dri/i965/intel_tex_obj.h b/src/mesa/drivers/dri/i965/intel_tex_obj.h
index 2d2211b0045..e078e0a7553 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_obj.h
+++ b/src/mesa/drivers/dri/i965/intel_tex_obj.h
@@ -44,8 +44,8 @@ struct intel_texture_object
    unsigned int validated_first_level;
    unsigned int validated_last_level;
 
-   /* On validation any active images held in main memory or in other
-    * regions will be copied to this region and the old storage freed.
+   /* The miptree of pixel data for the texture (if !needs_validate).  After
+    * validation, the images will also have references to the same mt.
     */
    struct intel_mipmap_tree *mt;
 
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 891a46d198f..5d797500e8b 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -99,7 +99,7 @@ intel_blit_texsubimage(struct gl_context * ctx,
       return false;
 
    /* Prior to Sandybridge, the blitter can't handle Y tiling */
-   if (brw->gen < 6 && intelImage->mt->region->tiling == I915_TILING_Y)
+   if (brw->gen < 6 && intelImage->mt->tiling == I915_TILING_Y)
       return false;
 
    if (texImage->TexObject->Target != GL_TEXTURE_2D)
@@ -111,7 +111,7 @@ intel_blit_texsubimage(struct gl_context * ctx,
    if (brw->gen >= 6)
       return false;
 
-   if (!drm_intel_bo_busy(intelImage->mt->region->bo))
+   if (!drm_intel_bo_busy(intelImage->mt->bo))
       return false;
 
    DBG("BLT subimage %s target %s level %d offset %d,%d %dx%d\n",
@@ -139,7 +139,7 @@ intel_blit_texsubimage(struct gl_context * ctx,
 
    if (!_mesa_texstore(ctx, 2, texImage->_BaseFormat,
 		       texImage->TexFormat,
-		       temp_mt->region->pitch,
+		       temp_mt->pitch,
 		       &dst,
 		       width, height, 1,
 		       format, type, pixels, packing)) {
@@ -596,8 +596,8 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
       ctx->Driver.AllocTextureImageBuffer(ctx, texImage);
 
    if (!image->mt ||
-       (image->mt->region->tiling != I915_TILING_X &&
-       image->mt->region->tiling != I915_TILING_Y)) {
+       (image->mt->tiling != I915_TILING_X &&
+       image->mt->tiling != I915_TILING_Y)) {
       /* The algorithm is written only for X- or Y-tiled memory. */
       return false;
    }
@@ -607,7 +607,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
     */
    intel_miptree_resolve_color(brw, image->mt);
 
-   bo = image->mt->region->bo;
+   bo = image->mt->bo;
 
    if (drm_intel_bo_references(brw->batch.bo, bo)) {
       perf_debug("Flushing before mapping a referenced bo.\n");
@@ -630,7 +630,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
        "packing=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d) "
        "for_glTexImage=%d\n",
        __FUNCTION__, texImage->Level, xoffset, yoffset, width, height,
-       format, type, texImage->TexFormat, image->mt->region->tiling,
+       format, type, texImage->TexFormat, image->mt->tiling,
        packing->Alignment, packing->RowLength, packing->SkipPixels,
        packing->SkipRows, for_glTexImage);
 
@@ -644,9 +644,9 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
       xoffset * cpp, (xoffset + width) * cpp,
       yoffset, yoffset + height,
       bo->virtual, pixels - yoffset * src_pitch - xoffset * cpp,
-      image->mt->region->pitch, src_pitch,
+      image->mt->pitch, src_pitch,
       brw->has_swizzling,
-      image->mt->region->tiling,
+      image->mt->tiling,
       mem_copy
    );