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authorEric Anholt <[email protected]>2011-01-10 14:03:39 -0800
committerEric Anholt <[email protected]>2011-01-10 17:21:11 -0800
commitbdc6dc1d7e7891ab00a2d08818093d5ecf249920 (patch)
tree5594038c20dae8cab2756d8246a2c7c700149038 /src/mesa/drivers/dri
parent48024fb44cbbccd0c688949084ef249d3c1208ab (diff)
intel: Don't relayout the texture on maxlevel change.
This avoids relayouts in the common case of glGenerateMipmap() or people doing similar things. Bug #30366.
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_validate.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index ab8aba31fe0..81795e48d9a 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -122,18 +122,17 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
/* Check tree can hold all active levels. Check tree matches
* target, imageFormat, etc.
- *
- * XXX: For some layouts (eg i945?), the test might have to be
- * first_level == firstLevel, as the tree isn't valid except at the
- * original start level. Hope to get around this by
- * programming minLod, maxLod, baseLevel into the hardware and
- * leaving the tree alone.
+ *
+ * For pre-gen4, we have to match first_level == tObj->BaseLevel,
+ * because we don't have the control that gen4 does to make min/mag
+ * determination happen at a nonzero (hardware) baselevel. Because
+ * of that, we just always relayout on baselevel change.
*/
if (intelObj->mt &&
(intelObj->mt->target != intelObj->base.Target ||
intelObj->mt->internal_format != firstImage->base.InternalFormat ||
intelObj->mt->first_level != tObj->BaseLevel ||
- intelObj->mt->last_level != intelObj->_MaxLevel ||
+ intelObj->mt->last_level < intelObj->_MaxLevel ||
intelObj->mt->width0 != firstImage->base.Width ||
intelObj->mt->height0 != firstImage->base.Height ||
intelObj->mt->depth0 != firstImage->base.Depth ||