i965: Removed the field etc_format from the struct intel_mipmap_tree

After the previous changes to emulate the ETC/EAC formats using the
secondary shadow miptree, the etc_format field of the intel_mipmap_tree
struct became redundant and the remaining check that used it has been
replaced. (Nanley Chery)

Reviewed-by: Nanley Chery <[email protected]>

3 files changed, 1 insertions, 18 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 19a46fcf243..a0984791614 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -520,7 +520,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
           * is safe because texture views aren't allowed on depth/stencil.
           */
          mesa_fmt = mt->format;
-      } else if (mt->etc_format != MESA_FORMAT_NONE) {
+      } else if (intel_miptree_has_etc_shadow(brw, mt)) {
          mesa_fmt = mt->shadow_mt->format;
       } else if (plane > 0) {
          mesa_fmt = mt->format;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7146fcb6582..426782c5883 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -706,7 +706,6 @@ miptree_create(struct brw_context *brw,
 
    if (intel_miptree_needs_fake_etc(brw, mt)) {
       mesa_format decomp_format = intel_lower_compressed_format(brw, format);
-      mt->etc_format = format;
       mt->shadow_mt = make_surface(brw, target, decomp_format, first_level,
                                    last_level, width0, height0, depth0,
                                    num_samples, tiling_flags,
@@ -717,10 +716,6 @@ miptree_create(struct brw_context *brw,
          intel_miptree_release(&mt);
          return NULL;
       }
-
-      mt->shadow_mt->etc_format = MESA_FORMAT_NONE;
-   } else {
-      mt->etc_format = MESA_FORMAT_NONE;
    }
 
    if (needs_separate_stencil(brw, mt, format)) {
@@ -1302,8 +1297,6 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
       mt_format = MESA_FORMAT_Z24_UNORM_S8_UINT;
    if (mt->format == MESA_FORMAT_Z_FLOAT32 && mt->stencil_mt)
       mt_format = MESA_FORMAT_Z32_FLOAT_S8X24_UINT;
-   if (mt->etc_format != MESA_FORMAT_NONE)
-      mt_format = mt->etc_format;
 
    if (_mesa_get_srgb_format_linear(image->TexFormat) !=
        _mesa_get_srgb_format_linear(mt_format))
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 752aeaaf9b7..3e53a0049cc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -215,21 +215,11 @@ struct intel_mipmap_tree
     * MESA_FORMAT_Z_FLOAT32, otherwise for MESA_FORMAT_Z24_UNORM_S8_UINT objects it will be
     * MESA_FORMAT_Z24_UNORM_X8_UINT.
     *
-    * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
-    * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
-    *
     * @see RENDER_SURFACE_STATE.SurfaceFormat
     * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
     */
    mesa_format format;
 
-   /**
-    * This variable stores the value of ETC compressed texture format
-    *
-    * @see RENDER_SURFACE_STATE.SurfaceFormat
-    */
-   mesa_format etc_format;
-
    GLuint first_level;
    GLuint last_level;