Merge commit 'origin/master' into gallium-sw-api-2

Conflicts:
	src/gallium/drivers/llvmpipe/lp_setup.c
	src/gallium/drivers/softpipe/sp_texture.c
	src/gallium/drivers/softpipe/sp_winsys.h
	src/gallium/state_trackers/egl/common/egl_g3d.c
	src/gallium/state_trackers/egl/x11/native_x11.c
	src/gallium/state_trackers/egl/x11/native_x11.h
	src/gallium/state_trackers/egl/x11/native_ximage.c

107 files changed, 1380 insertions, 8784 deletions

diff --git a/src/mesa/drivers/dri/i810/Makefile b/src/mesa/drivers/dri/i810/Makefile
index 3874faee518..54a837d5ea9 100644
--- a/src/mesa/drivers/dri/i810/Makefile
+++ b/src/mesa/drivers/dri/i810/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = i810_dri.so
 
-# Not yet
-# MINIGLX_SOURCES = server/i810_dri.c 
-
 DRIVER_SOURCES = \
 	i810context.c \
 	i810ioctl.c \
diff --git a/src/mesa/drivers/dri/i810/server/i810_dri.c b/src/mesa/drivers/dri/i810/server/i810_dri.c
deleted file mode 100644
index f52797c5ed2..00000000000
--- a/src/mesa/drivers/dri/i810/server/i810_dri.c
+++ /dev/null
@@ -1,975 +0,0 @@
-/**
- * \file server/i810_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- * 
- * Copyright (C) 2004 Dave Airlie ([email protected])
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-
-#include "i810.h"
-#include "i810_dri.h"
-#include "i810_reg.h"
-
-
-static int i810_pitches[] = {
-   512,
-   1024,
-   2048,
-   4096,
-   0
-};
-
-static int i810_pitch_flags[] = {
-   0x0,
-   0x1,
-   0x2,
-   0x3,
-   0
-};
-
-static unsigned int i810_drm_version = 0;
-
-static int
-I810AllocLow(I810MemRange * result, I810MemRange * pool, int size)
-{
-   if (size > pool->Size)
-      return 0;
-
-   pool->Size -= size;
-   result->Size = size;
-   result->Start = pool->Start;
-   result->End = pool->Start += size;
-
-   return 1;
-}
-
-static int
-I810AllocHigh(I810MemRange * result, I810MemRange * pool, int size)
-{
-   if (size > pool->Size)
-      return 0;
-
-   pool->Size -= size;
-   result->Size = size;
-   result->End = pool->End;
-   result->Start = pool->End -= size;
-
-   return 1;
-}
-
-
-/**
- * \brief Wait for free FIFO entries.
- *
- * \param ctx display handle.
- * \param entries number of free entries to wait.
- *
- * It polls the free entries from the chip until it reaches the requested value
- * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out.
- */
-static void I810WaitForFifo( const DRIDriverContext *ctx,
-			       int entries )
-{
-}
-
-/**
- * \brief Reset graphics card to known state.
- *
- * \param ctx display handle.
- *
- * Resets the values of several I810 registers.
- */
-static void I810EngineReset( const DRIDriverContext *ctx )
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the i810 command processor engine (i.e., the ringbuffer).
- */
-static int I810EngineRestore( const DRIDriverContext *ctx )
-{
-   I810Ptr info = ctx->driverPrivate;
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-
-   fprintf(stderr, "%s\n", __FUNCTION__);
-
-   return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int I810EngineShutdown( const DRIDriverContext *ctx )
-{
-  drmI810Init info;
-  int ret;
-
-  memset(&info, 0, sizeof(drmI810Init));
-  info.func = I810_CLEANUP_DMA;
-  
-  ret = drmCommandWrite(ctx->drmFD, DRM_I810_INIT, &info, sizeof(drmI810Init));
-  if (ret>0)
-  {
-    fprintf(stderr,"[dri] I810 DMA Cleanup failed\n");
-    return -errno;
-  }
-  return 0;
-}
-
-/**
- * \brief Compute base 2 logarithm.
- *
- * \param val value.
- * 
- * \return base 2 logarithm of \p val.
- */
-static int I810MinBits(int val)
-{
-   int  bits;
-
-   if (!val) return 1;
-   for (bits = 0; val; val >>= 1, ++bits);
-   return bits;
-}
-
-static int I810DRIAgpPreInit( const DRIDriverContext *ctx, I810Ptr info)
-{
-
-  if (drmAgpAcquire(ctx->drmFD) < 0) {
-    fprintf(stderr, "[gart] AGP not available\n");
-    return 0;
-  }
-  
-  
-  if (drmAgpEnable(ctx->drmFD, 0) < 0) {
-    fprintf(stderr, "[gart] AGP not enabled\n");
-    drmAgpRelease(ctx->drmFD);
-    return 0;
-  }
-}
-
-/**
- * \brief Initialize the AGP state
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- * 
- * Acquires and enables the AGP device. Reserves memory in the AGP space for
- * the ring buffer, vertex buffers and textures. Initialize the I810
- * registers to point to that memory and add client mappings.
- */
-static int I810DRIAgpInit( const DRIDriverContext *ctx, I810Ptr info)
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-   int            ret;
-   int            s, l;
-   unsigned long dcacheHandle;
-   unsigned long agpHandle;
-   int pitch_idx = 0;
-   int back_size = 0;
-   int sysmem_size = 0;
-   int width = ctx->shared.virtualWidth * ctx->cpp;
-
-
-   info->backHandle = DRM_AGP_NO_HANDLE;
-   info->zHandle = DRM_AGP_NO_HANDLE;
-   info->sysmemHandle = DRM_AGP_NO_HANDLE;
-   info->dcacheHandle = DRM_AGP_NO_HANDLE;
-
-   memset(&info->DcacheMem, 0, sizeof(I810MemRange));
-   memset(&info->BackBuffer, 0, sizeof(I810MemRange));
-   memset(&info->DepthBuffer, 0, sizeof(I810MemRange));
-   
-   drmAgpAlloc(ctx->drmFD, 4096 * 1024, 1, NULL, &dcacheHandle);
-   info->dcacheHandle = dcacheHandle;
-   
-   fprintf(stderr, "[agp] dcacheHandle : 0x%x\n", dcacheHandle);
-
-#define Elements(x) sizeof(x)/sizeof(*x)
-   for (pitch_idx = 0; pitch_idx < Elements(i810_pitches); pitch_idx++)
-     if (width <= i810_pitches[pitch_idx])
-       break;
-   
-   if (pitch_idx == Elements(i810_pitches)) {
-     fprintf(stderr,"[dri] Couldn't find depth/back buffer pitch\n");
-     exit(-1);
-   }
-   else
-   {
-     int lines = (ctx->shared.virtualWidth + 15) / 16 * 16;
-     back_size = i810_pitches[pitch_idx] * lines;
-     back_size = ((back_size + 4096 - 1) / 4096) * 4096;
-   }
-
-   sysmem_size = ctx->shared.fbSize;
-   fprintf(stderr,"sysmem_size is %lu back_size is %lu\n", sysmem_size, back_size);
-   if (dcacheHandle != DRM_AGP_NO_HANDLE) {
-     if (back_size > 4 * 1024 * 1024) {
-       fprintf(stderr,"[dri] Backsize is larger then 4 meg\n");
-       sysmem_size = sysmem_size - 2 * back_size;
-       drmAgpFree(ctx->drmFD, dcacheHandle);
-       info->dcacheHandle = dcacheHandle = DRM_AGP_NO_HANDLE;
-     } else {
-       sysmem_size = sysmem_size - back_size;
-     }
-   } else {
-     sysmem_size = sysmem_size - 2 * back_size;
-   }
-   
-   info->SysMem.Start=0;
-   info->SysMem.Size = sysmem_size;
-   info->SysMem.End = sysmem_size;
-   
-   if (dcacheHandle != DRM_AGP_NO_HANDLE) {
-      if (drmAgpBind(ctx->drmFD, dcacheHandle, info->DepthOffset) == 0) {
-	memset(&info->DcacheMem, 0, sizeof(I810MemRange));
-	fprintf(stderr,"[agp] GART: Found 4096K Z buffer memory\n");
-	info->DcacheMem.Start = info->DepthOffset;
-	 info->DcacheMem.Size = 1024 * 4096;
-	 info->DcacheMem.End =  info->DcacheMem.Start + info->DcacheMem.Size;
-      } else {
-	fprintf(stderr, "[agp] GART: dcache bind failed\n");
-	drmAgpFree(ctx->drmFD, dcacheHandle);
-	info->dcacheHandle = dcacheHandle = DRM_AGP_NO_HANDLE;
-      }
-   } else {
-     fprintf(stderr, "[agp] GART: no dcache memory found\n");
-   }
-   
-   drmAgpAlloc(ctx->drmFD, back_size, 0, NULL, &agpHandle);
-   info->backHandle = agpHandle;
-
-   if (agpHandle != DRM_AGP_NO_HANDLE) {
-      if (drmAgpBind(ctx->drmFD, agpHandle, info->BackOffset) == 0) {
-	fprintf(stderr, "[agp] Bound backbuffer memory\n");
-
-	info->BackBuffer.Start = info->BackOffset;
-	info->BackBuffer.Size = back_size;
-	info->BackBuffer.End = (info->BackBuffer.Start +
-				 info->BackBuffer.Size);
-      } else {
-	fprintf(stderr,"[agp] Unable to bind backbuffer.  Disabling DRI.\n");
-	return 0;
-      }
-   } else {
-     fprintf(stderr, "[dri] Unable to allocate backbuffer memory.  Disabling DRI.\n");
-     return 0;
-   }
-
-   if (dcacheHandle == DRM_AGP_NO_HANDLE) {
-     drmAgpAlloc(ctx->drmFD, back_size, 0, NULL, &agpHandle);
-
-     info->zHandle = agpHandle;
-
-     if (agpHandle != DRM_AGP_NO_HANDLE) {
-       if (drmAgpBind(ctx->drmFD, agpHandle, info->DepthOffset) == 0) {
-	 fprintf(stderr,"[agp] Bound depthbuffer memory\n");
-	 info->DepthBuffer.Start = info->DepthOffset;
-	 info->DepthBuffer.Size = back_size;
-	 info->DepthBuffer.End = (info->DepthBuffer.Start +
-				   info->DepthBuffer.Size);
-       } else {
-	 fprintf(stderr,"[agp] Unable to bind depthbuffer.  Disabling DRI.\n");
-	 return 0;
-       }
-     } else {
-       fprintf(stderr,"[agp] Unable to allocate depthbuffer memory.  Disabling DRI.\n");
-       return 0;
-     }
-   }
-
-   /* Now allocate and bind the agp space.  This memory will include the
-    * regular framebuffer as well as texture memory.
-    */
-   drmAgpAlloc(ctx->drmFD, sysmem_size, 0, NULL, &agpHandle);
-   info->sysmemHandle = agpHandle;
-   
-   if (agpHandle != DRM_AGP_NO_HANDLE) {
-     if (drmAgpBind(ctx->drmFD, agpHandle, 0) == 0) {
-       fprintf(stderr, "[agp] Bound System Texture Memory\n");
-     } else {
-       fprintf(stderr, "[agp] Unable to bind system texture memory. Disabling DRI.\n");
-       return 0;
-     }
-   } else {
-     fprintf(stderr, "[agp] Unable to allocate system texture memory. Disabling DRI.\n");
-     return 0;
-   }
-   
-   info->auxPitch = i810_pitches[pitch_idx];
-   info->auxPitchBits = i810_pitch_flags[pitch_idx];
-   
-   return 1;
-}
-
-
-/**
- * \brief Initialize the kernel data structures and enable the CP engine.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * This function is a wrapper around the DRM_I810_CP_INIT command, passing
- * all the parameters in a drmI810Init structure.
- */
-static int I810DRIKernelInit( const DRIDriverContext *ctx,
-			       I810Ptr info)
-{
-   int cpp = ctx->bpp / 8;
-   drmI810Init  drmInfo;
-   int ret;
-   I810RingBuffer *ring = &(info->LpRing);
-
-   /* This is the struct passed to the kernel module for its initialization */
-   memset(&drmInfo, 0, sizeof(drmI810Init));
-   
-   /* make sure we have at least 1.4 */
-   drmInfo.func             = I810_INIT_DMA_1_4;
-
-   drmInfo.ring_start = ring->mem.Start;
-   drmInfo.ring_end = ring->mem.End;
-   drmInfo.ring_size = ring->mem.Size;
-
-   drmInfo.mmio_offset         = (unsigned int)info->regs;
-   drmInfo.buffers_offset      = (unsigned int)info->buffer_map;
-   drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-
-   drmInfo.front_offset        = 0;
-   drmInfo.back_offset         = info->BackBuffer.Start;
-   drmInfo.depth_offset        = info->DepthBuffer.Start;
-
-   drmInfo.w                   = ctx->shared.virtualWidth;
-   drmInfo.h                   = ctx->shared.virtualHeight;
-   drmInfo.pitch               = info->auxPitch;
-   drmInfo.pitch_bits          = info->auxPitchBits;
-   
-
-   ret = drmCommandWrite(ctx->drmFD, DRM_I810_INIT, &drmInfo, 
-			 sizeof(drmI810Init));
-
-   return ret >= 0;
-}
-
-
-/**
- * \brief Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Calls drmAddBufs() with the previously allocated vertex buffers.
- */
-static int I810DRIBufInit( const DRIDriverContext *ctx, I810Ptr info )
-{
-   /* Initialize vertex buffers */
-   info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				 I810_DMA_BUF_NR,
-				 I810_DMA_BUF_SZ,
-				 DRM_AGP_BUFFER,
-				 info->BufferMem.Start);
-
-   if (info->bufNumBufs <= 0) {
-      fprintf(stderr,
-	      "[drm] Could not create vertex/indirect buffers list\n");
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] Added %d %d byte vertex/indirect buffers\n",
-	   info->bufNumBufs, I810_DMA_BUF_SZ);
-   
-   return 1;
-}
-
-/**
- * \brief Install an IRQ handler.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
- * IRQ-free operation on failure.
- */
-static void I810DRIIrqInit(const DRIDriverContext *ctx,
-			     I810Ptr info)
-{
-   if (!info->irq) {
-      info->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					   ctx->pciBus,
-					   ctx->pciDevice,
-					   ctx->pciFunc);
-
-      if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
-	 fprintf(stderr,
-		 "[drm] failure adding irq handler, "
-		 "there is a device already using that irq\n"
-		 "[drm] falling back to irq-free operation\n");
-	 info->irq = 0;
-      }
-   }
-
-   if (info->irq)
-      fprintf(stderr,
-	      "[drm] dma control initialized, using IRQ %d\n",
-	      info->irq);
-}
-
-static int I810CheckDRMVersion( const DRIDriverContext *ctx,
-				  I810Ptr info )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-   if (version) {
-      int req_minor, req_patch;
-
-      req_minor = 4;
-      req_patch = 0;	
-
-      i810_drm_version = (version->version_major<<16) | version->version_minor;
-      if (version->version_major != 1 ||
-	  version->version_minor < req_minor ||
-	  (version->version_minor == req_minor && 
-	   version->version_patchlevel < req_patch)) {
-	 /* Incompatible drm version */
-	 fprintf(stderr,
-		 "[dri] I810DRIScreenInit failed because of a version "
-		 "mismatch.\n"
-		 "[dri] i810.o kernel module version is %d.%d.%d "
-		 "but version 1.%d.%d or newer is needed.\n"
-		 "[dri] Disabling DRI.\n",
-		 version->version_major,
-		 version->version_minor,
-		 version->version_patchlevel,
-		 req_minor,
-		 req_patch);
-	 drmFreeVersion(version);
-	 return 0;
-      }
-
-      info->drmMinor = version->version_minor;
-      drmFreeVersion(version);
-   }
-
-   return 1;
-}
-
-static int I810MemoryInit( const DRIDriverContext *ctx, I810Ptr info )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        cpp         = ctx->cpp;
-   int        bufferSize  = (ctx->shared.virtualHeight * width_bytes);
-   int        depthSize   = (((ctx->shared.virtualHeight+15) & ~15) * width_bytes);
-   int        l;
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->BackBuffer.Start,
-		 info->BackBuffer.Size, DRM_AGP, 0,
-		 &info->backbuffer) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(backbuffer) failed.  Disabling DRI\n");
-     return 0;
-   }
-   
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->DepthBuffer.Start,
-		 info->DepthBuffer.Size, DRM_AGP, 0,
-		 &info->depthbuffer) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(depthbuffer) failed.  Disabling DRI.\n");
-      return 0;
-   }
-
-   if (!I810AllocLow(&(info->FrontBuffer), &(info->SysMem), (((ctx->shared.virtualHeight * width_bytes) + 4095) & ~4095)))
-   {
-     fprintf(stderr,"Framebuffer allocation failed\n");
-     return 0;
-   }
-   else
-     fprintf(stderr,"Frame buffer at 0x%.8x (%luk, %lu bytes)\n",
-	     info->FrontBuffer.Start,
-	     info->FrontBuffer.Size / 1024, info->FrontBuffer.Size);
-   
-   memset(&(info->LpRing), 0, sizeof(I810RingBuffer));
-   if (I810AllocLow(&(info->LpRing.mem), &(info->SysMem), 16 * 4096)) {
-     fprintf(stderr,
-	    "Ring buffer at 0x%.8x (%luk, %lu bytes)\n",
-	     info->LpRing.mem.Start,
-	     info->LpRing.mem.Size / 1024, info->LpRing.mem.Size);
-     
-     info->LpRing.tail_mask = info->LpRing.mem.Size - 1;
-     info->LpRing.virtual_start = info->LpRing.mem.Start;
-     info->LpRing.head = 0;
-     info->LpRing.tail = 0;
-     info->LpRing.space = 0;
-   } else {
-     fprintf(stderr, "Ring buffer allocation failed\n");
-     return (0);
-   }
-
-   /* Allocate buffer memory */
-   I810AllocHigh(&(info->BufferMem), &(info->SysMem),
-		 I810_DMA_BUF_NR * I810_DMA_BUF_SZ);
-   
-
-   fprintf(stderr, "[dri] Buffer map : %lx\n",
-	      info->BufferMem.Start);
-
-   if (info->BufferMem.Start == 0 ||
-       info->BufferMem.End - info->BufferMem.Start >
-       I810_DMA_BUF_NR * I810_DMA_BUF_SZ) {
-     fprintf(stderr,"[dri] Not enough memory for dma buffers.  Disabling DRI.\n");
-     return 0;
-   }
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->BufferMem.Start,
-		 info->BufferMem.Size, DRM_AGP, 0, &info->buffer_map) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(buffer_map) failed.  Disabling DRI.\n");
-     return 0;
-   }
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->LpRing.mem.Start,
-		 info->LpRing.mem.Size, DRM_AGP, 0, &info->ring_map) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(ring_map) failed.  Disabling DRI. \n");
-     return 0;
-   }
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   info->textureSize = info->SysMem.Size;
-
-   if (info->textureSize < 0) 
-      return 0;
-
-   
-   l = I810MinBits((info->textureSize-1) / I810_NR_TEX_REGIONS);
-   if (l < I810_LOG_MIN_TEX_REGION_SIZE) l = I810_LOG_MIN_TEX_REGION_SIZE;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   info->logTextureGranularity = l;
-   info->textureSize = (info->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (info->textureSize < 512 * 1024) {
-      info->textureOffset = 0;
-      info->textureSize = 0;
-   }
-
-   I810AllocLow(&(info->TexMem), &(info->SysMem), info->textureSize);
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->TexMem.Start,
-		 info->TexMem.Size, DRM_AGP, 0, &info->textures) < 0) {
-     fprintf(stderr,
-		 "[drm] drmAddMap(textures) failed.  Disabling DRI.\n");
-      return 0;
-   }
-
-   /* Reserve space for textures */
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   info->BackOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   info->DepthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   info->TexMem.Size/1024, info->TexMem.Start);
-
-   return 1;
-} 
-
-
-
-/**
- * Called at the start of each server generation.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Performs static frame buffer allocation. Opens the DRM device and add maps
- * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
- * information. Creates a \e server context to grab the lock for the
- * initialization ioctls and calls the other initilization functions in this
- * file. Starts the CP engine via the DRM_I810_CP_START command.
- *
- * Setups a I810DRIRec structure to be passed to i810_dri.so for its
- * initialization.
- */
-static int I810ScreenInit( DRIDriverContext *ctx, I810Ptr info )
-{
-   I810DRIPtr   pI810DRI;
-   int err;
-
-   usleep(100);
-   /*assert(!ctx->IsClient);*/
-
-   /* from XFree86 driver */
-   info->DepthOffset = 0x3000000;
-   info->BackOffset = 0x3800000;
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-
-   info->regsSize = ctx->MMIOSize;
-   ctx->shared.SAREASize = 0x2000;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("i810", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &info->regs) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08x\n", info->regs);
-
-   I810DRIAgpPreInit(ctx, info);
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-		  0,
-#else
-		  DRM_READ_ONLY,
-#endif
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-   /* Check the i810 DRM version */
-   if (!I810CheckDRMVersion(ctx, info)) {
-      return 0;
-   }
-
-   /* Initialize AGP */
-   if (!I810DRIAgpInit(ctx, info)) {
-      return 0;
-   }
-
-
-   /* Memory manager setup */
-   if (!I810MemoryInit(ctx, info)) {
-      return 0;
-   }
-
-   /* Initialize the SAREA private data structure */
-   {
-      I810SAREAPtr pSAREAPriv;
-      pSAREAPriv = (I810SAREAPtr)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-      //      pSAREAPriv->pf_enabled=1;
-   }
-
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the vertex buffers list */
-   if (!I810DRIBufInit(ctx, info)) {
-      fprintf(stderr, "I810DRIBufInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize the kernel data structures */
-   if (!I810DRIKernelInit(ctx, info)) {
-      fprintf(stderr, "I810DRIKernelInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize IRQ */
-   I810DRIIrqInit(ctx, info);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-#if 0
-   memset((char *)ctx->FBAddress,
-	  0,
-	  info->auxPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   memset((char *)info->backbuffer,
-	  0,
-	  info->auxPitch * ctx->cpp * ctx->shared.virtualHeight );
-#endif
-
-   /* This is the struct passed to i810_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(I810DRIRec));
-   ctx->driverClientMsgSize = sizeof(I810DRIRec);
-   pI810DRI                    = (I810DRIPtr)ctx->driverClientMsg;
-
-   pI810DRI->regs              = info->regs;
-   pI810DRI->regsSize          = info->regsSize;
-   // regsMap is unused
-
-   pI810DRI->backbufferSize    = info->BackBuffer.Size;
-   pI810DRI->backbuffer        = info->backbuffer;
-
-   pI810DRI->depthbufferSize   = info->DepthBuffer.Size;
-   pI810DRI->depthbuffer       = info->depthbuffer;
-
-   pI810DRI->textures          = info->textures;
-   pI810DRI->textureSize       = info->textureSize;
-
-   pI810DRI->agp_buffers       = info->buffer_map;
-   pI810DRI->agp_buf_size      = info->BufferMem.Size;
-
-   pI810DRI->deviceID          = info->Chipset;
-   pI810DRI->width             = ctx->shared.virtualWidth;
-   pI810DRI->height            = ctx->shared.virtualHeight;
-   pI810DRI->mem               = ctx->shared.fbSize;
-   pI810DRI->cpp               = ctx->bpp / 8;
-   pI810DRI->bitsPerPixel      = ctx->bpp;
-   pI810DRI->fbOffset          = info->FrontBuffer.Start;
-   pI810DRI->fbStride          = info->auxPitch;
-   
-   pI810DRI->backOffset        = info->BackBuffer.Start;
-   pI810DRI->depthOffset       = info->DepthBuffer.Start;
-
-   pI810DRI->auxPitch          = info->auxPitch;
-   pI810DRI->auxPitchBits      = info->auxPitchBits;
-
-   pI810DRI->logTextureGranularity = info->logTextureGranularity;
-   pI810DRI->textureOffset     = info->TexMem.Start;
-  
-   pI810DRI->ringOffset        = info->LpRing.mem.Start;
-   pI810DRI->ringSize          = info->LpRing.mem.Size;
-
-   // drmBufs looks unused 
-   pI810DRI->irq               = info->irq;
-   pI810DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   /* Don't release the lock now - let the VT switch handler do it. */
-   return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i810ValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-   I810Ptr info = ctx->driverPrivate;
-
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i810PostValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-   I810Ptr info = ctx->driverPrivate;
-
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls I810ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int i810InitFBDev( DRIDriverContext *ctx )
-{
-  I810Ptr info = calloc(1, sizeof(*info));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)info;
-   
-   info->Chipset = ctx->chipset;
-
-   if (!I810ScreenInit( ctx, info ))
-      return 0;
-
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void i810HaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-extern void i810NotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   i810ValidateMode,
-   i810PostValidateMode,
-   i810InitFBDev,
-   i810HaltFBDev,
-   I810EngineShutdown,
-   I810EngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   i810NotifyFocus, 
-#endif
-};
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index dc15ae425c9..5b49d0c77c6 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -4,8 +4,6 @@ include $(TOP)/configs/current
 
 LIBNAME = i915_dri.so
 
-MINIGLX_SOURCES = server/intel_dri.c
-
 DRIVER_SOURCES = \
 	i830_context.c \
 	i830_state.c \
diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h
index b755d48678b..d7eb9c2d44b 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -34,7 +34,8 @@
 #define I830_FALLBACK_COLORMASK		 0x2000
 #define I830_FALLBACK_STENCIL		 0x4000
 #define I830_FALLBACK_STIPPLE		 0x8000
-#define I830_FALLBACK_LOGICOP		 0x10000
+#define I830_FALLBACK_LOGICOP		 0x20000
+#define I830_FALLBACK_DRAW_OFFSET	 0x200000
 
 #define I830_UPLOAD_CTX              0x1
 #define I830_UPLOAD_BUFFERS          0x2
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index 7525f9f2e05..e8f7e378ec7 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -122,6 +122,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
    GLuint *state = i830->state.Tex[unit], format, pitch;
    GLint lodbias;
    GLubyte border[4];
+   GLuint dst_x, dst_y;
 
    memset(state, 0, sizeof(state));
 
@@ -132,7 +133,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
        i830->state.tex_buffer[unit] = NULL;
    }
 
-   if (!intelObj->imageOverride && !intel_finalize_mipmap_tree(intel, unit))
+   if (!intel_finalize_mipmap_tree(intel, unit))
       return GL_FALSE;
 
    /* Get first image here, since intelObj->firstLevel will get set in
@@ -140,42 +141,20 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
     */
    firstImage = tObj->Image[0][intelObj->firstLevel];
 
-   if (intelObj->imageOverride) {
-      i830->state.tex_buffer[unit] = NULL;
-      i830->state.tex_offset[unit] = intelObj->textureOffset;
+   intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0,
+				  &dst_x, &dst_y);
 
-      switch (intelObj->depthOverride) {
-      case 32:
-	 format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
-	 break;
-      case 24:
-      default:
-	 format = MAPSURF_32BIT | MT_32BIT_XRGB8888;
-	 break;
-      case 16:
-	 format = MAPSURF_16BIT | MT_16BIT_RGB565;
-	 break;
-      }
-
-      pitch = intelObj->pitchOverride;
-   } else {
-      GLuint dst_x, dst_y;
-
-      intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0,
-				     &dst_x, &dst_y);
-
-      dri_bo_reference(intelObj->mt->region->buffer);
-      i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
-      /* XXX: This calculation is probably broken for tiled images with
-       * a non-page-aligned offset.
-       */
-      i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) *
-	 intelObj->mt->cpp;
+   dri_bo_reference(intelObj->mt->region->buffer);
+   i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
+   /* XXX: This calculation is probably broken for tiled images with
+    * a non-page-aligned offset.
+    */
+   i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) *
+      intelObj->mt->cpp;
 
-      format = translate_texture_format(firstImage->TexFormat,
-					firstImage->InternalFormat);
-      pitch = intelObj->mt->pitch * intelObj->mt->cpp;
-   }
+   format = translate_texture_format(firstImage->TexFormat,
+				     firstImage->InternalFormat);
+   pitch = intelObj->mt->pitch * intelObj->mt->cpp;
 
    state[I830_TEXREG_TM0LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
                                (LOAD_TEXTURE_MAP0 << unit) | 4);
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index a8df77c600e..be96419ff19 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -496,15 +496,13 @@ i830_emit_state(struct intel_context *intel)
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
-		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                state->draw_region->draw_offset);
+		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 
       if (state->depth_region) {
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
          OUT_RELOC(state->depth_region->buffer,
-		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                   state->depth_region->draw_offset);
+		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
       }
 
       OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
@@ -598,6 +596,7 @@ i830_set_draw_region(struct intel_context *intel,
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    GLuint value;
    struct i830_hw_state *state = &i830->state;
+   uint32_t draw_x, draw_y;
 
    if (state->draw_region != color_regions[0]) {
       intel_region_release(&state->draw_region);
@@ -652,14 +651,40 @@ i830_set_draw_region(struct intel_context *intel,
    }
    state->Buffer[I830_DESTREG_DV1] = value;
 
+   /* We set up the drawing rectangle to be offset into the color
+    * region's location in the miptree.  If it doesn't match with
+    * depth's offsets, we can't render to it.
+    *
+    * (Well, not actually true -- the hw grew a bit to let depth's
+    * offset get forced to 0,0.  We may want to use that if people are
+    * hitting that case.  Also, some configurations may be supportable
+    * by tweaking the start offset of the buffers around, which we
+    * can't do in general due to tiling)
+    */
+   FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
+	    (depth_region && color_regions[0]) &&
+	    (depth_region->draw_x != color_regions[0]->draw_x ||
+	     depth_region->draw_y != color_regions[0]->draw_y));
+
+   if (color_regions[0]) {
+      draw_x = color_regions[0]->draw_x;
+      draw_y = color_regions[0]->draw_y;
+   } else if (depth_region) {
+      draw_x = depth_region->draw_x;
+      draw_y = depth_region->draw_y;
+   } else {
+      draw_x = 0;
+      draw_y = 0;
+   }
+
    state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
    state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
-   state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+   state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
    state->Buffer[I830_DESTREG_DRAWRECT3] =
-      (ctx->DrawBuffer->Width & 0xffff) |
-      (ctx->DrawBuffer->Height << 16);
-   state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
-   state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
+      ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
+      ((ctx->DrawBuffer->Height + draw_y) << 16);
+   state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
+   state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
 
    I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
 }
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 3ee4c8653a9..a1ab8f8b6d2 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -150,7 +150,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
        i915->state.tex_buffer[unit] = NULL;
    }
 
-   if (!intelObj->imageOverride && !intel_finalize_mipmap_tree(intel, unit))
+   if (!intel_finalize_mipmap_tree(intel, unit))
       return GL_FALSE;
 
    /* Get first image here, since intelObj->firstLevel will get set in
@@ -158,34 +158,14 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
     */
    firstImage = tObj->Image[0][intelObj->firstLevel];
 
-   if (intelObj->imageOverride) {
-      i915->state.tex_buffer[unit] = NULL;
-      i915->state.tex_offset[unit] = intelObj->textureOffset;
+   dri_bo_reference(intelObj->mt->region->buffer);
+   i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
+   i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */
 
-      switch (intelObj->depthOverride) {
-      case 32:
-	 format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
-	 break;
-      case 24:
-      default:
-	 format = MAPSURF_32BIT | MT_32BIT_XRGB8888;
-	 break;
-      case 16:
-	 format = MAPSURF_16BIT | MT_16BIT_RGB565;
-	 break;
-      }
-
-      pitch = intelObj->pitchOverride;
-   } else {
-      dri_bo_reference(intelObj->mt->region->buffer);
-      i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
-      i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */
-
-      format = translate_texture_format(firstImage->TexFormat,
-					firstImage->InternalFormat,
-					tObj->DepthMode);
-      pitch = intelObj->mt->pitch * intelObj->mt->cpp;
-   }
+   format = translate_texture_format(firstImage->TexFormat,
+				     firstImage->InternalFormat,
+				     tObj->DepthMode);
+   pitch = intelObj->mt->pitch * intelObj->mt->cpp;
 
    state[I915_TEXREG_MS3] =
       (((firstImage->Height - 1) << MS3_HEIGHT_SHIFT) |
diff --git a/src/mesa/drivers/dri/i915/server/intel_dri.c b/src/mesa/drivers/dri/i915/server/intel_dri.c
deleted file mode 120000
index effdd26448a..00000000000
--- a/src/mesa/drivers/dri/i915/server/intel_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../intel/server/intel_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index f98a1a27db2..a242580273f 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -99,7 +99,6 @@ DRIVER_SOURCES = \
 
 C_SOURCES = \
 	$(COMMON_SOURCES) \
-	$(MINIGLX_SOURCES) \
 	$(DRIVER_SOURCES)
 
 ASM_SOURCES = 
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 6f2ead793d2..4e78b08cfed 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -179,7 +179,6 @@ static GLfloat fixed_plane[6][4] = {
  */
 static void prepare_constant_buffer(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    GLcontext *ctx = &brw->intel.ctx;
    const struct brw_vertex_program *vp =
       brw_vertex_program_const(brw->vertex_program);
@@ -307,7 +306,7 @@ static void prepare_constant_buffer(struct brw_context *brw)
       if (brw->curbe.curbe_bo != NULL &&
 	  brw->curbe.curbe_next_offset + bufsz > brw->curbe.curbe_bo->size)
       {
-	 intel_bo_unmap_gtt_preferred(intel, brw->curbe.curbe_bo);
+	 drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
 	 dri_bo_unreference(brw->curbe.curbe_bo);
 	 brw->curbe.curbe_bo = NULL;
       }
@@ -319,7 +318,7 @@ static void prepare_constant_buffer(struct brw_context *brw)
 	 brw->curbe.curbe_bo = dri_bo_alloc(brw->intel.bufmgr, "CURBE",
 					    4096, 1 << 6);
 	 brw->curbe.curbe_next_offset = 0;
-	 intel_bo_map_gtt_preferred(intel, brw->curbe.curbe_bo, GL_TRUE);
+	 drm_intel_gem_bo_map_gtt(brw->curbe.curbe_bo);
       }
 
       brw->curbe.curbe_offset = brw->curbe.curbe_next_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f0a4e8ad65d..71a43577bfd 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -276,7 +276,6 @@ copy_array_to_vbo_array( struct brw_context *brw,
 			 struct brw_vertex_element *element,
 			 GLuint dst_stride)
 {
-   struct intel_context *intel = &brw->intel;
    GLuint size = element->count * dst_stride;
 
    get_space(brw, size, &element->bo, &element->offset);
@@ -289,52 +288,26 @@ copy_array_to_vbo_array( struct brw_context *brw,
    }
 
    if (dst_stride == element->glarray->StrideB) {
-      if (intel->intelScreen->kernel_exec_fencing) {
-	 drm_intel_gem_bo_map_gtt(element->bo);
-	 memcpy((char *)element->bo->virtual + element->offset,
-		element->glarray->Ptr, size);
-	 drm_intel_gem_bo_unmap_gtt(element->bo);
-      } else {
-	 dri_bo_subdata(element->bo,
-			element->offset,
-			size,
-			element->glarray->Ptr);
-      }
+      drm_intel_gem_bo_map_gtt(element->bo);
+      memcpy((char *)element->bo->virtual + element->offset,
+	     element->glarray->Ptr, size);
+      drm_intel_gem_bo_unmap_gtt(element->bo);
    } else {
       char *dest;
       const unsigned char *src = element->glarray->Ptr;
       int i;
 
-      if (intel->intelScreen->kernel_exec_fencing) {
-	 drm_intel_gem_bo_map_gtt(element->bo);
-	 dest = element->bo->virtual;
-	 dest += element->offset;
-
-	 for (i = 0; i < element->count; i++) {
-	    memcpy(dest, src, dst_stride);
-	    src += element->glarray->StrideB;
-	    dest += dst_stride;
-	 }
-
-	 drm_intel_gem_bo_unmap_gtt(element->bo);
-      } else {
-	 void *data;
-
-	 data = malloc(dst_stride * element->count);
-	 dest = data;
-	 for (i = 0; i < element->count; i++) {
-	    memcpy(dest, src, dst_stride);
-	    src += element->glarray->StrideB;
-	    dest += dst_stride;
-	 }
-
-	 dri_bo_subdata(element->bo,
-			element->offset,
-			size,
-			data);
+      drm_intel_gem_bo_map_gtt(element->bo);
+      dest = element->bo->virtual;
+      dest += element->offset;
 
-	 free(data);
+      for (i = 0; i < element->count; i++) {
+	 memcpy(dest, src, dst_stride);
+	 src += element->glarray->StrideB;
+	 dest += dst_stride;
       }
+
+      drm_intel_gem_bo_unmap_gtt(element->bo);
    }
 }
 
@@ -646,13 +619,9 @@ static void brw_prepare_indices(struct brw_context *brw)
 
       /* Straight upload
        */
-      if (intel->intelScreen->kernel_exec_fencing) {
-	 drm_intel_gem_bo_map_gtt(bo);
-	 memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size);
-	 drm_intel_gem_bo_unmap_gtt(bo);
-      } else {
-	 dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr);
-      }
+      drm_intel_gem_bo_map_gtt(bo);
+      memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size);
+      drm_intel_gem_bo_unmap_gtt(bo);
    } else {
       offset = (GLuint) (unsigned long) index_buffer->ptr;
       brw->ib.start_vertex_offset = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index 8e6839b8120..57d1c29ade1 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -46,7 +46,6 @@
 static void compile_sf_prog( struct brw_context *brw,
 			     struct brw_sf_prog_key *key )
 {
-   GLcontext *ctx = &brw->intel.ctx;
    struct brw_sf_compile c;
    const GLuint *program;
    GLuint program_size;
@@ -69,20 +68,14 @@ static void compile_sf_prog( struct brw_context *brw,
 
    /* Construct map from attribute number to position in the vertex.
     */
-   for (i = idx = 0; i < VERT_RESULT_MAX; i++) 
+   for (i = idx = 0; i < VERT_RESULT_MAX; i++) {
       if (c.key.attrs & BITFIELD64_BIT(i)) {
 	 c.attr_to_idx[i] = idx;
 	 c.idx_to_attr[idx] = i;
-	 if (i >= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) {
-            c.point_attrs[i].CoordReplace = 
-               ctx->Point.CoordReplace[i - VERT_RESULT_TEX0];
-	 }
-         else {
-            c.point_attrs[i].CoordReplace = GL_FALSE;
-         }
 	 idx++;
       }
-   
+   }
+
    /* Which primitive?  Or all three? 
     */
    switch (key->primitive) {
@@ -162,6 +155,14 @@ static void upload_sf_prog(struct brw_context *brw)
    }
 
    key.do_point_sprite = ctx->Point.PointSprite;
+   if (key.do_point_sprite) {
+      int i;
+
+      for (i = 0; i < 8; i++) {
+	 if (ctx->Point.CoordReplace[i])
+	    key.point_sprite_coord_replace |= (1 << i);
+      }
+   }
    key.sprite_origin_lower_left = (ctx->Point.SpriteOrigin == GL_LOWER_LEFT);
    /* _NEW_LIGHT */
    key.do_flat_shading = (ctx->Light.ShadeModel == GL_FLAT);
diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h
index 0ba731fac99..a0680a56f2c 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -46,6 +46,7 @@
 
 struct brw_sf_prog_key {
    GLbitfield64 attrs;
+   uint8_t point_sprite_coord_replace;
    GLuint primitive:2;
    GLuint do_twoside_color:1;
    GLuint do_flat_shading:1;
@@ -56,10 +57,6 @@ struct brw_sf_prog_key {
    GLuint pad:24;
 };
 
-struct brw_sf_point_tex {
-   GLboolean CoordReplace;	
-};
-
 struct brw_sf_compile {
    struct brw_compile func;
    struct brw_sf_prog_key key;
@@ -100,7 +97,6 @@ struct brw_sf_compile {
 
    GLubyte attr_to_idx[VERT_RESULT_MAX];   
    GLubyte idx_to_attr[VERT_RESULT_MAX];   
-   struct brw_sf_point_tex point_attrs[VERT_RESULT_MAX];
 };
 
  
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index bb08055e3bb..56f7c986e78 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -354,6 +354,33 @@ static GLboolean calculate_masks( struct brw_sf_compile *c,
    return is_last_attr;
 }
 
+/* Calculates the predicate control for which channels of a reg
+ * (containing 2 attrs) to do point sprite coordinate replacement on.
+ */
+static uint16_t
+calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg)
+{
+   int attr1, attr2;
+   uint16_t pc = 0;
+
+   attr1 = c->idx_to_attr[reg * 2];
+   if (attr1 >= VERT_RESULT_TEX0 && attr1 <= VERT_RESULT_TEX7) {
+      if (c->key.point_sprite_coord_replace & (1 << (attr1 - VERT_RESULT_TEX0)))
+	 pc |= 0x0f;
+   }
+
+   if (reg * 2 + 1 < c->nr_setup_attrs) {
+       attr2 = c->idx_to_attr[reg * 2 + 1];
+       if (attr2 >= VERT_RESULT_TEX0 && attr2 <= VERT_RESULT_TEX7) {
+	  if (c->key.point_sprite_coord_replace & (1 << (attr2 -
+							 VERT_RESULT_TEX0)))
+	     pc |= 0xf0;
+       }
+   }
+
+   return pc;
+}
+
 
 
 void brw_emit_tri_setup( struct brw_sf_compile *c, GLboolean allocate)
@@ -529,22 +556,27 @@ void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate)
    copy_z_inv_w(c);
    for (i = 0; i < c->nr_setup_regs; i++)
    {
-      struct brw_sf_point_tex *tex = &c->point_attrs[c->idx_to_attr[2*i]];
       struct brw_reg a0 = offset(c->vert[0], i);
-      GLushort pc, pc_persp, pc_linear;
+      GLushort pc, pc_persp, pc_linear, pc_coord_replace;
       GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
-            
-      if (pc_persp)
-      {				
-	  if (!tex->CoordReplace) {
-	      brw_set_predicate_control_flag_value(p, pc_persp);
-	      brw_MUL(p, a0, a0, c->inv_w[0]);
-	  }
+
+      pc_coord_replace = calculate_point_sprite_mask(c, i);
+      pc_persp &= ~pc_coord_replace;
+
+      if (pc_persp) {
+	 brw_set_predicate_control_flag_value(p, pc_persp);
+	 brw_MUL(p, a0, a0, c->inv_w[0]);
       }
 
-      if (tex->CoordReplace) {
-	  /* Caculate 1.0/PointWidth */
-	  brw_math(&c->func,
+      /* Point sprite coordinate replacement: A texcoord with this
+       * enabled gets replaced with the value (x, y, 0, 1) where x and
+       * y vary from 0 to 1 across the horizontal and vertical of the
+       * point.
+       */
+      if (pc_coord_replace) {
+	 brw_set_predicate_control_flag_value(p, pc_coord_replace);
+	 /* Caculate 1.0/PointWidth */
+	 brw_math(&c->func,
 		  c->tmp,
 		  BRW_MATH_FUNCTION_INV,
 		  BRW_MATH_SATURATE_NONE,
@@ -553,50 +585,51 @@ void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate)
 		  BRW_MATH_DATA_SCALAR,
 		  BRW_MATH_PRECISION_FULL);
 
-	  if (c->key.sprite_origin_lower_left) {
-	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
-		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
-	  	brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0]));
-		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
-	  } else {
-	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
-		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
-	  	brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]);
-		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
-	  }
-      } else {
-	  brw_MOV(p, c->m1Cx, brw_imm_ud(0));
-	  brw_MOV(p, c->m2Cy, brw_imm_ud(0));
-      }
+	 brw_set_access_mode(p, BRW_ALIGN_16);
 
-      {
-	 brw_set_predicate_control_flag_value(p, pc); 
-	 if (tex->CoordReplace) {
-	     if (c->key.sprite_origin_lower_left) {
-		 brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0));
-		 brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0));
-	     }
-	     else
-		 brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+	 /* dA/dx, dA/dy */
+	 brw_MOV(p, c->m1Cx, brw_imm_f(0.0));
+	 brw_MOV(p, c->m2Cy, brw_imm_f(0.0));
+	 brw_MOV(p, brw_writemask(c->m1Cx, WRITEMASK_X), c->tmp);
+	 if (c->key.sprite_origin_lower_left) {
+	    brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), negate(c->tmp));
 	 } else {
-	 	brw_MOV(p, c->m3C0, a0); /* constant value */
+	    brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), c->tmp);
 	 }
 
-	 /* Copy m0..m3 to URB. 
-	  */
-	 brw_urb_WRITE(p, 
-		       brw_null_reg(),
-		       0,
-		       brw_vec8_grf(0, 0),
-		       0, 	/* allocate */
-		       1,	/* used */
-		       4, 	/* msg len */
-		       0,	/* response len */
-		       last, 	/* eot */
-		       last, 	/* writes complete */
-		       i*4,	/* urb destination offset */
-		       BRW_URB_SWIZZLE_TRANSPOSE);
+	 /* attribute constant offset */
+	 brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+	 if (c->key.sprite_origin_lower_left) {
+	    brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_YW), brw_imm_f(1.0));
+	 } else {
+	    brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_W), brw_imm_f(1.0));
+	 }
+
+	 brw_set_access_mode(p, BRW_ALIGN_1);
       }
+
+      if (pc & ~pc_coord_replace) {
+	 brw_set_predicate_control_flag_value(p, pc & ~pc_coord_replace);
+	 brw_MOV(p, c->m1Cx, brw_imm_ud(0));
+	 brw_MOV(p, c->m2Cy, brw_imm_ud(0));
+	 brw_MOV(p, c->m3C0, a0); /* constant value */
+      }
+
+
+      brw_set_predicate_control_flag_value(p, pc);
+      /* Copy m0..m3 to URB. */
+      brw_urb_WRITE(p,
+		    brw_null_reg(),
+		    0,
+		    brw_vec8_grf(0, 0),
+		    0, 	/* allocate */
+		    1,	/* used */
+		    4, 	/* msg len */
+		    0,	/* response len */
+		    last, 	/* eot */
+		    last, 	/* writes complete */
+		    i*4,	/* urb destination offset */
+		    BRW_URB_SWIZZLE_TRANSPOSE);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index ead623fc0ea..4007b5a15ce 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -67,13 +67,13 @@ brw_vs_update_constant_buffer(struct brw_context *brw)
     */
    _mesa_load_state_parameters(&brw->intel.ctx, vp->program.Base.Parameters);
 
-   intel_bo_map_gtt_preferred(intel, const_buffer, GL_TRUE);
+   drm_intel_gem_bo_map_gtt(const_buffer);
    for (i = 0; i < params->NumParameters; i++) {
       memcpy(const_buffer->virtual + i * 4 * sizeof(float),
 	     params->ParameterValues[i],
 	     4 * sizeof(float));
    }
-   intel_bo_unmap_gtt_preferred(intel, const_buffer);
+   drm_intel_gem_bo_unmap_gtt(const_buffer);
 
    return const_buffer;
 }
@@ -104,7 +104,7 @@ brw_update_vs_constant_surface( GLcontext *ctx,
    /* If there's no constant buffer, then no surface BO is needed to point at
     * it.
     */
-   if (vp->const_buffer == 0) {
+   if (vp->const_buffer == NULL) {
       drm_intel_bo_unreference(brw->vs.surf_bo[surf]);
       brw->vs.surf_bo[surf] = NULL;
       return;
@@ -132,7 +132,7 @@ brw_update_vs_constant_surface( GLcontext *ctx,
    brw->vs.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
                                             BRW_SS_SURFACE,
                                             &key, sizeof(key),
-                                            &key.bo, key.bo ? 1 : 0,
+                                            &key.bo, 1,
                                             NULL);
    if (brw->vs.surf_bo[surf] == NULL) {
       brw->vs.surf_bo[surf] = brw_create_constant_surface(brw, &key);
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 27a2a3e8a7e..96a44bfbec7 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -144,7 +144,7 @@ static void brw_finish_batch(struct intel_context *intel)
    brw_emit_query_end(brw);
 
    if (brw->curbe.curbe_bo) {
-      intel_bo_unmap_gtt_preferred(intel, brw->curbe.curbe_bo);
+      drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
       drm_intel_bo_unreference(brw->curbe.curbe_bo);
       brw->curbe.curbe_bo = NULL;
    }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index c232cd27914..d7650af3d9d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -89,7 +89,6 @@ struct wm_sampler_key {
       float max_aniso;
       GLenum minfilter, magfilter;
       GLenum comparemode, comparefunc;
-      dri_bo *sdc_bo;
 
       /** If target is cubemap, take context setting.
        */
@@ -230,7 +229,7 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
    GLcontext *ctx = &brw->intel.ctx;
    int unit;
 
-   memset(key, 0, sizeof(*key));
+   key->sampler_count = 0;
 
    for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
       if (ctx->Texture.Unit[unit]._ReallyEnabled) {
@@ -241,6 +240,8 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
 	 struct gl_texture_image *firstImage =
 	    texObj->Image[0][intelObj->firstLevel];
 
+	 memset(entry, 0, sizeof(*entry));
+
          entry->tex_target = texObj->Target;
 
 	 entry->seamless_cube_map = (texObj->Target == GL_TEXTURE_CUBE_MAP)
@@ -289,7 +290,7 @@ static void upload_wm_samplers( struct brw_context *brw )
 {
    GLcontext *ctx = &brw->intel.ctx;
    struct wm_sampler_key key;
-   int i;
+   int i, sampler_key_size;
 
    brw_wm_sampler_populate_key(brw, &key);
 
@@ -303,8 +304,11 @@ static void upload_wm_samplers( struct brw_context *brw )
    if (brw->wm.sampler_count == 0)
       return;
 
+   /* Only include the populated portion of the key in the search. */
+   sampler_key_size = offsetof(struct wm_sampler_key,
+			       sampler[key.sampler_count]);
    brw->wm.sampler_bo = brw_search_cache(&brw->cache, BRW_SAMPLER,
-					 &key, sizeof(key),
+					 &key, sampler_key_size,
 					 brw->wm.sdc_bo, key.sampler_count,
 					 NULL);
 
@@ -324,7 +328,7 @@ static void upload_wm_samplers( struct brw_context *brw )
       }
 
       brw->wm.sampler_bo = brw_upload_cache(&brw->cache, BRW_SAMPLER,
-					    &key, sizeof(key),
+					    &key, sampler_key_size,
 					    brw->wm.sdc_bo, key.sampler_count,
 					    &sampler, sizeof(sampler));
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a42067611ce..ce0bf0b97d2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -207,33 +207,14 @@ brw_create_texture_surface( struct brw_context *brw,
 
    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
    surf.ss0.surface_type = translate_tex_target(key->target);
-   if (key->bo) {
-      surf.ss0.surface_format = translate_tex_format(key->format,
-						     key->internal_format,
-						     key->depthmode);
-   }
-   else {
-      switch (key->depth) {
-      case 32:
-         surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-         break;
-      default:
-      case 24:
-         surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
-         break;
-      case 16:
-         surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
-         break;
-      }
-   }
+   surf.ss0.surface_format = translate_tex_format(key->format,
+						  key->internal_format,
+						  key->depthmode);
 
    /* This is ok for all textures with channel width 8bit or less:
     */
 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
-   if (key->bo)
-      surf.ss1.base_addr = key->bo->offset; /* reloc */
-   else
-      surf.ss1.base_addr = key->offset;
+   surf.ss1.base_addr = key->bo->offset; /* reloc */
 
    surf.ss2.mip_count = key->last_level - key->first_level;
    surf.ss2.width = key->width - 1;
@@ -255,17 +236,14 @@ brw_create_texture_surface( struct brw_context *brw,
 
    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 			 key, sizeof(*key),
-			 &key->bo, key->bo ? 1 : 0,
+			 &key->bo, 1,
 			 &surf, sizeof(surf));
 
-   if (key->bo) {
-      /* Emit relocation to surface contents */
-      dri_bo_emit_reloc(bo,
-			I915_GEM_DOMAIN_SAMPLER, 0,
-			0,
-			offsetof(struct brw_surface_state, ss1),
-			key->bo);
-   }
+   /* Emit relocation to surface contents */
+   drm_intel_bo_emit_reloc(bo, offsetof(struct brw_surface_state, ss1),
+			   key->bo, 0,
+			   I915_GEM_DOMAIN_SAMPLER, 0);
+
    return bo;
 }
 
@@ -281,19 +259,12 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 
    memset(&key, 0, sizeof(key));
 
-   if (intelObj->imageOverride) {
-      key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
-      key.depth = intelObj->depthOverride;
-      key.bo = NULL;
-      key.offset = intelObj->textureOffset;
-   } else {
-      key.format = firstImage->TexFormat;
-      key.internal_format = firstImage->InternalFormat;
-      key.pitch = intelObj->mt->pitch;
-      key.depth = firstImage->Depth;
-      key.bo = intelObj->mt->region->buffer;
-      key.offset = 0;
-   }
+   key.format = firstImage->TexFormat;
+   key.internal_format = firstImage->InternalFormat;
+   key.pitch = intelObj->mt->pitch;
+   key.depth = firstImage->Depth;
+   key.bo = intelObj->mt->region->buffer;
+   key.offset = 0;
 
    key.target = tObj->Target;
    key.depthmode = tObj->DepthMode;
@@ -308,7 +279,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
                                             BRW_SS_SURFACE,
                                             &key, sizeof(key),
-                                            &key.bo, key.bo ? 1 : 0,
+                                            &key.bo, 1,
                                             NULL);
    if (brw->wm.surf_bo[surf] == NULL) {
       brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
@@ -336,10 +307,7 @@ brw_create_constant_surface( struct brw_context *brw,
    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 
    assert(key->bo);
-   if (key->bo)
-      surf.ss1.base_addr = key->bo->offset; /* reloc */
-   else
-      surf.ss1.base_addr = key->offset;
+   surf.ss1.base_addr = key->bo->offset; /* reloc */
 
    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
@@ -349,20 +317,16 @@ brw_create_constant_surface( struct brw_context *brw,
  
    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 			 key, sizeof(*key),
-			 &key->bo, key->bo ? 1 : 0,
+			 &key->bo, 1,
 			 &surf, sizeof(surf));
 
-   if (key->bo) {
-      /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
-       * bspec ("Data Cache") says that the data cache does not exist as
-       * a separate cache and is just the sampler cache.
-       */
-      dri_bo_emit_reloc(bo,
-			I915_GEM_DOMAIN_SAMPLER, 0,
-			0,
-			offsetof(struct brw_surface_state, ss1),
-			key->bo);
-   }
+   /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
+    * bspec ("Data Cache") says that the data cache does not exist as
+    * a separate cache and is just the sampler cache.
+    */
+   drm_intel_bo_emit_reloc(bo, offsetof(struct brw_surface_state, ss1),
+			   key->bo, 0,
+			   I915_GEM_DOMAIN_SAMPLER, 0);
 
    return bo;
 }
@@ -420,7 +384,7 @@ brw_update_wm_constant_surface( GLcontext *ctx,
    /* If there's no constant buffer, then no surface BO is needed to point at
     * it.
     */
-   if (fp->const_buffer == 0) {
+   if (fp->const_buffer == NULL) {
       drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
       brw->wm.surf_bo[surf] = NULL;
       return;
@@ -448,7 +412,7 @@ brw_update_wm_constant_surface( GLcontext *ctx,
    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
                                             BRW_SS_SURFACE,
                                             &key, sizeof(key),
-                                            &key.bo, key.bo ? 1 : 0,
+                                            &key.bo, 1,
                                             NULL);
    if (brw->wm.surf_bo[surf] == NULL) {
       brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 42b41f3210c..f7acad69129 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -32,8 +32,9 @@
 #include "intel_batchbuffer.h"
 #include "main/macros.h"
 
-struct brw_blend_state_key {
+struct gen6_blend_state_key {
    GLboolean color_blend, alpha_enabled;
+   GLboolean dither;
 
    GLenum logic_op;
 
@@ -42,13 +43,11 @@ struct brw_blend_state_key {
    GLenum blend_dst_rgb, blend_dst_a;
 
    GLenum alpha_func;
-
-   GLboolean dither;
 };
 
 static void
 blend_state_populate_key(struct brw_context *brw,
-			 struct brw_blend_state_key *key)
+			 struct gen6_blend_state_key *key)
 {
    GLcontext *ctx = &brw->intel.ctx;
 
@@ -86,7 +85,7 @@ blend_state_populate_key(struct brw_context *brw,
  */
 static drm_intel_bo *
 blend_state_create_from_key(struct brw_context *brw,
-			    struct brw_blend_state_key *key)
+			    struct gen6_blend_state_key *key)
 {
    struct gen6_blend_state blend;
    drm_intel_bo *bo;
@@ -149,7 +148,7 @@ blend_state_create_from_key(struct brw_context *brw,
 static void
 prepare_blend_state(struct brw_context *brw)
 {
-   struct brw_blend_state_key key;
+   struct gen6_blend_state_key key;
 
    blend_state_populate_key(brw, &key);
 
@@ -172,7 +171,7 @@ const struct brw_tracked_state gen6_blend_state = {
    .prepare = prepare_blend_state,
 };
 
-struct brw_color_calc_state_key {
+struct gen6_color_calc_state_key {
    GLubyte blend_constant_color[4];
    GLclampf alpha_ref;
    GLubyte stencil_ref[2];
@@ -180,7 +179,7 @@ struct brw_color_calc_state_key {
 
 static void
 color_calc_state_populate_key(struct brw_context *brw,
-			      struct brw_color_calc_state_key *key)
+			      struct gen6_color_calc_state_key *key)
 {
    GLcontext *ctx = &brw->intel.ctx;
 
@@ -210,7 +209,7 @@ color_calc_state_populate_key(struct brw_context *brw,
  */
 static drm_intel_bo *
 color_calc_state_create_from_key(struct brw_context *brw,
-				 struct brw_color_calc_state_key *key)
+				 struct gen6_color_calc_state_key *key)
 {
    struct gen6_color_calc_state cc;
    drm_intel_bo *bo;
@@ -239,7 +238,7 @@ color_calc_state_create_from_key(struct brw_context *brw,
 static void
 prepare_color_calc_state(struct brw_context *brw)
 {
-   struct brw_color_calc_state_key key;
+   struct gen6_color_calc_state_key key;
 
    color_calc_state_populate_key(brw, &key);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 08e6753a910..8d96b44f1dc 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -32,6 +32,25 @@
 #include "main/macros.h"
 #include "intel_batchbuffer.h"
 
+static uint32_t
+get_attr_override(struct brw_context *brw, int attr)
+{
+   uint32_t attr_override;
+   int attr_index = 0, i;
+
+   /* Find the source index (0 = first attribute after the 4D position)
+    * for this output attribute.  attr is currently a VERT_RESULT_* but should
+    * be FRAG_ATTRIB_*.
+    */
+   for (i = 0; i < attr; i++) {
+      if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(i))
+	 attr_index++;
+   }
+   attr_override = attr_index;
+
+   return attr_index;
+}
+
 static void
 upload_sf_state(struct brw_context *brw)
 {
@@ -45,10 +64,11 @@ upload_sf_state(struct brw_context *brw)
    int i;
    /* _NEW_BUFFER */
    GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   int attr = 0;
 
    dw1 =
       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
-      num_inputs << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
+      (num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
       3 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
    dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
       GEN6_SF_STATISTICS_ENABLE;
@@ -122,8 +142,27 @@ upload_sf_state(struct brw_context *brw)
    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
    for (i = 0; i < 8; i++) {
-      /* attribute overrides */
-      OUT_BATCH(0);
+      uint32_t attr_overrides = 0;
+
+      /* These should be generating FS inputs read instead of VS
+       * outputs written
+       */
+      for (; attr < 64; attr++) {
+	 if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(attr)) {
+	    attr_overrides |= get_attr_override(brw, attr);
+	    attr++;
+	    break;
+	 }
+      }
+
+      for (; attr < 64; attr++) {
+	 if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(attr)) {
+	    attr_overrides |= get_attr_override(brw, attr) << 16;
+	    attr++;
+	    break;
+	 }
+      }
+      OUT_BATCH(attr_overrides);
    }
    OUT_BATCH(0); /* point sprite texcoord bitmask */
    OUT_BATCH(0); /* constant interp bitmask */
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 211a6231c9f..fe597dfb945 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -65,13 +65,13 @@ upload_vs_state(struct brw_context *brw)
       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
 				       nr_params * 4 * sizeof(float),
 				       4096);
-      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      drm_intel_gem_bo_map_gtt(constant_bo);
       for (i = 0; i < nr_params; i++) {
 	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
 		vp->program.Base.Parameters->ParameterValues[i],
 		4 * sizeof(float));
       }
-      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+      drm_intel_gem_bo_unmap_gtt(constant_bo);
 
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index e3552617691..1eb17ca627d 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -63,13 +63,13 @@ upload_wm_state(struct brw_context *brw)
       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
 				       nr_params * 4 * sizeof(float),
 				       4096);
-      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      drm_intel_gem_bo_map_gtt(constant_bo);
       for (i = 0; i < nr_params; i++) {
 	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
 		fp->program.Base.Parameters->ParameterValues[i],
 		4 * sizeof(float));
       }
-      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+      drm_intel_gem_bo_unmap_gtt(constant_bo);
 
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
diff --git a/src/mesa/drivers/dri/i965/server/intel_dri.c b/src/mesa/drivers/dri/i965/server/intel_dri.c
deleted file mode 120000
index effdd26448a..00000000000
--- a/src/mesa/drivers/dri/i965/server/intel_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../intel/server/intel_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index a7bfd62b285..9768b0deee7 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -210,6 +210,8 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 {
    int ret;
 
+   assert(delta < buffer->size);
+
    if (batch->ptr - batch->map > batch->buf->size)
     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 	    batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
@@ -234,6 +236,8 @@ intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
 {
    int ret;
 
+   assert(delta < buffer->size);
+
    if (batch->ptr - batch->map > batch->buf->size)
     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 	    batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index 79bdbc17ae1..e5ad2617ab9 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -24,11 +24,13 @@ struct intel_batchbuffer
 
    GLuint size;
 
+#ifdef DEBUG
    /** Tracking of BEGIN_BATCH()/OUT_BATCH()/ADVANCE_BATCH() debugging */
    struct {
       GLuint total;
       GLubyte *start_ptr;
    } emit;
+#endif
 
    GLuint dirty_state;
    GLuint reserved_space;
@@ -71,6 +73,17 @@ GLboolean intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
 					      uint32_t offset);
 void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch);
 
+static INLINE uint32_t float_as_int(float f)
+{
+   union {
+      float f;
+      uint32_t d;
+   } fi;
+
+   fi.f = f;
+   return fi.d;
+}
+
 /* Inline functions - might actually be better off with these
  * non-inlined.  Certainly better off switching all command packets to
  * be passed as structs rather than dwords, but that's a little bit of
@@ -86,67 +99,73 @@ intel_batchbuffer_space(struct intel_batchbuffer *batch)
 static INLINE void
 intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword)
 {
-   assert(batch->map);
+#ifdef DEBUG
    assert(intel_batchbuffer_space(batch) >= 4);
+#endif
    *(GLuint *) (batch->ptr) = dword;
    batch->ptr += 4;
 }
 
 static INLINE void
+intel_batchbuffer_emit_float(struct intel_batchbuffer *batch, float f)
+{
+   intel_batchbuffer_emit_dword(batch, float_as_int(f));
+}
+
+static INLINE void
 intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
                                 GLuint sz)
 {
+#ifdef DEBUG
    assert(sz < batch->size - 8);
+#endif
    if (intel_batchbuffer_space(batch) < sz)
       intel_batchbuffer_flush(batch);
 }
 
-static INLINE uint32_t float_as_int(float f)
+static INLINE void
+intel_batchbuffer_begin(struct intel_batchbuffer *batch, int n)
 {
-   union {
-      float f;
-      uint32_t d;
-   } fi;
+   intel_batchbuffer_require_space(batch, n * 4);
+#ifdef DEBUG
+   assert(batch->map);
+   assert(batch->emit.start_ptr == NULL);
+   batch->emit.total = n * 4;
+   batch->emit.start_ptr = batch->ptr;
+#endif
+}
 
-   fi.f = f;
-   return fi.d;
+static INLINE void
+intel_batchbuffer_advance(struct intel_batchbuffer *batch)
+{
+#ifdef DEBUG
+   unsigned int _n = batch->ptr - batch->emit.start_ptr;
+   assert(batch->emit.start_ptr != NULL);
+   if (_n != batch->emit.total) {
+      fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
+	      _n, batch->emit.total);
+      abort();
+   }
+   batch->emit.start_ptr = NULL;
+#endif
 }
 
 /* Here are the crusty old macros, to be removed:
  */
 #define BATCH_LOCALS
 
-#define BEGIN_BATCH(n) do {				\
-   intel_batchbuffer_require_space(intel->batch, (n)*4); \
-   assert(intel->batch->emit.start_ptr == NULL);			\
-   intel->batch->emit.total = (n) * 4;					\
-   intel->batch->emit.start_ptr = intel->batch->ptr;			\
-} while (0)
-
+#define BEGIN_BATCH(n) intel_batchbuffer_begin(intel->batch, n)
 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d)
-#define OUT_BATCH_F(f) intel_batchbuffer_emit_dword(intel->batch,	\
-						    float_as_int(f))
-
+#define OUT_BATCH_F(f) intel_batchbuffer_emit_float(intel->batch,f)
 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {		\
-   assert((unsigned) (delta) < buf->size);				\
    intel_batchbuffer_emit_reloc(intel->batch, buf,			\
 				read_domains, write_domain, delta);	\
 } while (0)
 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do {	\
-   assert((unsigned) (delta) < buf->size);				\
    intel_batchbuffer_emit_reloc_fenced(intel->batch, buf,		\
 				       read_domains, write_domain, delta); \
 } while (0)
 
-#define ADVANCE_BATCH() do {						\
-   unsigned int _n = intel->batch->ptr - intel->batch->emit.start_ptr;	\
-   assert(intel->batch->emit.start_ptr != NULL);			\
-   if (_n != intel->batch->emit.total) {				\
-      fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",	\
-	      _n, intel->batch->emit.total);				\
-      abort();								\
-   }									\
-   intel->batch->emit.start_ptr = NULL;					\
-} while(0)
+#define ADVANCE_BATCH() intel_batchbuffer_advance(intel->batch);
 
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 6d6af863476..f2769aa3e8c 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -122,8 +122,8 @@ intelEmitCopyBlit(struct intel_context *intel,
    intel_prepare_render(intel);
 
    if (pass >= 2) {
-      intel_bo_map_gtt_preferred(intel, dst_buffer, GL_TRUE);
-      intel_bo_map_gtt_preferred(intel, src_buffer, GL_FALSE);
+      drm_intel_gem_bo_map_gtt(dst_buffer);
+      drm_intel_gem_bo_map_gtt(src_buffer);
       _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
 		      cpp,
 		      dst_pitch,
@@ -132,8 +132,8 @@ intelEmitCopyBlit(struct intel_context *intel,
 		      (GLubyte *)src_buffer->virtual + src_offset,
 		      src_pitch,
 		      src_x, src_y);
-      intel_bo_unmap_gtt_preferred(intel, src_buffer);
-      intel_bo_unmap_gtt_preferred(intel, dst_buffer);
+      drm_intel_gem_bo_unmap_gtt(src_buffer);
+      drm_intel_gem_bo_unmap_gtt(dst_buffer);
 
       return GL_TRUE;
    }
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 312866d865d..103aaf2b956 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -31,10 +31,12 @@
 #include "main/macros.h"
 #include "main/bufferobj.h"
 
-#include "intel_context.h"
 #include "intel_blit.h"
 #include "intel_buffer_objects.h"
 #include "intel_batchbuffer.h"
+#include "intel_context.h"
+#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
 #include "intel_regions.h"
 
 static GLboolean
@@ -285,7 +287,7 @@ intel_bufferobj_map(GLcontext * ctx,
       return NULL;
    }
 
-   if (write_only && intel->intelScreen->kernel_exec_fencing) {
+   if (write_only) {
       drm_intel_gem_bo_map_gtt(intel_obj->buffer);
       intel_obj->mapped_gtt = GL_TRUE;
    } else {
@@ -379,8 +381,7 @@ intel_bufferobj_map_range(GLcontext * ctx,
 	 intel_obj->range_map_bo = drm_intel_bo_alloc(intel->bufmgr,
 						      "range map",
 						      length, 64);
-	 if (!(access & GL_MAP_READ_BIT) &&
-	     intel->intelScreen->kernel_exec_fencing) {
+	 if (!(access & GL_MAP_READ_BIT)) {
 	    drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo);
 	    intel_obj->mapped_gtt = GL_TRUE;
 	 } else {
@@ -393,8 +394,7 @@ intel_bufferobj_map_range(GLcontext * ctx,
       return obj->Pointer;
    }
 
-   if (!(access & GL_MAP_READ_BIT) &&
-       intel->intelScreen->kernel_exec_fencing) {
+   if (!(access & GL_MAP_READ_BIT)) {
       drm_intel_gem_bo_map_gtt(intel_obj->buffer);
       intel_obj->mapped_gtt = GL_TRUE;
    } else {
@@ -588,6 +588,126 @@ intel_bufferobj_copy_subdata(GLcontext *ctx,
    intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
+#if FEATURE_APPLE_object_purgeable
+static GLenum
+intel_buffer_purgeable(GLcontext * ctx,
+                       drm_intel_bo *buffer,
+                       GLenum option)
+{
+   int retained = 0;
+
+   if (buffer != NULL)
+      retained = drm_intel_bo_madvise (buffer, I915_MADV_DONTNEED);
+
+   return retained ? GL_VOLATILE_APPLE : GL_RELEASED_APPLE;
+}
+
+static GLenum
+intel_buffer_object_purgeable(GLcontext * ctx,
+                              struct gl_buffer_object *obj,
+                              GLenum option)
+{
+   struct intel_buffer_object *intel;
+
+   intel = intel_buffer_object (obj);
+   if (intel->buffer != NULL)
+      return intel_buffer_purgeable (ctx, intel->buffer, option);
+
+   if (option == GL_RELEASED_APPLE) {
+      if (intel->sys_buffer != NULL) {
+         free(intel->sys_buffer);
+         intel->sys_buffer = NULL;
+      }
+
+      return GL_RELEASED_APPLE;
+   } else {
+      /* XXX Create the buffer and madvise(MADV_DONTNEED)? */
+      return intel_buffer_purgeable (ctx,
+                                     intel_bufferobj_buffer(intel_context(ctx),
+                                                            intel, INTEL_READ),
+                                     option);
+   }
+}
+
+static GLenum
+intel_texture_object_purgeable(GLcontext * ctx,
+                               struct gl_texture_object *obj,
+                               GLenum option)
+{
+   struct intel_texture_object *intel;
+
+   intel = intel_texture_object(obj);
+   if (intel->mt == NULL || intel->mt->region == NULL)
+      return GL_RELEASED_APPLE;
+
+   return intel_buffer_purgeable (ctx, intel->mt->region->buffer, option);
+}
+
+static GLenum
+intel_render_object_purgeable(GLcontext * ctx,
+                              struct gl_renderbuffer *obj,
+                              GLenum option)
+{
+   struct intel_renderbuffer *intel;
+
+   intel = intel_renderbuffer(obj);
+   if (intel->region == NULL)
+      return GL_RELEASED_APPLE;
+
+   return intel_buffer_purgeable (ctx, intel->region->buffer, option);
+}
+
+static GLenum
+intel_buffer_unpurgeable(GLcontext * ctx,
+                         drm_intel_bo *buffer,
+                         GLenum option)
+{
+   int retained;
+
+   retained = 0;
+   if (buffer != NULL)
+      retained = drm_intel_bo_madvise (buffer, I915_MADV_WILLNEED);
+
+   return retained ? GL_RETAINED_APPLE : GL_UNDEFINED_APPLE;
+}
+
+static GLenum
+intel_buffer_object_unpurgeable(GLcontext * ctx,
+                                struct gl_buffer_object *obj,
+                                GLenum option)
+{
+   return intel_buffer_unpurgeable (ctx, intel_buffer_object (obj)->buffer, option);
+}
+
+static GLenum
+intel_texture_object_unpurgeable(GLcontext * ctx,
+                                 struct gl_texture_object *obj,
+                                 GLenum option)
+{
+   struct intel_texture_object *intel;
+
+   intel = intel_texture_object(obj);
+   if (intel->mt == NULL || intel->mt->region == NULL)
+      return GL_UNDEFINED_APPLE;
+
+   return intel_buffer_unpurgeable (ctx, intel->mt->region->buffer, option);
+}
+
+static GLenum
+intel_render_object_unpurgeable(GLcontext * ctx,
+                                struct gl_renderbuffer *obj,
+                                GLenum option)
+{
+   struct intel_renderbuffer *intel;
+
+   intel = intel_renderbuffer(obj);
+   if (intel->region == NULL)
+      return GL_UNDEFINED_APPLE;
+
+   return intel_buffer_unpurgeable (ctx, intel->region->buffer, option);
+}
+#endif
+
 void
 intelInitBufferObjectFuncs(struct dd_function_table *functions)
 {
@@ -601,4 +721,14 @@ intelInitBufferObjectFuncs(struct dd_function_table *functions)
    functions->FlushMappedBufferRange = intel_bufferobj_flush_mapped_range;
    functions->UnmapBuffer = intel_bufferobj_unmap;
    functions->CopyBufferSubData = intel_bufferobj_copy_subdata;
+
+#if FEATURE_APPLE_object_purgeable
+   functions->BufferObjectPurgeable = intel_buffer_object_purgeable;
+   functions->TextureObjectPurgeable = intel_texture_object_purgeable;
+   functions->RenderObjectPurgeable = intel_render_object_purgeable;
+
+   functions->BufferObjectUnpurgeable = intel_buffer_object_unpurgeable;
+   functions->TextureObjectUnpurgeable = intel_texture_object_unpurgeable;
+   functions->RenderObjectUnpurgeable = intel_render_object_unpurgeable;
+#endif
 }
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index ec379a77ace..d6a1ba69524 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -755,12 +755,6 @@ intelInitContext(struct intel_context *intel,
    }
    intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
 					       "texture_tiling");
-   if (intel->use_texture_tiling &&
-       !intel->intelScreen->kernel_exec_fencing) {
-      fprintf(stderr, "No kernel support for execution fencing, "
-	      "disabling texture tiling\n");
-      intel->use_texture_tiling = GL_FALSE;
-   }
    intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
 
    intel->prim.primitive = ~0;
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index d20d44497e1..22736a93279 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -475,25 +475,4 @@ is_power_of_two(uint32_t value)
    return (value & (value - 1)) == 0;
 }
 
-static INLINE void
-intel_bo_map_gtt_preferred(struct intel_context *intel,
-			   drm_intel_bo *bo,
-			   GLboolean write)
-{
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_map_gtt(bo);
-   else
-      drm_intel_bo_map(bo, write);
-}
-
-static INLINE void
-intel_bo_unmap_gtt_preferred(struct intel_context *intel,
-			     drm_intel_bo *bo)
-{
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_unmap_gtt(bo);
-   else
-      drm_intel_bo_unmap(bo);
-}
-
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_depthtmp.h b/src/mesa/drivers/dri/intel/intel_depthtmp.h
deleted file mode 100644
index a9c75d44cf3..00000000000
--- a/src/mesa/drivers/dri/intel/intel_depthtmp.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <[email protected]>
- *
- */
-
-/**
- * Wrapper around the depthtmp.h macrofest to generate spans code for
- * all the tiling styles.
- */
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) \
-   (*(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual +	\
-			  NO_TILE(_x, _y)) = d)
-#define READ_DEPTH(d, _x, _y) \
-   d = *(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual +	\
-			     NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_gttmap_##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(NO_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(X_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(X_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_XTile_##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(Y_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(Y_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_YTile_##x)
-#include "depthtmp.h"
-
-#undef INTEL_VALUE_TYPE
-#undef INTEL_WRITE_DEPTH
-#undef INTEL_READ_DEPTH
-#undef INTEL_TAG
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c
index e16c33b33d7..a1aac699c91 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -58,6 +58,7 @@
 #define need_GL_EXT_secondary_color
 #define need_GL_EXT_stencil_two_side
 #define need_GL_APPLE_vertex_array_object
+#define need_GL_APPLE_object_purgeable
 #define need_GL_ATI_separate_stencil
 #define need_GL_ATI_envmap_bumpmap
 #define need_GL_NV_point_sprite
@@ -121,6 +122,7 @@ static const struct dri_extension card_extensions[] = {
    { "GL_EXT_texture_lod_bias",           NULL },
    { "GL_3DFX_texture_compression_FXT1",  NULL },
    { "GL_APPLE_client_storage",           NULL },
+   { "GL_APPLE_object_purgeable",         GL_APPLE_object_purgeable_functions },
    { "GL_APPLE_vertex_array_object",      GL_APPLE_vertex_array_object_functions},
    { "GL_MESA_pack_invert",               NULL },
    { "GL_MESA_ycbcr_texture",             NULL },
@@ -182,6 +184,7 @@ static const struct dri_extension arb_oq_extensions[] = {
    { NULL, NULL }
 };
 
+
 static const struct dri_extension fragment_shader_extensions[] = {
    { "GL_ARB_fragment_shader",            NULL },
    { NULL, NULL }
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index b388a3de2ef..a429f8d003d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -70,9 +70,6 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
 
    ASSERT(irb);
 
-   if (irb->span_cache != NULL)
-      free(irb->span_cache);
-
    if (intel && irb->region) {
       intel_region_release(&irb->region);
    }
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 586dbbbb25a..72413f73694 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -40,9 +40,6 @@ struct intel_renderbuffer
 {
    struct gl_renderbuffer Base;
    struct intel_region *region;
-
-   uint8_t *span_cache;
-   unsigned long span_cache_offset;
 };
 
 
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index a20ea5afdb7..4f14946ec72 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -119,8 +119,7 @@ intel_miptree_create(struct intel_context *intel,
    struct intel_mipmap_tree *mt;
    uint32_t tiling;
 
-   if (intel->use_texture_tiling && compress_byte == 0 &&
-       intel->intelScreen->kernel_exec_fencing) {
+   if (intel->use_texture_tiling && compress_byte == 0) {
       if (intel->gen >= 4 &&
 	  (base_format == GL_DEPTH_COMPONENT ||
 	   base_format == GL_DEPTH_STENCIL_EXT))
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index e3c0635e5ba..f042bcbc28c 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -118,8 +118,7 @@ intel_region_map(struct intel_context *intel, struct intel_region *region)
       if (region->pbo)
          intel_region_cow(intel, region);
 
-      if (region->tiling != I915_TILING_NONE &&
-	  intel->intelScreen->kernel_exec_fencing)
+      if (region->tiling != I915_TILING_NONE)
 	 drm_intel_gem_bo_map_gtt(region->buffer);
       else
 	 dri_bo_map(region->buffer, GL_TRUE);
@@ -134,8 +133,7 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region)
 {
    _DBG("%s %p\n", __FUNCTION__, region);
    if (!--region->map_refcount) {
-      if (region->tiling != I915_TILING_NONE &&
-	  intel->intelScreen->kernel_exec_fencing)
+      if (region->tiling != I915_TILING_NONE)
 	 drm_intel_gem_bo_unmap_gtt(region->buffer);
       else
 	 dri_bo_unmap(region->buffer);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index a42af71104a..6e4bb643651 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -47,9 +47,6 @@
 #include "i915_drm.h"
 
 #define DRI_CONF_TEXTURE_TILING(def) \
-	DRI_CONF_OPT_BEGIN(texture_tiling, bool, def)		\
-		DRI_CONF_DESC(en, "Enable texture tiling")	\
-	DRI_CONF_OPT_END					\
 
 PUBLIC const char __driConfigOptions[] =
    DRI_CONF_BEGIN
@@ -65,11 +62,9 @@ PUBLIC const char __driConfigOptions[] =
 	 DRI_CONF_DESC_END
       DRI_CONF_OPT_END
 
-#ifdef I915
-     DRI_CONF_TEXTURE_TILING(false)
-#else
-     DRI_CONF_TEXTURE_TILING(true)
-#endif
+      DRI_CONF_OPT_BEGIN(texture_tiling, bool, true)
+	 DRI_CONF_DESC(en, "Enable texture tiling")
+      DRI_CONF_OPT_END
 
       DRI_CONF_OPT_BEGIN(early_z, bool, false)
 	 DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).")
@@ -101,11 +96,6 @@ const GLuint __driNConfigOptions = 11;
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE */
 
-static const __DRItexOffsetExtension intelTexOffsetExtension = {
-   { __DRI_TEX_OFFSET },
-   intelSetTexOffset,
-};
-
 static const __DRItexBufferExtension intelTexBufferExtension = {
     { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
    intelSetTexBuffer,
@@ -232,7 +222,6 @@ static struct __DRIimageExtensionRec intelImageExtension = {
 
 static const __DRIextension *intelScreenExtensions[] = {
     &driReadDrawableExtension,
-    &intelTexOffsetExtension.base,
     &intelTexBufferExtension.base,
     &intelFlushExtension.base,
     &intelImageExtension.base,
@@ -421,10 +410,11 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
       return GL_FALSE;
    }
 
-   if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences))
-      intelScreen->kernel_exec_fencing = !!num_fences;
-   else
-      intelScreen->kernel_exec_fencing = GL_FALSE;
+   if (!intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences) ||
+       num_fences == 0) {
+      fprintf(stderr, "[%s: %u] Kernel 2.6.29 required.\n", __func__, __LINE__);
+      return GL_FALSE;
+   }
 
    drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
 
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 1ce476dacaa..5863093f001 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -46,7 +46,6 @@ struct intel_screen
 
    GLboolean no_vbo;
    dri_bufmgr *bufmgr;
-   GLboolean kernel_exec_fencing;
    struct _mesa_HashTable *named_regions;
 
    /**
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 0072bb15fc3..fb5c01bc4dc 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -43,218 +43,6 @@ static void
 intel_set_span_functions(struct intel_context *intel,
 			 struct gl_renderbuffer *rb);
 
-#define SPAN_CACHE_SIZE		4096
-
-static void
-get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   if (irb->span_cache == NULL) {
-      irb->span_cache = malloc(SPAN_CACHE_SIZE);
-      irb->span_cache_offset = -1;
-   }
-
-   if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
-      irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
-      dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
-			 SPAN_CACHE_SIZE, irb->span_cache);
-   }
-}
-
-static void
-clear_span_cache(struct intel_renderbuffer *irb)
-{
-   irb->span_cache_offset = -1;
-}
-
-static uint32_t
-pread_32(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static uint32_t
-pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
-      0xff000000;
-}
-
-static uint16_t
-pread_16(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static uint8_t
-pread_8(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static void
-pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 4, &val);
-}
-
-static void
-pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 3, &val);
-}
-
-static void
-pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 2, &val);
-}
-
-static void
-pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 1, &val);
-}
-
-static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
-				int x, int y)
-{
-	return (y * irb->region->pitch + x) * irb->region->cpp;
-}
-
-/*
- * Deal with tiled surfaces
- */
-
-static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
-			       int x, int y)
-{
-	int	tile_stride;
-	int	xbyte;
-	int	x_tile_off, y_tile_off;
-	int	x_tile_number, y_tile_number;
-	int	tile_off, tile_base;
-	
-        x += irb->region->draw_x;
-        y += irb->region->draw_y;
-
-	tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
-
-	xbyte = x * irb->region->cpp;
-
-	x_tile_off = xbyte & 0x1ff;
-	y_tile_off = y & 7;
-
-	x_tile_number = xbyte >> 9;
-	y_tile_number = y >> 3;
-
-	tile_off = (y_tile_off << 9) + x_tile_off;
-
-	switch (irb->region->bit_6_swizzle) {
-	case I915_BIT_6_SWIZZLE_NONE:
-	   break;
-	case I915_BIT_6_SWIZZLE_9:
-	   tile_off ^= ((tile_off >> 3) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
-	      ((tile_off >> 5) & 64);
-	   break;
-	default:
-	   fprintf(stderr, "Unknown tile swizzling mode %d\n",
-		   irb->region->bit_6_swizzle);
-	   exit(1);
-	}
-
-	tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
-
-#if 0
-	printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
-	       x, y, tile_off, tile_base,
-	       tile_off + tile_base,
-	       irb->region->pitch, tile_stride);
-#endif
-
-	return tile_base + tile_off;
-}
-
-static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
-			       int x, int y)
-{
-	int	tile_stride;
-	int	xbyte;
-	int	x_tile_off, y_tile_off;
-	int	x_tile_number, y_tile_number;
-	int	tile_off, tile_base;
-	
-        x += irb->region->draw_x;
-        y += irb->region->draw_y;
-
-	tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
-
-	xbyte = x * irb->region->cpp;
-
-	x_tile_off = xbyte & 0x7f;
-	y_tile_off = y & 0x1f;
-
-	x_tile_number = xbyte >> 7;
-	y_tile_number = y >> 5;
-
-	tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
-	   (x_tile_off & 0xf);
-
-	switch (irb->region->bit_6_swizzle) {
-	case I915_BIT_6_SWIZZLE_NONE:
-	   break;
-	case I915_BIT_6_SWIZZLE_9:
-	   tile_off ^= ((tile_off >> 3) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
-	      ((tile_off >> 5) & 64);
-	   break;
-	default:
-	   fprintf(stderr, "Unknown tile swizzling mode %d\n",
-		   irb->region->bit_6_swizzle);
-	   exit(1);
-	}
-
-	tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
-
-	return tile_base + tile_off;
-}
-
-/*
-  break intelWriteRGBASpan_ARGB8888
-*/
-
 #undef DBG
 #define DBG 0
 
@@ -280,50 +68,43 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 
 #define HW_UNLOCK()
 
-/* Convenience macros to avoid typing the swizzle argument over and over */
-#define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X), (_Y))
-#define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X), (_Y))
-#define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X), (_Y))
+/* Convenience macros to avoid typing the address argument over and over */
+#define NO_TILE(_X, _Y) (((_Y) * irb->region->pitch + (_X)) * irb->region->cpp)
 
 /* r5g6b5 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_RGB
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_RGB565
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+#define TAG(x) intel_##x##_RGB565
+#define TAG2(x,y) intel_##x##y_RGB565
+#include "spantmp2.h"
 
 /* a4r4g4b4 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB4444
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
+#define TAG(x) intel_##x##_ARGB4444
+#define TAG2(x,y) intel_##x##y_ARGB4444
+#include "spantmp2.h"
 
 /* a1r5g5b5 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB1555
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
+#define TAG(x) intel_##x##_ARGB1555
+#define TAG2(x,y) intel_##x##y##_ARGB1555
+#include "spantmp2.h"
 
 /* a8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define INTEL_READ_VALUE(offset) pread_32(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB8888
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+#define TAG(x) intel_##x##_ARGB8888
+#define TAG2(x,y) intel_##x##y##_ARGB8888
+#include "spantmp2.h"
 
 /* x8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGR
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
-#define INTEL_TAG(x) x##_xRGB8888
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGR
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+#define TAG(x) intel_##x##_xRGB8888
+#define TAG2(x,y) intel_##x##y##_xRGB8888
+#include "spantmp2.h"
 
 #define LOCAL_DEPTH_VARS						\
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);		\
@@ -339,52 +120,22 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 
 /* z16 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLushort
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
-#define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
-#define INTEL_TAG(name) name##_z16
-#include "intel_depthtmp.h"
-
-/* z24x8 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLuint
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
-#define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
-#define INTEL_TAG(name) name##_z24_x8
-#include "intel_depthtmp.h"
-
-
-/**
- ** 8-bit stencil function (XXX FBO: This is obsolete)
- **/
-/* XXX */
-#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
-#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
-#define TAG(x) intel_gttmap_##x##_z24_s8
-#include "stenciltmp.h"
-
-/**
- ** 8-bit stencil function (XXX FBO: This is obsolete)
- **/
-#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
-#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
-#define TAG(x) intel##x##_z24_s8
-#include "stenciltmp.h"
-
-/**
- ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
- **/
-#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
-#define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
-#define TAG(x) intel_XTile_##x##_z24_s8
-#include "stenciltmp.h"
-
-/**
- ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
- **/
-#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
-#define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
-#define TAG(x) intel_YTile_##x##_z24_s8
-#include "stenciltmp.h"
+#define VALUE_TYPE GLushort
+#define WRITE_DEPTH(_x, _y, d) \
+   (*(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
+#define READ_DEPTH(d, _x, _y) \
+   d = *(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
+#define TAG(x) intel_##x##_z16
+#include "depthtmp.h"
+
+/* z24_s8 and z24_x8 depthbuffer functions. */
+#define VALUE_TYPE GLuint
+#define WRITE_DEPTH(_x, _y, d) \
+   (*(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
+#define READ_DEPTH(d, _x, _y) \
+   d = *(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
+#define TAG(x) intel_##x##_z24_x8
+#include "depthtmp.h"
 
 void
 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
@@ -394,8 +145,7 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
    if (irb == NULL || irb->region == NULL)
       return;
 
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_map_gtt(irb->region->buffer);
+   drm_intel_gem_bo_map_gtt(irb->region->buffer);
 
    intel_set_span_functions(intel, rb);
 }
@@ -409,10 +159,7 @@ intel_renderbuffer_unmap(struct intel_context *intel,
    if (irb == NULL || irb->region == NULL)
       return;
 
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
-   else
-      clear_span_cache(irb);
+   drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
 
    rb->GetRow = NULL;
    rb->PutRow = NULL;
@@ -592,182 +339,34 @@ intel_set_span_functions(struct intel_context *intel,
 			 struct gl_renderbuffer *rb)
 {
    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
-   uint32_t tiling = irb->region->tiling;
-
-   if (intel->intelScreen->kernel_exec_fencing) {
-      switch (irb->Base.Format) {
-      case MESA_FORMAT_RGB565:
-	 intel_gttmap_InitPointers_RGB565(rb);
-	 break;
-      case MESA_FORMAT_ARGB4444:
-	 intel_gttmap_InitPointers_ARGB4444(rb);
-	 break;
-      case MESA_FORMAT_ARGB1555:
-	 intel_gttmap_InitPointers_ARGB1555(rb);
-	 break;
-      case MESA_FORMAT_XRGB8888:
-         intel_gttmap_InitPointers_xRGB8888(rb);
-	 break;
-      case MESA_FORMAT_ARGB8888:
-	 intel_gttmap_InitPointers_ARGB8888(rb);
-	 break;
-      case MESA_FORMAT_Z16:
-	 intel_gttmap_InitDepthPointers_z16(rb);
-	 break;
-      case MESA_FORMAT_X8_Z24:
-	 intel_gttmap_InitDepthPointers_z24_x8(rb);
-	 break;
-      case MESA_FORMAT_S8_Z24:
-	 /* There are a few different ways SW asks us to access the S8Z24 data:
-	  * Z24 depth-only depth reads
-	  * S8Z24 depth reads
-	  * S8Z24 stencil reads.
-	  */
-	 if (rb->Format == MESA_FORMAT_S8_Z24) {
-	    intel_gttmap_InitDepthPointers_z24_x8(rb);
-	 } else if (rb->Format == MESA_FORMAT_S8) {
-	    intel_gttmap_InitStencilPointers_z24_s8(rb);
-	 }
-	 break;
-      default:
-	 _mesa_problem(NULL,
-		       "Unexpected MesaFormat %d in intelSetSpanFunctions",
-		       irb->Base.Format);
-	 break;
-      }
-      return;
-   }
 
-   /* If in GEM mode, we need to do the tile address swizzling ourselves,
-    * instead of the fence registers handling it.
-    */
    switch (irb->Base.Format) {
    case MESA_FORMAT_RGB565:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_RGB565(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_RGB565(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_RGB565(rb);
-	 break;
-      }
+      intel_InitPointers_RGB565(rb);
       break;
    case MESA_FORMAT_ARGB4444:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_ARGB4444(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_ARGB4444(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_ARGB4444(rb);
-	 break;
-      }
+      intel_InitPointers_ARGB4444(rb);
       break;
    case MESA_FORMAT_ARGB1555:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_ARGB1555(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_ARGB1555(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_ARGB1555(rb);
-	 break;
-      }
+      intel_InitPointers_ARGB1555(rb);
       break;
    case MESA_FORMAT_XRGB8888:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-         intelInitPointers_xRGB8888(rb);
-         break;
-      case I915_TILING_X:
-         intel_XTile_InitPointers_xRGB8888(rb);
-         break;
-      case I915_TILING_Y:
-         intel_YTile_InitPointers_xRGB8888(rb);
-         break;
-      }
+      intel_InitPointers_xRGB8888(rb);
       break;
    case MESA_FORMAT_ARGB8888:
-      /* 8888 RGBA */
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_ARGB8888(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_ARGB8888(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_ARGB8888(rb);
-	 break;
-      }
+      intel_InitPointers_ARGB8888(rb);
       break;
    case MESA_FORMAT_Z16:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitDepthPointers_z16(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitDepthPointers_z16(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitDepthPointers_z16(rb);
-	 break;
-      }
+      intel_InitDepthPointers_z16(rb);
       break;
    case MESA_FORMAT_X8_Z24:
    case MESA_FORMAT_S8_Z24:
-      /* There are a few different ways SW asks us to access the S8Z24 data:
-       * Z24 depth-only depth reads
-       * S8Z24 depth reads
-       * S8Z24 stencil reads.
-       */
-      if (rb->Format == MESA_FORMAT_S8_Z24) {
-	 switch (tiling) {
-	 case I915_TILING_NONE:
-	 default:
-	    intelInitDepthPointers_z24_x8(rb);
-	    break;
-	 case I915_TILING_X:
-	    intel_XTile_InitDepthPointers_z24_x8(rb);
-	    break;
-	 case I915_TILING_Y:
-	    intel_YTile_InitDepthPointers_z24_x8(rb);
-	    break;
-	 }
-      } else if (rb->Format == MESA_FORMAT_S8) {
-	 switch (tiling) {
-	 case I915_TILING_NONE:
-	 default:
-	    intelInitStencilPointers_z24_s8(rb);
-	    break;
-	 case I915_TILING_X:
-	    intel_XTile_InitStencilPointers_z24_s8(rb);
-	    break;
-	 case I915_TILING_Y:
-	    intel_YTile_InitStencilPointers_z24_s8(rb);
-	    break;
-	 }
-      } else {
-	 _mesa_problem(NULL,
-		       "Unexpected ActualFormat in intelSetSpanFunctions");
-      }
+      intel_InitDepthPointers_z24_x8(rb);
       break;
    default:
       _mesa_problem(NULL,
-                    "Unexpected MesaFormat in intelSetSpanFunctions");
+		    "Unexpected MesaFormat %d in intelSetSpanFunctions",
+		    irb->Base.Format);
       break;
    }
 }
diff --git a/src/mesa/drivers/dri/intel/intel_spantmp.h b/src/mesa/drivers/dri/intel/intel_spantmp.h
deleted file mode 100644
index bad03398f68..00000000000
--- a/src/mesa/drivers/dri/intel/intel_spantmp.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <[email protected]>
- *
- */
-
-/**
- * Wrapper around the spantmp.h macrofest to generate spans code for
- * all the tiling styles.
- */
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define TAG(x) INTEL_TAG(intel_gttmap_##x)
-#define TAG2(x, y) INTEL_TAG(intel_gttmap_##x##y)
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(NO_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel##x)
-#define TAG2(x, y) INTEL_TAG(intel##x)##y
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(X_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(X_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_XTile_##x)
-#define TAG2(x, y) INTEL_TAG(intel_XTile_##x)##y
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(Y_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(Y_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_YTile_##x)
-#define TAG2(x, y) INTEL_TAG(intel_YTile_##x)##y
-#include "spantmp2.h"
-
-#undef INTEL_PIXEL_FMT
-#undef INTEL_PIXEL_TYPE
-#undef INTEL_WRITE_VALUE
-#undef INTEL_READ_VALUE
-#undef INTEL_TAG
diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src/mesa/drivers/dri/intel/intel_tex.h
index f3cc0fff5c8..4bb012dc65e 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.h
+++ b/src/mesa/drivers/dri/intel/intel_tex.h
@@ -45,8 +45,6 @@ void intelInitTextureCopyImageFuncs(struct dd_function_table *functions);
 gl_format intelChooseTextureFormat(GLcontext *ctx, GLint internalFormat,
                                    GLenum format, GLenum type);
 
-void intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
-		       unsigned long long offset, GLint depth, GLuint pitch);
 void intelSetTexBuffer(__DRIcontext *pDRICtx,
 		       GLint target, __DRIdrawable *pDraw);
 void intelSetTexBuffer2(__DRIcontext *pDRICtx,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index f586aee9929..bac36eeb569 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -706,29 +706,6 @@ intelGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level,
 		       texObj, texImage, GL_TRUE);
 }
 
-
-void
-intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
-		  unsigned long long offset, GLint depth, GLuint pitch)
-{
-   struct intel_context *intel = pDRICtx->driverPrivate;
-   struct gl_texture_object *tObj = _mesa_lookup_texture(&intel->ctx, texname);
-   struct intel_texture_object *intelObj = intel_texture_object(tObj);
-
-   if (!intelObj)
-      return;
-
-   if (intelObj->mt)
-      intel_miptree_release(intel, &intelObj->mt);
-
-   intelObj->imageOverride = GL_TRUE;
-   intelObj->depthOverride = depth;
-   intelObj->pitchOverride = pitch;
-
-   if (offset)
-      intelObj->textureOffset = offset;
-}
-
 void
 intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
 		   GLint texture_format,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_obj.h b/src/mesa/drivers/dri/intel/intel_tex_obj.h
index 3ad10d3d238..5f60e0ea4f3 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_obj.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_obj.h
@@ -46,10 +46,6 @@ struct intel_texture_object
     * regions will be copied to this region and the old storage freed.
     */
    struct intel_mipmap_tree *mt;
-
-   GLboolean imageOverride;
-   GLint depthOverride;
-   GLuint pitchOverride;
 };
 
 struct intel_texture_image
diff --git a/src/mesa/drivers/dri/intel/server/intel_dri.c b/src/mesa/drivers/dri/intel/server/intel_dri.c
deleted file mode 100644
index e49c4214ad4..00000000000
--- a/src/mesa/drivers/dri/intel/server/intel_dri.c
+++ /dev/null
@@ -1,1306 +0,0 @@
-/**
- * \file server/intel_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- * 
- * Copyright (C) 2006 Dave Airlie ([email protected])
-
- Permission is hereby granted, free of charge, to any person obtaining a
- copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sub license, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
- 
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial portions
- of the Software.
- 
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR
- ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-
-#include "intel.h"
-#include "i830_dri.h"
-
-#include "memops.h"
-#include "pciaccess.h"
-
-static size_t drm_page_size;
-static int nextTile = 0;
-#define xf86DrvMsg(...) do {} while(0)
-
-static const int pitches[] = {
-  128 * 8,
-  128 * 16,
-  128 * 32,
-  128 * 64,
-  0
-};
-
-static Bool I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea);
-
-static unsigned long
-GetBestTileAlignment(unsigned long size)
-{
-   unsigned long i;
-
-   for (i = KB(512); i < size; i <<= 1)
-      ;
-
-   if (i > MB(64))
-      i = MB(64);
-
-   return i;
-}
-
-static void SetFenceRegs(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  int i;
-  unsigned char *MMIO = ctx->MMIOAddress;
-
-  for (i = 0; i < 8; i++) {
-    OUTREG(FENCE + i * 4, pI830->Fence[i]);
-    //    if (I810_DEBUG & DEBUG_VERBOSE_VGA)
-    fprintf(stderr,"Fence Register : %x\n", pI830->Fence[i]);
-  }
-}
-
-/* Tiled memory is good... really, really good...
- *
- * Need to make it less likely that we miss out on this - probably
- * need to move the frontbuffer away from the 'guarenteed' alignment
- * of the first memory segment, or perhaps allocate a discontigous
- * framebuffer to get more alignment 'sweet spots'.
- */
-static void
-SetFence(const DRIDriverContext *ctx, I830Rec *pI830,
-	 int nr, unsigned int start, unsigned int pitch,
-         unsigned int size)
-{
-   unsigned int val;
-   unsigned int fence_mask = 0;
-   unsigned int fence_pitch;
-
-   if (nr < 0 || nr > 7) {
-      fprintf(stderr,
-		 "SetFence: fence %d out of range\n",nr);
-      return;
-   }
-
-   pI830->Fence[nr] = 0;
-
-   if (IS_I9XX(pI830))
-   	fence_mask = ~I915G_FENCE_START_MASK;
-   else
-   	fence_mask = ~I830_FENCE_START_MASK;
-
-   if (start & fence_mask) {
-      fprintf(stderr,
-		 "SetFence: %d: start (0x%08x) is not %s aligned\n",
-		 nr, start, (IS_I9XX(pI830)) ? "1MB" : "512k");
-      return;
-   }
-
-   if (start % size) {
-      fprintf(stderr,
-		 "SetFence: %d: start (0x%08x) is not size (%dk) aligned\n",
-		 nr, start, size / 1024);
-      return;
-   }
-
-   if (pitch & 127) {
-      fprintf(stderr,
-		 "SetFence: %d: pitch (%d) not a multiple of 128 bytes\n",
-		 nr, pitch);
-      return;
-   }
-
-   val = (start | FENCE_X_MAJOR | FENCE_VALID);
-
-   if (IS_I9XX(pI830)) {
-   	switch (size) {
-	   case MB(1):
-      		val |= I915G_FENCE_SIZE_1M;
-      		break;
-   	   case MB(2):
-      		val |= I915G_FENCE_SIZE_2M;
-      		break;
-   	   case MB(4):
-      		val |= I915G_FENCE_SIZE_4M;
-      		break;
-   	   case MB(8):
-      		val |= I915G_FENCE_SIZE_8M;
-      		break;
-   	   case MB(16):
-      		val |= I915G_FENCE_SIZE_16M;
-      		break;
-   	   case MB(32):
-      		val |= I915G_FENCE_SIZE_32M;
-      		break;
-   	   case MB(64):
-      		val |= I915G_FENCE_SIZE_64M;
-      		break;
-   	   default:
-      		fprintf(stderr,
-		 "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024);
-      		return;
-   	}
-    } else {
-   	switch (size) {
-	   case KB(512):
-      		val |= FENCE_SIZE_512K;
-      		break;
-	   case MB(1):
-      		val |= FENCE_SIZE_1M;
-      		break;
-   	   case MB(2):
-      		val |= FENCE_SIZE_2M;
-      		break;
-   	   case MB(4):
-      		val |= FENCE_SIZE_4M;
-      		break;
-   	   case MB(8):
-      		val |= FENCE_SIZE_8M;
-      		break;
-   	   case MB(16):
-      		val |= FENCE_SIZE_16M;
-      		break;
-   	   case MB(32):
-      		val |= FENCE_SIZE_32M;
-      		break;
-   	   case MB(64):
-      		val |= FENCE_SIZE_64M;
-      		break;
-   	   default:
-      		fprintf(stderr,
-		 "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024);
-      		return;
-   	}
-   }
-
-   if (IS_I9XX(pI830))
-	fence_pitch = pitch / 512;
-   else
-	fence_pitch = pitch / 128;
-
-   switch (fence_pitch) {
-   case 1:
-      val |= FENCE_PITCH_1;
-      break;
-   case 2:
-      val |= FENCE_PITCH_2;
-      break;
-   case 4:
-      val |= FENCE_PITCH_4;
-      break;
-   case 8:
-      val |= FENCE_PITCH_8;
-      break;
-   case 16:
-      val |= FENCE_PITCH_16;
-      break;
-   case 32:
-      val |= FENCE_PITCH_32;
-      break;
-   case 64:
-      val |= FENCE_PITCH_64;
-      break;
-   default:
-      fprintf(stderr,
-		 "SetFence: %d: illegal pitch (%d)\n", nr, pitch);
-      return;
-   }
-
-   pI830->Fence[nr] = val;
-}
-
-static Bool
-MakeTiles(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *pMem)
-{
-   int pitch, ntiles, i;
-
-   pitch = pMem->Pitch * ctx->cpp;
-   /*
-    * Simply try to break the region up into at most four pieces of size
-    * equal to the alignment.
-    */
-   ntiles = ROUND_TO(pMem->Size, pMem->Alignment) / pMem->Alignment;
-   if (ntiles >= 4) {
-      return FALSE;
-   }
-
-   for (i = 0; i < ntiles; i++, nextTile++) {
-     SetFence(ctx, pI830, nextTile, pMem->Start + i * pMem->Alignment,
-	       pitch, pMem->Alignment);
-   }
-   return TRUE;
-}
-
-static void I830SetupMemoryTiling(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  int i;
-
-  /* Clear out */
-  for (i = 0; i < 8; i++)
-    pI830->Fence[i] = 0;
-  
-  nextTile = 0;
-
-  if (pI830->BackBuffer.Alignment >= KB(512)) {
-    if (MakeTiles(ctx, pI830, &(pI830->BackBuffer))) {
-      fprintf(stderr,
-		 "Activating tiled memory for the back buffer.\n");
-    } else {
-      fprintf(stderr,
-		 "MakeTiles failed for the back buffer.\n");
-      pI830->allowPageFlip = FALSE;
-    }
-  }
-  
-  if (pI830->DepthBuffer.Alignment >= KB(512)) {
-    if (MakeTiles(ctx, pI830, &(pI830->DepthBuffer))) {
-      fprintf(stderr,
-		 "Activating tiled memory for the depth buffer.\n");
-    } else {
-      fprintf(stderr,
-		 "MakeTiles failed for the depth buffer.\n");
-    }
-  }
-
-  return;
-}
-
-static int I830DetectMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  struct pci_device host_bridge, ig_dev;
-  uint32_t gmch_ctrl;
-  int memsize = 0;
-  int range;
-  uint32_t aper_size;
-  uint32_t membase2 = 0;
-      
-  memset(&host_bridge, 0, sizeof(host_bridge));
-  memset(&ig_dev, 0, sizeof(ig_dev));
-
-  ig_dev.dev = 2;
-
-  pci_device_cfg_read_u32(&host_bridge, &gmch_ctrl, I830_GMCH_CTRL);
-
-  if (IS_I830(pI830) || IS_845G(pI830)) {
-    if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
-      aper_size = 0x80000000;
-    } else {
-      aper_size = 0x40000000;
-    }
-  } else {
-    if (IS_I9XX(pI830)) {
-      int ret;
-      ret = pci_device_cfg_read_u32(&ig_dev, &membase2, 0x18);
-      if (membase2 & 0x08000000)
-	aper_size = 0x8000000;
-      else
-	aper_size = 0x10000000;
-
-      fprintf(stderr,"aper size is %08X %08x %d\n", aper_size, membase2, ret);
-    } else
-      aper_size = 0x8000000;
-  }
-
-  pI830->aper_size = aper_size;
-
-
-  /* We need to reduce the stolen size, by the GTT and the popup.
-   * The GTT varying according the the FbMapSize and the popup is 4KB */
-  range = (ctx->shared.fbSize / (1024*1024)) + 4;
-
-   if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-      case I855_GMCH_GMS_STOLEN_1M:
-	 memsize = MB(1) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_4M:
-	 memsize = MB(4) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_8M:
-	 memsize = MB(8) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_16M:
-	 memsize = MB(16) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_32M:
-	 memsize = MB(32) - KB(range);
-	 break;
-      case I915G_GMCH_GMS_STOLEN_48M:
-	 if (IS_I9XX(pI830))
-	    memsize = MB(48) - KB(range);
-	 break;
-      case I915G_GMCH_GMS_STOLEN_64M:
-	 if (IS_I9XX(pI830))
-	    memsize = MB(64) - KB(range);
-	 break;
-      }
-   } else {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-      case I830_GMCH_GMS_STOLEN_512:
-	 memsize = KB(512) - KB(range);
-	 break;
-      case I830_GMCH_GMS_STOLEN_1024:
-	 memsize = MB(1) - KB(range);
-	 break;
-      case I830_GMCH_GMS_STOLEN_8192:
-	 memsize = MB(8) - KB(range);
-	 break;
-      case I830_GMCH_GMS_LOCAL:
-	 memsize = 0;
-	 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		    "Local memory found, but won't be used.\n");
-	 break;
-      }
-   }
-   if (memsize > 0) {
-     fprintf(stderr,
-		 "detected %d kB stolen memory.\n", memsize / 1024);
-   } else {
-     fprintf(stderr,
-		 "no video memory detected.\n");
-   }
-   return memsize;
-}
-
-static int AgpInit(const DRIDriverContext *ctx, I830Rec *info)
-{
-  unsigned long mode = 0x4;
-
-  if (drmAgpAcquire(ctx->drmFD) < 0) {
-    fprintf(stderr, "[gart] AGP not available\n");
-    return 0;
-  }
-  
-  if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-    fprintf(stderr, "[gart] AGP not enabled\n");
-    drmAgpRelease(ctx->drmFD);
-    return 0;
-  }
-  else
-    fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
-
-  return 1;
-}
-
-/*
- * Allocate memory from the given pool.  Grow the pool if needed and if
- * possible.
- */
-static unsigned long
-AllocFromPool(const DRIDriverContext *ctx, I830Rec *pI830, 
-	      I830MemRange *result, I830MemPool *pool,
-	      long size, unsigned long alignment, int flags)
-{
-   long needed, start, end;
-
-   if (!result || !pool || !size)
-      return 0;
-
-   /* Calculate how much space is needed. */
-   if (alignment <= GTT_PAGE_SIZE)
-      needed = size;
-   else {
-	 start = ROUND_TO(pool->Free.Start, alignment);
-	 end = ROUND_TO(start + size, alignment);
-	 needed = end - pool->Free.Start;
-   }
-   if (needed > pool->Free.Size) {
-     return 0;
-   }
-
-   result->Start = ROUND_TO(pool->Free.Start, alignment);
-   pool->Free.Start += needed;
-   result->End = pool->Free.Start;
-
-   pool->Free.Size = pool->Free.End - pool->Free.Start;
-   result->Size = result->End - result->Start;
-   result->Pool = pool;
-   result->Alignment = alignment;
-   return needed;
-}
-
-static unsigned long AllocFromAGP(const DRIDriverContext *ctx, I830Rec *pI830, long size, unsigned long alignment, I830MemRange  *result)
-{
-   unsigned long start, end;
-   unsigned long newApStart, newApEnd;
-   int ret;
-   if (!result || !size)
-      return 0;
-   
-   if (!alignment)
-     alignment = 4;
-
-   start = ROUND_TO(pI830->MemoryAperture.Start, alignment);
-   end = ROUND_TO(start + size, alignment);
-   newApStart = end;
-   newApEnd = pI830->MemoryAperture.End;
-
-   ret=drmAgpAlloc(ctx->drmFD, size, 0, &(result->Physical), (drm_handle_t *)&(result->Key));
-   
-   if (ret)
-   {
-     fprintf(stderr,"drmAgpAlloc failed %d\n", ret);
-     return 0;
-   }
-   pI830->allocatedMemory += size;
-   pI830->MemoryAperture.Start = newApStart;
-   pI830->MemoryAperture.End = newApEnd;
-   pI830->MemoryAperture.Size = newApEnd - newApStart;
-   //   pI830->FreeMemory -= size;
-   result->Start = start;
-   result->End = start + size;
-   result->Size = size;
-   result->Offset = start;
-   result->Alignment = alignment;
-   result->Pool = NULL;
-  
-   return size;
-}
-
-unsigned long
-I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830,
-                I830MemRange *result, I830MemPool *pool, long size,
-                unsigned long alignment, int flags)
-{
-   unsigned long ret;
-
-   if (!result)
-      return 0;
-
-   /* Make sure these are initialised. */
-   result->Size = 0;
-   result->Key = -1;
-
-   if (!size) {
-      return 0;
-   }
-
-   if (pool->Free.Size < size) {
-      ret = AllocFromAGP(ctx, pI830, size, alignment, result);
-   }
-   else {
-      ret = AllocFromPool(ctx, pI830, result, pool, size, alignment, flags);
-      if (ret == 0)
-         ret = AllocFromAGP(ctx, pI830, size, alignment, result);
-   }
-   return ret;
-}
-
-static Bool BindAgpRange(const DRIDriverContext *ctx, I830MemRange *mem)
-{
-  if (!mem)
-    return FALSE;
-  
-  if (mem->Key == -1)
-    return TRUE;
-
-  return !drmAgpBind(ctx->drmFD, mem->Key, mem->Offset);
-}
-
-/* simple memory allocation routines needed */
-/* put ring buffer in low memory */
-/* need to allocate front, back, depth buffers aligned correctly,
-   allocate ring buffer, 
-*/
-
-/* */
-static Bool
-I830AllocateMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned long size, ret;
-  unsigned long lines, lineSize, align;
-
-  /* allocate ring buffer */
-  memset(pI830->LpRing, 0, sizeof(I830RingBuffer));
-  pI830->LpRing->mem.Key = -1;
-
-  size = PRIMARY_RINGBUFFER_SIZE;
-  
-  ret = I830AllocVidMem(ctx, pI830, &pI830->LpRing->mem, &pI830->StolenPool, size, 0x1000, 0);
-  
-  if (ret != size)
-  {
-    fprintf(stderr,"unable to allocate ring buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  pI830->LpRing->tail_mask = pI830->LpRing->mem.Size - 1;
-
-  
-  /* allocate front buffer */
-  memset(&(pI830->FrontBuffer), 0, sizeof(pI830->FrontBuffer));
-  pI830->FrontBuffer.Key = -1;
-  pI830->FrontBuffer.Pitch = ctx->shared.virtualWidth;
-
-  align = KB(512);  
-
-  lineSize = ctx->shared.virtualWidth * ctx->cpp;
-  lines = (ctx->shared.virtualHeight + 15) / 16 * 16;
-  size = lineSize * lines;
-  size = ROUND_TO_PAGE(size);
-
-  align = GetBestTileAlignment(size);
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->FrontBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate front buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  memset(&(pI830->BackBuffer), 0, sizeof(pI830->BackBuffer));
-  pI830->BackBuffer.Key = -1;
-  pI830->BackBuffer.Pitch = ctx->shared.virtualWidth;
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->BackBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate back buffer %ld\n", ret);
-    return FALSE;
-  }
-  
-  memset(&(pI830->DepthBuffer), 0, sizeof(pI830->DepthBuffer));
-  pI830->DepthBuffer.Key = -1;
-  pI830->DepthBuffer.Pitch = ctx->shared.virtualWidth;
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->DepthBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate depth buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  memset(&(pI830->ContextMem), 0, sizeof(pI830->ContextMem));
-  pI830->ContextMem.Key = -1;
-  size = KB(32);
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->ContextMem, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate context buffer %ld\n", ret);
-    return FALSE;
-  }
-
-#if 0  
-  memset(&(pI830->TexMem), 0, sizeof(pI830->TexMem));
-  pI830->TexMem.Key = -1;
-
-  size = 32768 * 1024;
-  ret = AllocFromAGP(ctx, pI830, size, align, &pI830->TexMem);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate texture memory %ld\n", ret);
-    return FALSE;
-  }
-#endif
-
-  return TRUE;
-}
-
-static Bool
-I830BindMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  if (!BindAgpRange(ctx, &pI830->LpRing->mem))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->FrontBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->BackBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->DepthBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->ContextMem))
-    return FALSE;
-#if 0
-  if (!BindAgpRange(ctx, &pI830->TexMem))
-    return FALSE;
-#endif
-  return TRUE;
-}
-
-static void SetupDRIMM(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned long aperEnd = ROUND_DOWN_TO(pI830->aper_size, GTT_PAGE_SIZE) / GTT_PAGE_SIZE;
-  unsigned long aperStart = ROUND_TO(pI830->aper_size - KB(32768), GTT_PAGE_SIZE) / GTT_PAGE_SIZE;
-
-  fprintf(stderr, "aper size is %08X\n", ctx->shared.fbSize);
-  if (drmMMInit(ctx->drmFD, aperStart, aperEnd - aperStart, DRM_BO_MEM_TT)) {
-      fprintf(stderr,
-	      "DRM MM Initialization Failed\n");
-  } else {
-    fprintf(stderr,
-	    "DRM MM Initialized at offset 0x%lx length %d page\n", aperStart, aperEnd-aperStart);
-  }
-
-}
-
-static Bool
-I830CleanupDma(const DRIDriverContext *ctx)
-{
-   drmI830Init info;
-
-   memset(&info, 0, sizeof(drmI830Init));
-   info.func = I830_CLEANUP_DMA;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT,
-		       &info, sizeof(drmI830Init))) {
-     fprintf(stderr, "I830 Dma Cleanup Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static Bool
-I830InitDma(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-   I830RingBuffer *ring = pI830->LpRing;
-   drmI830Init info;
-
-   memset(&info, 0, sizeof(drmI830Init));
-   info.func = I830_INIT_DMA;
-
-   info.ring_start = ring->mem.Start + pI830->LinearAddr;
-   info.ring_end = ring->mem.End + pI830->LinearAddr;
-   info.ring_size = ring->mem.Size;
-
-   info.mmio_offset = (unsigned int)ctx->MMIOStart;
-
-   info.sarea_priv_offset = sizeof(drm_sarea_t);
-
-   info.front_offset = pI830->FrontBuffer.Start;
-   info.back_offset = pI830->BackBuffer.Start;
-   info.depth_offset = pI830->DepthBuffer.Start;
-   info.w = ctx->shared.virtualWidth;
-   info.h = ctx->shared.virtualHeight;
-   info.pitch = ctx->shared.virtualWidth;
-   info.back_pitch = pI830->BackBuffer.Pitch;
-   info.depth_pitch = pI830->DepthBuffer.Pitch;
-   info.cpp = ctx->cpp;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT,
-		       &info, sizeof(drmI830Init))) {
-      fprintf(stderr,
-		 "I830 Dma Initialization Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static int I830CheckDRMVersion( const DRIDriverContext *ctx,
-				  I830Rec *pI830 )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-
-   if (version) {
-     int req_minor, req_patch;
-
-     req_minor = 4;
-     req_patch = 0;	
-
-     if (version->version_major != 1 ||
-	 version->version_minor < req_minor ||
-	 (version->version_minor == req_minor && 
-	  version->version_patchlevel < req_patch)) {
-       /* Incompatible drm version */
-       fprintf(stderr,
-	       "[dri] I830DRIScreenInit failed because of a version "
-	       "mismatch.\n"
-	       "[dri] i915.o kernel module version is %d.%d.%d "
-	       "but version 1.%d.%d or newer is needed.\n"
-	       "[dri] Disabling DRI.\n",
-	       version->version_major,
-	       version->version_minor,
-	       version->version_patchlevel,
-	       req_minor,
-	       req_patch);
-       drmFreeVersion(version);
-       return 0;
-     }
-     
-     pI830->drmMinor = version->version_minor;
-     drmFreeVersion(version);
-   }
-   return 1;
-}
-
-static void
-I830SetRingRegs(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned int itemp;
-  unsigned char *MMIO = ctx->MMIOAddress;
-
-   OUTREG(LP_RING + RING_LEN, 0);
-   OUTREG(LP_RING + RING_TAIL, 0);
-   OUTREG(LP_RING + RING_HEAD, 0);
-
-   if ((long)(pI830->LpRing->mem.Start & I830_RING_START_MASK) !=
-       pI830->LpRing->mem.Start) {
-      fprintf(stderr,
-		 "I830SetRingRegs: Ring buffer start (%lx) violates its "
-		 "mask (%x)\n", pI830->LpRing->mem.Start, I830_RING_START_MASK);
-   }
-   /* Don't care about the old value.  Reserved bits must be zero anyway. */
-   itemp = pI830->LpRing->mem.Start & I830_RING_START_MASK;
-   OUTREG(LP_RING + RING_START, itemp);
-
-   if (((pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES) !=
-       pI830->LpRing->mem.Size - 4096) {
-      fprintf(stderr,
-		 "I830SetRingRegs: Ring buffer size - 4096 (%lx) violates its "
-		 "mask (%x)\n", pI830->LpRing->mem.Size - 4096,
-		 I830_RING_NR_PAGES);
-   }
-   /* Don't care about the old value.  Reserved bits must be zero anyway. */
-   itemp = (pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES;
-   itemp |= (RING_NO_REPORT | RING_VALID);
-   OUTREG(LP_RING + RING_LEN, itemp);
-
-   pI830->LpRing->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
-   pI830->LpRing->tail = INREG(LP_RING + RING_TAIL);
-   pI830->LpRing->space = pI830->LpRing->head - (pI830->LpRing->tail + 8);
-   if (pI830->LpRing->space < 0)
-      pI830->LpRing->space += pI830->LpRing->mem.Size;
-
-   SetFenceRegs(ctx, pI830);
-   
-   /* RESET THE DISPLAY PIPE TO POINT TO THE FRONTBUFFER - hacky
-      hacky hacky */
-   OUTREG(DSPABASE, pI830->FrontBuffer.Start + pI830->LinearAddr);
-
-}
-
-static Bool
-I830SetParam(const DRIDriverContext *ctx, int param, int value)
-{
-   drmI830SetParam sp;
-
-   memset(&sp, 0, sizeof(sp));
-   sp.param = param;
-   sp.value = value;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_SETPARAM, &sp, sizeof(sp))) {
-      fprintf(stderr, "I830 SetParam Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static Bool
-I830DRIMapScreenRegions(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-   fprintf(stderr,
-              "[drm] Mapping front buffer\n");
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
-                 sarea->front_size,
-                 DRM_FRAME_BUFFER,  /*DRM_AGP,*/
-                 0,
-                 &sarea->front_handle) < 0) {
-     fprintf(stderr,
-	     "[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   ctx->shared.hFrameBuffer = sarea->front_handle;
-   ctx->shared.fbSize = sarea->front_size;
-   fprintf(stderr, "[drm] Front Buffer = 0x%08x\n",
-	   sarea->front_handle);
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)(sarea->back_offset),
-                 sarea->back_size, DRM_AGP, 0,
-                 &sarea->back_handle) < 0) {
-      fprintf(stderr,
-                 "[drm] drmAddMap(back_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] Back Buffer = 0x%08x\n",
-              sarea->back_handle);
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)sarea->depth_offset,
-                 sarea->depth_size, DRM_AGP, 0,
-                 &sarea->depth_handle) < 0) {
-      fprintf(stderr,
-                 "[drm] drmAddMap(depth_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] Depth Buffer = 0x%08x\n",
-              sarea->depth_handle);
-
-#if 0
-   if (drmAddMap(ctx->drmFD,
-		 (drm_handle_t)sarea->tex_offset,
-		 sarea->tex_size, DRM_AGP, 0,
-		 &sarea->tex_handle) < 0) {
-      fprintf(stderr,
-		 "[drm] drmAddMap(tex_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] textures = 0x%08x\n",
-	      sarea->tex_handle);
-#endif
-   return TRUE;
-}
-
-
-static void
-I830DRIUnmapScreenRegions(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-#if 1
-   if (sarea->front_handle) {
-      drmRmMap(ctx->drmFD, sarea->front_handle);
-      sarea->front_handle = 0;
-   }
-#endif
-   if (sarea->back_handle) {
-      drmRmMap(ctx->drmFD, sarea->back_handle);
-      sarea->back_handle = 0;
-   }
-   if (sarea->depth_handle) {
-      drmRmMap(ctx->drmFD, sarea->depth_handle);
-      sarea->depth_handle = 0;
-   }
-   if (sarea->tex_handle) {
-      drmRmMap(ctx->drmFD, sarea->tex_handle);
-      sarea->tex_handle = 0;
-   }
-}
-
-static Bool
-I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-  if (drmAddMap(ctx->drmFD,
-		(drm_handle_t)pI830->LpRing->mem.Start,
-		pI830->LpRing->mem.Size, DRM_AGP, 0,
-		&pI830->ring_map) < 0) {
-    fprintf(stderr,
-	    "[drm] drmAddMap(ring_map) failed. Disabling DRI\n");
-    return FALSE;
-  }
-  fprintf(stderr, "[drm] ring buffer = 0x%08x\n",
-	  pI830->ring_map);
-
-  if (I830InitDma(ctx, pI830) == FALSE) {
-    return FALSE;
-  }
-  
-   /* init to zero to be safe */
-
-  I830DRIMapScreenRegions(ctx, pI830, sarea);
-  SetupDRIMM(ctx, pI830);
-
-   if (ctx->pciDevice != PCI_CHIP_845_G &&
-       ctx->pciDevice != PCI_CHIP_I830_M) {
-      I830SetParam(ctx, I830_SETPARAM_USE_MI_BATCHBUFFER_START, 1 );
-   }
-
-   /* Okay now initialize the dma engine */
-   {
-      pI830->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					    ctx->pciBus,
-					    ctx->pciDevice,
-					    ctx->pciFunc);
-
-      if (drmCtlInstHandler(ctx->drmFD, pI830->irq)) {
-	 fprintf(stderr,
-		    "[drm] failure adding irq handler\n");
-	 pI830->irq = 0;
-	 return FALSE;
-      }
-      else
-	 fprintf(stderr,
-		    "[drm] dma control initialized, using IRQ %d\n",
-		    pI830->irq);
-   }
-
-   fprintf(stderr, "[dri] visual configs initialized\n");
-
-   return TRUE;
-}
-
-static Bool
-I830ClearScreen(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-  /* need to drmMap front and back buffers and zero them */
-  drmAddress map_addr;
-  int ret;
-
-  ret = drmMap(ctx->drmFD,
-	       sarea->front_handle,
-	       sarea->front_size,
-	       &map_addr);
-
-  if (ret)
-  {
-    fprintf(stderr, "Unable to map front buffer\n");
-    return FALSE;
-  }
-
-  drimemsetio((char *)map_addr,
-	      0,
-	      sarea->front_size);
-  drmUnmap(map_addr, sarea->front_size);
-
-
-  ret = drmMap(ctx->drmFD,
-	       sarea->back_handle,
-	       sarea->back_size,
-	       &map_addr);
-
-  if (ret)
-  {
-    fprintf(stderr, "Unable to map back buffer\n");
-    return FALSE;
-  }
-
-  drimemsetio((char *)map_addr,
-	      0,
-	      sarea->back_size);
-  drmUnmap(map_addr, sarea->back_size);
-
-  return TRUE;
-}
-
-static Bool
-I830ScreenInit(DRIDriverContext *ctx, I830Rec *pI830)
-		  
-{
-   I830DRIPtr pI830DRI;
-   drmI830Sarea *pSAREAPriv;
-   int err;
-      
-   drm_page_size = getpagesize();   
-
-   pI830->registerSize = ctx->MMIOSize;
-   /* This is a hack for now.  We have to have more than a 4k page here
-    * because of the size of the state.  However, the state should be
-    * in a per-context mapping.  This will be added in the Mesa 3.5 port
-    * of the I830 driver.
-    */
-   ctx->shared.SAREASize = SAREA_MAX;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("i915", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-     fprintf(stderr, "[drm] drmAddMap failed\n");
-     return 0;
-   }
-
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08x\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-   
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   
-   }
-   
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08x to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pI830->registerHandle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08x\n", pI830->registerHandle);
-
-
-   if (!I830CheckDRMVersion(ctx, pI830)) {
-     return FALSE;
-   }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the SAREA private data structure */
-   pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + 
-				 sizeof(drm_sarea_t));
-   memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
-   pI830->StolenMemory.Size = I830DetectMemory(ctx, pI830);
-   pI830->StolenMemory.Start = 0;
-   pI830->StolenMemory.End = pI830->StolenMemory.Size;
-
-   pI830->MemoryAperture.Start = pI830->StolenMemory.End;
-   pI830->MemoryAperture.End = KB(40000);
-   pI830->MemoryAperture.Size = pI830->MemoryAperture.End - pI830->MemoryAperture.Start;
-
-   pI830->StolenPool.Fixed = pI830->StolenMemory;
-   pI830->StolenPool.Total = pI830->StolenMemory;
-   pI830->StolenPool.Free = pI830->StolenPool.Total;
-   pI830->FreeMemory = pI830->StolenPool.Total.Size;
-
-   if (!AgpInit(ctx, pI830))
-     return FALSE;
-
-   if (I830AllocateMemory(ctx, pI830) == FALSE)
-   {
-     return FALSE;
-   }
-
-   if (I830BindMemory(ctx, pI830) == FALSE)
-   {
-     return FALSE;
-   }
-
-   pSAREAPriv->rotated_offset = -1;
-   pSAREAPriv->rotated_size = 0;
-   pSAREAPriv->rotated_pitch = ctx->shared.virtualWidth;
-
-   pSAREAPriv->front_offset = pI830->FrontBuffer.Start;
-   pSAREAPriv->front_size = pI830->FrontBuffer.Size;
-   pSAREAPriv->width = ctx->shared.virtualWidth;
-   pSAREAPriv->height = ctx->shared.virtualHeight;
-   pSAREAPriv->pitch = ctx->shared.virtualWidth;
-   pSAREAPriv->virtualX = ctx->shared.virtualWidth;
-   pSAREAPriv->virtualY = ctx->shared.virtualHeight;
-   pSAREAPriv->back_offset = pI830->BackBuffer.Start;
-   pSAREAPriv->back_size = pI830->BackBuffer.Size;
-   pSAREAPriv->depth_offset = pI830->DepthBuffer.Start;
-   pSAREAPriv->depth_size = pI830->DepthBuffer.Size;
-#if 0
-   pSAREAPriv->tex_offset = pI830->TexMem.Start;
-   pSAREAPriv->tex_size = pI830->TexMem.Size;
-#endif
-   pSAREAPriv->log_tex_granularity = pI830->TexGranularity;
-
-   ctx->driverClientMsg = malloc(sizeof(I830DRIRec));
-   ctx->driverClientMsgSize = sizeof(I830DRIRec);
-   pI830DRI = (I830DRIPtr)ctx->driverClientMsg;
-   pI830DRI->deviceID = pI830->Chipset;
-   pI830DRI->regsSize = I830_REG_SIZE;
-   pI830DRI->width = ctx->shared.virtualWidth;
-   pI830DRI->height = ctx->shared.virtualHeight;
-   pI830DRI->mem = ctx->shared.fbSize;
-   pI830DRI->cpp = ctx->cpp;
-
-   pI830DRI->bitsPerPixel = ctx->bpp;
-   pI830DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-   
-   err = I830DRIDoMappings(ctx, pI830, pSAREAPriv);
-   if (err == FALSE)
-       return FALSE;
-
-   I830SetupMemoryTiling(ctx, pI830);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   I830ClearScreen(ctx, pI830, pSAREAPriv);
-
-   I830SetRingRegs(ctx, pI830);
-
-   return TRUE;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int i830ValidateMode( const DRIDriverContext *ctx )
-{
-  return 1;
-}
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i830PostValidateMode( const DRIDriverContext *ctx )
-{
-  I830Rec *pI830 = ctx->driverPrivate;
-
-  I830SetRingRegs(ctx, pI830);
-  return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls I810ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int i830InitFBDev( DRIDriverContext *ctx )
-{
-  I830Rec *pI830 = calloc(1, sizeof(I830Rec));
-  int i;
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-      ctx->shared.Width = ctx->shared.virtualWidth;
-   }
-
-
-   for (i = 0; pitches[i] != 0; i++) {
-     if (pitches[i] >= ctx->shared.virtualWidth) {
-       ctx->shared.virtualWidth = pitches[i];
-       break;
-     }
-   }
-
-   ctx->driverPrivate = (void *)pI830;
-   
-   pI830->LpRing = calloc(1, sizeof(I830RingBuffer));
-   pI830->Chipset = ctx->chipset;
-   pI830->LinearAddr = ctx->FBStart;
-
-   if (!I830ScreenInit( ctx, pI830 ))
-      return 0;
-
-   
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void i830HaltFBDev( DRIDriverContext *ctx )
-{
-  drmI830Sarea *pSAREAPriv;
-  I830Rec *pI830 = ctx->driverPrivate;
-
-   if (pI830->irq) {
-       drmCtlUninstHandler(ctx->drmFD);
-       pI830->irq = 0;   }
-
-   I830CleanupDma(ctx);
-
-  pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + 
-				sizeof(drm_sarea_t));
-
-  I830DRIUnmapScreenRegions(ctx, pI830, pSAREAPriv);
-  drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-  drmClose(ctx->drmFD);
-  
-  if (ctx->driverPrivate) {
-    free(ctx->driverPrivate);
-    ctx->driverPrivate = 0;
-  }
-}
-
-
-extern void i810NotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   i830ValidateMode,
-   i830PostValidateMode,
-   i830InitFBDev,
-   i830HaltFBDev,
-   NULL,//I830EngineShutdown,
-   NULL, //I830EngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   i810NotifyFocus, 
-#endif
-};
diff --git a/src/mesa/drivers/dri/mach64/Makefile b/src/mesa/drivers/dri/mach64/Makefile
index a8f463e9fd0..c20fdece297 100644
--- a/src/mesa/drivers/dri/mach64/Makefile
+++ b/src/mesa/drivers/dri/mach64/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = mach64_dri.so
 
-# Not yet
-# MINIGLX_SOURCES = server/mach64_dri.c 
-
 DRIVER_SOURCES = \
 	mach64_context.c \
 	mach64_ioctl.c \
diff --git a/src/mesa/drivers/dri/mga/Makefile b/src/mesa/drivers/dri/mga/Makefile
index 0cc329fb22d..92533bccc29 100644
--- a/src/mesa/drivers/dri/mga/Makefile
+++ b/src/mesa/drivers/dri/mga/Makefile
@@ -5,8 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = mga_dri.so
 
-MINIGLX_SOURCES = server/mga_dri.c 
-
 DRIVER_SOURCES = \
 	mgadd.c \
 	mgaioctl.c \
diff --git a/src/mesa/drivers/dri/mga/server/mga_dri.c b/src/mesa/drivers/dri/mga/server/mga_dri.c
deleted file mode 100644
index bc575e62ee8..00000000000
--- a/src/mesa/drivers/dri/mga/server/mga_dri.c
+++ /dev/null
@@ -1,1088 +0,0 @@
-
-/*
- * Copyright 2000 VA Linux Systems Inc., Fremont, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Keith Whitwell <[email protected]>
- *    Gareth Hughes <[email protected]>
- */
-
-#include <errno.h>
-#include <unistd.h>
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <inttypes.h>
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "mga_reg.h"
-#include "mga.h"
-#include "mga_macros.h"
-#include "mga_dri.h"
-
-
-/* Quiescence, locking
- */
-#define MGA_TIMEOUT		2048
-
-static void MGAWaitForIdleDMA( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   drm_lock_t lock;
-   int ret;
-   int i = 0;
-
-   memset( &lock, 0, sizeof(lock) );
-
-   for (;;) {
-      do {
-         /* first ask for quiescent and flush */
-         lock.flags = DRM_LOCK_QUIESCENT | DRM_LOCK_FLUSH;
-         do {
-	    ret = drmCommandWrite( ctx->drmFD, DRM_MGA_FLUSH,
-                                   &lock, sizeof( lock ) );
-         } while ( ret == -EBUSY && i++ < DRM_MGA_IDLE_RETRY );
-
-         /* if it's still busy just try quiescent */
-         if ( ret == -EBUSY ) { 
-            lock.flags = DRM_LOCK_QUIESCENT;
-            do {
-	       ret = drmCommandWrite( ctx->drmFD, DRM_MGA_FLUSH,
-                                      &lock, sizeof( lock ) );
-            } while ( ret == -EBUSY && i++ < DRM_MGA_IDLE_RETRY );
-         }
-      } while ( ( ret == -EBUSY ) && ( i++ < MGA_TIMEOUT ) );
-
-      if ( ret == 0 )
-	 return;
-
-      fprintf( stderr,
-               "[dri] Idle timed out, resetting engine...\n" );
-
-      drmCommandNone( ctx->drmFD, DRM_MGA_RESET );
-   }
-}
-
-static unsigned int mylog2( unsigned int n )
-{
-   unsigned int log2 = 1;
-   while ( n > 1 ) n >>= 1, log2++;
-   return log2;
-}
-
-static int MGADRIAgpInit(struct DRIDriverContextRec *ctx, MGAPtr pMga)
-{
-   unsigned long mode;
-   unsigned int vendor, device;
-   int ret, count, i;
-
-   if(pMga->agpSize < 12)pMga->agpSize = 12;
-   if(pMga->agpSize > 64)pMga->agpSize = 64; /* cap */
-
-   /* FIXME: Make these configurable...
-    */
-   pMga->agp.size = pMga->agpSize * 1024 * 1024;
-
-   pMga->warp.offset = 0;
-   pMga->warp.size = MGA_WARP_UCODE_SIZE;
-
-   pMga->primary.offset = (pMga->warp.offset +
-				    pMga->warp.size);
-   pMga->primary.size = 1024 * 1024;
-
-   pMga->buffers.offset = (pMga->primary.offset +
-				    pMga->primary.size);
-   pMga->buffers.size = MGA_NUM_BUFFERS * MGA_BUFFER_SIZE;
-
-
-   pMga->agpTextures.offset = (pMga->buffers.offset +
-                                    pMga->buffers.size);
-
-   pMga->agpTextures.size = pMga->agp.size -
-                                     pMga->agpTextures.offset;
-
-   if ( drmAgpAcquire( ctx->drmFD ) < 0 ) {
-     fprintf( stderr, "[agp] AGP not available\n" );
-      return 0;
-   }
-
-   mode   = drmAgpGetMode( ctx->drmFD );        /* Default mode */
-   vendor = drmAgpVendorId( ctx->drmFD );
-   device = drmAgpDeviceId( ctx->drmFD );
-
-   mode &= ~MGA_AGP_MODE_MASK;
-   switch ( pMga->agpMode ) {
-   case 4:
-      mode |= MGA_AGP_4X_MODE;
-   case 2:
-      mode |= MGA_AGP_2X_MODE;
-   case 1:
-   default:
-      mode |= MGA_AGP_1X_MODE;
-   }
-
-#if 0
-   fprintf( stderr,
-            "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
-            mode, vendor, device,
-            ctx->pciVendor,
-            ctx->pciChipType );
-#endif
-
-   if ( drmAgpEnable( ctx->drmFD, mode ) < 0 ) {
-     fprintf( stderr, "[agp] AGP not enabled\n" );
-      drmAgpRelease( ctx->drmFD );
-      return 0;
-   }
-
-   if ( pMga->Chipset == PCI_CHIP_MGAG200 ) {
-      switch ( pMga->agpMode ) {
-      case 2:
-	 fprintf( stderr,
-		     "[drm] Enabling AGP 2x PLL encoding\n" );
-	 OUTREG( MGAREG_AGP_PLL, MGA_AGP2XPLL_ENABLE );
-	 break;
-
-      case 1:
-      default:
-	 fprintf( stderr,
-		     "[drm] Disabling AGP 2x PLL encoding\n" );
-	 OUTREG( MGAREG_AGP_PLL, MGA_AGP2XPLL_DISABLE );
-	 pMga->agpMode = 1;
-	 break;
-      }
-   }
-
-   ret = drmAgpAlloc( ctx->drmFD, pMga->agp.size,
-		      0, NULL, &pMga->agp.handle );
-   if ( ret < 0 ) {
-      fprintf( stderr, "[agp] Out of memory (%d)\n", ret );
-      drmAgpRelease( ctx->drmFD );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] %d kB allocated with handle 0x%08x\n",
-	       pMga->agp.size/1024, (unsigned int)pMga->agp.handle );
-
-   if ( drmAgpBind( ctx->drmFD, pMga->agp.handle, 0 ) < 0 ) {
-      fprintf( stderr, "[agp] Could not bind memory\n" );
-      drmAgpFree( ctx->drmFD, pMga->agp.handle );
-      drmAgpRelease( ctx->drmFD );
-      return 0;
-   }
-
-   /* WARP microcode space
-    */
-   if ( drmAddMap( ctx->drmFD,
-		   pMga->warp.offset,
-		   pMga->warp.size,
-		   DRM_AGP, DRM_READ_ONLY,
-		   &pMga->warp.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not add WARP microcode mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[agp] WARP microcode handle = 0x%08x\n",
-	       pMga->warp.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->warp.handle,
-		pMga->warp.size,
-		&pMga->warp.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map WARP microcode\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] WARP microcode mapped at 0x%08lx\n",
-	       (unsigned long)pMga->warp.map );
-
-   /* Primary DMA space
-    */
-   if ( drmAddMap( ctx->drmFD,
-		   pMga->primary.offset,
-		   pMga->primary.size,
-		   DRM_AGP, DRM_READ_ONLY,
-		   &pMga->primary.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not add primary DMA mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[agp] Primary DMA handle = 0x%08x\n",
-	       pMga->primary.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->primary.handle,
-		pMga->primary.size,
-		&pMga->primary.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map primary DMA\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] Primary DMA mapped at 0x%08lx\n",
-	       (unsigned long)pMga->primary.map );
-
-   /* DMA buffers
-    */
-   if ( drmAddMap( ctx->drmFD,
-		   pMga->buffers.offset,
-		   pMga->buffers.size,
-		   DRM_AGP, 0,
-		   &pMga->buffers.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not add DMA buffers mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[agp] DMA buffers handle = 0x%08x\n",
-	       pMga->buffers.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->buffers.handle,
-		pMga->buffers.size,
-		&pMga->buffers.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map DMA buffers\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] DMA buffers mapped at 0x%08lx\n",
-	       (unsigned long)pMga->buffers.map );
-
-   count = drmAddBufs( ctx->drmFD,
-		       MGA_NUM_BUFFERS, MGA_BUFFER_SIZE,
-		       DRM_AGP_BUFFER, pMga->buffers.offset );
-   if ( count <= 0 ) {
-      fprintf( stderr,
-		  "[drm] failure adding %d %d byte DMA buffers\n",
-		  MGA_NUM_BUFFERS, MGA_BUFFER_SIZE );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[drm] Added %d %d byte DMA buffers\n",
-	       count, MGA_BUFFER_SIZE );
-
-   i = mylog2(pMga->agpTextures.size / MGA_NR_TEX_REGIONS);
-   if(i < MGA_LOG_MIN_TEX_REGION_SIZE)
-      i = MGA_LOG_MIN_TEX_REGION_SIZE;
-   pMga->agpTextures.size = (pMga->agpTextures.size >> i) << i;
-
-   if ( drmAddMap( ctx->drmFD,
-                   pMga->agpTextures.offset,
-                   pMga->agpTextures.size,
-                   DRM_AGP, 0,
-                   &pMga->agpTextures.handle ) < 0 ) {
-      fprintf( stderr,
-                  "[agp] Could not add agpTexture mapping\n" );
-      return 0;
-   }
-/* should i map it ? */
-   fprintf( stderr,
-               "[agp] agpTexture handle = 0x%08x\n",
-               pMga->agpTextures.handle );
-   fprintf( stderr,
-               "[agp] agpTexture size: %d kb\n", pMga->agpTextures.size/1024 );
-
-   return 1;
-}
-
-static int MGADRIMapInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   pMga->registers.size = MGAIOMAPSIZE;
-
-   if ( drmAddMap( ctx->drmFD,
-		   (drm_handle_t)pMga->IOAddress,
-		   pMga->registers.size,
-		   DRM_REGISTERS, DRM_READ_ONLY,
-		   &pMga->registers.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[drm] Could not add MMIO registers mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[drm] Registers handle = 0x%08lx\n",
-	       pMga->registers.handle );
-
-   pMga->status.size = SAREA_MAX;
-
-   if ( drmAddMap( ctx->drmFD, 0, pMga->status.size,
-		   DRM_SHM, DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
-		   &pMga->status.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[drm] Could not add status page mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[drm] Status handle = 0x%08x\n",
-	       pMga->status.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->status.handle,
-		pMga->status.size,
-		&pMga->status.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map status page\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] Status page mapped at 0x%08lx\n",
-	       (unsigned long)pMga->status.map );
-
-   return 1;
-}
-
-static int MGADRIKernelInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   drm_mga_init_t init;
-   int ret;
-
-   memset( &init, 0, sizeof(init) );
-
-   init.func = MGA_INIT_DMA;
-   init.sarea_priv_offset = sizeof(drm_sarea_t);
-
-   switch ( pMga->Chipset ) {
-   case PCI_CHIP_MGAG550:
-   case PCI_CHIP_MGAG400:
-      init.chipset = MGA_CARD_TYPE_G400;
-      break;
-   case PCI_CHIP_MGAG200:
-   case PCI_CHIP_MGAG200_PCI:
-      init.chipset = MGA_CARD_TYPE_G200;
-      break;
-   default:
-      return 0;
-   }
-
-   init.sgram = 0; /* FIXME !pMga->HasSDRAM; */
-
-
-   switch (ctx->bpp)
-     {
-     case 16:
-       init.maccess = MGA_MACCESS_PW16;
-       break;
-     case 32:
-       init.maccess = MGA_MACCESS_PW32;
-       break;
-     default:
-       fprintf( stderr, "[mga] invalid bpp (%d)\n", ctx->bpp );
-       return 0;
-     }
-
-
-   init.fb_cpp		= ctx->bpp / 8;
-   init.front_offset	= pMga->frontOffset;
-   init.front_pitch	= pMga->frontPitch / init.fb_cpp;
-   init.back_offset	= pMga->backOffset;
-   init.back_pitch	= pMga->backPitch / init.fb_cpp;
-
-   init.depth_cpp	= ctx->bpp / 8;
-   init.depth_offset	= pMga->depthOffset;
-   init.depth_pitch	= pMga->depthPitch / init.depth_cpp;
-
-   init.texture_offset[0] = pMga->textureOffset;
-   init.texture_size[0] = pMga->textureSize;
-
-   init.fb_offset = ctx->shared.hFrameBuffer;
-   init.mmio_offset = pMga->registers.handle;
-   init.status_offset = pMga->status.handle;
-
-   init.warp_offset = pMga->warp.handle;
-   init.primary_offset = pMga->primary.handle;
-   init.buffers_offset = pMga->buffers.handle;
-
-   init.texture_offset[1] = pMga->agpTextures.handle;
-   init.texture_size[1] = pMga->agpTextures.size;
-
-   ret = drmCommandWrite( ctx->drmFD, DRM_MGA_INIT, &init, sizeof(init));
-   if ( ret < 0 ) {
-      fprintf( stderr,
-		  "[drm] Failed to initialize DMA! (%d)\n", ret );
-      return 0;
-   }
-
-   return 1;
-}
-
-static void MGADRIIrqInit(struct DRIDriverContextRec *ctx, MGAPtr pMga)
-{
-  if (!pMga->irq)
-    {
-      pMga->irq = drmGetInterruptFromBusID(ctx->drmFD,
-                                           ctx->pciBus,
-                                           ctx->pciDevice,
-                                           ctx->pciFunc);
-
-      fprintf(stderr, "[drm] got IRQ %d\n", pMga->irq);
-
-    if((drmCtlInstHandler(ctx->drmFD, pMga->irq)) != 0)
-      {
-        fprintf(stderr,
-                "[drm] failure adding irq handler, "
-                "there is a device already using that irq\n"
-                "[drm] falling back to irq-free operation\n");
-        pMga->irq = 0;
-      }
-    else
-      {
-        pMga->reg_ien = INREG( MGAREG_IEN );
-      }
-    }
-
-  if (pMga->irq)
-    fprintf(stderr,
-            "[drm] dma control initialized, using IRQ %d\n",
-            pMga->irq);
-}
-
-static int MGADRIBuffersInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   pMga->drmBuffers = drmMapBufs( ctx->drmFD );
-   if ( !pMga->drmBuffers )
-     {
-       fprintf( stderr,
-                "[drm] Failed to map DMA buffers list\n" );
-       return 0;
-     }
-   
-   fprintf( stderr,
-            "[drm] Mapped %d DMA buffers\n",
-            pMga->drmBuffers->count );
-
-   return 1;
-}
-
-static int MGAMemoryInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        bufferSize  = ((ctx->shared.virtualHeight * width_bytes
-			      + MGA_BUFFER_ALIGN)
-			     & ~MGA_BUFFER_ALIGN);
-   int        depthSize   = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
-			      + MGA_BUFFER_ALIGN)
-			     & ~MGA_BUFFER_ALIGN);
-   int        l;
-
-   pMga->frontOffset = 0;
-   pMga->frontPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-   fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", pMga->agpSize);
-   fprintf(stderr, 
-	   "Using %d MB for vertex/indirect buffers\n", pMga->buffers.size>>20);
-   fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", pMga->agpTextures.size>>20);
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   pMga->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
-   if (pMga->textureSize < 0) 
-      return 0;
-
-   l = mylog2( pMga->textureSize / MGA_NR_TEX_REGIONS );
-   if ( l < MGA_LOG_MIN_TEX_REGION_SIZE )
-      l = MGA_LOG_MIN_TEX_REGION_SIZE;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   pMga->logTextureGranularity = l;
-   pMga->textureSize = (pMga->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (pMga->textureSize < 512 * 1024) {
-      pMga->textureOffset = 0;
-      pMga->textureSize = 0;
-   }
-
-   /* Reserve space for textures */
-   pMga->textureOffset = ((ctx->shared.fbSize - pMga->textureSize +
-			   MGA_BUFFER_ALIGN) &
-			  ~MGA_BUFFER_ALIGN);
-
-   /* Reserve space for the shared depth
-    * buffer.
-    */
-   pMga->depthOffset = ((pMga->textureOffset - depthSize +
-			 MGA_BUFFER_ALIGN) &
-			~MGA_BUFFER_ALIGN);
-   pMga->depthPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-   pMga->backOffset = ((pMga->depthOffset - bufferSize +
-			MGA_BUFFER_ALIGN) &
-                        ~MGA_BUFFER_ALIGN);
-   pMga->backPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   pMga->backOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   pMga->depthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   pMga->textureSize/1024, pMga->textureOffset);
-
-   return 1;
-} 
-
-static int MGACheckDRMVersion( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-  drmVersionPtr version;
-
-  /* Check the MGA DRM version */
-  version = drmGetVersion(ctx->drmFD);
-  if ( version ) {
-    if ( version->version_major != 3 ||
-         version->version_minor < 0 ) {
-            /* incompatible drm version */
-      fprintf( stderr,
-               "[dri] MGADRIScreenInit failed because of a version mismatch.\n"
-               "[dri] mga.o kernel module version is %d.%d.%d but version 3.0.x is needed.\n"
-               "[dri] Disabling DRI.\n",
-               version->version_major,
-               version->version_minor,
-               version->version_patchlevel );
-      drmFreeVersion( version );
-      return 0;
-    }
-    drmFreeVersion( version );
-  }
-
-  return 1;
-}
-
-static void print_client_msg( MGADRIPtr pMGADRI )
-{
-  fprintf( stderr, "chipset:                  %d\n", pMGADRI->chipset );
-
-  fprintf( stderr, "width:                    %d\n", pMGADRI->width );
-  fprintf( stderr, "height:                   %d\n", pMGADRI->height );
-  fprintf( stderr, "mem:                      %d\n", pMGADRI->mem );
-  fprintf( stderr, "cpp:                      %d\n", pMGADRI->cpp );
-
-  fprintf( stderr, "agpMode:                  %d\n", pMGADRI->agpMode );
-
-  fprintf( stderr, "frontOffset:              %d\n", pMGADRI->frontOffset );
-  fprintf( stderr, "frontPitch:               %d\n", pMGADRI->frontPitch );
-
-  fprintf( stderr, "backOffset:               %d\n", pMGADRI->backOffset );
-  fprintf( stderr, "backPitch:                %d\n", pMGADRI->backPitch );
-
-  fprintf( stderr, "depthOffset:              %d\n", pMGADRI->depthOffset );
-  fprintf( stderr, "depthPitch:               %d\n", pMGADRI->depthPitch );
-
-  fprintf( stderr, "textureOffset:            %d\n", pMGADRI->textureOffset );
-  fprintf( stderr, "textureSize:              %d\n", pMGADRI->textureSize );
-
-  fprintf( stderr, "logTextureGranularity:    %d\n", pMGADRI->logTextureGranularity );
-  fprintf( stderr, "logAgpTextureGranularity: %d\n", pMGADRI->logAgpTextureGranularity );
-
-  fprintf( stderr, "agpTextureHandle:         %u\n", (unsigned int)pMGADRI->agpTextureOffset );
-  fprintf( stderr, "agpTextureSize:           %u\n", (unsigned int)pMGADRI->agpTextureSize );
-
-#if 0
-   pMGADRI->registers.handle	= pMga->registers.handle;
-   pMGADRI->registers.size	= pMga->registers.size;
-   pMGADRI->status.handle	= pMga->status.handle;
-   pMGADRI->status.size		= pMga->status.size;
-   pMGADRI->primary.handle	= pMga->primary.handle;
-   pMGADRI->primary.size	= pMga->primary.size;
-   pMGADRI->buffers.handle	= pMga->buffers.handle;
-   pMGADRI->buffers.size	= pMga->buffers.size;
-   pMGADRI->sarea_priv_offset = sizeof(drm_sarea_t);
-#endif
-}
-
-static int MGAScreenInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-  int       i;
-  int       err;
-  MGADRIPtr pMGADRI;
-
-  usleep(100);
-  /*assert(!ctx->IsClient);*/
-
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-   switch(pMga->Chipset) {
-   case PCI_CHIP_MGAG550:
-   case PCI_CHIP_MGAG400:
-   case PCI_CHIP_MGAG200:
-#if 0
-   case PCI_CHIP_MGAG200_PCI:
-#endif
-      break;
-   default:
-      fprintf(stderr, "[drm] Direct rendering only supported with G200/G400/G550 AGP\n");
-      return 0;
-   }
-
-   fprintf( stderr,
-	       "[drm] bpp: %d depth: %d\n",
-            ctx->bpp, ctx->bpp /* FIXME: depth */ );
-
-   if ( (ctx->bpp / 8) != 2 &&
-	(ctx->bpp / 8) != 4 ) {
-      fprintf( stderr,
-		  "[dri] Direct rendering only supported in 16 and 32 bpp modes\n" );
-      return 0;
-   }
-
-   ctx->shared.SAREASize = SAREA_MAX;
-
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("mga", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-     
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-		  0,
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-
-#if 0 /* will be done in MGADRIMapInit */
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->FixedInfo.mmio_start,
-		 ctx->FixedInfo.mmio_len,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pMga->registers.handle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08lx\n", pMga->registers.handle);
-#endif
-
-
-   /* Check the mga DRM version */
-   if (!MGACheckDRMVersion(ctx, pMga)) {
-      return 0;
-   }
-
-   if ( !MGADRIAgpInit( ctx, pMga ) ) {
-      return 0;
-   }
-
-   if ( !MGADRIMapInit( ctx, pMga ) ) {
-      return 0;
-   }
-
-   /* Memory manager setup */
-   if (!MGAMemoryInit(ctx, pMga)) {
-      return 0;
-   }
-
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the kernel data structures */
-   if (!MGADRIKernelInit(ctx, pMga)) {
-      fprintf(stderr, "MGADRIKernelInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize the vertex buffers list */
-   if (!MGADRIBuffersInit(ctx, pMga)) {
-      fprintf(stderr, "MGADRIBuffersInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize IRQ */
-   MGADRIIrqInit(ctx, pMga);
-
-
-   /* Initialize the SAREA private data structure */
-   {
-      drm_mga_sarea_t *pSAREAPriv;
-      pSAREAPriv = (drm_mga_sarea_t *)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-   }
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   drimemsetio((char *)ctx->FBAddress + pMga->frontOffset,
-	  0,
-	  pMga->frontPitch * ctx->shared.virtualHeight );
-
-   drimemsetio((char *)ctx->FBAddress + pMga->backOffset,
-	  0,
-	  pMga->backPitch * ctx->shared.virtualHeight );
-
-   /* Can release the lock now */
-/*   DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);*/
-
-   /* This is the struct passed to radeon_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(MGADRIRec));
-   ctx->driverClientMsgSize = sizeof(MGADRIRec);
-
-   pMGADRI                    = (MGADRIPtr)ctx->driverClientMsg;
-
-
-   switch(pMga->Chipset) {
-   case PCI_CHIP_MGAG550:
-   case PCI_CHIP_MGAG400:
-      pMGADRI->chipset = MGA_CARD_TYPE_G400;
-      break;
-   case PCI_CHIP_MGAG200:
-   case PCI_CHIP_MGAG200_PCI:
-      pMGADRI->chipset = MGA_CARD_TYPE_G200;
-      break;
-   default:
-      return 0;
-   }
-   pMGADRI->width		= ctx->shared.virtualWidth;
-   pMGADRI->height		= ctx->shared.virtualHeight;
-   pMGADRI->mem			= ctx->shared.fbSize;
-   pMGADRI->cpp			= ctx->bpp / 8;
-
-   pMGADRI->agpMode		= pMga->agpMode;
-
-   pMGADRI->frontOffset		= pMga->frontOffset;
-   pMGADRI->frontPitch		= pMga->frontPitch;
-   pMGADRI->backOffset		= pMga->backOffset;
-   pMGADRI->backPitch		= pMga->backPitch;
-   pMGADRI->depthOffset		= pMga->depthOffset;
-   pMGADRI->depthPitch		= pMga->depthPitch;
-   pMGADRI->textureOffset	= pMga->textureOffset;
-   pMGADRI->textureSize		= pMga->textureSize;
-   pMGADRI->logTextureGranularity = pMga->logTextureGranularity;
-
-   i = mylog2( pMga->agpTextures.size / MGA_NR_TEX_REGIONS );
-   if ( i < MGA_LOG_MIN_TEX_REGION_SIZE )
-      i = MGA_LOG_MIN_TEX_REGION_SIZE;
-
-   pMGADRI->logAgpTextureGranularity = i;
-   pMGADRI->agpTextureOffset = (unsigned int)pMga->agpTextures.handle;
-   pMGADRI->agpTextureSize = (unsigned int)pMga->agpTextures.size;
-
-   pMGADRI->registers.handle	= pMga->registers.handle;
-   pMGADRI->registers.size	= pMga->registers.size;
-   pMGADRI->status.handle	= pMga->status.handle;
-   pMGADRI->status.size		= pMga->status.size;
-   pMGADRI->primary.handle	= pMga->primary.handle;
-   pMGADRI->primary.size	= pMga->primary.size;
-   pMGADRI->buffers.handle	= pMga->buffers.handle;
-   pMGADRI->buffers.size	= pMga->buffers.size;
-   pMGADRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   print_client_msg( pMGADRI );
-
-   return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa mgaValidateMode().
- */
-static int mgaValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa mgaValidateMode().
- */
-static int mgaPostValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls MGAScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memomry accessing it directly.
- */
-static int mgaInitFBDev( struct DRIDriverContextRec *ctx )
-{
-   MGAPtr pMga = calloc(1, sizeof(*pMga));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)pMga;
-   
-   pMga->agpMode       = MGA_DEFAULT_AGP_MODE;
-   pMga->agpSize       = MGA_DEFAULT_AGP_SIZE;
-  
-   pMga->Chipset = ctx->chipset;
-
-   pMga->IOAddress = ctx->MMIOStart;
-   pMga->IOBase    = ctx->MMIOAddress;
-
-   pMga->frontPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-   if (!MGAScreenInit( ctx, pMga ))
-      return 0;
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void mgaHaltFBDev( struct DRIDriverContextRec *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = NULL;
-    }
-}
-
-
-static int mgaEngineShutdown( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s() is not yet implemented!\n", __FUNCTION__);
-
-   return 1;
-}
-
-static int mgaEngineRestore( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s() is not yet implemented!\n", __FUNCTION__);
-
-   return 1;
-}
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-struct DRIDriverRec __driDriver = {
-   mgaValidateMode,
-   mgaPostValidateMode,
-   mgaInitFBDev,
-   mgaHaltFBDev,
-   mgaEngineShutdown,
-   mgaEngineRestore,
-   0
-};
-
-
-
-
-#if 0
-void MGADRICloseScreen( ScreenPtr pScreen )
-{
-   ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-   MGAPtr pMga = MGAPTR(pScrn);
-   MGADRIServerPrivatePtr pMga = pMga->DRIServerInfo;
-   drmMGAInit init;
-
-   if ( pMga->drmBuffers ) {
-      drmUnmapBufs( pMga->drmBuffers );
-      pMga->drmBuffers = NULL;
-   }
-
-   if (pMga->irq) {
-      drmCtlUninstHandler(ctx->drmFD);
-      pMga->irq = 0;
-   }
-
-   /* Cleanup DMA */
-   memset( &init, 0, sizeof(drmMGAInit) );
-   init.func = MGA_CLEANUP_DMA;
-   drmCommandWrite( ctx->drmFD, DRM_MGA_INIT, &init, sizeof(drmMGAInit) );
-
-   if ( pMga->status.map ) {
-      drmUnmap( pMga->status.map, pMga->status.size );
-      pMga->status.map = NULL;
-   }
-   if ( pMga->buffers.map ) {
-      drmUnmap( pMga->buffers.map, pMga->buffers.size );
-      pMga->buffers.map = NULL;
-   }
-   if ( pMga->primary.map ) {
-      drmUnmap( pMga->primary.map, pMga->primary.size );
-      pMga->primary.map = NULL;
-   }
-   if ( pMga->warp.map ) {
-      drmUnmap( pMga->warp.map, pMga->warp.size );
-      pMga->warp.map = NULL;
-   }
-
-   if ( pMga->agpTextures.map ) {
-      drmUnmap( pMga->agpTextures.map, pMga->agpTextures.size );
-      pMga->agpTextures.map = NULL;
-   }
-
-   if ( pMga->agp.handle ) {
-      drmAgpUnbind( ctx->drmFD, pMga->agp.handle );
-      drmAgpFree( ctx->drmFD, pMga->agp.handle );
-      pMga->agp.handle = 0;
-      drmAgpRelease( ctx->drmFD );
-   }
-
-   DRICloseScreen( pScreen );
-
-   if ( pMga->pDRIInfo ) {
-      if ( pMga->pDRIpMga->devPrivate ) {
-	 xfree( pMga->pDRIpMga->devPrivate );
-	 pMga->pDRIpMga->devPrivate = 0;
-      }
-      DRIDestroyInfoRec( pMga->pDRIInfo );
-      pMga->pDRIInfo = 0;
-   }
-   if ( pMga->DRIServerInfo ) {
-      xfree( pMga->DRIServerInfo );
-      pMga->DRIServerInfo = 0;
-   }
-   if ( pMga->pVisualConfigs ) {
-      xfree( pMga->pVisualConfigs );
-   }
-   if ( pMga->pVisualConfigsPriv ) {
-      xfree( pMga->pVisualConfigsPriv );
-   }
-}
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/Makefile b/src/mesa/drivers/dri/nouveau/Makefile
index 49e89335614..7be19b26fda 100644
--- a/src/mesa/drivers/dri/nouveau/Makefile
+++ b/src/mesa/drivers/dri/nouveau/Makefile
@@ -8,8 +8,6 @@ DRI_LIB_DEPS += $(shell pkg-config libdrm_nouveau --libs)
 
 LIBNAME = nouveau_vieux_dri.so
 
-MINIGLX_SOURCES =
-
 DRIVER_SOURCES = \
 	nouveau_screen.c \
 	nouveau_context.c \
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index 26297332732..502e01255cb 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -43,18 +43,23 @@
 
 #define need_GL_EXT_framebuffer_object
 #define need_GL_EXT_fog_coord
+#define need_GL_EXT_secondary_color
 
 #include "main/remap_helper.h"
 
 static const struct dri_extension nouveau_extensions[] = {
-	{ "GL_EXT_framebuffer_object",  GL_EXT_framebuffer_object_functions },
 	{ "GL_ARB_multitexture",	NULL },
-	{ "GL_EXT_texture_lod_bias",	NULL },
-	{ "GL_SGIS_generate_mipmap",	NULL },
+	{ "GL_ARB_texture_env_add",	NULL },
 	{ "GL_ARB_texture_env_combine",	NULL },
 	{ "GL_ARB_texture_env_dot3",	NULL },
-	{ "GL_ARB_texture_env_add",	NULL },
+	{ "GL_ARB_texture_mirrored_repeat", NULL },
 	{ "GL_EXT_fog_coord",		GL_EXT_fog_coord_functions },
+	{ "GL_EXT_framebuffer_object",	GL_EXT_framebuffer_object_functions },
+	{ "GL_EXT_secondary_color",	GL_EXT_secondary_color_functions },
+	{ "GL_EXT_stencil_wrap",	NULL },
+	{ "GL_EXT_texture_lod_bias",	NULL },
+	{ "GL_NV_blend_square",         NULL },
+	{ "GL_SGIS_generate_mipmap",	NULL },
 	{ NULL,				NULL }
 };
 
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c b/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
index 846478650e2..2ec3dc92420 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
@@ -72,7 +72,7 @@ set_renderbuffer_format(struct gl_renderbuffer *rb, GLenum internalFormat)
 	case GL_DEPTH24_STENCIL8_EXT:
 		rb->_BaseFormat  = GL_DEPTH_STENCIL;
 		rb->Format = MESA_FORMAT_Z24_S8;
-		rb->DataType = GL_UNSIGNED_INT;
+		rb->DataType = GL_UNSIGNED_INT_24_8_EXT;
 		s->cpp = 4;
 		break;
 	default:
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state.c b/src/mesa/drivers/dri/nouveau/nouveau_state.c
index e1871db0eb9..bc610451b40 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_state.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_state.c
@@ -150,6 +150,7 @@ nouveau_enable(GLcontext *ctx, GLenum cap, GLboolean state)
 		break;
 	case GL_COLOR_SUM_EXT:
 		context_dirty(ctx, FRAG);
+		context_dirty(ctx, LIGHT_MODEL);
 		break;
 	case GL_CULL_FACE:
 		context_dirty(ctx, CULL_FACE);
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state.h b/src/mesa/drivers/dri/nouveau/nouveau_state.h
index d001fa259aa..d01d962c9f2 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_state.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_state.h
@@ -47,7 +47,6 @@ enum {
 	NOUVEAU_STATE_FRAG,
 	NOUVEAU_STATE_FRAMEBUFFER,
 	NOUVEAU_STATE_FOG,
-	NOUVEAU_STATE_INDEX_MASK,
 	NOUVEAU_STATE_LIGHT_ENABLE,
 	NOUVEAU_STATE_LIGHT_MODEL,
 	NOUVEAU_STATE_LIGHT_SOURCE0,
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c b/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
index 02c85807608..a365b977f29 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
@@ -24,8 +24,11 @@
  *
  */
 
-#include "main/bufferobj.h"
 #include "nouveau_bufferobj.h"
+#include "nouveau_util.h"
+
+#include "main/bufferobj.h"
+#include "main/image.h"
 
 /* Arbitrary pushbuf length we can assume we can get with a single
  * WAIT_RING. */
@@ -58,7 +61,11 @@ vbo_init_array(struct nouveau_array_state *a, int attr, int stride,
 	} else {
 		nouveau_bo_ref(NULL, &a->bo);
 		a->offset = 0;
-		a->buf = ptr;
+
+		if (map)
+			a->buf = ptr;
+		else
+			a->buf = NULL;
 	}
 
 	if (a->buf)
@@ -94,11 +101,20 @@ vbo_init_arrays(GLcontext *ctx, const struct _mesa_index_buffer *ib,
 
 		if (attr >= 0) {
 			const struct gl_client_array *array = arrays[attr];
+			int stride;
+
+			if (render->mode == VBO &&
+			    !_mesa_is_bufferobj(array->BufferObj))
+				/* Pack client buffers. */
+				stride = align(_mesa_sizeof_type(array->Type)
+					       * array->Size, 4);
+			else
+				stride = array->StrideB;
 
 			vbo_init_array(&render->attrs[attr], attr,
-				       array->StrideB, array->Size,
-				       array->Type, array->BufferObj,
-				       array->Ptr, render->mode == IMM);
+				       stride, array->Size, array->Type,
+				       array->BufferObj, array->Ptr,
+				       render->mode == IMM);
 		}
 	}
 }
@@ -227,6 +243,23 @@ vbo_choose_attrs(GLcontext *ctx, const struct gl_client_array **arrays)
 	vbo_emit_attr(ctx, arrays, VERT_ATTRIB_POS);
 }
 
+static unsigned
+get_max_client_stride(GLcontext *ctx)
+{
+	struct nouveau_render_state *render = to_render_state(ctx);
+	int i, s = 0;
+
+	for (i = 0; i < render->attr_count; i++) {
+		int attr = render->map[i];
+		struct nouveau_array_state *a = &render->attrs[attr];
+
+		if (attr >= 0 && !a->bo)
+			s = MAX2(a->stride, s);
+	}
+
+	return s;
+}
+
 static void
 TAG(vbo_render_prims)(GLcontext *ctx, const struct gl_client_array **arrays,
 		      const struct _mesa_prim *prims, GLuint nr_prims,
@@ -241,12 +274,20 @@ vbo_maybe_split(GLcontext *ctx, const struct gl_client_array **arrays,
 	    GLuint min_index, GLuint max_index)
 {
 	struct nouveau_context *nctx = to_nouveau_context(ctx);
+	struct nouveau_render_state *render = to_render_state(ctx);
 	unsigned pushbuf_avail = PUSHBUF_DWORDS - 2 * nctx->bo.count,
 		vert_avail = get_max_vertices(ctx, NULL, pushbuf_avail),
 		idx_avail = get_max_vertices(ctx, ib, pushbuf_avail);
+	int stride;
 
-	if ((ib && ib->count > idx_avail) ||
-	    (!ib && max_index - min_index > vert_avail)) {
+	/* Try to keep client buffers smaller than the scratch BOs. */
+	if (render->mode == VBO &&
+	    (stride = get_max_client_stride(ctx)))
+		    vert_avail = MIN2(vert_avail,
+				      RENDER_SCRATCH_SIZE / stride);
+
+	if (max_index - min_index > vert_avail ||
+	    (ib && ib->count > idx_avail)) {
 		struct split_limits limits = {
 			.max_verts = vert_avail,
 			.max_indices = idx_avail,
@@ -276,17 +317,21 @@ vbo_bind_vertices(GLcontext *ctx, const struct gl_client_array **arrays,
 		if (attr >= 0) {
 			const struct gl_client_array *array = arrays[attr];
 			struct nouveau_array_state *a = &render->attrs[attr];
-			unsigned delta = (basevertex + min_index) * a->stride,
-				size = (max_index - min_index + 1) * a->stride;
+			unsigned delta = (basevertex + min_index)
+				* array->StrideB;
 
 			if (a->bo) {
 				a->offset = (intptr_t)array->Ptr + delta;
 			} else {
-				void *scratch = get_scratch_vbo(ctx, size,
-								&a->bo,
-								&a->offset);
-
-				memcpy(scratch, a->buf + delta, size);
+				int j, n = max_index - min_index + 1;
+				char *sp = (char *)array->Ptr + delta;
+				char *dp = get_scratch_vbo(ctx, n * a->stride,
+							   &a->bo, &a->offset);
+
+				for (j = 0; j < n; j++)
+					memcpy(dp + j * a->stride,
+					       sp + j * array->StrideB,
+					       a->stride);
 			}
 		}
 	}
diff --git a/src/mesa/drivers/dri/nouveau/nv04_context.c b/src/mesa/drivers/dri/nouveau/nv04_context.c
index 1acd41de54d..a442425e448 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_context.c
@@ -265,7 +265,6 @@ const struct nouveau_driver nv04_driver = {
 		nouveau_emit_nothing,
 		nouveau_emit_nothing,
 		nouveau_emit_nothing,
-		nouveau_emit_nothing,
 		nv04_emit_scissor,
 		nv04_defer_blend,
 		nv04_defer_control,
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_fb.c b/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
index aad1e491d2f..5e5e0c58742 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
@@ -63,7 +63,7 @@ nv04_emit_framebuffer(GLcontext *ctx, int emit)
 		return;
 
 	/* Render target */
-	if (fb->_NumColorDrawBuffers) {
+	if (fb->_ColorDrawBuffers[0]) {
 		s = &to_nouveau_renderbuffer(
 			fb->_ColorDrawBuffers[0])->surface;
 
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_raster.c b/src/mesa/drivers/dri/nouveau/nv04_state_raster.c
index 89c6753694c..c191571a5f8 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_raster.c
@@ -71,6 +71,10 @@ get_stencil_op(unsigned op)
 		return 0x5;
 	case GL_INVERT:
 		return 0x6;
+	case GL_INCR_WRAP:
+		return 0x7;
+	case GL_DECR_WRAP:
+		return 0x8;
 	default:
 		assert(0);
 	}
@@ -271,6 +275,10 @@ nv04_emit_blend(GLcontext *ctx, int emit)
 		else
 			blend |= NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT;
 
+		/* Secondary color */
+		if (NEED_SECONDARY_COLOR(ctx))
+			blend |= NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE;
+
 		/* Fog. */
 		if (ctx->Fog.Enabled)
 			blend |= NV04_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE;
@@ -305,6 +313,10 @@ nv04_emit_blend(GLcontext *ctx, int emit)
 		else
 			blend |= get_texenv_mode(GL_MODULATE);
 
+		/* Secondary color */
+		if (NEED_SECONDARY_COLOR(ctx))
+			blend |= NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE;
+
 		/* Fog. */
 		if (ctx->Fog.Enabled)
 			blend |= NV04_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE;
diff --git a/src/mesa/drivers/dri/nouveau/nv10_context.c b/src/mesa/drivers/dri/nouveau/nv10_context.c
index 8e70c419ede..860d0aeb8f5 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_context.c
@@ -370,7 +370,6 @@ const struct nouveau_driver nv10_driver = {
 		nv10_emit_frag,
 		nv10_emit_framebuffer,
 		nv10_emit_fog,
-		nv10_emit_index_mask,
 		nv10_emit_light_enable,
 		nv10_emit_light_model,
 		nv10_emit_light_source,
diff --git a/src/mesa/drivers/dri/nouveau/nv10_driver.h b/src/mesa/drivers/dri/nouveau/nv10_driver.h
index b5ab19b3bc0..d662712533b 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_driver.h
+++ b/src/mesa/drivers/dri/nouveau/nv10_driver.h
@@ -100,9 +100,6 @@ void
 nv10_emit_dither(GLcontext *ctx, int emit);
 
 void
-nv10_emit_index_mask(GLcontext *ctx, int emit);
-
-void
 nv10_emit_logic_opcode(GLcontext *ctx, int emit);
 
 void
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
index 05c36b4f8f5..6bd383ebcd3 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
@@ -111,7 +111,7 @@ nv10_emit_framebuffer(GLcontext *ctx, int emit)
 	}
 
 	/* Render target */
-	if (fb->_NumColorDrawBuffers) {
+	if (fb->_ColorDrawBuffers[0]) {
 		s = &to_nouveau_renderbuffer(
 			fb->_ColorDrawBuffers[0])->surface;
 
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_raster.c b/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
index 68882ef05f2..a62cd807a91 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
@@ -119,11 +119,6 @@ nv10_emit_dither(GLcontext *ctx, int emit)
 }
 
 void
-nv10_emit_index_mask(GLcontext *ctx, int emit)
-{
-}
-
-void
 nv10_emit_logic_opcode(GLcontext *ctx, int emit)
 {
 	struct nouveau_channel *chan = context_chan(ctx);
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c
index 6db14d83b83..406e24c455d 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c
@@ -201,8 +201,10 @@ nv10_emit_light_model(GLcontext *ctx, int emit)
 	BEGIN_RING(chan, celsius, NV10TCL_LIGHT_MODEL, 1);
 	OUT_RING(chan, ((m->LocalViewer ?
 			 NV10TCL_LIGHT_MODEL_LOCAL_VIEWER : 0) |
-			(m->ColorControl == GL_SEPARATE_SPECULAR_COLOR ?
-			 NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR : 0)));
+			(NEED_SECONDARY_COLOR(ctx) ?
+			 NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR : 0) |
+			(!ctx->Light.Enabled && ctx->Fog.ColorSumEnabled ?
+			 NV10TCL_LIGHT_MODEL_VERTEX_SPECULAR : 0)));
 }
 
 static float
diff --git a/src/mesa/drivers/dri/nouveau/nv20_context.c b/src/mesa/drivers/dri/nouveau/nv20_context.c
index 635b5c09968..db39ef70750 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_context.c
@@ -459,7 +459,6 @@ const struct nouveau_driver nv20_driver = {
 		nv20_emit_frag,
 		nv20_emit_framebuffer,
 		nv20_emit_fog,
-		nv10_emit_index_mask,
 		nv10_emit_light_enable,
 		nv20_emit_light_model,
 		nv20_emit_light_source,
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_fb.c b/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
index 869acd6e317..d638541df9e 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
@@ -67,7 +67,7 @@ nv20_emit_framebuffer(GLcontext *ctx, int emit)
 		return;
 
 	/* Render target */
-	if (fb->_NumColorDrawBuffers) {
+	if (fb->_ColorDrawBuffers[0]) {
 		s = &to_nouveau_renderbuffer(
 			fb->_ColorDrawBuffers[0])->surface;
 
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c
index 0d566064f67..43f8c723122 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c
@@ -158,7 +158,7 @@ nv20_emit_light_model(GLcontext *ctx, int emit)
 	OUT_RING(chan, ((m->LocalViewer ?
 			 NV20TCL_LIGHT_MODEL_VIEWER_LOCAL :
 			 NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL) |
-			(m->ColorControl == GL_SEPARATE_SPECULAR_COLOR ?
+			(NEED_SECONDARY_COLOR(ctx) ?
 			 NV20TCL_LIGHT_MODEL_SEPARATE_SPECULAR :
 			 0)));
 
diff --git a/src/mesa/drivers/dri/r128/Makefile b/src/mesa/drivers/dri/r128/Makefile
index 52c5a38a705..8144c9b43ff 100644
--- a/src/mesa/drivers/dri/r128/Makefile
+++ b/src/mesa/drivers/dri/r128/Makefile
@@ -5,8 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = r128_dri.so
 
-MINIGLX_SOURCES = server/r128_dri.c 
-
 DRIVER_SOURCES = \
 	r128_context.c \
 	r128_lock.c \
diff --git a/src/mesa/drivers/dri/r128/server/r128_dri.c b/src/mesa/drivers/dri/r128/server/r128_dri.c
deleted file mode 100644
index 6e3db948af7..00000000000
--- a/src/mesa/drivers/dri/r128/server/r128_dri.c
+++ /dev/null
@@ -1,1112 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- *                      Precision Insight, Inc., Cedar Park, Texas, and
- *                      VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- *   Kevin E. Martin <[email protected]>
- *   Rickard E. Faith <[email protected]>
- *   Daryll Strauss <[email protected]>
- *   Gareth Hughes <[email protected]>
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-// Fix this to use kernel pci_ids.h when all of these IDs make it into the kernel 
-#include "pci_ids.h"
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "r128.h"
-#include "r128_dri.h"
-#include "r128_macros.h"
-#include "r128_reg.h"
-#include "r128_version.h"
-#include "r128_drm.h"
-
-static size_t r128_drm_page_size;
-
-/* Compute log base 2 of val. */
-static int R128MinBits(int val)
-{
-    int bits;
-
-    if (!val) return 1;
-    for (bits = 0; val; val >>= 1, ++bits);
-    return bits;
-}
-
-/* Initialize the AGP state.  Request memory for use in AGP space, and
-   initialize the Rage 128 registers to point to that memory. */
-static GLboolean R128DRIAgpInit(const DRIDriverContext *ctx)
-{
-    unsigned char *R128MMIO = ctx->MMIOAddress;
-    R128InfoPtr info = ctx->driverPrivate;
-    unsigned long mode;
-    unsigned int  vendor, device;
-    int           ret;
-    unsigned long cntl, chunk;
-    int           s, l;
-    int           flags;
-    unsigned long agpBase;
-
-    if (drmAgpAcquire(ctx->drmFD) < 0) {
-	fprintf(stderr, "[agp] AGP not available\n");
-	return GL_FALSE;
-    }
-
-				/* Modify the mode if the default mode is
-				   not appropriate for this particular
-				   combination of graphics card and AGP
-				   chipset. */
-
-    mode   = drmAgpGetMode(ctx->drmFD);        /* Default mode */
-    vendor = drmAgpVendorId(ctx->drmFD);
-    device = drmAgpDeviceId(ctx->drmFD);
-
-    mode &= ~R128_AGP_MODE_MASK;
-    switch (info->agpMode) {
-    case 4:          mode |= R128_AGP_4X_MODE;
-    case 2:          mode |= R128_AGP_2X_MODE;
-    case 1: default: mode |= R128_AGP_1X_MODE;
-    }
-
-    fprintf(stderr,
-	       "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
-	       mode, vendor, device,
-	       0x1002,
-	       info->Chipset);
-
-    if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-	fprintf(stderr, "[agp] AGP not enabled\n");
-	drmAgpRelease(ctx->drmFD);
-	return GL_FALSE;
-    }
-
-    info->agpOffset = 0;
-
-    if ((ret = drmAgpAlloc(ctx->drmFD, info->agpSize*1024*1024, 0, NULL,
-			   &info->agpMemHandle)) < 0) {
-	fprintf(stderr, "[agp] Out of memory (%d)\n", ret);
-	drmAgpRelease(ctx->drmFD);
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] %d kB allocated with handle 0x%08x\n",
-	       info->agpSize*1024, info->agpMemHandle);
-
-    if (drmAgpBind(ctx->drmFD, info->agpMemHandle, info->agpOffset) < 0) {
-	fprintf(stderr, "[agp] Could not bind\n");
-	drmAgpFree(ctx->drmFD, info->agpMemHandle);
-	drmAgpRelease(ctx->drmFD);
-	return GL_FALSE;
-    }
-
-				/* Initialize the CCE ring buffer data */
-    info->ringStart       = info->agpOffset;
-    info->ringMapSize     = info->ringSize*1024*1024 + r128_drm_page_size;
-    info->ringSizeLog2QW  = R128MinBits(info->ringSize*1024*1024/8) - 1;
-
-    info->ringReadOffset  = info->ringStart + info->ringMapSize;
-    info->ringReadMapSize = r128_drm_page_size;
-
-				/* Reserve space for vertex/indirect buffers */
-    info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-    info->bufMapSize      = info->bufSize*1024*1024;
-
-				/* Reserve the rest for AGP textures */
-    info->agpTexStart     = info->bufStart + info->bufMapSize;
-    s = (info->agpSize*1024*1024 - info->agpTexStart);
-    l = R128MinBits((s-1) / R128_NR_TEX_REGIONS);
-    if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY;
-    info->agpTexMapSize   = (s >> l) << l;
-    info->log2AGPTexGran  = l;
-
-    if (info->CCESecure) flags = DRM_READ_ONLY;
-    else                  flags = 0;
-
-    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		  DRM_AGP, flags, &info->ringHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add ring mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] ring handle = 0x%08x\n", info->ringHandle);
-
-    if (drmMap(ctx->drmFD, info->ringHandle, info->ringMapSize,
-	       (drmAddressPtr)&info->ring) < 0) {
-	fprintf(stderr, "[agp] Could not map ring\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] Ring mapped at 0x%08lx\n",
-	       (unsigned long)info->ring);
-
-    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		  DRM_AGP, flags, &info->ringReadPtrHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add ring read ptr mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
- 	       "[agp] ring read ptr handle = 0x%08x\n",
-	       info->ringReadPtrHandle);
-
-    if (drmMap(ctx->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
-	       (drmAddressPtr)&info->ringReadPtr) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not map ring read ptr\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] Ring read ptr mapped at 0x%08lx\n",
-	       (unsigned long)info->ringReadPtr);
-
-    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		  DRM_AGP, 0, &info->bufHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add vertex/indirect buffers mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] vertex/indirect buffers handle = 0x%08lx\n",
-	       info->bufHandle);
-
-    if (drmMap(ctx->drmFD, info->bufHandle, info->bufMapSize,
-	       (drmAddressPtr)&info->buf) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not map vertex/indirect buffers\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] Vertex/indirect buffers mapped at 0x%08lx\n",
-	       (unsigned long)info->buf);
-
-    if (drmAddMap(ctx->drmFD, info->agpTexStart, info->agpTexMapSize,
-		  DRM_AGP, 0, &info->agpTexHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add AGP texture map mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] AGP texture map handle = 0x%08lx\n",
-	       info->agpTexHandle);
-
-    if (drmMap(ctx->drmFD, info->agpTexHandle, info->agpTexMapSize,
-	       (drmAddressPtr)&info->agpTex) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not map AGP texture map\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] AGP Texture map mapped at 0x%08lx\n",
-	       (unsigned long)info->agpTex);
-
-				/* Initialize Rage 128's AGP registers */
-    cntl  = INREG(R128_AGP_CNTL);
-    cntl &= ~R128_AGP_APER_SIZE_MASK;
-    switch (info->agpSize) {
-    case 256: cntl |= R128_AGP_APER_SIZE_256MB; break;
-    case 128: cntl |= R128_AGP_APER_SIZE_128MB; break;
-    case  64: cntl |= R128_AGP_APER_SIZE_64MB;  break;
-    case  32: cntl |= R128_AGP_APER_SIZE_32MB;  break;
-    case  16: cntl |= R128_AGP_APER_SIZE_16MB;  break;
-    case   8: cntl |= R128_AGP_APER_SIZE_8MB;   break;
-    case   4: cntl |= R128_AGP_APER_SIZE_4MB;   break;
-    default:
-	fprintf(stderr,
-		   "[agp] Illegal aperture size %d kB\n",
-		   info->agpSize*1024);
-	return GL_FALSE;
-    }
-    agpBase = drmAgpBase(ctx->drmFD);
-    OUTREG(R128_AGP_BASE, agpBase); 
-    OUTREG(R128_AGP_CNTL, cntl);
-
-				/* Disable Rage 128's PCIGART registers */
-    chunk = INREG(R128_BM_CHUNK_0_VAL);
-    chunk &= ~(R128_BM_PTR_FORCE_TO_PCI |
-	       R128_BM_PM4_RD_FORCE_TO_PCI |
-	       R128_BM_GLOBAL_FORCE_TO_PCI);
-    OUTREG(R128_BM_CHUNK_0_VAL, chunk);
-
-    OUTREG(R128_PCI_GART_PAGE, 1); /* Ensure AGP GART is used (for now) */
-
-    return GL_TRUE;
-}
-
-static GLboolean R128DRIPciInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    unsigned char *R128MMIO = ctx->MMIOAddress;
-    uint32_t chunk;
-    int ret;
-    int flags;
-
-    info->agpOffset = 0;
-
-    ret = drmScatterGatherAlloc(ctx->drmFD, info->agpSize*1024*1024,
-				&info->pciMemHandle);
-    if (ret < 0) {
-	fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] %d kB allocated with handle 0x%08x\n",
-	       info->agpSize*1024, info->pciMemHandle);
-
-				/* Initialize the CCE ring buffer data */
-    info->ringStart       = info->agpOffset;
-    info->ringMapSize     = info->ringSize*1024*1024 + r128_drm_page_size;
-    info->ringSizeLog2QW  = R128MinBits(info->ringSize*1024*1024/8) - 1;
-
-    info->ringReadOffset  = info->ringStart + info->ringMapSize;
-    info->ringReadMapSize = r128_drm_page_size;
-
-				/* Reserve space for vertex/indirect buffers */
-    info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-    info->bufMapSize      = info->bufSize*1024*1024;
-
-    flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
-
-    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] ring handle = 0x%08lx\n", info->ringHandle);
-
-    if (drmMap(ctx->drmFD, info->ringHandle, info->ringMapSize,
-	       (drmAddressPtr)&info->ring) < 0) {
-	fprintf(stderr, "[pci] Could not map ring\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] Ring mapped at 0x%08lx\n",
-	       (unsigned long)info->ring);
-    fprintf(stderr,
-	       "[pci] Ring contents 0x%08lx\n",
-	       *(unsigned long *)info->ring);
-
-    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring read ptr mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] ring read ptr handle = 0x%08lx\n",
-	       info->ringReadPtrHandle);
-
-    if (drmMap(ctx->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
-	       (drmAddressPtr)&info->ringReadPtr) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not map ring read ptr\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] Ring read ptr mapped at 0x%08lx\n",
-	       (unsigned long)info->ringReadPtr);
-    fprintf(stderr,
-	       "[pci] Ring read ptr contents 0x%08lx\n",
-	       *(unsigned long *)info->ringReadPtr);
-
-    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		  DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add vertex/indirect buffers mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] vertex/indirect buffers handle = 0x%08lx\n",
-	       info->bufHandle);
-
-    if (drmMap(ctx->drmFD, info->bufHandle, info->bufMapSize,
-	       (drmAddressPtr)&info->buf) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not map vertex/indirect buffers\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] Vertex/indirect buffers mapped at 0x%08lx\n",
-	       (unsigned long)info->buf);
-    fprintf(stderr,
-	       "[pci] Vertex/indirect buffers contents 0x%08lx\n",
-	       *(unsigned long *)info->buf);
-
-    if (!info->IsPCI) {
-	/* This is really an AGP card, force PCI GART mode */
-        chunk = INREG(R128_BM_CHUNK_0_VAL);
-        chunk |= (R128_BM_PTR_FORCE_TO_PCI |
-		  R128_BM_PM4_RD_FORCE_TO_PCI |
-		  R128_BM_GLOBAL_FORCE_TO_PCI);
-        OUTREG(R128_BM_CHUNK_0_VAL, chunk);
-        OUTREG(R128_PCI_GART_PAGE, 0); /* Ensure PCI GART is used */
-    }
-
-    return GL_TRUE;
-}
-
-/* Add a map for the MMIO registers that will be accessed by any
-   DRI-based clients. */
-static GLboolean R128DRIMapInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    int flags;
-
-    if (info->CCESecure) flags = DRM_READ_ONLY;
-    else                 flags = 0;
-
-				/* Map registers */
-    if (drmAddMap(ctx->drmFD, ctx->MMIOStart, ctx->MMIOSize,
-		  DRM_REGISTERS, flags, &info->registerHandle) < 0) {
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[drm] register handle = 0x%08x\n", info->registerHandle);
-
-    return GL_TRUE;
-}
-
-/* Initialize the kernel data structures. */
-static int R128DRIKernelInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    drm_r128_init_t drmInfo;
-
-    memset( &drmInfo, 0, sizeof(&drmInfo) );
-
-    drmInfo.func                = R128_INIT_CCE;
-    drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-    drmInfo.is_pci              = info->IsPCI;
-    drmInfo.cce_mode            = info->CCEMode;
-    drmInfo.cce_secure          = info->CCESecure;
-    drmInfo.ring_size           = info->ringSize*1024*1024;
-    drmInfo.usec_timeout        = info->CCEusecTimeout;
-
-    drmInfo.fb_bpp              = ctx->bpp;
-    drmInfo.depth_bpp           = ctx->bpp;
-
-    drmInfo.front_offset        = info->frontOffset;
-    drmInfo.front_pitch         = info->frontPitch;
-
-    drmInfo.back_offset         = info->backOffset;
-    drmInfo.back_pitch          = info->backPitch;
-
-    drmInfo.depth_offset        = info->depthOffset;
-    drmInfo.depth_pitch         = info->depthPitch;
-    drmInfo.span_offset         = info->spanOffset;
-
-    drmInfo.fb_offset           = info->LinearAddr;
-    drmInfo.mmio_offset         = info->registerHandle;
-    drmInfo.ring_offset         = info->ringHandle;
-    drmInfo.ring_rptr_offset    = info->ringReadPtrHandle;
-    drmInfo.buffers_offset      = info->bufHandle;
-    drmInfo.agp_textures_offset = info->agpTexHandle;
-
-    if (drmCommandWrite(ctx->drmFD, DRM_R128_INIT,
-                        &drmInfo, sizeof(drmInfo)) < 0)
-        return GL_FALSE;
-
-    return GL_TRUE;
-}
-
-/* Add a map for the vertex buffers that will be accessed by any
-   DRI-based clients. */
-static GLboolean R128DRIBufInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-				/* Initialize vertex buffers */
-    if (info->IsPCI) {
-	info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				      info->bufMapSize / R128_BUFFER_SIZE,
-				      R128_BUFFER_SIZE,
-				      DRM_SG_BUFFER,
-				      info->bufStart);
-    } else {
-	info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				      info->bufMapSize / R128_BUFFER_SIZE,
-				      R128_BUFFER_SIZE,
-				      DRM_AGP_BUFFER,
-				      info->bufStart);
-    }
-    if (info->bufNumBufs <= 0) {
-	fprintf(stderr,
-		   "[drm] Could not create vertex/indirect buffers list\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[drm] Added %d %d byte vertex/indirect buffers\n",
-	       info->bufNumBufs, R128_BUFFER_SIZE);
-
-    if (!(info->buffers = drmMapBufs(ctx->drmFD))) {
-	fprintf(stderr,
-		   "[drm] Failed to map vertex/indirect buffers list\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[drm] Mapped %d vertex/indirect buffers\n",
-	       info->buffers->count);
-
-    return GL_TRUE;
-}
-
-static void R128DRIIrqInit(const DRIDriverContext *ctx)
-{
-   R128InfoPtr info = ctx->driverPrivate;
-   unsigned char *R128MMIO = ctx->MMIOAddress;
-   
-   if (!info->irq) {
-       info->irq = drmGetInterruptFromBusID(
-	   ctx->drmFD,
-	   ctx->pciBus,
-	   ctx->pciDevice,
-	   ctx->pciFunc);
-
-      if((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
-	 fprintf(stderr,
-		    "[drm] failure adding irq handler, "
-		    "there is a device already using that irq\n"
-		    "[drm] falling back to irq-free operation\n");
-	 info->irq = 0;
-      } else {
-          info->gen_int_cntl = INREG( R128_GEN_INT_CNTL );
-      }
-   }
-
-   if (info->irq)
-      fprintf(stderr,
-		 "[drm] dma control initialized, using IRQ %d\n",
-		 info->irq);
-}
-
-static int R128CCEStop(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    drm_r128_cce_stop_t stop;
-    int            ret, i;
-
-    stop.flush = 1;
-    stop.idle  = 1;
-
-    ret = drmCommandWrite( ctx->drmFD, DRM_R128_CCE_STOP,
-                           &stop, sizeof(stop) );
-
-    if ( ret == 0 ) {
-        return 0;
-    } else if ( errno != EBUSY ) {
-        return -errno;
-    }
-
-    stop.flush = 0;
-
-    i = 0;
-    do {
-        ret = drmCommandWrite( ctx->drmFD, DRM_R128_CCE_STOP,
-                               &stop, sizeof(stop) );
-    } while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
-
-    if ( ret == 0 ) {
-        return 0;
-    } else if ( errno != EBUSY ) {
-        return -errno;
-    }
-
-    stop.idle = 0;
-
-    if ( drmCommandWrite( ctx->drmFD, DRM_R128_CCE_STOP,
-                          &stop, sizeof(stop) )) {
-        return -errno;
-    } else {
-        return 0;
-    }
-}
-
-/* Initialize the CCE state, and start the CCE (if used by the X server) */
-static void R128DRICCEInit(const DRIDriverContext *ctx)
-{
-   R128InfoPtr info = ctx->driverPrivate;
-
-				/* Turn on bus mastering */
-    info->BusCntl &= ~R128_BUS_MASTER_DIS;
-
-				/* CCEMode is initialized in r128_driver.c */
-    switch (info->CCEMode) {
-    case R128_PM4_NONPM4:                 info->CCEFifoSize = 0;   break;
-    case R128_PM4_192PIO:                 info->CCEFifoSize = 192; break;
-    case R128_PM4_192BM:                  info->CCEFifoSize = 192; break;
-    case R128_PM4_128PIO_64INDBM:         info->CCEFifoSize = 128; break;
-    case R128_PM4_128BM_64INDBM:          info->CCEFifoSize = 128; break;
-    case R128_PM4_64PIO_128INDBM:         info->CCEFifoSize = 64;  break;
-    case R128_PM4_64BM_128INDBM:          info->CCEFifoSize = 64;  break;
-    case R128_PM4_64PIO_64VCBM_64INDBM:   info->CCEFifoSize = 64;  break;
-    case R128_PM4_64BM_64VCBM_64INDBM:    info->CCEFifoSize = 64;  break;
-    case R128_PM4_64PIO_64VCPIO_64INDPIO: info->CCEFifoSize = 64;  break;
-    }
-
-    /* Make sure the CCE is on for the X server */
-    R128CCE_START(ctx, info);
-}
-
-
-static int R128MemoryInit(const DRIDriverContext *ctx)
-{
-   R128InfoPtr info = ctx->driverPrivate;
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        cpp         = ctx->cpp;
-   int        bufferSize  = ((ctx->shared.virtualHeight * width_bytes
-			      + R128_BUFFER_ALIGN)
-			     & ~R128_BUFFER_ALIGN);
-   int        depthSize   = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
-			      + R128_BUFFER_ALIGN)
-			     & ~R128_BUFFER_ALIGN);
-   int        l;
-
-   info->frontOffset = 0;
-   info->frontPitch = ctx->shared.virtualWidth;
-
-   fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", info->agpSize);
-   fprintf(stderr, 
-	   "Using %d MB for the ring buffer\n", info->ringSize);
-   fprintf(stderr, 
-	   "Using %d MB for vertex/indirect buffers\n", info->bufSize);
-   fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", info->agpTexSize);
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
-   if (info->textureSize < 0) 
-      return 0;
-
-   l = R128MinBits((info->textureSize-1) / R128_NR_TEX_REGIONS);
-   if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   info->log2TexGran = l;
-   info->textureSize = (info->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (info->textureSize < 512 * 1024) {
-      info->textureOffset = 0;
-      info->textureSize = 0;
-   }
-
-   /* Reserve space for textures */
-   info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
-			   R128_BUFFER_ALIGN) &
-			  ~R128_BUFFER_ALIGN);
-
-   /* Reserve space for the shared depth
-    * buffer.
-    */
-   info->depthOffset = ((info->textureOffset - depthSize +
-			 R128_BUFFER_ALIGN) &
-			~R128_BUFFER_ALIGN);
-   info->depthPitch = ctx->shared.virtualWidth;
-
-   info->backOffset = ((info->depthOffset - bufferSize +
-			R128_BUFFER_ALIGN) &
-		       ~R128_BUFFER_ALIGN);
-   info->backPitch = ctx->shared.virtualWidth;
-
-
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   info->backOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   info->depthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   info->textureSize/1024, info->textureOffset);
-
-   return 1;
-} 
-
-
-/* Initialize the screen-specific data structures for the DRI and the
-   Rage 128.  This is the main entry point to the device-specific
-   initialization code.  It calls device-independent DRI functions to
-   create the DRI data structures and initialize the DRI state. */
-static GLboolean R128DRIScreenInit(DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    R128DRIPtr    pR128DRI;
-    int           err, major, minor, patch;
-    drmVersionPtr version;
-    drm_r128_sarea_t *pSAREAPriv;
-
-    switch (ctx->bpp) {
-    case 8:
-	/* These modes are not supported (yet). */
-    case 15:
-    case 24:
-	fprintf(stderr,
-		   "[dri] R128DRIScreenInit failed (depth %d not supported).  "
-		   "[dri] Disabling DRI.\n", ctx->bpp);
-	return GL_FALSE;
-
-	/* Only 16 and 32 color depths are supports currently. */
-    case 16:
-    case 32:
-	break;
-    }
-    r128_drm_page_size = getpagesize();
-    
-    info->registerSize = ctx->MMIOSize;
-    ctx->shared.SAREASize = SAREA_MAX;
-
-    /* Note that drmOpen will try to load the kernel module, if needed. */
-    ctx->drmFD = drmOpen("r128", NULL );
-    if (ctx->drmFD < 0) {
-	fprintf(stderr, "[drm] drmOpen failed\n");
-	return 0;
-    }
-    
-    /* Check the r128 DRM version */
-    version = drmGetVersion(ctx->drmFD);
-    if (version) {
-	if (version->version_major != 2 ||
-	    version->version_minor < 2) {
-	    /* incompatible drm version */
-	    fprintf(stderr,
-		"[dri] R128DRIScreenInit failed because of a version mismatch.\n"
-		"[dri] r128.o kernel module version is %d.%d.%d but version 2.2 or greater is needed.\n"
-		"[dri] Disabling the DRI.\n",
-		version->version_major,
-		version->version_minor,
-		version->version_patchlevel);
-	    drmFreeVersion(version);
-	    return GL_FALSE;
-	}
-	info->drmMinor = version->version_minor;
-	drmFreeVersion(version);
-    }
-    
-    if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-	fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-		ctx->drmFD, ctx->pciBusID, strerror(-err));
-	return 0;
-    }
-    
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-		  0,
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-   if (!R128MemoryInit(ctx))
-	return GL_FALSE;
-   
-				/* Initialize AGP */
-    if (!info->IsPCI && !R128DRIAgpInit(ctx)) {
-	info->IsPCI = GL_TRUE;
-	fprintf(stderr,
-		   "[agp] AGP failed to initialize -- falling back to PCI mode.\n");
-	fprintf(stderr,
-		   "[agp] Make sure you have the agpgart kernel module loaded.\n");
-    }
-
-				/* Initialize PCIGART */
-    if (info->IsPCI && !R128DRIPciInit(ctx)) {
-	return GL_FALSE;
-    }
-
-				/* DRIScreenInit doesn't add all the
-				   common mappings.  Add additional
-				   mappings here. */
-    if (!R128DRIMapInit(ctx)) {
-	return GL_FALSE;
-    }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-    /* Initialize the kernel data structures */
-    if (!R128DRIKernelInit(ctx)) {
-	return GL_FALSE;
-    }
-
-    /* Initialize the vertex buffers list */
-    if (!R128DRIBufInit(ctx)) {
-	return GL_FALSE;
-    }
-
-    /* Initialize IRQ */
-    R128DRIIrqInit(ctx);
-
-    /* Initialize and start the CCE if required */
-    R128DRICCEInit(ctx);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   drimemsetio((char *)ctx->FBAddress + info->frontOffset,
-	  0,
-	  info->frontPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   drimemsetio((char *)ctx->FBAddress + info->backOffset,
-	  0,
-	  info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
-    
-    pSAREAPriv = (drm_r128_sarea_t *)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-    memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
-   /* This is the struct passed to radeon_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(R128DRIRec));
-   ctx->driverClientMsgSize = sizeof(R128DRIRec);
-   
-    pR128DRI                    = (R128DRIPtr)ctx->driverClientMsg;
-    pR128DRI->deviceID          = info->Chipset;
-    pR128DRI->width             = ctx->shared.virtualWidth;
-    pR128DRI->height            = ctx->shared.virtualHeight;
-    pR128DRI->depth             = ctx->bpp;
-    pR128DRI->bpp               = ctx->bpp;
-
-    pR128DRI->IsPCI             = info->IsPCI;
-    pR128DRI->AGPMode           = info->agpMode;
-
-    pR128DRI->frontOffset       = info->frontOffset;
-    pR128DRI->frontPitch        = info->frontPitch;
-    pR128DRI->backOffset        = info->backOffset;
-    pR128DRI->backPitch         = info->backPitch;
-    pR128DRI->depthOffset       = info->depthOffset;
-    pR128DRI->depthPitch        = info->depthPitch;
-    pR128DRI->spanOffset        = info->spanOffset;
-    pR128DRI->textureOffset     = info->textureOffset;
-    pR128DRI->textureSize       = info->textureSize;
-    pR128DRI->log2TexGran       = info->log2TexGran;
-
-    pR128DRI->registerHandle    = info->registerHandle;
-    pR128DRI->registerSize      = info->registerSize;
-
-    pR128DRI->agpTexHandle      = info->agpTexHandle;
-    pR128DRI->agpTexMapSize     = info->agpTexMapSize;
-    pR128DRI->log2AGPTexGran    = info->log2AGPTexGran;
-    pR128DRI->agpTexOffset      = info->agpTexStart;
-    pR128DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-    return GL_TRUE;
-}
-
-/* The screen is being closed, so clean up any state and free any
-   resources used by the DRI. */
-void R128DRICloseScreen(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    drm_r128_init_t drmInfo;
-
-    /* Stop the CCE if it is still in use */
-    R128CCE_STOP(ctx, info);
-
-    if (info->irq) {
-	drmCtlUninstHandler(ctx->drmFD);
-	info->irq = 0;
-    }
-
-    /* De-allocate vertex buffers */
-    if (info->buffers) {
-	drmUnmapBufs(info->buffers);
-	info->buffers = NULL;
-    }
-
-    /* De-allocate all kernel resources */
-    memset(&drmInfo, 0, sizeof(drmInfo));
-    drmInfo.func = R128_CLEANUP_CCE;
-    drmCommandWrite(ctx->drmFD, DRM_R128_INIT,
-                    &drmInfo, sizeof(drmInfo));
-
-    /* De-allocate all AGP resources */
-    if (info->agpTex) {
-	drmUnmap(info->agpTex, info->agpTexMapSize);
-	info->agpTex = NULL;
-    }
-    if (info->buf) {
-	drmUnmap(info->buf, info->bufMapSize);
-	info->buf = NULL;
-    }
-    if (info->ringReadPtr) {
-	drmUnmap(info->ringReadPtr, info->ringReadMapSize);
-	info->ringReadPtr = NULL;
-    }
-    if (info->ring) {
-	drmUnmap(info->ring, info->ringMapSize);
-	info->ring = NULL;
-    }
-    if (info->agpMemHandle != DRM_AGP_NO_HANDLE) {
-	drmAgpUnbind(ctx->drmFD, info->agpMemHandle);
-	drmAgpFree(ctx->drmFD, info->agpMemHandle);
-	info->agpMemHandle = 0;
-	drmAgpRelease(ctx->drmFD);
-    }
-    if (info->pciMemHandle) {
-	drmScatterGatherFree(ctx->drmFD, info->pciMemHandle);
-	info->pciMemHandle = 0;
-    }
-}
-
-static GLboolean R128PreInitDRI(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-
-    /*info->CCEMode = R128_DEFAULT_CCE_PIO_MODE;*/
-    info->CCEMode = R128_DEFAULT_CCE_BM_MODE;
-    info->CCESecure = GL_TRUE;
-
-    info->agpMode        = R128_DEFAULT_AGP_MODE;
-    info->agpSize        = R128_DEFAULT_AGP_SIZE;
-    info->ringSize       = R128_DEFAULT_RING_SIZE;
-    info->bufSize        = R128_DEFAULT_BUFFER_SIZE;
-    info->agpTexSize     = R128_DEFAULT_AGP_TEX_SIZE;
-
-    info->CCEusecTimeout = R128_DEFAULT_CCE_TIMEOUT;
-
-    return GL_TRUE;
-}
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls R128ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int R128InitFBDev( DRIDriverContext *ctx )
-{
-   R128InfoPtr info = calloc(1, sizeof(*info));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)info;
-   
-   info->Chipset = ctx->chipset;
-
-   switch (info->Chipset) {
-   case PCI_DEVICE_ID_ATI_RAGE128_LE:
-   case PCI_DEVICE_ID_ATI_RAGE128_RE:
-   case PCI_DEVICE_ID_ATI_RAGE128_RK:
-   case PCI_DEVICE_ID_ATI_RAGE128_PD:
-   case PCI_DEVICE_ID_ATI_RAGE128_PP:
-   case PCI_DEVICE_ID_ATI_RAGE128_PR:
-       /* This is a PCI card */
-       info->IsPCI = GL_TRUE;
-       break;
-   default:
-       /* This is an AGP card */
-       info->IsPCI = GL_FALSE;
-       break;
-   }
-
-   info->frontPitch = ctx->shared.virtualWidth;
-   info->LinearAddr = ctx->FBStart & 0xfc000000;
-   
-   if (!R128PreInitDRI(ctx))
-       return 0;
-
-   if (!R128DRIScreenInit(ctx))
-      return 0;
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void R128HaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa R128PostValidateMode().
- */
-static int R128ValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa R128ValidateMode().
- */
-static int R128PostValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int R128EngineShutdown( const DRIDriverContext *ctx )
-{
-    return 1;
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the R128 command processor engine (i.e., the ringbuffer).
- */
-static int R128EngineRestore( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   R128ValidateMode,
-   R128PostValidateMode,
-   R128InitFBDev,
-   R128HaltFBDev,
-   R128EngineShutdown,
-   R128EngineRestore,  
-   0,
-};
diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
index 14eb96c1bab..3f871005705 100644
--- a/src/mesa/drivers/dri/r200/Makefile
+++ b/src/mesa/drivers/dri/r200/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = r200_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c 
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
@@ -26,7 +24,9 @@ RADEON_COMMON_SOURCES = \
 	radeon_queryobj.c \
 	radeon_span.c \
 	radeon_texture.c \
-	radeon_tex_copy.c
+	radeon_tex_copy.c \
+	radeon_tex_getimage.c \
+	radeon_tile.c
 
 DRIVER_SOURCES = r200_context.c \
 		 r200_ioctl.c \
diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c
index b56327dad5f..30757600934 100644
--- a/src/mesa/drivers/dri/r200/r200_blit.c
+++ b/src/mesa/drivers/dri/r200/r200_blit.c
@@ -211,19 +211,16 @@ static GLboolean validate_buffers(struct r200_context *r200,
                                   struct radeon_bo *dst_bo)
 {
     int ret;
-    ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
-                                        src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-    if (ret)
-        return GL_FALSE;
+
+    radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs);
 
     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
-                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+                                        src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
     if (ret)
         return GL_FALSE;
 
     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
-                                        first_elem(&r200->radeon.dma.reserved)->bo,
-                                        RADEON_GEM_DOMAIN_GTT, 0);
+                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
     if (ret)
         return GL_FALSE;
 
diff --git a/src/mesa/drivers/dri/r200/radeon_tex_getimage.c b/src/mesa/drivers/dri/r200/radeon_tex_getimage.c
new file mode 120000
index 00000000000..d9836d7326e
--- /dev/null
+++ b/src/mesa/drivers/dri/r200/radeon_tex_getimage.c
@@ -0,0 +1 @@
+../radeon/radeon_tex_getimage.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r200/radeon_tile.c b/src/mesa/drivers/dri/r200/radeon_tile.c
new file mode 120000
index 00000000000..d4bfe27da64
--- /dev/null
+++ b/src/mesa/drivers/dri/r200/radeon_tile.c
@@ -0,0 +1 @@
+../radeon/radeon_tile.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r200/radeon_tile.h b/src/mesa/drivers/dri/r200/radeon_tile.h
new file mode 120000
index 00000000000..31074c581ea
--- /dev/null
+++ b/src/mesa/drivers/dri/r200/radeon_tile.h
@@ -0,0 +1 @@
+../radeon/radeon_tile.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r200/server/radeon_dri.c b/src/mesa/drivers/dri/r200/server/radeon_dri.c
deleted file mode 120000
index d05847d650f..00000000000
--- a/src/mesa/drivers/dri/r200/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile
index 04459c2ddfa..4257a32b89f 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = r300_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
@@ -36,7 +34,9 @@ RADEON_COMMON_SOURCES = \
 	radeon_span.c \
 	radeon_queryobj.c \
 	radeon_texture.c \
-	radeon_tex_copy.c
+	radeon_tex_copy.c \
+	radeon_tex_getimage.c \
+	radeon_tile.c
 
 DRIVER_SOURCES = \
 		 radeon_screen.c \
diff --git a/src/mesa/drivers/dri/r300/r300_blit.c b/src/mesa/drivers/dri/r300/r300_blit.c
index 2bc761bc208..d870c7f852a 100644
--- a/src/mesa/drivers/dri/r300/r300_blit.c
+++ b/src/mesa/drivers/dri/r300/r300_blit.c
@@ -381,19 +381,16 @@ static GLboolean validate_buffers(struct r300_context *r300,
                                   struct radeon_bo *dst_bo)
 {
     int ret;
-    ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
-                                        src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-    if (ret)
-        return GL_FALSE;
+
+    radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
 
     ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
-                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+                                        src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
     if (ret)
         return GL_FALSE;
 
     ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
-                                        first_elem(&r300->radeon.dma.reserved)->bo,
-                                        RADEON_GEM_DOMAIN_GTT, 0);
+                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
     if (ret)
         return GL_FALSE;
 
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 4787bafc66a..6cfa5686f4a 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -90,8 +90,7 @@ void r300_emit_vpu(struct r300_context *r300,
 {
     BATCH_LOCALS(&r300->radeon);
 
-    BEGIN_BATCH_NO_AUTOSTATE(5 + len);
-    OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+    BEGIN_BATCH_NO_AUTOSTATE(3 + len);
     OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
     OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR);
     OUT_BATCH_TABLE(data, len);
@@ -778,24 +777,6 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	/* VPU only on TCL */
 	if (has_tcl) {
 		int i;
-		if (r300->radeon.radeonScreen->kernel_mm) {
-			ALLOC_STATE(vap_flush, always, 10, 0);
-			/* flush processing vertices */
-			r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
-			r300->hw.vap_flush.cmd[1] = 0;
-			r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
-			r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
-			r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
-			r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
-			r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
-			r300->hw.vap_flush.cmd[7] = 0xffffff;
-			r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
-			r300->hw.vap_flush.cmd[9] = 0;
-		} else {
-			ALLOC_STATE(vap_flush, never, 10, 0);
-		}
-
-
 		ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 		r300->hw.vpi.cmd[0] =
 			cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index df4cc11da42..ff35cd52753 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -109,7 +109,6 @@ static const struct dri_extension card_extensions[] = {
   {"GL_EXT_blend_func_separate",	GL_EXT_blend_func_separate_functions},
   {"GL_EXT_blend_minmax",		GL_EXT_blend_minmax_functions},
   {"GL_EXT_blend_subtract",		NULL},
-  {"GL_EXT_packed_depth_stencil",	NULL},
   {"GL_EXT_fog_coord",			GL_EXT_fog_coord_functions },
   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
@@ -456,6 +455,9 @@ static void r300InitGLExtensions(GLcontext *ctx)
 	}
 	if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350)
   		_mesa_enable_extension(ctx, "GL_ARB_half_float_vertex");
+
+	if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+		_mesa_enable_extension(ctx, "GL_EXT_packed_depth_stencil");
 }
 
 static void r300InitIoctlFuncs(struct dd_function_table *functions)
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 78ab43a99f9..df7115e7dae 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -355,7 +355,6 @@ struct r300_hw_state {
 	struct radeon_state_atom zb_hiz_offset;	/* (4F44) */
 	struct radeon_state_atom zb_hiz_pitch;	/* (4F54) */
 
-	struct radeon_state_atom vap_flush;
 	struct radeon_state_atom vpi;	/* vp instructions */
 	struct radeon_state_atom vpp;	/* vp parameters */
 	struct radeon_state_atom vps;	/* vertex point size (?) */
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 9d1ff6e2ba2..5979dedac4f 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -366,7 +366,6 @@ static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
 	p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
 	ip = (GLint *)ctx->Transform._ClipUserPlane[p];
 
-	R300_STATECHANGE( rmesa, vap_flush );
 	R300_STATECHANGE( rmesa, vpucp[p] );
 	rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
 	rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
@@ -794,12 +793,14 @@ static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
 		R300_STATECHANGE(r300, ga_point_minmax);
 		r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK;
 		r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0);
+		r300PointSize(ctx, ctx->Point.Size);
 		break;
 	case GL_POINT_SIZE_MAX:
 		R300_STATECHANGE(r300, ga_point_minmax);
 		r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK;
 		r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0)
 			<< R300_GA_POINT_MINMAX_MAX_SHIFT;
+		r300PointSize(ctx, ctx->Point.Size);
 		break;
 	case GL_POINT_DISTANCE_ATTENUATION:
 		break;
@@ -1762,8 +1763,6 @@ static void r300ResetHwState(r300ContextPtr r300)
 	if (RADEON_DEBUG & RADEON_STATE)
 		fprintf(stderr, "%s\n", __FUNCTION__);
 
-	radeon_firevertices(&r300->radeon);
-
 	r300ColorMask(ctx,
 		      ctx->Color.ColorMask[0][RCOMP],
 		      ctx->Color.ColorMask[0][GCOMP],
@@ -1985,23 +1984,6 @@ void r300UpdateShaders(r300ContextPtr rmesa)
 	if (rmesa->options.hw_tcl_enabled) {
 		struct r300_vertex_program *vp;
 
-		if (rmesa->radeon.NewGLState) {
-			int i;
-			for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
-				rmesa->temp_attrib[i] =
-				    TNL_CONTEXT(ctx)->vb.AttribPtr[i];
-				TNL_CONTEXT(ctx)->vb.AttribPtr[i] =
-				    &rmesa->dummy_attrib[i];
-			}
-
-			_tnl_UpdateFixedFunctionProgram(ctx);
-
-			for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
-				TNL_CONTEXT(ctx)->vb.AttribPtr[i] =
-				    rmesa->temp_attrib[i];
-			}
-		}
-
 		vp = r300SelectAndTranslateVertexShader(ctx);
 
 		r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, vp->error);
diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c
index cbe4cb83047..129004fee78 100644
--- a/src/mesa/drivers/dri/r300/r300_vertprog.c
+++ b/src/mesa/drivers/dri/r300/r300_vertprog.c
@@ -342,8 +342,6 @@ static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_ver
 
 	assert((code->length > 0) && (code->length % 4 == 0));
 
-	R300_STATECHANGE( r300, vap_flush );
-
 	switch ((dest >> 8) & 0xf) {
 		case 0:
 			R300_STATECHANGE(r300, vpi);
@@ -381,7 +379,7 @@ void r300SetupVertexProgram(r300ContextPtr rmesa)
 	((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0;
 	((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0;
 
-	R300_STATECHANGE(rmesa, vap_flush);
+	R300_STATECHANGE(rmesa, vap_cntl);
 	R300_STATECHANGE(rmesa, vpp);
 	param_count = r300VertexProgUpdateParams(ctx, prog, (float *)&rmesa->hw.vpp.cmd[R300_VPP_PARAM_0]);
 	bump_vpu_count(rmesa->hw.vpp.cmd, param_count);
diff --git a/src/mesa/drivers/dri/r300/radeon_tex_getimage.c b/src/mesa/drivers/dri/r300/radeon_tex_getimage.c
new file mode 120000
index 00000000000..d9836d7326e
--- /dev/null
+++ b/src/mesa/drivers/dri/r300/radeon_tex_getimage.c
@@ -0,0 +1 @@
+../radeon/radeon_tex_getimage.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r300/radeon_tile.c b/src/mesa/drivers/dri/r300/radeon_tile.c
new file mode 120000
index 00000000000..d4bfe27da64
--- /dev/null
+++ b/src/mesa/drivers/dri/r300/radeon_tile.c
@@ -0,0 +1 @@
+../radeon/radeon_tile.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r300/radeon_tile.h b/src/mesa/drivers/dri/r300/radeon_tile.h
new file mode 120000
index 00000000000..31074c581ea
--- /dev/null
+++ b/src/mesa/drivers/dri/r300/radeon_tile.h
@@ -0,0 +1 @@
+../radeon/radeon_tile.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r300/server/radeon_dri.c b/src/mesa/drivers/dri/r300/server/radeon_dri.c
deleted file mode 120000
index d05847d650f..00000000000
--- a/src/mesa/drivers/dri/r300/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile
index 5d509415393..f76859d11e2 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = r600_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
@@ -36,7 +34,9 @@ RADEON_COMMON_SOURCES = \
 	radeon_span.c \
 	radeon_texture.c \
 	radeon_queryobj.c \
-	radeon_tex_copy.c
+	radeon_tex_copy.c \
+	radeon_tex_getimage.c \
+	radeon_tile.c
 
 DRIVER_SOURCES = \
 		 radeon_screen.c \
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 9d17463cae1..244fdc4ffbb 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -1533,13 +1533,15 @@ static GLboolean validate_buffers(context_t *rmesa,
 {
     int ret;
 
+    radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
+
     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
-					src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
+					src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
     if (ret)
         return GL_FALSE;
 
     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
-                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
     if (ret)
         return GL_FALSE;
 
@@ -1549,12 +1551,6 @@ static GLboolean validate_buffers(context_t *rmesa,
     if (ret)
         return GL_FALSE;
 
-    ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
-                                        first_elem(&rmesa->radeon.dma.reserved)->bo,
-                                        RADEON_GEM_DOMAIN_GTT, 0);
-    if (ret)
-        return GL_FALSE;
-
     return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 3d6802e735b..134e97e7c33 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -140,6 +140,7 @@ static const struct dri_extension card_extensions[] = {
   {"GL_NV_blend_square",		NULL},
   {"GL_NV_vertex_program",		GL_NV_vertex_program_functions},
   {"GL_SGIS_generate_mipmap",		NULL},
+  {"GL_ARB_pixel_buffer_object",        NULL},
   {NULL,				NULL}
   /* *INDENT-ON* */
 };
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 4ebdbbfad25..6f156b54096 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -911,10 +911,12 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
 	case GL_POINT_SIZE_MIN:
 		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
 			 MIN_SIZE_shift, MIN_SIZE_mask);
+		r700PointSize(ctx, ctx->Point.Size);
 		break;
 	case GL_POINT_SIZE_MAX:
 		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
 			 MAX_SIZE_shift, MAX_SIZE_mask);
+		r700PointSize(ctx, ctx->Point.Size);
 		break;
 	case GL_POINT_DISTANCE_ATTENUATION:
 		break;
@@ -1626,8 +1628,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
     int id = 0;
 
-    radeon_firevertices(&context->radeon);
-
     r700->TA_CNTL_AUX.u32All = 0;
     SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
     r700->VC_ENHANCE.u32All = 0;
diff --git a/src/mesa/drivers/dri/r600/radeon_tex_getimage.c b/src/mesa/drivers/dri/r600/radeon_tex_getimage.c
new file mode 120000
index 00000000000..d9836d7326e
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_tex_getimage.c
@@ -0,0 +1 @@
+../radeon/radeon_tex_getimage.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_tile.c b/src/mesa/drivers/dri/r600/radeon_tile.c
new file mode 120000
index 00000000000..d4bfe27da64
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_tile.c
@@ -0,0 +1 @@
+../radeon/radeon_tile.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_tile.h b/src/mesa/drivers/dri/r600/radeon_tile.h
new file mode 120000
index 00000000000..31074c581ea
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_tile.h
@@ -0,0 +1 @@
+../radeon/radeon_tile.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_dri.c b/src/mesa/drivers/dri/r600/server/radeon_dri.c
deleted file mode 120000
index d05847d650f..00000000000
--- a/src/mesa/drivers/dri/r600/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile
index a54ea16ec63..6904ebbee3b 100644
--- a/src/mesa/drivers/dri/radeon/Makefile
+++ b/src/mesa/drivers/dri/radeon/Makefile
@@ -8,8 +8,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = radeon_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c 
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
@@ -27,7 +25,9 @@ RADEON_COMMON_SOURCES = \
 	radeon_queryobj.c \
 	radeon_span.c \
 	radeon_texture.c \
-	radeon_tex_copy.c
+	radeon_tex_copy.c \
+	radeon_tex_getimage.c \
+	radeon_tile.c
 
 DRIVER_SOURCES = \
 	radeon_context.c \
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c
index e188a122d53..e1e1f215508 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.c
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.c
@@ -204,19 +204,16 @@ static GLboolean validate_buffers(struct r100_context *r100,
                                   struct radeon_bo *dst_bo)
 {
     int ret;
-    ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs,
-                                        src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
-    if (ret)
-        return GL_FALSE;
+
+    radeon_cs_space_reset_bos(r100->radeon.cmdbuf.cs);
 
     ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs,
-                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
+                                        src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
     if (ret)
         return GL_FALSE;
 
     ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs,
-                                        first_elem(&r100->radeon.dma.reserved)->bo,
-                                        RADEON_GEM_DOMAIN_GTT, 0);
+                                        dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
     if (ret)
         return GL_FALSE;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 79f3ff7da65..13f1f0611b8 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -1325,11 +1325,6 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n,
 		       const char *function,
 		       int line)
 {
-	if (!rmesa->cmdbuf.cs->cdw && dostate) {
-		radeon_print(RADEON_STATE, RADEON_NORMAL,
-				"Reemit state after flush (from %s)\n", function);
-		radeonEmitState(rmesa);
-	}
 	radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line);
 
     radeon_print(RADEON_CS, RADEON_VERBOSE, "BEGIN_BATCH(%d) at %d, from %s:%i\n",
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index cd843d965e5..c6cc417dd6c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -36,6 +36,7 @@
 #include "main/texobj.h"
 #include "main/enums.h"
 #include "radeon_texture.h"
+#include "radeon_tile.h"
 
 static unsigned get_aligned_compressed_row_stride(
 		gl_format format,
@@ -69,16 +70,51 @@ static unsigned get_aligned_compressed_row_stride(
 	return stride;
 }
 
-static unsigned get_compressed_image_size(
+unsigned get_texture_image_size(
 		gl_format format,
 		unsigned rowStride,
-		unsigned height)
+		unsigned height,
+		unsigned depth,
+		unsigned tiling)
 {
-	unsigned blockWidth, blockHeight;
+	if (_mesa_is_format_compressed(format)) {
+		unsigned blockWidth, blockHeight;
 
-	_mesa_get_format_block_size(format, &blockWidth, &blockHeight);
+		_mesa_get_format_block_size(format, &blockWidth, &blockHeight);
+
+		return rowStride * ((height + blockHeight - 1) / blockHeight) * depth;
+	} else if (tiling) {
+		/* Need to align height to tile height */
+		unsigned tileWidth, tileHeight;
 
-	return rowStride * ((height + blockHeight - 1) / blockHeight);
+		get_tile_size(format, &tileWidth, &tileHeight);
+		tileHeight--;
+
+		height = (height + tileHeight) & ~tileHeight;
+	}
+
+	return rowStride * height * depth;
+}
+
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
+{
+	if (_mesa_is_format_compressed(format)) {
+		return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
+	} else {
+		unsigned row_align;
+
+		if (!_mesa_is_pow_two(width)) {
+			row_align = rmesa->texture_rect_row_align - 1;
+		} else if (tiling) {
+			unsigned tileWidth, tileHeight;
+			get_tile_size(format, &tileWidth, &tileHeight);
+			row_align = tileWidth * _mesa_get_format_bytes(format) - 1;
+		} else {
+			row_align = rmesa->texture_row_align - 1;
+		}
+
+		return (_mesa_format_row_stride(format, width) + row_align) & ~row_align;
+	}
 }
 
 /**
@@ -92,34 +128,15 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = &mt->levels[level];
-	uint32_t row_align;
 	GLuint height;
 
 	height = _mesa_next_pow_two_32(lvl->height);
 
-	/* Find image size in bytes */
-	if (_mesa_is_format_compressed(mt->mesaFormat)) {
-		lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align);
-		lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height);
-	} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
-		row_align = rmesa->texture_rect_row_align - 1;
-		lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
-		lvl->size = lvl->rowstride * height;
-	} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
-		/* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
-		 * though the actual offset may be different (if texture is less than
-		 * 32 bytes width) to the untiled case */
-		lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31;
-		lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth;
-	} else {
-		row_align = rmesa->texture_row_align - 1;
-		lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
-		lvl->size = lvl->rowstride * height * lvl->depth;
-	}
+	lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
+	lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, lvl->height, lvl->depth, mt->tilebits);
+
 	assert(lvl->size > 0);
 
-	/* All images are aligned to a 32-byte offset */
-	*curOffset = (*curOffset + 0x1f) & ~0x1f;
 	lvl->faces[face].offset = *curOffset;
 	*curOffset += lvl->size;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index c911688c1a5..088f9701722 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -89,4 +89,13 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t);
 GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 				   GLuint face, GLuint level);
 uint32_t get_base_teximage_offset(radeonTexObj *texObj);
+
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling);
+
+unsigned get_texture_image_size(
+		gl_format format,
+		unsigned rowStride,
+		unsigned height,
+		unsigned depth,
+		unsigned tiling);
 #endif /* __RADEON_MIPMAP_TREE_H_ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
index 89fe9915a70..a4bb03d5d39 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
@@ -53,6 +53,10 @@ do_copy_texsubimage(GLcontext *ctx,
     unsigned src_width;
     unsigned dst_width;
 
+    if (!radeon->vtbl.blit) {
+        return GL_FALSE;
+    }
+
     if (_mesa_get_format_bits(timg->base.TexFormat, GL_DEPTH_BITS) > 0) {
         rrb = radeon_get_depthbuffer(radeon);
     } else {
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c b/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c
new file mode 100644
index 00000000000..7bf6dcc2e32
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_getimage.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2009 Maciej Cencora.
+ * Copyright (C) 2008 Nicolai Haehnle.
+ * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
+ *
+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
+ * initial release of the Radeon 8500 driver under the XFree86 license.
+ * This notice must be preserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "radeon_common_context.h"
+#include "radeon_texture.h"
+#include "radeon_mipmap_tree.h"
+
+#include "main/texgetimage.h"
+
+/**
+ * Need to map texture image into memory before copying image data,
+ * then unmap it.
+ */
+static void
+radeon_get_tex_image(GLcontext * ctx, GLenum target, GLint level,
+             GLenum format, GLenum type, GLvoid * pixels,
+             struct gl_texture_object *texObj,
+             struct gl_texture_image *texImage, int compressed)
+{
+    radeon_texture_image *image = get_radeon_texture_image(texImage);
+
+    radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
+                 "%s(%p, tex %p, image %p) compressed %d.\n",
+                 __func__, ctx, texObj, image, compressed);
+
+    if (image->mt) {
+        /* Map the texture image read-only */
+        radeon_teximage_map(image, GL_FALSE);
+    } else {
+        /* Image hasn't been uploaded to a miptree yet */
+        assert(image->base.Data);
+    }
+
+    if (compressed) {
+        /* FIXME: this can't work for small textures (mips) which
+                 use different hw stride */
+        _mesa_get_compressed_teximage(ctx, target, level, pixels,
+                          texObj, texImage);
+    } else {
+        _mesa_get_teximage(ctx, target, level, format, type, pixels,
+                   texObj, texImage);
+    }
+
+    if (image->mt) {
+        radeon_teximage_unmap(image);
+    }
+}
+
+void
+radeonGetTexImage(GLcontext * ctx, GLenum target, GLint level,
+          GLenum format, GLenum type, GLvoid * pixels,
+          struct gl_texture_object *texObj,
+          struct gl_texture_image *texImage)
+{
+    radeon_get_tex_image(ctx, target, level, format, type, pixels,
+                 texObj, texImage, 0);
+}
+
+void
+radeonGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level,
+                GLvoid *pixels,
+                struct gl_texture_object *texObj,
+                struct gl_texture_image *texImage)
+{
+    radeon_get_tex_image(ctx, target, level, 0, 0, pixels,
+                 texObj, texImage, 1);
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index ff37fd3e86e..3ccc711253b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -39,7 +39,6 @@
 #include "main/texstore.h"
 #include "main/teximage.h"
 #include "main/texobj.h"
-#include "main/texgetimage.h"
 
 #include "xmlpool.h"		/* for symbolic values of enum-type options */
 
@@ -559,6 +558,15 @@ gl_format radeonChooseTextureFormat(GLcontext * ctx,
 	case GL_COMPRESSED_SLUMINANCE_ALPHA:
 		return MESA_FORMAT_SLA8;
 
+	case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT:
+		return MESA_FORMAT_SRGB_DXT1;
+	case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT:
+		return MESA_FORMAT_SRGBA_DXT1;
+	case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT:
+		return MESA_FORMAT_SRGBA_DXT3;
+	case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT:
+		return MESA_FORMAT_SRGBA_DXT5;
+
 	default:
 		_mesa_problem(ctx,
 			      "unexpected internalFormat 0x%x in %s",
@@ -664,6 +672,7 @@ static void radeon_store_teximage(GLcontext* ctx, int dims,
 		struct gl_texture_image *texImage,
 		int compressed)
 {
+	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 	radeonTexObj *t = radeon_tex_obj(texObj);
 	radeon_texture_image* image = get_radeon_texture_image(texImage);
 
@@ -678,8 +687,7 @@ static void radeon_store_teximage(GLcontext* ctx, int dims,
 		dstRowStride = image->mt->levels[image->mtlevel].rowstride;
 	} else if (t->bo) {
 		/* TFP case */
-		/* TODO */
-		assert(0);
+		dstRowStride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0);
 	} else {
 		dstRowStride = _mesa_format_row_stride(texImage->TexFormat, texImage->Width);
 	}
@@ -998,62 +1006,3 @@ void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level,
 	radeon_texsubimage(ctx, 3, target, level, xoffset, yoffset, zoffset, width, height, depth, 0,
 		format, type, pixels, packing, texObj, texImage, 0);
 }
-
-/**
- * Need to map texture image into memory before copying image data,
- * then unmap it.
- */
-static void
-radeon_get_tex_image(GLcontext * ctx, GLenum target, GLint level,
-		     GLenum format, GLenum type, GLvoid * pixels,
-		     struct gl_texture_object *texObj,
-		     struct gl_texture_image *texImage, int compressed)
-{
-	radeon_texture_image *image = get_radeon_texture_image(texImage);
-
-	radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
-			"%s(%p, tex %p, image %p) compressed %d.\n",
-			__func__, ctx, texObj, image, compressed);
-
-	if (image->mt) {
-		/* Map the texture image read-only */
-		radeon_teximage_map(image, GL_FALSE);
-	} else {
-		/* Image hasn't been uploaded to a miptree yet */
-		assert(image->base.Data);
-	}
-
-	if (compressed) {
-		/* FIXME: this can't work for small textures (mips) which
-		         use different hw stride */
-		_mesa_get_compressed_teximage(ctx, target, level, pixels,
-					      texObj, texImage);
-	} else {
-		_mesa_get_teximage(ctx, target, level, format, type, pixels,
-				   texObj, texImage);
-	}
-     
-	if (image->mt) {
-		radeon_teximage_unmap(image);
-	}
-}
-
-void
-radeonGetTexImage(GLcontext * ctx, GLenum target, GLint level,
-		  GLenum format, GLenum type, GLvoid * pixels,
-		  struct gl_texture_object *texObj,
-		  struct gl_texture_image *texImage)
-{
-	radeon_get_tex_image(ctx, target, level, format, type, pixels,
-			     texObj, texImage, 0);
-}
-
-void
-radeonGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level,
-			    GLvoid *pixels,
-			    struct gl_texture_object *texObj,
-			    struct gl_texture_image *texImage)
-{
-	radeon_get_tex_image(ctx, target, level, 0, 0, pixels,
-			     texObj, texImage, 1);
-}
diff --git a/src/mesa/drivers/dri/radeon/radeon_tile.c b/src/mesa/drivers/dri/radeon/radeon_tile.c
new file mode 100644
index 00000000000..403da110106
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_tile.c
@@ -0,0 +1,512 @@
+/*
+ * Copyright (C) 2010 Maciej Cencora <[email protected]>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "radeon_tile.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#include "main/macros.h"
+#include "radeon_debug.h"
+
+#define MICRO_TILE_SIZE 32
+
+static void micro_tile_8_x_4_8bit(const void * const src, unsigned src_pitch,
+                                  void * const dst, unsigned dst_pitch,
+                                  unsigned width, unsigned height)
+{
+    unsigned row; /* current source row */
+    unsigned col; /* current source column */
+    unsigned k; /* number of processed tiles */
+    const unsigned tile_width = 8, tile_height = 4;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint8_t *src2 = (uint8_t *)src + src_pitch * row + col;
+            uint8_t *dst2 = (uint8_t *)dst + row * dst_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint8_t);
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint8_t));
+                dst2 += tile_width;
+                src2 += src_pitch;
+            }
+        }
+    }
+}
+
+static void micro_tile_4_x_4_16bit(const void * const src, unsigned src_pitch,
+                                   void * const dst, unsigned dst_pitch,
+                                   unsigned width, unsigned height)
+{
+    unsigned row; /* current source row */
+    unsigned col; /* current source column */
+    unsigned k; /* number of processed tiles */
+    const unsigned tile_width = 4, tile_height = 4;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint16_t *src2 = (uint16_t *)src + src_pitch * row + col;
+            uint16_t *dst2 = (uint16_t *)dst + row * dst_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint16_t);
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint16_t));
+                dst2 += tile_width;
+                src2 += src_pitch;
+            }
+        }
+    }
+}
+
+static void micro_tile_8_x_2_16bit(const void * const src, unsigned src_pitch,
+                                   void * const dst, unsigned dst_pitch,
+                                   unsigned width, unsigned height)
+{
+    unsigned row; /* current source row */
+    unsigned col; /* current source column */
+    unsigned k; /* number of processed tiles */
+    const unsigned tile_width = 8, tile_height = 2;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint16_t *src2 = (uint16_t *)src + src_pitch * row + col;
+            uint16_t *dst2 = (uint16_t *)dst + row * dst_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint16_t);
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint16_t));
+                dst2 += tile_width;
+                src2 += src_pitch;
+            }
+        }
+    }
+}
+
+static void micro_tile_4_x_2_32bit(const void * const src, unsigned src_pitch,
+                                   void * const dst, unsigned dst_pitch,
+                                   unsigned width, unsigned height)
+{
+    unsigned row; /* current source row */
+    unsigned col; /* current source column */
+    unsigned k; /* number of processed tiles */
+    const unsigned tile_width = 4, tile_height = 2;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint32_t *src2 = (uint32_t *)src + src_pitch * row + col;
+            uint32_t *dst2 = (uint32_t *)dst + row * dst_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint32_t);
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint32_t));
+                dst2 += tile_width;
+                src2 += src_pitch;
+            }
+        }
+    }
+}
+
+static void micro_tile_2_x_2_64bit(const void * const src, unsigned src_pitch,
+                                   void * const dst, unsigned dst_pitch,
+                                   unsigned width, unsigned height)
+{
+    unsigned row; /* current source row */
+    unsigned col; /* current source column */
+    unsigned k; /* number of processed tiles */
+    const unsigned tile_width = 2, tile_height = 2;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint64_t *src2 = (uint64_t *)src + src_pitch * row + col;
+            uint64_t *dst2 = (uint64_t *)dst + row * dst_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint64_t);
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint64_t));
+                dst2 += tile_width;
+                src2 += src_pitch;
+            }
+        }
+    }
+}
+
+static void micro_tile_1_x_1_128bit(const void * src, unsigned src_pitch,
+                                    void * dst, unsigned dst_pitch,
+                                    unsigned width, unsigned height)
+{
+    unsigned i, j;
+    const unsigned elem_size = 16; /* sizeof(uint128_t) */
+
+    for (j = 0; j < height; ++j)
+    {
+        for (i = 0; i < width; ++i)
+        {
+            memcpy(dst, src, width * elem_size);
+            dst += dst_pitch * elem_size;
+            src += src_pitch * elem_size;
+        }
+    }
+}
+
+void tile_image(const void * src, unsigned src_pitch,
+                void *dst, unsigned dst_pitch,
+                gl_format format, unsigned width, unsigned height)
+{
+    assert(src_pitch >= width);
+    assert(dst_pitch >= width);
+
+    radeon_print(RADEON_TEXTURE, RADEON_TRACE,
+                 "Software tiling: src_pitch %d, dst_pitch %d, width %d, height %d, bpp %d\n",
+                 src_pitch, dst_pitch, width, height, _mesa_get_format_bytes(format));
+
+    switch (_mesa_get_format_bytes(format))
+    {
+        case 16:
+            micro_tile_1_x_1_128bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        case 8:
+            micro_tile_2_x_2_64bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        case 4:
+            micro_tile_4_x_2_32bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        case 2:
+            if (_mesa_get_format_bits(format, GL_DEPTH_BITS))
+            {
+                micro_tile_4_x_4_16bit(src, src_pitch, dst, dst_pitch, width, height);
+            }
+            else
+            {
+                micro_tile_8_x_2_16bit(src, src_pitch, dst, dst_pitch, width, height);
+            }
+            break;
+        case 1:
+            micro_tile_8_x_4_8bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+}
+
+static void micro_untile_8_x_4_8bit(const void * const src, unsigned src_pitch,
+                                    void * const dst, unsigned dst_pitch,
+                                    unsigned width, unsigned height)
+{
+    unsigned row; /* current destination row */
+    unsigned col; /* current destination column */
+    unsigned k; /* current tile number */
+    const unsigned tile_width = 8, tile_height = 4;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    assert(src_pitch % tile_width == 0);
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint8_t *src2 = (uint8_t *)src + row * src_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint8_t);
+            uint8_t *dst2 = (uint8_t *)dst + dst_pitch * row + col;
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint8_t));
+                dst2 += dst_pitch;
+                src2 += tile_width;
+            }
+        }
+    }
+}
+
+static void micro_untile_8_x_2_16bit(const void * const src, unsigned src_pitch,
+                                     void * const dst, unsigned dst_pitch,
+                                     unsigned width, unsigned height)
+{
+    unsigned row; /* current destination row */
+    unsigned col; /* current destination column */
+    unsigned k; /* current tile number */
+    const unsigned tile_width = 8, tile_height = 2;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    assert(src_pitch % tile_width == 0);
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint16_t *src2 = (uint16_t *)src + row * src_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint16_t);
+            uint16_t *dst2 = (uint16_t *)dst + dst_pitch * row + col;
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint16_t));
+                dst2 += dst_pitch;
+                src2 += tile_width;
+            }
+        }
+    }
+}
+
+static void micro_untile_4_x_4_16bit(const void * const src, unsigned src_pitch,
+                                     void * const dst, unsigned dst_pitch,
+                                     unsigned width, unsigned height)
+{
+    unsigned row; /* current destination row */
+    unsigned col; /* current destination column */
+    unsigned k; /* current tile number */
+    const unsigned tile_width = 4, tile_height = 4;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    assert(src_pitch % tile_width == 0);
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint16_t *src2 = (uint16_t *)src + row * src_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint16_t);
+            uint16_t *dst2 = (uint16_t *)dst + dst_pitch * row + col;
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint16_t));
+                dst2 += dst_pitch;
+                src2 += tile_width;
+            }
+        }
+    }
+}
+
+static void micro_untile_4_x_2_32bit(const void * const src, unsigned src_pitch,
+                                     void * const dst, unsigned dst_pitch,
+                                     unsigned width, unsigned height)
+{
+    unsigned row; /* current destination row */
+    unsigned col; /* current destination column */
+    unsigned k; /* current tile number */
+    const unsigned tile_width = 4, tile_height = 2;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    assert(src_pitch % tile_width == 0);
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint32_t *src2 = (uint32_t *)src + row * src_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint32_t);
+            uint32_t *dst2 = (uint32_t *)dst + dst_pitch * row + col;
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint32_t));
+                dst2 += dst_pitch;
+                src2 += tile_width;
+            }
+        }
+    }
+}
+
+static void micro_untile_2_x_2_64bit(const void * const src, unsigned src_pitch,
+                                     void * const dst, unsigned dst_pitch,
+                                     unsigned width, unsigned height)
+{
+    unsigned row; /* current destination row */
+    unsigned col; /* current destination column */
+    unsigned k; /* current tile number */
+    const unsigned tile_width = 2, tile_height = 2;
+    const unsigned tiles_in_row = (width + (tile_width - 1)) / tile_width;
+
+    assert(src_pitch % tile_width == 0);
+
+    k = 0;
+    for (row = 0; row < height; row += tile_height)
+    {
+        for (col = 0; col < width; col += tile_width, ++k)
+        {
+            uint64_t *src2 = (uint64_t *)src + row * src_pitch +
+                             (k % tiles_in_row) * MICRO_TILE_SIZE / sizeof(uint64_t);
+            uint64_t *dst2 = (uint64_t *)dst + dst_pitch * row + col;
+            unsigned j;
+
+            for (j = 0; j < MIN2(tile_height, height - row); ++j)
+            {
+                unsigned columns = MIN2(tile_width, width - col);
+                memcpy(dst2, src2, columns * sizeof(uint64_t));
+                dst2 += dst_pitch;
+                src2 += tile_width;
+            }
+        }
+    }
+}
+
+static void micro_untile_1_x_1_128bit(const void * src, unsigned src_pitch,
+                                      void * dst, unsigned dst_pitch,
+                                      unsigned width, unsigned height)
+{
+    unsigned i, j;
+    const unsigned elem_size = 16; /* sizeof(uint128_t) */
+
+    for (j = 0; j < height; ++j)
+    {
+        for (i = 0; i < width; ++i)
+        {
+            memcpy(dst, src, width * elem_size);
+            dst += dst_pitch * elem_size;
+            src += src_pitch * elem_size;
+        }
+    }
+}
+
+void untile_image(const void * src, unsigned src_pitch,
+                  void *dst, unsigned dst_pitch,
+                  gl_format format, unsigned width, unsigned height)
+{
+    assert(src_pitch >= width);
+    assert(dst_pitch >= width);
+
+    radeon_print(RADEON_TEXTURE, RADEON_TRACE,
+                 "Software untiling: src_pitch %d, dst_pitch %d, width %d, height %d, bpp %d\n",
+                 src_pitch, dst_pitch, width, height, _mesa_get_format_bytes(format));
+
+    switch (_mesa_get_format_bytes(format))
+    {
+        case 16:
+            micro_untile_1_x_1_128bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        case 8:
+            micro_untile_2_x_2_64bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        case 4:
+            micro_untile_4_x_2_32bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        case 2:
+            if (_mesa_get_format_bits(format, GL_DEPTH_BITS))
+            {
+                micro_untile_4_x_4_16bit(src, src_pitch, dst, dst_pitch, width, height);
+            }
+            else
+            {
+                micro_untile_8_x_2_16bit(src, src_pitch, dst, dst_pitch, width, height);
+            }
+            break;
+        case 1:
+            micro_untile_8_x_4_8bit(src, src_pitch, dst, dst_pitch, width, height);
+            break;
+        default:
+            assert(0);
+            break;
+    }
+}
+
+void get_tile_size(gl_format format, unsigned *block_width, unsigned *block_height)
+{
+    switch (_mesa_get_format_bytes(format))
+    {
+        case 16:
+            *block_width = 1;
+            *block_height = 1;
+            break;
+        case 8:
+            *block_width = 2;
+            *block_height = 2;
+            break;
+        case 4:
+            *block_width = 4;
+            *block_height = 2;
+            break;
+        case 2:
+            if (_mesa_get_format_bits(format, GL_DEPTH_BITS))
+            {
+                *block_width = 4;
+                *block_height = 4;
+            }
+            else
+            {
+                *block_width = 8;
+                *block_height = 2;
+            }
+            break;
+        case 1:
+            *block_width = 8;
+            *block_height = 4;
+            break;
+        default:
+            assert(0);
+            break;
+    }
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_tile.h b/src/mesa/drivers/dri/radeon/radeon_tile.h
new file mode 100644
index 00000000000..31d9c5611c3
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_tile.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Maciej Cencora <[email protected]>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <main/formats.h>
+
+void tile_image(const void * src, unsigned src_pitch,
+                void *dst, unsigned dst_pitch,
+                gl_format format, unsigned width, unsigned height);
+
+void untile_image(const void * src, unsigned src_pitch,
+                  void *dst, unsigned dst_pitch,
+                  gl_format format, unsigned width, unsigned height);
+
+void get_tile_size(gl_format format, unsigned *block_width, unsigned *block_height);
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
deleted file mode 100644
index 7ead588dac8..00000000000
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-/**
- * \file server/radeon_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "radeon.h"
-#include "radeon_dri.h"
-#include "radeon_macros.h"
-#include "radeon_reg.h"
-#include "drm_sarea.h"
-
-static size_t radeon_drm_page_size;
-
-static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value)
-{
-   drm_radeon_setparam_t sp;
-
-   memset(&sp, 0, sizeof(sp));
-   sp.param = param;
-   sp.value = value;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) {
-     return -1;
-   }
-
-   return 0;
-}
-
-/**
- * \brief Wait for free FIFO entries.
- *
- * \param ctx display handle.
- * \param entries number of free entries to wait.
- *
- * It polls the free entries from the chip until it reaches the requested value
- * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out.
- */
-static void RADEONWaitForFifo( const DRIDriverContext *ctx,
-			       int entries )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   int i;
-
-   for (i = 0; i < 3000; i++) {
-      int fifo_slots =
-	 INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
-      if (fifo_slots >= entries) return;
-   }
-
-   /* There are recoveries possible, but I haven't seen them work
-    * in practice:
-    */
-   fprintf(stderr, "FIFO timed out: %d entries, stat=0x%08x\n",
-	   INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
-	   INREG(RADEON_RBBM_STATUS));
-   exit(1);
-}
-
-/**
- * \brief Read a PLL register.
- *
- * \param ctx display handle.
- * \param addr PLL register index.
- *
- * \return value of the PLL register.
- */
-static unsigned int RADEONINPLL( const DRIDriverContext *ctx, int addr)
-{
-    unsigned char *RADEONMMIO = ctx->MMIOAddress;
-    unsigned int data;
-
-    OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
-    data = INREG(RADEON_CLOCK_CNTL_DATA);
-
-    return data;
-}
-
-/**
- * \brief Reset graphics card to known state.
- *
- * \param ctx display handle.
- *
- * Resets the values of several Radeon registers.
- */
-static void RADEONEngineReset( const DRIDriverContext *ctx )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   unsigned int clock_cntl_index;
-   unsigned int mclk_cntl;
-   unsigned int rbbm_soft_reset;
-   unsigned int host_path_cntl;
-   int i;
-
-   OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT,
-	   RADEON_RB2D_DC_FLUSH_ALL,
-	   ~RADEON_RB2D_DC_FLUSH_ALL);
-   for (i = 0; i < 512; i++) {
-      if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY))
-	 break;
-   }
-
-   clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
-
-   mclk_cntl = INPLL(ctx, RADEON_MCLK_CNTL);
-   OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
-			     RADEON_FORCEON_MCLKA |
-			     RADEON_FORCEON_MCLKB |
-			     RADEON_FORCEON_YCLKA |
-			     RADEON_FORCEON_YCLKB |
-			     RADEON_FORCEON_MC |
-			     RADEON_FORCEON_AIC));
-
-   /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
-    * unexpected behaviour on some machines.  Here we use
-    * RADEON_HOST_PATH_CNTL to reset it.
-    */
-   host_path_cntl = INREG(RADEON_HOST_PATH_CNTL);
-   rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
-
-   OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-				   RADEON_SOFT_RESET_CP |
-				   RADEON_SOFT_RESET_HI |
-				   RADEON_SOFT_RESET_SE |
-				   RADEON_SOFT_RESET_RE |
-				   RADEON_SOFT_RESET_PP |
-				   RADEON_SOFT_RESET_E2 |
-				   RADEON_SOFT_RESET_RB));
-   INREG(RADEON_RBBM_SOFT_RESET);
-   OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 
-				   (unsigned int) ~(RADEON_SOFT_RESET_CP |
-						    RADEON_SOFT_RESET_HI |
-						    RADEON_SOFT_RESET_SE |
-						    RADEON_SOFT_RESET_RE |
-						    RADEON_SOFT_RESET_PP |
-						    RADEON_SOFT_RESET_E2 |
-						    RADEON_SOFT_RESET_RB)));
-   INREG(RADEON_RBBM_SOFT_RESET);
-
-   OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET);
-   INREG(RADEON_HOST_PATH_CNTL);
-   OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
-
-   OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
-
-   OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
-   OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the radeon command processor engine (i.e., the ringbuffer).
- */
-static int RADEONEngineRestore( const DRIDriverContext *ctx )
-{
-   RADEONInfoPtr info = ctx->driverPrivate;
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   int pitch64, datatype, dp_gui_master_cntl, err;
-
-   fprintf(stderr, "%s\n", __FUNCTION__);
-
-   OUTREG(RADEON_RB3D_CNTL, 0);
-   RADEONEngineReset( ctx );
-
-   switch (ctx->bpp) {
-   case 16: datatype = 4; break;
-   case 32: datatype = 6; break;
-   default: return 0;
-   }
-
-   dp_gui_master_cntl =
-      ((datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
-       | RADEON_GMC_CLR_CMP_CNTL_DIS);
-
-   pitch64 = ((ctx->shared.virtualWidth * (ctx->bpp / 8) + 0x3f)) >> 6;
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DEFAULT_OFFSET) & 0xC0000000)
-				  | (pitch64 << 22)));
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
-					   | RADEON_DEFAULT_SC_BOTTOM_MAX));
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_DP_GUI_MASTER_CNTL, (dp_gui_master_cntl
-				      | RADEON_GMC_BRUSH_SOLID_COLOR
-				      | RADEON_GMC_SRC_DATATYPE_COLOR));
-
-   RADEONWaitForFifo(ctx, 7);
-   OUTREG(RADEON_DST_LINE_START,    0);
-   OUTREG(RADEON_DST_LINE_END,      0);
-   OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
-   OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0);
-   OUTREG(RADEON_DP_SRC_FRGD_CLR,   0xffffffff);
-   OUTREG(RADEON_DP_SRC_BKGD_CLR,   0);
-   OUTREG(RADEON_DP_WRITE_MASK,     0xffffffff);
-   OUTREG(RADEON_AUX_SC_CNTL,       0);
-
-/*    RADEONWaitForIdleMMIO(ctx); */
-   usleep(100); 
-
-
-   OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
-   if (info->colorTiling)
-	   info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
-   OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-
-   /* Initialize and start the CP if required */
-   if ((err = drmCommandNone(ctx->drmFD, DRM_RADEON_CP_START)) != 0) {
-      fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int RADEONEngineShutdown( const DRIDriverContext *ctx )
-{
-   drm_radeon_cp_stop_t  stop;
-   int              ret, i;
-
-   stop.flush = 1;
-   stop.idle  = 1;
-
-   ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, 
-			 sizeof(drm_radeon_cp_stop_t));
-
-   if (ret == 0) {
-      return 0;
-   } else if (errno != EBUSY) {
-      return -errno;
-   }
-
-   stop.flush = 0;
- 
-   i = 0;
-   do {
-      ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, 
-			    sizeof(drm_radeon_cp_stop_t));
-   } while (ret && errno == EBUSY && i++ < 10);
-
-   if (ret == 0) {
-      return 0;
-   } else if (errno != EBUSY) {
-      return -errno;
-   }
-
-   stop.idle = 0;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP,
-		       &stop, sizeof(drm_radeon_cp_stop_t))) {
-      return -errno;
-   } else {
-      return 0;
-   }
-}
-
-/**
- * \brief Compute base 2 logarithm.
- *
- * \param val value.
- * 
- * \return base 2 logarithm of \p val.
- */
-static int RADEONMinBits(int val)
-{
-   int  bits;
-
-   if (!val) return 1;
-   for (bits = 0; val; val >>= 1, ++bits);
-   return bits;
-}
-
-/**
- * \brief Initialize the AGP state
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- * 
- * Acquires and enables the AGP device. Reserves memory in the AGP space for
- * the ring buffer, vertex buffers and textures. Initialize the Radeon
- * registers to point to that memory and add client mappings.
- */
-static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   unsigned long  mode;
-   int            ret;
-   int            s, l;
-
-   if (drmAgpAcquire(ctx->drmFD) < 0) {
-      fprintf(stderr, "[gart] AGP not available\n");
-      return 0;
-   }
-    
-   /* Modify the mode if the default mode is not appropriate for this
-    * particular combination of graphics card and AGP chipset.
-    */
-   mode   = drmAgpGetMode(ctx->drmFD);	/* Default mode */
-
-   /* Disable fast write entirely - too many lockups.
-    */
-   mode &= ~RADEON_AGP_MODE_MASK;
-   switch (ctx->agpmode) {
-   case 4:          mode |= RADEON_AGP_4X_MODE;
-   case 2:          mode |= RADEON_AGP_2X_MODE;
-   case 1: default: mode |= RADEON_AGP_1X_MODE;
-   }
-
-   if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-      fprintf(stderr, "[gart] AGP not enabled\n");
-      drmAgpRelease(ctx->drmFD);
-      return 0;
-   }
-   else
-     fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
-
-   /* Workaround for some hardware bugs */
-   if (info->ChipFamily < CHIP_FAMILY_R200)
-      OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
-
-   info->gartOffset = 0;
-
-   if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL,
-			  &info->gartMemHandle)) < 0) {
-      fprintf(stderr, "[gart] Out of memory (%d)\n", ret);
-      drmAgpRelease(ctx->drmFD);
-      return 0;
-   }
-   fprintf(stderr,
-	   "[gart] %d kB allocated with handle 0x%08x\n",
-	   info->gartSize*1024, (unsigned)info->gartMemHandle);
-    
-   if (drmAgpBind(ctx->drmFD,
-		  info->gartMemHandle, info->gartOffset) < 0) {
-      fprintf(stderr, "[gart] Could not bind\n");
-      drmAgpFree(ctx->drmFD, info->gartMemHandle);
-      drmAgpRelease(ctx->drmFD);
-      return 0;
-   }
-
-   /* Initialize the CP ring buffer data */
-   info->ringStart       = info->gartOffset;
-   info->ringMapSize     = info->ringSize*1024*1024 + radeon_drm_page_size;
-
-   info->ringReadOffset  = info->ringStart + info->ringMapSize;
-   info->ringReadMapSize = radeon_drm_page_size;
-
-   /* Reserve space for vertex/indirect buffers */
-   info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-   info->bufMapSize      = info->bufSize*1024*1024;
-
-   /* Reserve the rest for AGP textures */
-   info->gartTexStart     = info->bufStart + info->bufMapSize;
-   s = (info->gartSize*1024*1024 - info->gartTexStart);
-   l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
-   if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-   info->gartTexMapSize   = (s >> l) << l;
-   info->log2GARTTexGran  = l;
-
-   if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		 DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
-      fprintf(stderr, "[gart] Could not add ring mapping\n");
-      return 0;
-   }
-   fprintf(stderr, "[gart] ring handle = 0x%08x\n", info->ringHandle);
-    
-
-   if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		 DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
-      fprintf(stderr,
-	      "[gart] Could not add ring read ptr mapping\n");
-      return 0;
-   }
-    
-   fprintf(stderr,
- 	   "[gart] ring read ptr handle = 0x%08lx\n",
-	   info->ringReadPtrHandle);
-    
-   if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		 DRM_AGP, 0, &info->bufHandle) < 0) {
-      fprintf(stderr,
-	      "[gart] Could not add vertex/indirect buffers mapping\n");
-      return 0;
-   }
-   fprintf(stderr,
- 	   "[gart] vertex/indirect buffers handle = 0x%08x\n",
-	   info->bufHandle);
-
-   if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
-		 DRM_AGP, 0, &info->gartTexHandle) < 0) {
-      fprintf(stderr,
-	      "[gart] Could not add AGP texture map mapping\n");
-      return 0;
-   }
-   fprintf(stderr,
- 	   "[gart] AGP texture map handle = 0x%08lx\n",
-	   info->gartTexHandle);
-
-   /* Initialize Radeon's AGP registers */
-   /* Ring buffer is at AGP offset 0 */
-   OUTREG(RADEON_AGP_BASE, info->ringHandle);
-
-   return 1;
-}
-
-/* Initialize the PCI GART state.  Request memory for use in PCI space,
- * and initialize the Radeon registers to point to that memory.
- */
-static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info)
-{
-    int  ret;
-    int  flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
-    int            s, l;
-
-    ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024,
-				&info->gartMemHandle);
-    if (ret < 0) {
-	fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
-	return 0;
-    }
-    fprintf(stderr,
-	       "[pci] %d kB allocated with handle 0x%08lx\n",
-	       info->gartSize*1024, info->gartMemHandle);
-
-   info->gartOffset = 0;
-   
-   /* Initialize the CP ring buffer data */
-   info->ringStart       = info->gartOffset;
-   info->ringMapSize     = info->ringSize*1024*1024 + radeon_drm_page_size;
-
-   info->ringReadOffset  = info->ringStart + info->ringMapSize;
-   info->ringReadMapSize = radeon_drm_page_size;
-
-   /* Reserve space for vertex/indirect buffers */
-   info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-   info->bufMapSize      = info->bufSize*1024*1024;
-
-   /* Reserve the rest for AGP textures */
-   info->gartTexStart     = info->bufStart + info->bufMapSize;
-   s = (info->gartSize*1024*1024 - info->gartTexStart);
-   l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
-   if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-   info->gartTexMapSize   = (s >> l) << l;
-   info->log2GARTTexGran  = l;
-
-    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
-	       "[pci] ring handle = 0x%08x\n", info->ringHandle);
-
-    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring read ptr mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
- 	       "[pci] ring read ptr handle = 0x%08lx\n",
-	       info->ringReadPtrHandle);
-
-    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		  DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add vertex/indirect buffers mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
- 	       "[pci] vertex/indirect buffers handle = 0x%08lx\n",
-	       info->bufHandle);
-
-    if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
-		  DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add GART texture map mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
- 	       "[pci] GART texture map handle = 0x%08x\n",
-	       info->gartTexHandle);
-
-    return 1;
-}
-
-
-/**
- * \brief Initialize the kernel data structures and enable the CP engine.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing
- * all the parameters in a drm_radeon_init_t structure.
- */
-static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
-			       RADEONInfoPtr info)
-{
-   int cpp = ctx->bpp / 8;
-   drm_radeon_init_t  drmInfo;
-   int ret;
-
-   memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
-
-   if ( (info->ChipFamily == CHIP_FAMILY_R200) ||
-	(info->ChipFamily == CHIP_FAMILY_RV250) ||
-	(info->ChipFamily == CHIP_FAMILY_M9) ||
-	(info->ChipFamily == CHIP_FAMILY_RV280) )
-      drmInfo.func             = RADEON_INIT_R200_CP;
-   else
-      drmInfo.func             = RADEON_INIT_CP;
-
-   /* This is the struct passed to the kernel module for its initialization */
-   drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-   drmInfo.is_pci              = ctx->isPCI;
-   drmInfo.cp_mode             = RADEON_DEFAULT_CP_BM_MODE;
-   drmInfo.gart_size            = info->gartSize*1024*1024;
-   drmInfo.ring_size           = info->ringSize*1024*1024;
-   drmInfo.usec_timeout        = 1000;
-   drmInfo.fb_bpp              = ctx->bpp;
-   drmInfo.depth_bpp           = ctx->bpp;
-   drmInfo.front_offset        = info->frontOffset;
-   drmInfo.front_pitch         = info->frontPitch * cpp;
-   drmInfo.back_offset         = info->backOffset;
-   drmInfo.back_pitch          = info->backPitch * cpp;
-   drmInfo.depth_offset        = info->depthOffset;
-   drmInfo.depth_pitch         = info->depthPitch * cpp;
-   drmInfo.fb_offset           = info->LinearAddr;
-   drmInfo.mmio_offset         = info->registerHandle;
-   drmInfo.ring_offset         = info->ringHandle;
-   drmInfo.ring_rptr_offset    = info->ringReadPtrHandle;
-   drmInfo.buffers_offset      = info->bufHandle;
-   drmInfo.gart_textures_offset = info->gartTexHandle;
-
-   ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo, 
-			 sizeof(drm_radeon_init_t));
-
-   return ret >= 0;
-}
-
-
-/**
- * \brief Initialize the AGP heap.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing
- * all the parameters in a drm_radeon_mem_init_heap structure.
- */
-static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
-				 RADEONInfoPtr info)
-{
-   drm_radeon_mem_init_heap_t drmHeap;
-
-   /* Start up the simple memory manager for gart space */
-   drmHeap.region = RADEON_MEM_REGION_GART;
-   drmHeap.start  = 0;
-   drmHeap.size   = info->gartTexMapSize;
-    
-   if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP,
-		       &drmHeap, sizeof(drmHeap))) {
-      fprintf(stderr,
-	      "[drm] Failed to initialized gart heap manager\n");
-   } else {
-      fprintf(stderr,
-	      "[drm] Initialized kernel gart heap manager, %d\n",
-	      info->gartTexMapSize);
-   }
-}
-
-/**
- * \brief Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Calls drmAddBufs() with the previously allocated vertex buffers.
- */
-static int RADEONDRIBufInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   /* Initialize vertex buffers */
-   info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				 info->bufMapSize / RADEON_BUFFER_SIZE,
-				 RADEON_BUFFER_SIZE,
-				 ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
-				 info->bufStart);
-
-   if (info->bufNumBufs <= 0) {
-      fprintf(stderr,
-	      "[drm] Could not create vertex/indirect buffers list\n");
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] Added %d %d byte vertex/indirect buffers\n",
-	   info->bufNumBufs, RADEON_BUFFER_SIZE);
-   
-   return 1;
-}
-
-/**
- * \brief Install an IRQ handler.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
- * IRQ-free operation on failure.
- */
-static void RADEONDRIIrqInit(const DRIDriverContext *ctx,
-			     RADEONInfoPtr info)
-{
-   if (!info->irq) {
-      info->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					   ctx->pciBus,
-					   ctx->pciDevice,
-					   ctx->pciFunc);
-
-      if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
-	 fprintf(stderr,
-		 "[drm] failure adding irq handler, "
-		 "there is a device already using that irq\n"
-		 "[drm] falling back to irq-free operation\n");
-	 info->irq = 0;
-      }
-   }
-
-   if (info->irq)
-      fprintf(stderr,
-	      "[drm] dma control initialized, using IRQ %d\n",
-	      info->irq);
-}
-
-static int RADEONCheckDRMVersion( const DRIDriverContext *ctx,
-				  RADEONInfoPtr info )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-   if (version) {
-      int req_minor, req_patch;
-
-      /* Need 1.8.x for proper cleanup-on-client-exit behaviour.
-       */
-      req_minor = 8;
-      req_patch = 0;	
-
-      if (version->version_major != 1 ||
-	  version->version_minor < req_minor ||
-	  (version->version_minor == req_minor && 
-	   version->version_patchlevel < req_patch)) {
-	 /* Incompatible drm version */
-	 fprintf(stderr,
-		 "[dri] RADEONDRIScreenInit failed because of a version "
-		 "mismatch.\n"
-		 "[dri] radeon.o kernel module version is %d.%d.%d "
-		 "but version 1.%d.%d or newer is needed.\n"
-		 "[dri] Disabling DRI.\n",
-		 version->version_major,
-		 version->version_minor,
-		 version->version_patchlevel,
-		 req_minor,
-		 req_patch);
-	 drmFreeVersion(version);
-	 return 0;
-      }
-
-      info->drmMinor = version->version_minor;
-      drmFreeVersion(version);
-   }
-
-   return 1;
-}
-
-static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        cpp         = ctx->cpp;
-   int        bufferSize  = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes			     + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
-   int        depthSize   = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
-			     + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
-   int        l;
-
-   info->frontOffset = 0;
-   info->frontPitch = ctx->shared.virtualWidth;
-
-   fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", info->gartSize);
-   fprintf(stderr, 
-	   "Using %d MB for the ring buffer\n", info->ringSize);
-   fprintf(stderr, 
-	   "Using %d MB for vertex/indirect buffers\n", info->bufSize);
-   fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", info->gartTexSize);
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
-   if (ctx->colorTiling==1)
-   {
-	info->textureSize = ctx->shared.fbSize - ((ctx->shared.fbSize - info->textureSize + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes*16);
-   }
-
-   if (info->textureSize < 0) 
-      return 0;
-
-   l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
-   if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   info->log2TexGran = l;
-   info->textureSize = (info->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (info->textureSize < 512 * 1024) {
-      info->textureOffset = 0;
-      info->textureSize = 0;
-   }
-
-   /* Reserve space for textures */
-   if (ctx->colorTiling==1)
-   {
-      info->textureOffset = ((ctx->shared.fbSize - info->textureSize) / 
-			(width_bytes * 16)) * (width_bytes*16);
-   }
-   else
-   {
-      info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
-   	 		   RADEON_BUFFER_ALIGN) &
-			  ~RADEON_BUFFER_ALIGN);
-   }
-   /* Reserve space for the shared depth
-    * buffer.
-    */
-   info->depthOffset = ((info->textureOffset - depthSize +
-			 RADEON_BUFFER_ALIGN) &
-			~RADEON_BUFFER_ALIGN);
-   info->depthPitch = ctx->shared.virtualWidth;
-
-   info->backOffset = ((info->depthOffset - bufferSize +
-			RADEON_BUFFER_ALIGN) &
-		       ~RADEON_BUFFER_ALIGN);
-   info->backPitch = ctx->shared.virtualWidth;
-
-
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   info->backOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   info->depthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   info->textureSize/1024, info->textureOffset);
-
-   info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
-			     (info->frontOffset >> 10));
-
-   info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
-			    (info->backOffset >> 10));
-
-   info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) |
-			     (info->depthOffset >> 10));
-
-   return 1;
-}
-
-static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        bufferSize  = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes			     + RADEON_BUFFER_ALIGN)
-			     & ~RADEON_BUFFER_ALIGN);
-   /* Setup color tiling */
-   if (info->drmMinor<14)
-      info->colorTiling=0;
-
-   if (info->colorTiling)
-   {
-
-      int colorTilingFlag;
-      drm_radeon_surface_alloc_t front,back;
-
-      RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0);
-      
-      /* Setup the surfaces */
-      if (info->ChipFamily < CHIP_FAMILY_R200)
-         colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO;
-      else
-         colorTilingFlag=R200_SURF_TILE_COLOR_MACRO;
-
-      front.address = info->frontOffset;
-      front.size = bufferSize;
-      front.flags = (width_bytes) | colorTilingFlag;
-      drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front)); 
- 
-      back.address = info->backOffset;
-      back.size = bufferSize;
-      back.flags = (width_bytes) | colorTilingFlag;
-      drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back)); 
-
-   }
-   return 1;
-} 
-
-
-
-/**
- * Called at the start of each server generation.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Performs static frame buffer allocation. Opens the DRM device and add maps
- * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
- * information. Creates a \e server context to grab the lock for the
- * initialization ioctls and calls the other initilization functions in this
- * file. Starts the CP engine via the DRM_RADEON_CP_START command.
- *
- * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its
- * initialization.
- */
-static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   RADEONDRIPtr   pRADEONDRI;
-   int err;
-
-   usleep(100);
-   /*assert(!ctx->IsClient);*/
-
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-
-   if (info->ChipFamily >= CHIP_FAMILY_R300) {
-      fprintf(stderr, 
-	      "Direct rendering not yet supported on "
-	      "Radeon 9700 and newer cards\n");
-      return 0;
-   }
-   
-   radeon_drm_page_size = getpagesize();   
-
-   info->registerSize = ctx->MMIOSize;
-   ctx->shared.SAREASize = SAREA_MAX;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("radeon", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-		  0,
-#else
-		  DRM_READ_ONLY,
-#endif
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &info->registerHandle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08lx\n", info->registerHandle);
-
-   /* Check the radeon DRM version */
-   if (!RADEONCheckDRMVersion(ctx, info)) {
-      return 0;
-   }
-
-   if (ctx->isPCI) {
-      /* Initialize PCI */
-      if (!RADEONDRIPciInit(ctx, info))
-         return 0;
-   }
-   else {
-      /* Initialize AGP */
-      if (!RADEONDRIAgpInit(ctx, info))
-         return 0;
-   }
-
-   /* Memory manager setup */
-   if (!RADEONMemoryInit(ctx, info)) {
-      return 0;
-   }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the kernel data structures */
-   if (!RADEONDRIKernelInit(ctx, info)) {
-      fprintf(stderr, "RADEONDRIKernelInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize the vertex buffers list */
-   if (!RADEONDRIBufInit(ctx, info)) {
-      fprintf(stderr, "RADEONDRIBufInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   RADEONColorTilingInit(ctx, info);
-
-   /* Initialize IRQ */
-   RADEONDRIIrqInit(ctx, info);
-
-   /* Initialize kernel gart memory manager */
-   RADEONDRIAgpHeapInit(ctx, info);
-
-   fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis");
-   fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis");
-   /* Initialize the SAREA private data structure */
-   {
-      drm_radeon_sarea_t *pSAREAPriv;
-      pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-      pSAREAPriv->pfState = info->page_flip_enable;
-   }
-
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   drimemsetio((char *)ctx->FBAddress + info->frontOffset,
-	  0,
-	  info->frontPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   drimemsetio((char *)ctx->FBAddress + info->backOffset,
-	  0,
-	  info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   /* This is the struct passed to radeon_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec));
-   ctx->driverClientMsgSize = sizeof(RADEONDRIRec);
-   pRADEONDRI                    = (RADEONDRIPtr)ctx->driverClientMsg;
-   pRADEONDRI->deviceID          = info->Chipset;
-   pRADEONDRI->width             = ctx->shared.virtualWidth;
-   pRADEONDRI->height            = ctx->shared.virtualHeight;
-   pRADEONDRI->depth             = ctx->bpp; /* XXX: depth */
-   pRADEONDRI->bpp               = ctx->bpp;
-   pRADEONDRI->IsPCI             = ctx->isPCI;
-   pRADEONDRI->AGPMode           = ctx->agpmode;
-   pRADEONDRI->frontOffset       = info->frontOffset;
-   pRADEONDRI->frontPitch        = info->frontPitch;
-   pRADEONDRI->backOffset        = info->backOffset;
-   pRADEONDRI->backPitch         = info->backPitch;
-   pRADEONDRI->depthOffset       = info->depthOffset;
-   pRADEONDRI->depthPitch        = info->depthPitch;
-   pRADEONDRI->textureOffset     = info->textureOffset;
-   pRADEONDRI->textureSize       = info->textureSize;
-   pRADEONDRI->log2TexGran       = info->log2TexGran;
-   pRADEONDRI->registerHandle    = info->registerHandle;
-   pRADEONDRI->registerSize      = info->registerSize; 
-   pRADEONDRI->statusHandle      = info->ringReadPtrHandle;
-   pRADEONDRI->statusSize        = info->ringReadMapSize;
-   pRADEONDRI->gartTexHandle      = info->gartTexHandle;
-   pRADEONDRI->gartTexMapSize     = info->gartTexMapSize;
-   pRADEONDRI->log2GARTTexGran    = info->log2GARTTexGran;
-   pRADEONDRI->gartTexOffset      = info->gartTexStart;
-   pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   /* Don't release the lock now - let the VT switch handler do it. */
-
-   return 1;
-}
-
-
-/**
- * \brief Get Radeon chip family from chipset number.
- * 
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily
- * according to the value of RADEONInfoRec::Chipset.  Fails if the
- * chipset is unrecognized or not appropriate for this driver (i.e., not
- * an r100 style radeon)
- */
-static int get_chipfamily_from_chipset( RADEONInfoPtr info )
-{
-    switch (info->Chipset) {
-    case PCI_CHIP_RADEON_LY:
-    case PCI_CHIP_RADEON_LZ:
-	info->ChipFamily = CHIP_FAMILY_M6;
-	break;
-
-    case PCI_CHIP_RADEON_QY:
-    case PCI_CHIP_RADEON_QZ:
-	info->ChipFamily = CHIP_FAMILY_VE;
-	break;
-
-    case PCI_CHIP_R200_QL:
-    case PCI_CHIP_R200_QN:
-    case PCI_CHIP_R200_QO:
-    case PCI_CHIP_R200_Ql:
-    case PCI_CHIP_R200_BB:
-	info->ChipFamily = CHIP_FAMILY_R200;
-	break;
-
-    case PCI_CHIP_RV200_QW: /* RV200 desktop */
-    case PCI_CHIP_RV200_QX:
-	info->ChipFamily = CHIP_FAMILY_RV200;
-	break;
-
-    case PCI_CHIP_RADEON_LW:
-    case PCI_CHIP_RADEON_LX:
-	info->ChipFamily = CHIP_FAMILY_M7;
-	break;
-
-    case PCI_CHIP_RV250_Id:
-    case PCI_CHIP_RV250_Ie:
-    case PCI_CHIP_RV250_If:
-    case PCI_CHIP_RV250_Ig:
-	info->ChipFamily = CHIP_FAMILY_RV250;
-	break;
-
-    case PCI_CHIP_RV250_Ld:
-    case PCI_CHIP_RV250_Le:
-    case PCI_CHIP_RV250_Lf:
-    case PCI_CHIP_RV250_Lg:
-	info->ChipFamily = CHIP_FAMILY_M9;
-	break;
-
-    case PCI_CHIP_RV280_Y_:
-    case PCI_CHIP_RV280_Ya:
-    case PCI_CHIP_RV280_Yb:
-    case PCI_CHIP_RV280_Yc:
-	info->ChipFamily = CHIP_FAMILY_RV280;
-        break;
-
-    case PCI_CHIP_R300_ND:
-    case PCI_CHIP_R300_NE:
-    case PCI_CHIP_R300_NF:
-    case PCI_CHIP_R300_NG:
-	info->ChipFamily = CHIP_FAMILY_R300;
-        break;
-
-    default:
-	/* Original Radeon/7200 */
-	info->ChipFamily = CHIP_FAMILY_RADEON;
-    }
-
-    return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int radeonValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   RADEONInfoPtr info = ctx->driverPrivate;
-
-   info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
-   info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
-
-   if (info->colorTiling)
-	   info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int radeonPostValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   RADEONInfoPtr info = ctx->driverPrivate;
-
-   RADEONColorTilingInit( ctx, info);
-   OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
-   if (info->colorTiling)
-	   info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
-   OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-   
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls RADEONScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int radeonInitFBDev( DRIDriverContext *ctx )
-{
-   RADEONInfoPtr info = calloc(1, sizeof(*info));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      if (ctx->colorTiling==1)
-      {
-         switch (ctx->bpp / 8) {
-         case 1: dummy = (ctx->shared.virtualWidth + 255) & ~255; break;
-         case 2: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-         case 3:
-         case 4: dummy = (ctx->shared.virtualWidth +  63) &  ~63; break;
-         }
-      } else {
-	 switch (ctx->bpp / 8) {
-         case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-         case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-         case 3:
-         case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-         }
-      }
-
-      ctx->shared.virtualWidth = dummy;
-      ctx->shared.Width = dummy;
-   }
-
-   fprintf(stderr,"shared virtual width is %d\n", ctx->shared.virtualWidth);
-   ctx->driverPrivate = (void *)info;
-   
-   info->gartFastWrite  = RADEON_DEFAULT_AGP_FAST_WRITE;
-   info->gartSize       = RADEON_DEFAULT_AGP_SIZE;
-   info->gartTexSize    = RADEON_DEFAULT_AGP_TEX_SIZE;
-   info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
-   info->ringSize      = RADEON_DEFAULT_RING_SIZE;
-   info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP;
-   info->colorTiling = ctx->colorTiling;
-  
-   info->Chipset = ctx->chipset;
-
-   if (!get_chipfamily_from_chipset( info )) {
-      fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n");
-      fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n");
-      return 0;
-   }
-
-   info->frontPitch = ctx->shared.virtualWidth;
-   info->LinearAddr = ctx->FBStart & 0xfc000000;
-    
-
-   if (!RADEONScreenInit( ctx, info ))
-      return 0;
-
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void radeonHaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-extern void radeonNotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   radeonValidateMode,
-   radeonPostValidateMode,
-   radeonInitFBDev,
-   radeonHaltFBDev,
-   RADEONEngineShutdown,
-   RADEONEngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   radeonNotifyFocus, 
-#endif
-};
diff --git a/src/mesa/drivers/dri/savage/Makefile b/src/mesa/drivers/dri/savage/Makefile
index 2e5c40802c1..53511552c6d 100644
--- a/src/mesa/drivers/dri/savage/Makefile
+++ b/src/mesa/drivers/dri/savage/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = savage_dri.so
 
-# Doesn't exist yet.
-#MINIGLX_SOURCES = server/savage_dri.c 
-
 DRIVER_SOURCES = \
 	savage_xmesa.c \
 	savagedd.c \
diff --git a/src/mesa/drivers/dri/sis/Makefile b/src/mesa/drivers/dri/sis/Makefile
index ad009fc2398..6b4f938bab3 100644
--- a/src/mesa/drivers/dri/sis/Makefile
+++ b/src/mesa/drivers/dri/sis/Makefile
@@ -5,10 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = sis_dri.so
 
-
-# Not yet
-# MINIGLX_SOURCES = server/sis_dri.c 
-
 DRIVER_SOURCES = \
 	sis6326_state.c \
 	sis6326_clear.c \
diff --git a/src/mesa/drivers/dri/tdfx/Makefile b/src/mesa/drivers/dri/tdfx/Makefile
index b9f25db4fe8..96bd8f8202f 100644
--- a/src/mesa/drivers/dri/tdfx/Makefile
+++ b/src/mesa/drivers/dri/tdfx/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = tdfx_dri.so
 
-# not yet
-# MINIGLX_SOURCES = server/tdfx_dri.c 
-
 DRIVER_SOURCES = \
 	tdfx_context.c \
 	tdfx_dd.c \
diff --git a/src/mesa/drivers/dri/tdfx/server/tdfx_dri.c b/src/mesa/drivers/dri/tdfx/server/tdfx_dri.c
deleted file mode 100644
index 63fe875f59e..00000000000
--- a/src/mesa/drivers/dri/tdfx/server/tdfx_dri.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/*
- * Mesa 3-D graphics library
- * Version:  5.1
- *
- * Copyright (C) 1999-2003  Brian Paul   All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/* Authors:
- *    Keith Whitwell
- *    Daniel Borca
- */
-
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
- 
-#include "driver.h"
-#include "drm.h"
-#include "imports.h"
-
-#include "dri_util.h"
-
-#include "tdfx_context.h"
-#include "tdfx_dri.h"
-#include "xf86drm.h"
-
-
-#define TILE_WIDTH 128
-#define TILE_HEIGHT 32
-
-#define CMDFIFO_PAGES 64
-
-
-static int
-calcBufferStride (int xres, int tiled, int cpp)
-{
-  int strideInTiles;
-
-  if (tiled) {
-    /* Calculate tile width stuff */
-    strideInTiles = (xres+TILE_WIDTH-1)/TILE_WIDTH;
-
-    return strideInTiles*cpp*TILE_WIDTH;
-  } else {
-    return xres*cpp;
-  }
-} /* calcBufferStride */
-
-
-static int
-calcBufferHeightInTiles (int yres)
-{
-  int heightInTiles;            /* Height of buffer in tiles */
-
-  /* Calculate tile height stuff */
-  heightInTiles = yres >> 5;
-
-  if (yres & (TILE_HEIGHT - 1))
-    heightInTiles++;
-
-  return heightInTiles;
-
-} /* calcBufferHeightInTiles */
-
-
-static int
-calcBufferSize (int xres, int yres, int tiled, int cpp)
-{
-  int stride, height, bufSize;
-
-  if (tiled) {
-    stride = calcBufferStride(xres, tiled, cpp);
-    height = TILE_HEIGHT * calcBufferHeightInTiles(yres);
-  } else {
-    stride = xres*cpp;
-    height = yres;
-  }
-
-  bufSize = stride * height;
-
-  return bufSize;
-} /* calcBufferSize */
-
-
-static void allocateMemory (const DRIDriverContext *ctx, TDFXDRIPtr pTDFX)
-{
-  int memRemaining, fifoSize, screenSizeInTiles;
-  int fbSize;
-  char *str;
-  int pixmapCacheLinesMin;
-  int cursorOffset, cursorSize;
-
-  pTDFX->stride = calcBufferStride(pTDFX->width, !0, pTDFX->cpp);
-
-  /* enough to do DVD */
-  pixmapCacheLinesMin = ((720*480*pTDFX->cpp) + 
-					pTDFX->stride - 1)/pTDFX->stride;
-
-  if (pTDFX->deviceID > PCI_CHIP_VOODOO3) {
-  	if ((pixmapCacheLinesMin + pTDFX->height) > 4095)
-		pixmapCacheLinesMin = 4095 - pTDFX->height;
-  } else {
-  	if ((pixmapCacheLinesMin + pTDFX->height) > 2047)
-		pixmapCacheLinesMin = 2047 - pTDFX->height;
-  }
-
-  if (pTDFX->cpp!=3) {
-    screenSizeInTiles=calcBufferSize(pTDFX->width, pTDFX->height,
-				     !0, pTDFX->cpp);
-  }
-  else {
-    /* cpp==3 needs to bump up to 4 */
-    screenSizeInTiles=calcBufferSize(pTDFX->width, pTDFX->height,
-				     !0, 4);
-  }
-
-  /*
-   * Layout is:
-   *    cursor, fifo, fb, tex, bb, db
-   */
-
-  fbSize = (pTDFX->height + pixmapCacheLinesMin) * pTDFX->stride;
-
-  memRemaining=(pTDFX->mem - 1) &~ 0xFFF;
-  /* Note that a page is 4096 bytes, and a  */
-  /* tile is 32 x 128 = 4096 bytes.  So,    */
-  /* page and tile boundaries are the same  */
-  /* Place the depth offset first, forcing  */
-  /* it to be on an *odd* page boundary.    */
-  pTDFX->depthOffset = (memRemaining - screenSizeInTiles) &~ 0xFFF;
-  if ((pTDFX->depthOffset & (0x1 << 12)) == 0) {
-      pTDFX->depthOffset -= (0x1 << 12);
-  }
-  /* Now, place the back buffer, forcing it */
-  /* to be on an *even* page boundary.      */
-  pTDFX->backOffset = (pTDFX->depthOffset - screenSizeInTiles) &~ 0xFFF;
-  if (pTDFX->backOffset & (0x1 << 12)) {
-      pTDFX->backOffset -= (0x1 << 12);
-  }
-  /* Give the cmd fifo at least             */
-  /* CMDFIFO_PAGES pages, but no more than  */
-  /* 64. NOTE: Don't go higher than 64, as  */
-  /* there is suspect code in Glide3 !      */
-  fifoSize = ((64 <= CMDFIFO_PAGES) ? 64 : CMDFIFO_PAGES) << 12;
-
-  /* We give 4096 bytes to the cursor  */
-  cursorSize = 0/*4096*/;
-  cursorOffset = 0;
-
-  pTDFX->fifoOffset = cursorOffset + cursorSize;
-  pTDFX->fifoSize = fifoSize;
-  /* Now, place the front buffer, forcing   */
-  /* it to be on a page boundary too, just  */
-  /* for giggles.                           */
-  pTDFX->fbOffset = pTDFX->fifoOffset + pTDFX->fifoSize;
-  pTDFX->textureOffset = pTDFX->fbOffset + fbSize;
-  if (pTDFX->depthOffset <= pTDFX->textureOffset ||
-	pTDFX->backOffset <= pTDFX->textureOffset) {
-    /*
-     * pTDFX->textureSize < 0 means that the DRI is disabled.  pTDFX->backOffset
-     * is used to calculate the maximum amount of memory available for
-     * 2D offscreen use.  With DRI disabled, set this to the top of memory.
-     */
-
-    pTDFX->textureSize = -1;
-    pTDFX->backOffset = pTDFX->mem;
-    pTDFX->depthOffset = -1;
-    fprintf(stderr, 
-        "Not enough video memory available for textures and depth buffer\n"
-	"\tand/or back buffer.  Disabling DRI.  To use DRI try lower\n"
-	"\tresolution modes and/or a smaller virtual screen size\n");
-  } else {
-    pTDFX->textureSize = pTDFX->backOffset - pTDFX->textureOffset;
-  }
-}
-
-
-static int createScreen (DRIDriverContext *ctx, TDFXDRIPtr pTDFX)
-{
-   int err;
-   
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-   ctx->shared.SAREASize = SAREA_MAX;
-   pTDFX->regsSize = ctx->MMIOSize;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("tdfx", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-		  0,
-#else
-		  DRM_READ_ONLY,
-#endif
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pTDFX->regs) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08lx\n", pTDFX->regs);
-
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the kernel data structures */
-
-   /* Initialize kernel gart memory manager */
-   allocateMemory(ctx, pTDFX);
-
-   /* Initialize the SAREA private data structure */
-
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-
-
-   /* This is the struct passed to tdfx_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(TDFXDRIRec));
-   ctx->driverClientMsgSize = sizeof(TDFXDRIRec);
-   memcpy(ctx->driverClientMsg, pTDFX, ctx->driverClientMsgSize);
-   pTDFX = (TDFXDRIPtr)ctx->driverClientMsg;
-
-   /* Don't release the lock now - let the VT switch handler do it. */
-
-   return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa tdfxValidateMode().
- */
-static int tdfxValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa tdfxValidateMode().
- */
-static int tdfxPostValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int tdfxInitFBDev( DRIDriverContext *ctx )
-{
-   TDFXDRIPtr pTDFX = calloc(1, sizeof(TDFXDRIRec));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)pTDFX;
-
-   pTDFX->deviceID = ctx->chipset;
-   pTDFX->width    = ctx->shared.virtualWidth;
-   pTDFX->height   = ctx->shared.virtualHeight;
-   pTDFX->cpp      = ctx->cpp;
-   pTDFX->mem      = ctx->FBSize; /* ->shared.fbSize? mem probe? */
-   pTDFX->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   if (!createScreen(ctx, pTDFX))
-      return 0;
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void tdfxHaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the 3D engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int tdfxEngineShutdown( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s: not implemented\n", __FUNCTION__);
-   return 1;
-}
-
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on 3dfx
- */
-static int tdfxEngineRestore( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s: not implemented\n", __FUNCTION__);
-   return 1;
-}
-
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-struct DRIDriverRec __driDriver = {
-   tdfxValidateMode,
-   tdfxPostValidateMode,
-   tdfxInitFBDev,
-   tdfxHaltFBDev,
-   tdfxEngineShutdown,
-   tdfxEngineRestore,
-   0
-};
diff --git a/src/mesa/drivers/dri/unichrome/Makefile b/src/mesa/drivers/dri/unichrome/Makefile
index 344d34fce36..14cf9f30386 100644
--- a/src/mesa/drivers/dri/unichrome/Makefile
+++ b/src/mesa/drivers/dri/unichrome/Makefile
@@ -5,8 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = unichrome_dri.so
 
-MINIGLX_SOURCES = server/via_dri.c 
-
 DRIVER_SOURCES = \
 	via_context.c \
 	via_fb.c \
diff --git a/src/mesa/drivers/dri/unichrome/server/via_dri.c b/src/mesa/drivers/dri/unichrome/server/via_dri.c
deleted file mode 100644
index 74034485e28..00000000000
--- a/src/mesa/drivers/dri/unichrome/server/via_dri.c
+++ /dev/null
@@ -1,1251 +0,0 @@
-/*
- * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
- * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
- 
-#include "driver.h"
-#include "drm.h"
-#include "imports.h"
-
-#include "dri_util.h"
-
-#include "via_context.h"
-#include "via_dri.h"
-#include "via_driver.h"
-#include "xf86drm.h"
-
-static void VIAEnableMMIO(DRIDriverContext * ctx);
-static void VIADisableMMIO(DRIDriverContext * ctx);
-static void VIADisableExtendedFIFO(DRIDriverContext *ctx);
-static void VIAEnableExtendedFIFO(DRIDriverContext *ctx);
-static void VIAInitialize2DEngine(DRIDriverContext *ctx);
-static void VIAInitialize3DEngine(DRIDriverContext *ctx);
-
-static int VIADRIScreenInit(DRIDriverContext * ctx);
-static void VIADRICloseScreen(DRIDriverContext * ctx);
-static int VIADRIFinishScreenInit(DRIDriverContext * ctx);
-
-/* _SOLO : missing macros normally defined by X code */
-#define xf86DrvMsg(a, b, ...) fprintf(stderr, __VA_ARGS__)
-#define MMIO_IN8(base, addr) ((*(((volatile uint8_t*)base)+(addr)))+0)
-#define MMIO_OUT8(base, addr, val) ((*(((volatile uint8_t*)base)+(addr)))=((uint8_t)val))
-#define MMIO_OUT16(base, addr, val) ((*(volatile uint16_t*)(((uint8_t*)base)+(addr)))=((uint16_t)val))
-
-#define VIDEO	0 
-#define AGP		1
-#define AGP_PAGE_SIZE 4096
-#define AGP_PAGES 8192
-#define AGP_SIZE (AGP_PAGE_SIZE * AGP_PAGES)
-#define AGP_CMDBUF_PAGES 512
-#define AGP_CMDBUF_SIZE (AGP_PAGE_SIZE * AGP_CMDBUF_PAGES)
-
-static char VIAKernelDriverName[] = "via";
-static char VIAClientDriverName[] = "unichrome";
-
-static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia);
-static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia);
-static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia);
-static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia);
-static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia);
-
-static void VIADRIIrqInit( DRIDriverContext *ctx )
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-
-    pVIADRI->irqEnabled = drmGetInterruptFromBusID(pVia->drmFD,
-					   ctx->pciBus,
-					   ctx->pciDevice,
-					   ctx->pciFunc);
-
-    if ((drmCtlInstHandler(pVia->drmFD, pVIADRI->irqEnabled))) {
-	xf86DrvMsg(pScreen->myNum, X_WARNING,
-		   "[drm] Failure adding irq handler. "
-		   "Falling back to irq-free operation.\n");
-	pVIADRI->irqEnabled = 0;
-    }
-
-    if (pVIADRI->irqEnabled)
-	xf86DrvMsg(pScreen->myNum, X_INFO,
-		   "[drm] Irq handler installed, using IRQ %d.\n",
-		   pVIADRI->irqEnabled);
-}
-
-static void VIADRIIrqExit( DRIDriverContext *ctx ) {
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-
-    if (pVIADRI->irqEnabled) {
-	if (drmCtlUninstHandler(pVia->drmFD)) {
-	    xf86DrvMsg(pScreen-myNum, X_INFO,"[drm] Irq handler uninstalled.\n");
-	} else {
-	    xf86DrvMsg(pScreen->myNum, X_ERROR,
-		       "[drm] Could not uninstall irq handler.\n");
-	}
-    }
-}
-	    
-static void VIADRIRingBufferCleanup(DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-    drm_via_dma_init_t ringBufInit;
-
-    if (pVIADRI->ringBufActive) {
-	xf86DrvMsg(pScreen->myNum, X_INFO, 
-		   "[drm] Cleaning up DMA ring-buffer.\n");
-	ringBufInit.func = VIA_CLEANUP_DMA;
-	if (drmCommandWrite(pVia->drmFD, DRM_VIA_DMA_INIT, &ringBufInit,
-			    sizeof(ringBufInit))) {
-	    xf86DrvMsg(pScreen->myNum, X_WARNING, 
-		       "[drm] Failed to clean up DMA ring-buffer: %d\n", errno);
-	}
-	pVIADRI->ringBufActive = 0;
-    }
-}
-
-static int VIADRIRingBufferInit(DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-    drm_via_dma_init_t ringBufInit;
-    drmVersionPtr drmVer;
-
-    pVIADRI->ringBufActive = 0;
-
-    if (NULL == (drmVer = drmGetVersion(pVia->drmFD))) {
-	return GL_FALSE;
-    }
-
-    if (((drmVer->version_major <= 1) && (drmVer->version_minor <= 3))) {
-	return GL_FALSE;
-    } 
-
-    /*
-     * Info frome code-snippet on DRI-DEVEL list; Erdi Chen.
-     */
-
-    switch (pVia->ChipId) {
-    case PCI_CHIP_VT3259:
-    	ringBufInit.reg_pause_addr = 0x40c;
-	break;
-    default:
-    	ringBufInit.reg_pause_addr = 0x418;
-	break;
-    }
-   
-    ringBufInit.offset = pVia->agpSize;
-    ringBufInit.size = AGP_CMDBUF_SIZE;
-    ringBufInit.func = VIA_INIT_DMA;
-    if (drmCommandWrite(pVia->drmFD, DRM_VIA_DMA_INIT, &ringBufInit,
-			sizeof(ringBufInit))) {
-	xf86DrvMsg(pScreen->myNum, X_ERROR, 
-		   "[drm] Failed to initialize DMA ring-buffer: %d\n", errno);
-	return GL_FALSE;
-    }
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-	       "[drm] Initialized AGP ring-buffer, size 0x%lx at AGP offset 0x%lx.\n",
-	       ringBufInit.size, ringBufInit.offset);
-   
-    pVIADRI->ringBufActive = 1;
-    return GL_TRUE;
-}	    
-
-static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia)
-{
-    unsigned long  agp_phys;
-    drmAddress agpaddr;
-    VIADRIPtr pVIADRI;
-    pVIADRI = pVia->devPrivate;
-    pVia->agpSize = 0;
-
-    if (drmAgpAcquire(pVia->drmFD) < 0) {
-        xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpAcquire failed %d\n", errno);
-        return GL_FALSE;
-    }
-
-    if (drmAgpEnable(pVia->drmFD, drmAgpGetMode(pVia->drmFD)&~0x0) < 0) {
-         xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpEnable failed\n");
-        return GL_FALSE;
-    }
-    
-    xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] drmAgpEnabled succeeded\n");
-
-    if (drmAgpAlloc(pVia->drmFD, AGP_SIZE, 0, &agp_phys, &pVia->agpHandle) < 0) {
-        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                 "[drm] drmAgpAlloc failed\n");
-        drmAgpRelease(pVia->drmFD);
-        return GL_FALSE;
-    }
-   
-    if (drmAgpBind(pVia->drmFD, pVia->agpHandle, 0) < 0) {
-        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                 "[drm] drmAgpBind failed\n");
-        drmAgpFree(pVia->drmFD, pVia->agpHandle);
-        drmAgpRelease(pVia->drmFD);
-
-        return GL_FALSE;
-    }
-
-    /*
-     * Place the ring-buffer last in the AGP region, and restrict the
-     * public map not to include the buffer for security reasons.
-     */
-
-    pVia->agpSize = AGP_SIZE - AGP_CMDBUF_SIZE;
-    pVia->agpAddr = drmAgpBase(pVia->drmFD);
-    xf86DrvMsg(pScreen->myNum, X_INFO,
-                 "[drm] agpAddr = 0x%08lx\n",pVia->agpAddr);
-		 
-    pVIADRI->agp.size = pVia->agpSize;
-    if (drmAddMap(pVia->drmFD, (drm_handle_t)0,
-                 pVIADRI->agp.size, DRM_AGP, 0, 
-                 &pVIADRI->agp.handle) < 0) {
-	xf86DrvMsg(pScreen->myNum, X_ERROR,
-	    "[drm] Failed to map public agp area\n");
-        pVIADRI->agp.size = 0;
-        return GL_FALSE;
-    }  
-    /* Map AGP from kernel to Xserver - Not really needed */
-    drmMap(pVia->drmFD, pVIADRI->agp.handle,pVIADRI->agp.size, &agpaddr);
-
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-                "[drm] agpAddr = 0x%08lx\n", pVia->agpAddr);
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-                "[drm] agpSize = 0x%08lx\n", pVia->agpSize);
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-                "[drm] agp physical addr = 0x%08lx\n", agp_phys);
-
-    {
-	drm_via_agp_t agp;
-	agp.offset = 0;
-	agp.size = AGP_SIZE-AGP_CMDBUF_SIZE;
-	if (drmCommandWrite(pVia->drmFD, DRM_VIA_AGP_INIT, &agp,
-			    sizeof(drm_via_agp_t)) < 0) {
-	    drmUnmap(&agpaddr,pVia->agpSize);
-	    drmRmMap(pVia->drmFD,pVIADRI->agp.handle);
-	    drmAgpUnbind(pVia->drmFD, pVia->agpHandle);
-	    drmAgpFree(pVia->drmFD, pVia->agpHandle);
-	    drmAgpRelease(pVia->drmFD);
-	    return GL_FALSE;
-	}
-    }
-
-    return GL_TRUE;
-}
-
-static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia)
-{   
-    int FBSize = pVia->FBFreeEnd-pVia->FBFreeStart;
-    int FBOffset = pVia->FBFreeStart; 
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-    pVIADRI->fbOffset = FBOffset;
-    pVIADRI->fbSize = pVia->videoRambytes;
-
-    {
-	drm_via_fb_t fb;
-	fb.offset = FBOffset;
-	fb.size = FBSize;
-	
-	if (drmCommandWrite(pVia->drmFD, DRM_VIA_FB_INIT, &fb,
-			    sizeof(drm_via_fb_t)) < 0) {
-	    xf86DrvMsg(pScreen->myNum, X_ERROR,
-		       "[drm] failed to init frame buffer area\n");
-	    return GL_FALSE;
-	} else {
-	    xf86DrvMsg(pScreen->myNum, X_INFO,
-		       "[drm] FBFreeStart= 0x%08x FBFreeEnd= 0x%08x "
-		       "FBSize= 0x%08x\n",
-		       pVia->FBFreeStart, pVia->FBFreeEnd, FBSize);
-	    return GL_TRUE;	
-	}   
-    }
-}
-
-static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia)
-{
-    return GL_TRUE;	
-}
-
-static int VIADRIScreenInit(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI;
-    int err;
-
-#if 0
-    ctx->shared.SAREASize = ((sizeof(drm_sarea_t) + 0xfff) & 0x1000);
-#else
-    if (sizeof(drm_sarea_t)+sizeof(drm_via_sarea_t) > SAREA_MAX) {
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-			"Data does not fit in SAREA\n");
-	return GL_FALSE;
-    }
-    ctx->shared.SAREASize = SAREA_MAX;
-#endif
-
-    ctx->drmFD = drmOpen(VIAKernelDriverName, NULL);
-    if (ctx->drmFD < 0) {
-        fprintf(stderr, "[drm] drmOpen failed\n");
-        return 0;
-    }
-    pVia->drmFD = ctx->drmFD;
-
-    err = drmSetBusid(ctx->drmFD, ctx->pciBusID);
-    if (err < 0) {
-        fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-                ctx->drmFD, ctx->pciBusID, strerror(-err));
-        return 0;
-    }
-
-    err = drmAddMap(ctx->drmFD, 0, ctx->shared.SAREASize, DRM_SHM,
-                  DRM_CONTAINS_LOCK, &ctx->shared.hSAREA);
-    if (err < 0) {
-        fprintf(stderr, "[drm] drmAddMap failed\n");
-        return 0;
-    }
-    fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-            ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-    if (drmMap(ctx->drmFD,
-               ctx->shared.hSAREA,
-               ctx->shared.SAREASize,
-               (drmAddressPtr)(&ctx->pSAREA)) < 0)
-    {
-        fprintf(stderr, "[drm] drmMap failed\n");
-        return 0;
-    }
-    memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-    fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-            ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-
-    /* Need to AddMap the framebuffer and mmio regions here:
-     */
-    if (drmAddMap(ctx->drmFD,
-                  (drm_handle_t)ctx->FBStart,
-                  ctx->FBSize,
-                  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-                   0,
-#else
-                   DRM_READ_ONLY,
-#endif
-                   &ctx->shared.hFrameBuffer) < 0)
-    {
-        fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-        return 0;
-    }
-
-    fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-            ctx->shared.hFrameBuffer);
-
-    pVIADRI = (VIADRIPtr) CALLOC(sizeof(VIADRIRec));
-    if (!pVIADRI) {
-        drmClose(ctx->drmFD);
-        return GL_FALSE;
-    }
-    pVia->devPrivate = pVIADRI;
-    ctx->driverClientMsg = pVIADRI;
-    ctx->driverClientMsgSize = sizeof(*pVIADRI);
-
-    /* DRIScreenInit doesn't add all the common mappings.  Add additional mappings here. */
-    if (!VIADRIMapInit(ctx, pVia)) {
-	VIADRICloseScreen(ctx);
-	return GL_FALSE;
-    }
-
-    pVIADRI->regs.size = VIA_MMIO_REGSIZE;
-    pVIADRI->regs.handle = pVia->registerHandle;
-    xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] mmio Registers = 0x%08lx\n",
-	pVIADRI->regs.handle);
-
-    if (drmMap(pVia->drmFD,
-               pVIADRI->regs.handle,
-               pVIADRI->regs.size,
-               (drmAddress *)&pVia->MapBase) != 0)
-    {
-        VIADRICloseScreen(ctx);
-        return GL_FALSE;
-    }
-
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] mmio mapped.\n" );
-
-    VIAEnableMMIO(ctx);
-
-    /* Get video memory clock. */
-    VGAOUT8(0x3D4, 0x3D);
-    pVia->MemClk = (VGAIN8(0x3D5) & 0xF0) >> 4;
-    xf86DrvMsg(0, X_INFO, "[dri] MemClk (0x%x)\n", pVia->MemClk);
-
-    /* 3D rendering has noise if not enabled. */
-    VIAEnableExtendedFIFO(ctx);
-
-    VIAInitialize2DEngine(ctx);
-
-    /* Must disable MMIO or 3D won't work. */
-    VIADisableMMIO(ctx);
-
-    VIAInitialize3DEngine(ctx);
-
-    pVia->IsPCI = !VIADRIAgpInit(ctx, pVia);
-
-    if (pVia->IsPCI) {
-        VIADRIPciInit(ctx, pVia);
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use pci.\n" );
-    }
-    else
-        xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use agp.\n" );
-
-    if (!(VIADRIFBInit(ctx, pVia))) {
-	VIADRICloseScreen(ctx);
-        xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] frame buffer initialize fail .\n" );
-        return GL_FALSE;
-    }
-    
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] frame buffer initialized.\n" );
- 
-    return VIADRIFinishScreenInit(ctx);
-}
-
-static void
-VIADRICloseScreen(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI=(VIADRIPtr)pVia->devPrivate;
-
-    VIADRIRingBufferCleanup(ctx);
-
-    if (pVia->MapBase) {
-	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Unmapping MMIO registers\n");
-        drmUnmap(pVia->MapBase, pVIADRI->regs.size);
-    }
-
-    if (pVia->agpSize) {
-	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Freeing agp memory\n");
-        drmAgpFree(pVia->drmFD, pVia->agpHandle);
-	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Releasing agp module\n");
-    	drmAgpRelease(pVia->drmFD);
-    }
-
-#if 0
-    if (pVia->DRIIrqEnable) 
-#endif
-        VIADRIIrqExit(ctx);
-}
-
-static int
-VIADRIFinishScreenInit(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI;
-    int err;
-
-    err = drmCreateContext(ctx->drmFD, &ctx->serverContext);
-    if (err != 0) {
-        fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-        return GL_FALSE;
-    }
-
-    DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0);
-
-
-    if (!VIADRIKernelInit(ctx, pVia)) {
-	VIADRICloseScreen(ctx);
-	return GL_FALSE;
-    }
-    xf86DrvMsg(pScreen->myNum, X_INFO, "[dri] kernel data initialized.\n");
-
-    /* set SAREA value */
-    {
-	drm_via_sarea_t *saPriv;
-
-	saPriv=(drm_via_sarea_t*)(((char*)ctx->pSAREA) +
-                               sizeof(drm_sarea_t));
-	assert(saPriv);
-	memset(saPriv, 0, sizeof(*saPriv));
-	saPriv->ctxOwner = -1;
-    }
-    pVIADRI=(VIADRIPtr)pVia->devPrivate;
-    pVIADRI->deviceID=pVia->Chipset;  
-    pVIADRI->width=ctx->shared.virtualWidth;
-    pVIADRI->height=ctx->shared.virtualHeight;
-    pVIADRI->mem=ctx->shared.fbSize;
-    pVIADRI->bytesPerPixel= (ctx->bpp+7) / 8; 
-    pVIADRI->sarea_priv_offset = sizeof(drm_sarea_t);
-    /* TODO */
-    pVIADRI->scrnX=pVIADRI->width;
-    pVIADRI->scrnY=pVIADRI->height;
-
-    /* Initialize IRQ */
-#if 0
-    if (pVia->DRIIrqEnable) 
-#endif
-	VIADRIIrqInit(ctx);
-    
-    pVIADRI->ringBufActive = 0;
-    VIADRIRingBufferInit(ctx);
-
-    return GL_TRUE;
-}
-
-/* Initialize the kernel data structures. */
-static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia)
-{
-    drm_via_init_t drmInfo;
-    memset(&drmInfo, 0, sizeof(drm_via_init_t));
-    drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-    drmInfo.func = VIA_INIT_MAP;
-    drmInfo.fb_offset           = pVia->FrameBufferBase;
-    drmInfo.mmio_offset         = pVia->registerHandle;
-    if (pVia->IsPCI)
-	drmInfo.agpAddr = (uint32_t)NULL;
-    else
-	drmInfo.agpAddr = (uint32_t)pVia->agpAddr;
-
-    if ((drmCommandWrite(pVia->drmFD, DRM_VIA_MAP_INIT,&drmInfo,
-			     sizeof(drm_via_init_t))) < 0)
-	    return GL_FALSE;
-
-    return GL_TRUE;
-}
-/* Add a map for the MMIO registers */
-static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia)
-{
-    int flags = 0;
-
-    if (drmAddMap(pVia->drmFD, pVia->MmioBase, VIA_MMIO_REGSIZE,
-		  DRM_REGISTERS, flags, &pVia->registerHandle) < 0) {
-	return GL_FALSE;
-    }
-
-    xf86DrvMsg(pScreen->myNum, X_INFO,
-	"[drm] register handle = 0x%08lx\n", pVia->registerHandle);
-
-    return GL_TRUE;
-}
-
-static int viaValidateMode(const DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-
-    return 1;
-}
-
-static int viaPostValidateMode(const DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-
-    return 1;
-}
-
-static void VIAEnableMMIO(DRIDriverContext * ctx)
-{
-    /*vgaHWPtr hwp = VGAHWPTR(ctx);*/
-    VIAPtr pVia = VIAPTR(ctx);
-    unsigned char val;
-
-#if 0
-    if (xf86IsPrimaryPci(pVia->PciInfo)) {
-        /* If we are primary card, we still use std vga port. If we use
-         * MMIO, system will hang in vgaHWSave when our card used in
-         * PLE and KLE (integrated Trident MVP4)
-         */
-        vgaHWSetStdFuncs(hwp);
-    }
-    else {
-        vgaHWSetMmioFuncs(hwp, pVia->MapBase, 0x8000);
-    }
-#endif
-
-    val = VGAIN8(0x3c3);
-    VGAOUT8(0x3c3, val | 0x01);
-    val = VGAIN8(0x3cc);
-    VGAOUT8(0x3c2, val | 0x01);
-
-    /* Unlock Extended IO Space */
-    VGAOUT8(0x3c4, 0x10);
-    VGAOUT8(0x3c5, 0x01);
-
-    /* Enable MMIO */
-    if(!pVia->IsSecondary) {
-	VGAOUT8(0x3c4, 0x1a);
-	val = VGAIN8(0x3c5);
-#ifdef DEBUG
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "primary val = %x\n", val);
-#endif
-	VGAOUT8(0x3c5, val | 0x68);
-    }
-    else {
-	VGAOUT8(0x3c4, 0x1a);
-	val = VGAIN8(0x3c5);
-#ifdef DEBUG
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "secondary val = %x\n", val);
-#endif
-	VGAOUT8(0x3c5, val | 0x38);
-    }
-
-    /* Unlock CRTC registers */
-    VGAOUT8(0x3d4, 0x47);
-    VGAOUT8(0x3d5, 0x00);
-
-    return;
-}
-
-static void VIADisableMMIO(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    unsigned char val;
-
-    VGAOUT8(0x3c4, 0x1a);
-    val = VGAIN8(0x3c5);
-    VGAOUT8(0x3c5, val & 0x97);
-
-    return;
-}
-
-static void VIADisableExtendedFIFO(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    uint32_t  dwGE230, dwGE298;
-
-    /* Cause of exit XWindow will dump back register value, others chipset no
-     * need to set extended fifo value */
-    if (pVia->Chipset == VIA_CLE266 && pVia->ChipRev < 15 &&
-        (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary)) {
-        /* Turn off Extend FIFO */
-        /* 0x298[29] */
-        dwGE298 = VIAGETREG(0x298);
-        VIASETREG(0x298, dwGE298 | 0x20000000);
-        /* 0x230[21] */
-        dwGE230 = VIAGETREG(0x230);
-        VIASETREG(0x230, dwGE230 & ~0x00200000);
-        /* 0x298[29] */
-        dwGE298 = VIAGETREG(0x298);
-        VIASETREG(0x298, dwGE298 & ~0x20000000);
-    }
-}
-
-static void VIAEnableExtendedFIFO(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    uint8_t   bRegTemp;
-    uint32_t  dwGE230, dwGE298;
-
-    switch (pVia->Chipset) {
-    case VIA_CLE266:
-        if (pVia->ChipRev > 14) {  /* For 3123Cx */
-            if (pVia->HasSecondary) {  /* SAMM or DuoView case */
-                if (ctx->shared.virtualWidth >= 1024)
-    	        {
-    	            /* 3c5.16[0:5] */
-        	        VGAOUT8(0x3C4, 0x16);
-            	    bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x3F;
-        	        bRegTemp |= 0x1C;
-            	    VGAOUT8(0x3C5, bRegTemp);
-        	        /* 3c5.17[0:6] */
-            	    VGAOUT8(0x3C4, 0x17);
-                	bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x7F;
-        	        bRegTemp |= 0x3F;
-            	    VGAOUT8(0x3C5, bRegTemp);
-            	    pVia->EnableExtendedFIFO = GL_TRUE;
-    	        }
-            }
-            else   /* Single view or Simultaneoue case */
-            {
-                if (ctx->shared.virtualWidth > 1024)
-    	        {
-    	            /* 3c5.16[0:5] */
-        	        VGAOUT8(0x3C4, 0x16);
-            	    bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x3F;
-        	        bRegTemp |= 0x17;
-            	    VGAOUT8(0x3C5, bRegTemp);
-        	        /* 3c5.17[0:6] */
-            	    VGAOUT8(0x3C4, 0x17);
-                	bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x7F;
-        	        bRegTemp |= 0x2F;
-            	    VGAOUT8(0x3C5, bRegTemp);
-            	    pVia->EnableExtendedFIFO = GL_TRUE;
-    	        }
-            }
-            /* 3c5.18[0:5] */
-            VGAOUT8(0x3C4, 0x18);
-            bRegTemp = VGAIN8(0x3C5);
-            bRegTemp &= ~0x3F;
-            bRegTemp |= 0x17;
-            bRegTemp |= 0x40;  /* force the preq always higher than treq */
-            VGAOUT8(0x3C5, bRegTemp);
-        }
-        else {      /* for 3123Ax */
-            if (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary) {
-                /* Turn on Extend FIFO */
-                /* 0x298[29] */
-                dwGE298 = VIAGETREG(0x298);
-                VIASETREG(0x298, dwGE298 | 0x20000000);
-                /* 0x230[21] */
-                dwGE230 = VIAGETREG(0x230);
-                VIASETREG(0x230, dwGE230 | 0x00200000);
-                /* 0x298[29] */
-                dwGE298 = VIAGETREG(0x298);
-                VIASETREG(0x298, dwGE298 & ~0x20000000);
-
-                /* 3c5.16[0:5] */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp |= 0x17;
-                /* bRegTemp |= 0x10; */
-                VGAOUT8(0x3C5, bRegTemp);
-                /* 3c5.17[0:6] */
-                VGAOUT8(0x3C4, 0x17);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x7F;
-                bRegTemp |= 0x2F;
-                /*bRegTemp |= 0x1F;*/
-                VGAOUT8(0x3C5, bRegTemp);
-                /* 3c5.18[0:5] */
-                VGAOUT8(0x3C4, 0x18);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp |= 0x17;
-                bRegTemp |= 0x40;  /* force the preq always higher than treq */
-                VGAOUT8(0x3C5, bRegTemp);
-          	    pVia->EnableExtendedFIFO = GL_TRUE;
-            }
-        }
-        break;
-    case VIA_KM400:
-        if (pVia->HasSecondary) {  /* SAMM or DuoView case */
-            if ((ctx->shared.virtualWidth >= 1600) &&
-                (pVia->MemClk <= VIA_MEM_DDR200)) {
-        	    /* enable CRT extendded FIFO */
-            	VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x1C);
-    	        /* revise second display queue depth and read threshold */
-        	    VGAOUT8(0x3C4, 0x16);
-            	bRegTemp = VGAIN8(0x3C5);
-    	        bRegTemp &= ~0x3F;
-    	        bRegTemp = (bRegTemp) | (0x09);
-                VGAOUT8(0x3C5, bRegTemp);
-            }
-            else {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5,0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x1C);
-                VGAOUT8(0x3C5, bRegTemp);
-            }
-            /* 3c5.18[0:5] */
-            VGAOUT8(0x3C4, 0x18);
-            bRegTemp = VGAIN8(0x3C5);
-            bRegTemp &= ~0x3F;
-            bRegTemp |= 0x17;
-            bRegTemp |= 0x40;  /* force the preq always higher than treq */
-            VGAOUT8(0x3C5, bRegTemp);
-       	    pVia->EnableExtendedFIFO = GL_TRUE;
-        }
-        else {
-            if ( (ctx->shared.virtualWidth > 1024) && (ctx->shared.virtualWidth <= 1280) )
-            {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x17);
-                VGAOUT8(0x3C5, bRegTemp);
-           	    pVia->EnableExtendedFIFO = GL_TRUE;
-            }
-            else if ((ctx->shared.virtualWidth > 1280))
-            {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x1C);
-                VGAOUT8(0x3C5, bRegTemp);
-           	    pVia->EnableExtendedFIFO = GL_TRUE;
-            }
-            else
-            {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x10);
-                VGAOUT8(0x3C5, bRegTemp);
-            }
-            /* 3c5.18[0:5] */
-            VGAOUT8(0x3C4, 0x18);
-            bRegTemp = VGAIN8(0x3C5);
-            bRegTemp &= ~0x3F;
-            bRegTemp |= 0x17;
-            bRegTemp |= 0x40;  /* force the preq always higher than treq */
-            VGAOUT8(0x3C5, bRegTemp);
-        }
-        break;
-    case VIA_K8M800:
-        /*=* R1 Display FIFO depth (384 /8 -1 -> 0xbf) SR17[7:0] (8bits) *=*/
-        VGAOUT8(0x3c4, 0x17);
-        VGAOUT8(0x3c5, 0xbf);
-
-        /*=* R2 Display fetch datum threshold value (328/4 -> 0x52)
-             SR16[5:0], SR16[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x16);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x52 & 0x3F);
-        bRegTemp |= ((0x52 & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-
-        /*=* R3 Switch to the highest agent threshold value (74 -> 0x4a)
-             SR18[5:0], SR18[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x18);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x4a & 0x3F);
-        bRegTemp |= ((0x4a & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-#if 0
-        /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
-             SR1C[7:0], SR1D[1:0] (10bits) *=*/
-        wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
-        VGAOUT8(0x3c4, 0x1c);
-        VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
-        VGAOUT8(0x3c4, 0x1d);
-        bRegTemp = VGAIN8(0x3c5) & ~0x03;
-        VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
-#endif
-        if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
-        {
-            /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp | 0x10);
-        }
-        else
-        {
-            /*=* Max. length for a request SR22[4:0]
-                 (128/4 -> over flow 0x0) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp);
-        }
-        break;
-    case VIA_PM800:
-        /*=* R1 Display FIFO depth (96-1 -> 0x5f) SR17[7:0] (8bits) *=*/
-        VGAOUT8(0x3c4, 0x17);
-        VGAOUT8(0x3c5, 0x5f);
-
-        /*=* R2 Display fetch datum threshold value (32 -> 0x20)
-             SR16[5:0], SR16[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x16);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x20 & 0x3F);
-        bRegTemp |= ((0x20 & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-
-        /*=* R3 Switch to the highest agent threshold value (16 -> 0x10)
-             SR18[5:0], SR18[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x18);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x10 & 0x3F);
-        bRegTemp |= ((0x10 & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-#if 0
-        /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
-             SR1C[7:0], SR1D[1:0] (10bits) *=*/
-        wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
-        VGAOUT8(0x3c4, 0x1c);
-        VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
-        VGAOUT8(0x3c4, 0x1d);
-        bRegTemp = VGAIN8(0x3c5) & ~0x03;
-        VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
-#endif
-        if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
-        {
-            /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp | 0x10);
-        }
-        else
-        {
-            /*=* Max. length for a request SR22[4:0] (0x1F) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp | 0x1F);
-        }
-        break;
-    default:
-        break;
-    }
-}
-
-static void VIAInitialize2DEngine(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    uint32_t  dwVQStartAddr, dwVQEndAddr;
-    uint32_t  dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
-    uint32_t  dwGEMode;
-
-    /* init 2D engine regs to reset 2D engine */
-    VIASETREG(0x04, 0x0);
-    VIASETREG(0x08, 0x0);
-    VIASETREG(0x0c, 0x0);
-    VIASETREG(0x10, 0x0);
-    VIASETREG(0x14, 0x0);
-    VIASETREG(0x18, 0x0);
-    VIASETREG(0x1c, 0x0);
-    VIASETREG(0x20, 0x0);
-    VIASETREG(0x24, 0x0);
-    VIASETREG(0x28, 0x0);
-    VIASETREG(0x2c, 0x0);
-    VIASETREG(0x30, 0x0);
-    VIASETREG(0x34, 0x0);
-    VIASETREG(0x38, 0x0);
-    VIASETREG(0x3c, 0x0);
-    VIASETREG(0x40, 0x0);
-
-    VIADisableMMIO(ctx);
-
-    /* Init AGP and VQ regs */
-    VIASETREG(0x43c, 0x00100000);
-    VIASETREG(0x440, 0x00000000);
-    VIASETREG(0x440, 0x00333004);
-    VIASETREG(0x440, 0x60000000);
-    VIASETREG(0x440, 0x61000000);
-    VIASETREG(0x440, 0x62000000);
-    VIASETREG(0x440, 0x63000000);
-    VIASETREG(0x440, 0x64000000);
-    VIASETREG(0x440, 0x7D000000);
-
-    VIASETREG(0x43c, 0xfe020000);
-    VIASETREG(0x440, 0x00000000);
-
-    if (pVia->VQStart != 0) {
-        /* Enable VQ */
-        dwVQStartAddr = pVia->VQStart;
-        dwVQEndAddr = pVia->VQEnd;
-        dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
-        dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
-        dwVQStartEndH = 0x52000000 | ((dwVQStartAddr & 0xFF000000) >> 24) |
-                        ((dwVQEndAddr & 0xFF000000) >> 16);
-        dwVQLen = 0x53000000 | (VIA_VQ_SIZE >> 3);
-
-        VIASETREG(0x43c, 0x00fe0000);
-        VIASETREG(0x440, 0x080003fe);
-        VIASETREG(0x440, 0x0a00027c);
-        VIASETREG(0x440, 0x0b000260);
-        VIASETREG(0x440, 0x0c000274);
-        VIASETREG(0x440, 0x0d000264);
-        VIASETREG(0x440, 0x0e000000);
-        VIASETREG(0x440, 0x0f000020);
-        VIASETREG(0x440, 0x1000027e);
-        VIASETREG(0x440, 0x110002fe);
-        VIASETREG(0x440, 0x200f0060);
-
-        VIASETREG(0x440, 0x00000006);
-        VIASETREG(0x440, 0x40008c0f);
-        VIASETREG(0x440, 0x44000000);
-        VIASETREG(0x440, 0x45080c04);
-        VIASETREG(0x440, 0x46800408);
-
-        VIASETREG(0x440, dwVQStartEndH);
-        VIASETREG(0x440, dwVQStartL);
-        VIASETREG(0x440, dwVQEndL);
-        VIASETREG(0x440, dwVQLen);
-    }
-    else {
-        /* Diable VQ */
-        VIASETREG(0x43c, 0x00fe0000);
-        VIASETREG(0x440, 0x00000004);
-        VIASETREG(0x440, 0x40008c0f);
-        VIASETREG(0x440, 0x44000000);
-        VIASETREG(0x440, 0x45080c04);
-        VIASETREG(0x440, 0x46800408);
-    }
-
-    dwGEMode = 0;
-
-    switch (ctx->bpp) {
-    case 16:
-        dwGEMode |= VIA_GEM_16bpp;
-        break;
-    case 32:
-        dwGEMode |= VIA_GEM_32bpp;
-        break;
-    default:
-        dwGEMode |= VIA_GEM_8bpp;
-        break;
-    }
-
-#if 0
-    switch (ctx->shared.virtualWidth) {
-    case 800:
-        dwGEMode |= VIA_GEM_800;
-        break;
-    case 1024:
-        dwGEMode |= VIA_GEM_1024;
-        break;
-    case 1280:
-        dwGEMode |= VIA_GEM_1280;
-        break;
-    case 1600:
-        dwGEMode |= VIA_GEM_1600;
-        break;
-    case 2048:
-        dwGEMode |= VIA_GEM_2048;
-        break;
-    default:
-        dwGEMode |= VIA_GEM_640;
-        break;
-    }
-#endif
-    
-    VIAEnableMMIO(ctx);
-
-    /* Set BPP and Pitch */
-    VIASETREG(VIA_REG_GEMODE, dwGEMode);
-
-    /* Set Src and Dst base address and pitch, pitch is qword */
-    VIASETREG(VIA_REG_SRCBASE, 0x0);
-    VIASETREG(VIA_REG_DSTBASE, 0x0);
-    VIASETREG(VIA_REG_PITCH, VIA_PITCH_ENABLE |
-              ((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) |
-              (((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) << 16));
-}
-
-static int b3DRegsInitialized = 0;
-
-static void VIAInitialize3DEngine(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    int i;
-
-    if (!b3DRegsInitialized)
-    {
-
-        VIASETREG(0x43C, 0x00010000);
-
-        for (i = 0; i <= 0x7D; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x43C, 0x00020000);
-
-        for (i = 0; i <= 0x94; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x440, 0x82400000);
-
-        VIASETREG(0x43C, 0x01020000);
-
-
-        for (i = 0; i <= 0x94; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x440, 0x82400000);
-        VIASETREG(0x43C, 0xfe020000);
-
-        for (i = 0; i <= 0x03; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x43C, 0x00030000);
-
-        for (i = 0; i <= 0xff; i++)
-        {
-            VIASETREG(0x440, 0);
-        }
-        VIASETREG(0x43C, 0x00100000);
-        VIASETREG(0x440, 0x00333004);
-        VIASETREG(0x440, 0x10000002);
-        VIASETREG(0x440, 0x60000000);
-        VIASETREG(0x440, 0x61000000);
-        VIASETREG(0x440, 0x62000000);
-        VIASETREG(0x440, 0x63000000);
-        VIASETREG(0x440, 0x64000000);
-
-        VIASETREG(0x43C, 0x00fe0000);
-
-        if (pVia->ChipRev >= 3 )
-            VIASETREG(0x440,0x40008c0f);
-        else
-            VIASETREG(0x440,0x4000800f);
-
-        VIASETREG(0x440,0x44000000);
-        VIASETREG(0x440,0x45080C04);
-        VIASETREG(0x440,0x46800408);
-        VIASETREG(0x440,0x50000000);
-        VIASETREG(0x440,0x51000000);
-        VIASETREG(0x440,0x52000000);
-        VIASETREG(0x440,0x53000000);
-
-        b3DRegsInitialized = 1;
-        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-                   "3D Engine has been initialized.\n");
-    }
-
-    VIASETREG(0x43C,0x00fe0000);
-    VIASETREG(0x440,0x08000001);
-    VIASETREG(0x440,0x0A000183);
-    VIASETREG(0x440,0x0B00019F);
-    VIASETREG(0x440,0x0C00018B);
-    VIASETREG(0x440,0x0D00019B);
-    VIASETREG(0x440,0x0E000000);
-    VIASETREG(0x440,0x0F000000);
-    VIASETREG(0x440,0x10000000);
-    VIASETREG(0x440,0x11000000);
-    VIASETREG(0x440,0x20000000);
-}
-
-static int
-WaitIdleCLE266(VIAPtr pVia)
-{
-    int loop = 0;
-
-    /*mem_barrier();*/
-
-    while (!(VIAGETREG(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && (loop++ < MAXLOOP))
-        ;
-
-    while ((VIAGETREG(VIA_REG_STATUS) &
-          (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
-          (loop++ < MAXLOOP))
-        ;
-
-    return loop >= MAXLOOP;
-}
-
-static int viaInitFBDev(DRIDriverContext *ctx)
-{
-    VIAPtr pVia = CALLOC(sizeof(*pVia));
-
-    ctx->driverPrivate = (void *)pVia;
-
-    switch (ctx->chipset) {
-    case PCI_CHIP_CLE3122:
-    case PCI_CHIP_CLE3022:
-        pVia->Chipset = VIA_CLE266;
-        break;
-    case PCI_CHIP_VT7205:
-    case PCI_CHIP_VT3205:
-        pVia->Chipset = VIA_KM400;
-        break;
-    case PCI_CHIP_VT3204:
-    case PCI_CHIP_VT3344:
-        pVia->Chipset = VIA_K8M800;
-        break;
-    case PCI_CHIP_VT3259:
-        pVia->Chipset = VIA_PM800;
-        break;
-    default:
-        xf86DrvMsg(0, X_ERROR, "VIA: Unknown device ID (0x%x)\n", ctx->chipset);
-    }
-
-    /* _SOLO TODO XXX need to read ChipRev too */
-    pVia->ChipRev = 0;
-
-    pVia->videoRambytes = ctx->shared.fbSize;
-    pVia->MmioBase = ctx->MMIOStart;
-    pVia->FrameBufferBase = ctx->FBStart & 0xfc000000;
-
-    pVia->FBFreeStart = ctx->shared.virtualWidth * ctx->cpp *
-        ctx->shared.virtualHeight;
-
-#if 1
-    /* Alloc a second framebuffer for the second head */
-    pVia->FBFreeStart += ctx->shared.virtualWidth * ctx->cpp *
-	ctx->shared.virtualHeight;
-#endif
-
-    pVia->VQStart = pVia->FBFreeStart;
-    pVia->VQEnd = pVia->FBFreeStart + VIA_VQ_SIZE - 1;
-
-    pVia->FBFreeStart += VIA_VQ_SIZE;
-
-    pVia->FBFreeEnd = pVia->videoRambytes;
-
-    if (!VIADRIScreenInit(ctx))
-        return 0;
-
-    return 1;
-}
-
-static void viaHaltFBDev(DRIDriverContext *ctx)
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-        free(ctx->driverPrivate);
-        ctx->driverPrivate = 0;
-    }
-}
-
-static int viaEngineShutdown(const DRIDriverContext *ctx)
-{
-    return 1;
-}
-
-static int viaEngineRestore(const DRIDriverContext *ctx)
-{
-    return 1;
-}
-
-const struct DRIDriverRec __driDriver =
-{
-    viaValidateMode,
-    viaPostValidateMode,
-    viaInitFBDev,
-    viaHaltFBDev,
-    viaEngineShutdown,
-    viaEngineRestore,  
-    0,
-};
-