diff options
| author | Jason Ekstrand <[email protected]> | 2017-06-23 10:42:30 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2017-07-22 20:59:22 -0700 |
| commit | 987c09e0444e17343904b8d9ffd541f78517f8d2 (patch) | |
| tree | 255fcf1182abfd331d692a96deea551e7be8de1e /src/mesa/drivers/dri | |
| parent | 18a69bbc0f93f27629f9eb834fbe347195299be4 (diff) | |
i965/miptree: Tighten up finish_mcs_write
Multisample surfaces only have a single miplevel so there's no reason to
be passing the extra parameters around. It only leads to confusion.
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index b93e8afa15d..07e71cd17dd 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2079,18 +2079,18 @@ intel_miptree_finish_ccs_write(struct brw_context *brw, static void intel_miptree_finish_mcs_write(struct brw_context *brw, struct intel_mipmap_tree *mt, - uint32_t level, uint32_t layer, - bool written_with_aux) + uint32_t layer, + bool written_with_mcs) { - switch (intel_miptree_get_aux_state(mt, level, layer)) { + switch (intel_miptree_get_aux_state(mt, 0, layer)) { case ISL_AUX_STATE_CLEAR: - assert(written_with_aux); - intel_miptree_set_aux_state(brw, mt, level, layer, 1, + assert(written_with_mcs); + intel_miptree_set_aux_state(brw, mt, 0, layer, 1, ISL_AUX_STATE_COMPRESSED_CLEAR); break; case ISL_AUX_STATE_COMPRESSED_CLEAR: - assert(written_with_aux); + assert(written_with_mcs); break; /* Nothing to do */ case ISL_AUX_STATE_COMPRESSED_NO_CLEAR: @@ -2288,8 +2288,9 @@ intel_miptree_finish_write(struct brw_context *brw, return; if (mt->surf.samples > 1) { + assert(level == 0); for (uint32_t a = 0; a < num_layers; a++) { - intel_miptree_finish_mcs_write(brw, mt, level, start_layer + a, + intel_miptree_finish_mcs_write(brw, mt, start_layer + a, written_with_aux); } } else { |