Merge commit 'origin/master' into gallium-sampler-view

Conflicts:
	src/gallium/auxiliary/util/u_tile.c
	src/gallium/auxiliary/util/u_tile.h
	src/gallium/drivers/identity/id_context.c
	src/gallium/drivers/llvmpipe/lp_setup.c
	src/gallium/drivers/llvmpipe/lp_setup.h
	src/gallium/drivers/softpipe/sp_tex_tile_cache.c
	src/gallium/include/pipe/p_context.h
	src/mesa/state_tracker/st_cb_bitmap.c
	src/mesa/state_tracker/st_cb_drawpixels.c

38 files changed, 529 insertions, 657 deletions

diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
index 890ae513397..75c98825b79 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -698,7 +698,7 @@ setupLoaderExtensions(__DRIscreen *psp,
  * \param drm_version Version of the kernel DRM.
  * \param frame_buffer Data describing the location and layout of the
  *                     framebuffer.
- * \param pSAREA       Pointer the the SAREA.
+ * \param pSAREA       Pointer to the SAREA.
  * \param fd           Device handle for the DRM.
  * \param extensions   ??
  * \param driver_modes  Returns modes suppoted by the driver
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index a242580273f..842d4b7aa10 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -54,6 +54,7 @@ DRIVER_SOURCES = \
 	brw_gs_emit.c \
 	brw_gs_state.c \
 	brw_misc_state.c \
+	brw_optimize.c \
 	brw_program.c \
 	brw_queryobj.c \
 	brw_sf.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index a512896f315..241193c3579 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -156,6 +156,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
       brw->has_surface_tile_offset = GL_TRUE;
       brw->has_compr4 = GL_TRUE;
       brw->has_aa_line_parameters = GL_TRUE;
+      brw->has_pln = GL_TRUE;
   } else {
       brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965;
       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index d6fc37e4d89..2855c93ea66 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -446,6 +446,7 @@ struct brw_context
    GLboolean has_compr4;
    GLboolean has_negative_rhw_bug;
    GLboolean has_aa_line_parameters;
+   GLboolean has_pln;
 ;
    struct {
       struct brw_state_flags dirty;
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index bb1b5f5ef03..984e56d00c8 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -550,6 +550,7 @@
 #define BRW_OPCODE_DP2        87
 #define BRW_OPCODE_DPA2       88
 #define BRW_OPCODE_LINE       89
+#define BRW_OPCODE_PLN        90
 #define BRW_OPCODE_NOP        126
 
 #define BRW_PREDICATE_NONE             0
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 54699cf8d34..ad61770212c 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -50,6 +50,7 @@ struct {
     [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
+    [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
@@ -73,7 +74,7 @@ struct {
     [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
     [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
-    [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 },
+    [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 39eb88d7c2b..4f55158e8f3 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -795,6 +795,7 @@ ALU2(DPH)
 ALU2(DP3)
 ALU2(DP2)
 ALU2(LINE)
+ALU2(PLN)
 
 #undef ALU1
 #undef ALU2
@@ -965,4 +966,9 @@ void brw_math_invert( struct brw_compile *p,
 
 void brw_set_src1( struct brw_instruction *insn,
                           struct brw_reg reg );
+
+
+/* brw_optimize.c */
+void brw_optimize(struct brw_compile *p);
+
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f69d5296137..d2395dec288 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -573,7 +573,7 @@ ALU2(DPH)
 ALU2(DP3)
 ALU2(DP2)
 ALU2(LINE)
-
+ALU2(PLN)
 
 
 
@@ -1290,7 +1290,7 @@ void brw_SAMPLE(struct brw_compile *p,
 		GLuint simd_mode)
 {
    GLboolean need_stall = 0;
-   
+
    if (writemask == 0) {
       /*printf("%s: zero writemask??\n", __FUNCTION__); */
       return;
@@ -1327,8 +1327,14 @@ void brw_SAMPLE(struct brw_compile *p,
          /* printf("need stall %x %x\n", newmask , writemask); */
       }
       else {
+	 GLboolean dispatch_16 = GL_FALSE;
+
 	 struct brw_reg m1 = brw_message_reg(msg_reg_nr);
-	 
+
+	 guess_execution_size(p->current, dest);
+	 if (p->current->header.execution_size == BRW_EXECUTE_16)
+	    dispatch_16 = GL_TRUE;
+
 	 newmask = ~newmask & WRITEMASK_XYZW;
 
 	 brw_push_insn_state(p);
@@ -1343,7 +1349,13 @@ void brw_SAMPLE(struct brw_compile *p,
 
   	 src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); 
 	 dest = offset(dest, dst_offset);
-	 response_length = len * 2;
+
+	 /* For 16-wide dispatch, masked channels are skipped in the
+	  * response.  For 8-wide, masked channels still take up slots,
+	  * and are just not written to.
+	  */
+	 if (dispatch_16)
+	    response_length = len * 2;
       }
    }
 
diff --git a/src/mesa/drivers/dri/i965/brw_optimize.c b/src/mesa/drivers/dri/i965/brw_optimize.c
new file mode 100644
index 00000000000..57df9ea1151
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_optimize.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <[email protected]>
+ *
+ */
+
+#include "main/macros.h"
+#include "shader/program.h"
+#include "shader/prog_parameter.h"
+#include "shader/prog_print.h"
+#include "brw_context.h"
+#include "brw_defines.h"
+#include "brw_eu.h"
+
+static GLboolean
+is_single_channel_dp4(struct brw_instruction *insn)
+{
+   if (insn->header.opcode != BRW_OPCODE_DP4 ||
+       insn->header.execution_size != BRW_EXECUTE_8 ||
+       insn->header.access_mode != BRW_ALIGN_16 ||
+       insn->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
+      return GL_FALSE;
+
+   if (!is_power_of_two(insn->bits1.da16.dest_writemask))
+      return GL_FALSE;
+
+   return GL_TRUE;
+}
+
+/**
+ * Sets the dependency control fields on DP4 instructions.
+ *
+ * The hardware only tracks dependencies on a register basis, so when
+ * you do:
+ *
+ * DP4 dst.x src1 src2
+ * DP4 dst.y src1 src3
+ * DP4 dst.z src1 src4
+ * DP4 dst.w src1 src5
+ *
+ * It will wait to do the DP4 dst.y until the dst.x is resolved, etc.
+ * We can examine our instruction stream and set the dependency
+ * control fields to tell the hardware when to do it.
+ *
+ * We may want to extend this to other instructions that are used to
+ * fill in a channel at a time of the destination register.
+ */
+static void
+brw_set_dp4_dependency_control(struct brw_compile *p)
+{
+   int i;
+
+   for (i = 1; i < p->nr_insn; i++) {
+      struct brw_instruction *insn = &p->store[i];
+      struct brw_instruction *prev = &p->store[i - 1];
+
+      if (!is_single_channel_dp4(prev))
+	 continue;
+
+      if (!is_single_channel_dp4(insn)) {
+	 i++;
+	 continue;
+      }
+
+      /* Only avoid hw dep control if the write masks are different
+       * channels of one reg.
+       */
+      if (insn->bits1.da16.dest_writemask == prev->bits1.da16.dest_writemask)
+	 continue;
+      if (insn->bits1.da16.dest_reg_nr != prev->bits1.da16.dest_reg_nr)
+	 continue;
+
+      /* Check if the second instruction depends on the previous one
+       * for a src.
+       */
+      if (insn->bits1.da1.src0_reg_file == BRW_GENERAL_REGISTER_FILE &&
+	  (insn->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT ||
+	   insn->bits2.da1.src0_reg_nr == insn->bits1.da16.dest_reg_nr))
+	  continue;
+      if (insn->bits1.da1.src1_reg_file == BRW_GENERAL_REGISTER_FILE &&
+	  (insn->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT ||
+	   insn->bits3.da1.src1_reg_nr == insn->bits1.da16.dest_reg_nr))
+	  continue;
+
+      prev->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
+      insn->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
+   }
+}
+
+void
+brw_optimize(struct brw_compile *p)
+{
+   brw_set_dp4_dependency_control(p);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index a48804a660f..d16e916832e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -384,9 +384,8 @@ static void emit_sop( struct brw_vs_compile *c,
 {
    struct brw_compile *p = &c->func;
 
-   brw_MOV(p, dst, brw_imm_f(0.0f));
-   brw_CMP(p, brw_null_reg(), cond, arg0, arg1);
-   brw_MOV(p, dst, brw_imm_f(1.0f));
+   brw_CMP(p, brw_null_reg(), cond, arg1, arg0);
+   brw_SEL(p, dst, brw_null_reg(), brw_imm_f(1.0f));
    brw_set_predicate_control_flag_value(p, 0xff);
 }
 
@@ -1825,6 +1824,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
 
    post_vs_emit(c, end_inst, last_inst);
 
+   brw_optimize(p);
+
    if (INTEL_DEBUG & DEBUG_VS) {
       int i;
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 88d84ee82fe..47b764d24d1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -328,6 +328,12 @@ void emit_cinterp(struct brw_compile *p,
 		  const struct brw_reg *dst,
 		  GLuint mask,
 		  const struct brw_reg *arg0);
+void emit_cmp(struct brw_compile *p,
+	      const struct brw_reg *dst,
+	      GLuint mask,
+	      const struct brw_reg *arg0,
+	      const struct brw_reg *arg1,
+	      const struct brw_reg *arg2);
 void emit_ddxy(struct brw_compile *p,
 	       const struct brw_reg *dst,
 	       GLuint mask,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 9315bca3156..05e464d4b61 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -34,6 +34,23 @@
 #include "brw_context.h"
 #include "brw_wm.h"
 
+static GLboolean can_do_pln(struct intel_context *intel,
+			    const struct brw_reg *deltas)
+{
+   struct brw_context *brw = brw_context(&intel->ctx);
+
+   if (!brw->has_pln)
+      return GL_FALSE;
+
+   if (deltas[1].nr != deltas[0].nr + 1)
+      return GL_FALSE;
+
+   if (intel->gen < 6 && ((deltas[0].nr & 1) != 0))
+      return GL_FALSE;
+
+   return GL_TRUE;
+}
+
 /* Not quite sure how correct this is - need to understand horiz
  * vs. vertical strides a little better.
  */
@@ -45,7 +62,13 @@ static INLINE struct brw_reg sechalf( struct brw_reg reg )
 }
 
 
-/* Payload R0:
+/**
+ * Computes the screen-space x,y position of the pixels.
+ *
+ * This will be used by emit_delta_xy() or emit_wpos_xy() for
+ * interpolation of attributes..
+ *
+ * Payload R0:
  *
  * R0.0 -- pixel mask, one bit for each of 4 pixels in 4 tiles,
  *         corresponding to each of the 16 execution channels.
@@ -60,7 +83,6 @@ static INLINE struct brw_reg sechalf( struct brw_reg reg )
  * R1.7 -- ?
  * R1.8 -- ?
  */
-
 void emit_pixel_xy(struct brw_wm_compile *c,
 		   const struct brw_reg *dst,
 		   GLuint mask)
@@ -100,7 +122,14 @@ void emit_pixel_xy(struct brw_wm_compile *c,
    brw_pop_insn_state(p);
 }
 
-
+/**
+ * Computes the screen-space x,y distance of the pixels from the start
+ * vertex.
+ *
+ * This will be used in linterp or pinterp with the start vertex value
+ * and the Cx, Cy, and C0 coefficients passed in from the setup engine
+ * to produce interpolated attribute values.
+ */
 void emit_delta_xy(struct brw_compile *p,
 		   const struct brw_reg *dst,
 		   GLuint mask,
@@ -108,25 +137,27 @@ void emit_delta_xy(struct brw_compile *p,
 {
    struct brw_reg r1 = brw_vec1_grf(1, 0);
 
-   /* Calc delta X,Y by subtracting origin in r1 from the pixel
-    * centers.
-    */
-   if (mask & WRITEMASK_X) {
-      brw_ADD(p,
-	      dst[0],
-	      retype(arg0[0], BRW_REGISTER_TYPE_UW),
-	      negate(r1));
-   }
+   if (mask == 0)
+      return;
 
-   if (mask & WRITEMASK_Y) {
-      brw_ADD(p,
-	      dst[1],
-	      retype(arg0[1], BRW_REGISTER_TYPE_UW),
-	      negate(suboffset(r1,1)));
+   assert(mask == WRITEMASK_XY);
 
-   }
+   /* Calc delta X,Y by subtracting origin in r1 from the pixel
+    * centers produced by emit_pixel_xy().
+    */
+   brw_ADD(p,
+	   dst[0],
+	   retype(arg0[0], BRW_REGISTER_TYPE_UW),
+	   negate(r1));
+   brw_ADD(p,
+	   dst[1],
+	   retype(arg0[1], BRW_REGISTER_TYPE_UW),
+	   negate(suboffset(r1,1)));
 }
 
+/**
+ * Computes the pixel offset from the window origin for gl_FragCoord().
+ */
 void emit_wpos_xy(struct brw_wm_compile *c,
 		  const struct brw_reg *dst,
 		  GLuint mask,
@@ -134,9 +165,6 @@ void emit_wpos_xy(struct brw_wm_compile *c,
 {
    struct brw_compile *p = &c->func;
 
-   /* Calculate the pixel offset from window bottom left into destination
-    * X and Y channels.
-    */
    if (mask & WRITEMASK_X) {
       if (c->fp->program.PixelCenterInteger) {
 	 /* X' = X */
@@ -186,6 +214,7 @@ void emit_pixel_w(struct brw_wm_compile *c,
 		  const struct brw_reg *deltas)
 {
    struct brw_compile *p = &c->func;
+   struct intel_context *intel = &p->brw->intel;
 
    /* Don't need this if all you are doing is interpolating color, for
     * instance.
@@ -196,8 +225,12 @@ void emit_pixel_w(struct brw_wm_compile *c,
       /* Calc 1/w - just linterp wpos[3] optimized by putting the
        * result straight into a message reg.
        */
-      brw_LINE(p, brw_null_reg(), interp3, deltas[0]);
-      brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), deltas[1]);
+      if (can_do_pln(intel, deltas)) {
+	 brw_PLN(p, brw_message_reg(2), interp3, deltas[0]);
+      } else {
+	 brw_LINE(p, brw_null_reg(), interp3, deltas[0]);
+	 brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), deltas[1]);
+      }
 
       /* Calc w */
       if (c->dispatch_width == 16) {
@@ -224,6 +257,7 @@ void emit_linterp(struct brw_compile *p,
 		  const struct brw_reg *arg0,
 		  const struct brw_reg *deltas)
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_reg interp[4];
    GLuint nr = arg0[0].nr;
    GLuint i;
@@ -235,8 +269,12 @@ void emit_linterp(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
-	 brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
-	 brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 if (can_do_pln(intel, deltas)) {
+	    brw_PLN(p, dst[i], interp[i], deltas[0]);
+	 } else {
+	    brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
+	    brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 }
       }
    }
 }
@@ -249,6 +287,7 @@ void emit_pinterp(struct brw_compile *p,
 		  const struct brw_reg *deltas,
 		  const struct brw_reg *w)
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_reg interp[4];
    GLuint nr = arg0[0].nr;
    GLuint i;
@@ -260,8 +299,12 @@ void emit_pinterp(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
-	 brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
-	 brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 if (can_do_pln(intel, deltas)) {
+	    brw_PLN(p, dst[i], interp[i], deltas[0]);
+	 } else {
+	    brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
+	    brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 }
       }
    }
    for (i = 0; i < 4; i++) {
@@ -502,11 +545,8 @@ void emit_sop(struct brw_compile *p,
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {	
 	 brw_push_insn_state(p);
-	 brw_CMP(p, brw_null_reg(), cond, arg0[i], arg1[i]);
-	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-	 brw_MOV(p, dst[i], brw_imm_f(0));
-	 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
-	 brw_MOV(p, dst[i], brw_imm_f(1.0));
+	 brw_CMP(p, brw_null_reg(), cond, arg1[i], arg0[i]);
+	 brw_SEL(p, dst[i], brw_null_reg(), brw_imm_f(1.0));
 	 brw_pop_insn_state(p);
       }
    }
@@ -566,12 +606,12 @@ static void emit_sne( struct brw_compile *p,
    emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1);
 }
 
-static void emit_cmp( struct brw_compile *p, 
-		      const struct brw_reg *dst,
-		      GLuint mask,
-		      const struct brw_reg *arg0,
-		      const struct brw_reg *arg1,
-		      const struct brw_reg *arg2 )
+void emit_cmp(struct brw_compile *p,
+	      const struct brw_reg *dst,
+	      GLuint mask,
+	      const struct brw_reg *arg0,
+	      const struct brw_reg *arg1,
+	      const struct brw_reg *arg2)
 {
    GLuint i;
 
@@ -601,14 +641,10 @@ void emit_max(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {	
-	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg0[i]);
-	 brw_set_saturate(p, 0);
-
-	 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]);
+	 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], arg1[i]);
 
 	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg1[i]);
+	 brw_SEL(p, dst[i], arg0[i], arg1[i]);
 	 brw_set_saturate(p, 0);
 	 brw_set_predicate_control_flag_value(p, 0xff);
       }
@@ -625,14 +661,10 @@ void emit_min(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {	
-	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg1[i]);
-	 brw_set_saturate(p, 0);
-
 	 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]);
 
 	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg0[i]);
+	 brw_SEL(p, dst[i], arg0[i], arg1[i]);
 	 brw_set_saturate(p, 0);
 	 brw_set_predicate_control_flag_value(p, 0xff);
       }
@@ -1086,11 +1118,19 @@ static void emit_kil( struct brw_wm_compile *c,
 {
    struct brw_compile *p = &c->func;
    struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
-   GLuint i;
-   
-   /* XXX - usually won't need 4 compares!
-    */
+   GLuint i, j;
+
    for (i = 0; i < 4; i++) {
+      /* Check if we've already done the comparison for this reg
+       * -- common when someone does KIL TEMP.wwww.
+       */
+      for (j = 0; j < i; j++) {
+	 if (memcmp(&arg0[j], &arg0[i], sizeof(arg0[0])) == 0)
+	    break;
+      }
+      if (j != i)
+	 continue;
+
       brw_push_insn_state(p);
       brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], brw_imm_f(0));   
       brw_set_predicate_control_flag_value(p, 0xff);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index ea3c2405af9..0b66cc6c9f3 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -289,6 +289,7 @@ reclaim_temps(struct brw_wm_compile *c)
  */
 static void prealloc_reg(struct brw_wm_compile *c)
 {
+    struct intel_context *intel = &c->func.brw->intel;
     int i, j;
     struct brw_reg reg;
     int urb_read_length = 0;
@@ -413,6 +414,43 @@ static void prealloc_reg(struct brw_wm_compile *c)
 	}
     }
 
+    for (i = 0; i < c->nr_fp_insns; i++) {
+	const struct prog_instruction *inst = &c->prog_instructions[i];
+
+	switch (inst->Opcode) {
+	case WM_DELTAXY:
+	    /* Allocate WM_DELTAXY destination on G45/GM45 to an
+	     * even-numbered GRF if possible so that we can use the PLN
+	     * instruction.
+	     */
+	    if (inst->DstReg.WriteMask == WRITEMASK_XY &&
+		!c->wm_regs[inst->DstReg.File][inst->DstReg.Index][0].inited &&
+		!c->wm_regs[inst->DstReg.File][inst->DstReg.Index][1].inited &&
+		(IS_G4X(intel->intelScreen->deviceID) || intel->gen == 5)) {
+		int grf;
+
+		for (grf = c->first_free_grf & ~1;
+		     grf < BRW_WM_MAX_GRF;
+		     grf += 2)
+		{
+		    if (!c->used_grf[grf] && !c->used_grf[grf + 1]) {
+			c->used_grf[grf] = GL_TRUE;
+			c->used_grf[grf + 1] = GL_TRUE;
+			c->first_free_grf = grf + 2;  /* a guess */
+
+			set_reg(c, inst->DstReg.File, inst->DstReg.Index, 0,
+				brw_vec8_grf(grf, 0));
+			set_reg(c, inst->DstReg.File, inst->DstReg.Index, 1,
+				brw_vec8_grf(grf + 1, 0));
+			break;
+		    }
+		}
+	    }
+	default:
+	    break;
+	}
+    }
+
     /* An instruction may reference up to three constants.
      * They'll be found in these registers.
      * XXX alloc these on demand!
@@ -1869,6 +1907,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 	    case OPCODE_LG2:
 		emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]);
 		break;
+	    case OPCODE_CMP:
+		emit_cmp(p, dst, dst_flags, args[0], args[1], args[2]);
+		break;
 	    case OPCODE_MIN:	
 		emit_min(p, dst, dst_flags, args[0], args[1]);
 		break;
@@ -2026,8 +2067,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                }
                break;
 	    default:
-		printf("unsupported IR in fragment shader %d\n",
-			inst->Opcode);
+		printf("unsupported opcode %d (%s) in fragment shader\n",
+		       inst->Opcode, inst->Opcode < MAX_OPCODE ?
+		       _mesa_opcode_string(inst->Opcode) : "unknown");
 	}
 
 	/* Release temporaries containing any unaliased source regs. */
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index 502e01255cb..be57d48b8dd 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -69,8 +69,8 @@ nouveau_channel_flush_notify(struct nouveau_channel *chan)
 	struct nouveau_context *nctx = chan->user_private;
 	GLcontext *ctx = &nctx->base;
 
-	if (nctx->fallback < SWRAST && ctx->DrawBuffer)
-		nouveau_state_emit(&nctx->base);
+	if (nctx->fallback < SWRAST)
+		nouveau_bo_state_emit(ctx);
 }
 
 GLboolean
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.h b/src/mesa/drivers/dri/nouveau/nouveau_context.h
index 682f8a414e3..fe64fec930b 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.h
@@ -85,6 +85,8 @@ struct nouveau_context {
 	BITSET_SET(to_nouveau_context(ctx)->dirty, NOUVEAU_STATE_##s)
 #define context_dirty_i(ctx, s, i) \
 	BITSET_SET(to_nouveau_context(ctx)->dirty, NOUVEAU_STATE_##s##0 + i)
+#define context_emit(ctx, s) \
+	context_drv(ctx)->emit[NOUVEAU_STATE_##s](ctx, NOUVEAU_STATE_##s)
 
 GLboolean
 nouveau_context_create(const __GLcontextModes *visual, __DRIcontext *dri_ctx,
diff --git a/src/mesa/drivers/dri/nouveau/nv04_context.c b/src/mesa/drivers/dri/nouveau/nv04_context.c
index a442425e448..3624b3af921 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_context.c
@@ -75,18 +75,16 @@ nv04_channel_flush_notify(struct nouveau_channel *chan)
 	struct nouveau_context *nctx = chan->user_private;
 	GLcontext *ctx = &nctx->base;
 
-	if (nctx->fallback < SWRAST && ctx->DrawBuffer) {
-		GLcontext *ctx = &nctx->base;
-
+	if (nctx->fallback < SWRAST) {
 		/* Flushing seems to clobber the engine context. */
-		context_dirty_i(ctx, TEX_OBJ, 0);
-		context_dirty_i(ctx, TEX_OBJ, 1);
-		context_dirty_i(ctx, TEX_ENV, 0);
-		context_dirty_i(ctx, TEX_ENV, 1);
-		context_dirty(ctx, CONTROL);
-		context_dirty(ctx, BLEND);
-
-		nouveau_state_emit(ctx);
+		context_emit(ctx, TEX_OBJ0);
+		context_emit(ctx, TEX_OBJ1);
+		context_emit(ctx, TEX_ENV0);
+		context_emit(ctx, TEX_ENV1);
+		context_emit(ctx, CONTROL);
+		context_emit(ctx, BLEND);
+
+		nouveau_bo_state_emit(ctx);
 	}
 }
 
@@ -200,9 +198,9 @@ nv04_context_create(struct nouveau_screen *screen, const GLvisual *visual,
 	if (ret)
 		goto fail;
 
+	init_dummy_texture(ctx);
 	nv04_hwctx_init(ctx);
 	nv04_render_init(ctx);
-	init_dummy_texture(ctx);
 
 	return ctx;
 
diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c
index 24fbf8f5194..4ec4be9a47b 100644
--- a/src/mesa/drivers/dri/r128/r128_tex.c
+++ b/src/mesa/drivers/dri/r128/r128_tex.c
@@ -468,7 +468,7 @@ static void r128TexEnv( GLcontext *ctx, GLenum target,
 	  * certain point.  It is better than completely ignoring the LOD
 	  * bias.  Unfortunately there isn't much range in the bias, the
 	  * spec mentions strides that vary between 0.5 and 2.0 but these
-	  * numbers don't seem to relate the the GL LOD bias value at all.
+	  * numbers don't seem to relate to the GL LOD bias value at all.
 	  */
 	 if ( param[0] >= 1.0 ) {
 	    bias = -128;
diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
index 9ea81fd5059..c9c1346c3a2 100644
--- a/src/mesa/drivers/dri/r200/Makefile
+++ b/src/mesa/drivers/dri/r200/Makefile
@@ -34,7 +34,6 @@ DRIVER_SOURCES = r200_context.c \
 		 r200_state.c \
 		 r200_state_init.c \
 		 r200_cmdbuf.c \
-		 r200_pixel.c \
 		 r200_tex.c \
 		 r200_texstate.c \
 		 r200_tcl.c \
diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c
index 30757600934..e187fc0f61e 100644
--- a/src/mesa/drivers/dri/r200/r200_blit.c
+++ b/src/mesa/drivers/dri/r200/r200_blit.c
@@ -48,6 +48,11 @@ unsigned r200_check_blit(gl_format mesa_format)
     case MESA_FORMAT_ARGB4444:
     case MESA_FORMAT_ARGB1555:
     case MESA_FORMAT_A8:
+    case MESA_FORMAT_L8:
+    case MESA_FORMAT_I8:
+    /* swizzled */
+    case MESA_FORMAT_RGBA8888:
+    case MESA_FORMAT_RGBA8888_REV:
 	    break;
     default:
 	    return 0;
@@ -86,7 +91,8 @@ static inline void emit_vtx_state(struct r200_context *r200)
 }
 
 static void inline emit_tx_setup(struct r200_context *r200,
-				 gl_format mesa_format,
+				 gl_format src_mesa_format,
+				 gl_format dst_mesa_format,
 				 struct radeon_bo *bo,
 				 intptr_t offset,
 				 unsigned width,
@@ -101,10 +107,16 @@ static void inline emit_tx_setup(struct r200_context *r200,
     assert(offset % 32 == 0);
 
     /* XXX others?  BE/LE? */
-    switch (mesa_format) {
+    switch (src_mesa_format) {
     case MESA_FORMAT_ARGB8888:
 	    txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP;
 	    break;
+    case MESA_FORMAT_RGBA8888:
+	    txformat |= R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP;
+	    break;
+    case MESA_FORMAT_RGBA8888_REV:
+	    txformat |= R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP;
+	    break;
     case MESA_FORMAT_XRGB8888:
 	    txformat |= R200_TXFORMAT_ARGB8888;
 	    break;
@@ -118,26 +130,143 @@ static void inline emit_tx_setup(struct r200_context *r200,
 	    txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP;
 	    break;
     case MESA_FORMAT_A8:
+    case MESA_FORMAT_I8:
 	    txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP;
 	    break;
+    case MESA_FORMAT_L8:
+	    txformat |= R200_TXFORMAT_I8;
+	    break;
+    case MESA_FORMAT_AL88:
+	    txformat |= R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP;
+	    break;
+    default:
+	    break;
+    }
+
+    switch (dst_mesa_format) {
+    case MESA_FORMAT_ARGB8888:
+    case MESA_FORMAT_XRGB8888:
+    case MESA_FORMAT_RGB565:
+    case MESA_FORMAT_ARGB4444:
+    case MESA_FORMAT_ARGB1555:
+    case MESA_FORMAT_A8:
+    case MESA_FORMAT_L8:
+    case MESA_FORMAT_I8:
     default:
+	    /* no swizzle required */
+	    BEGIN_BATCH(10);
+	    OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
+					      RADEON_TEX_BLEND_0_ENABLE));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
+						  R200_TXC_ARG_B_ZERO |
+						  R200_TXC_ARG_C_R0_COLOR |
+						  R200_TXC_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
+						   R200_TXC_OUTPUT_REG_R0));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
+						  R200_TXA_ARG_B_ZERO |
+						  R200_TXA_ARG_C_R0_ALPHA |
+						  R200_TXA_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
+						   R200_TXA_OUTPUT_REG_R0));
+	    END_BATCH();
+	    break;
+    case MESA_FORMAT_RGBA8888:
+	    BEGIN_BATCH(10);
+	    OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
+					      RADEON_TEX_BLEND_0_ENABLE));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
+						  R200_TXC_ARG_B_ZERO |
+						  R200_TXC_ARG_C_R0_COLOR |
+						  R200_TXC_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
+						   R200_TXC_OUTPUT_ROTATE_GBA |
+						   R200_TXC_OUTPUT_REG_R0));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
+						  R200_TXA_ARG_B_ZERO |
+						  R200_TXA_ARG_C_R0_ALPHA |
+						  R200_TXA_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
+						   (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) |
+						   R200_TXA_OUTPUT_REG_R0));
+	    END_BATCH();
+	    break;
+    case MESA_FORMAT_RGBA8888_REV:
+	    BEGIN_BATCH(34);
+	    OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
+					      RADEON_TEX_BLEND_0_ENABLE |
+					      RADEON_TEX_BLEND_1_ENABLE |
+					      RADEON_TEX_BLEND_2_ENABLE |
+					      RADEON_TEX_BLEND_3_ENABLE));
+	    /* r1.r = r0.b */
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
+						  R200_TXC_ARG_B_ZERO |
+						  R200_TXC_ARG_C_R0_COLOR |
+						  R200_TXC_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
+						   R200_TXC_OUTPUT_MASK_R |
+						   (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_C_SHIFT) |
+						   R200_TXC_OUTPUT_REG_R1));
+	    /* r1.a = r0.a */
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
+						  R200_TXA_ARG_B_ZERO |
+						  R200_TXA_ARG_C_R0_ALPHA |
+						  R200_TXA_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 |
+						   R200_TXA_OUTPUT_REG_R1));
+	    /* r1.g = r0.g */
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1, (R200_TXC_ARG_A_ZERO |
+						  R200_TXC_ARG_B_ZERO |
+						  R200_TXC_ARG_C_R0_COLOR |
+						  R200_TXC_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 |
+						   R200_TXC_OUTPUT_MASK_G |
+						   (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_C_SHIFT) |
+						   R200_TXC_OUTPUT_REG_R1));
+	    /* r1.a = r0.a */
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND_1, (R200_TXA_ARG_A_ZERO |
+						  R200_TXA_ARG_B_ZERO |
+						  R200_TXA_ARG_C_R0_ALPHA |
+						  R200_TXA_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1, (R200_TXA_CLAMP_0_1 |
+						   R200_TXA_OUTPUT_REG_R1));
+	    /* r1.b = r0.r */
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2, (R200_TXC_ARG_A_ZERO |
+						  R200_TXC_ARG_B_ZERO |
+						  R200_TXC_ARG_C_R0_COLOR |
+						  R200_TXC_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 |
+						   R200_TXC_OUTPUT_MASK_B |
+						   (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_C_SHIFT) |
+						   R200_TXC_OUTPUT_REG_R1));
+	    /* r1.a = r0.a */
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND_2, (R200_TXA_ARG_A_ZERO |
+						  R200_TXA_ARG_B_ZERO |
+						  R200_TXA_ARG_C_R0_ALPHA |
+						  R200_TXA_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2, (R200_TXA_CLAMP_0_1 |
+						   R200_TXA_OUTPUT_REG_R1));
+	    /* r0.rgb = r1.rgb */
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3, (R200_TXC_ARG_A_ZERO |
+						  R200_TXC_ARG_B_ZERO |
+						  R200_TXC_ARG_C_R1_COLOR |
+						  R200_TXC_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 |
+						   R200_TXC_OUTPUT_REG_R0));
+	    /* r0.a = r1.a */
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND_3, (R200_TXA_ARG_A_ZERO |
+						  R200_TXA_ARG_B_ZERO |
+						  R200_TXA_ARG_C_R1_ALPHA |
+						  R200_TXA_OP_MADD));
+	    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 |
+						   R200_TXA_OUTPUT_REG_R0));
+	    END_BATCH();
 	    break;
     }
 
-    BEGIN_BATCH(28);
-    OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+    BEGIN_BATCH(18);
     OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0);
     OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0);
-    OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
-					  R200_TXC_ARG_B_ZERO |
-					  R200_TXC_ARG_C_R0_COLOR |
-					  R200_TXC_OP_MADD));
-    OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
-    OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
-					  R200_TXA_ARG_B_ZERO |
-					  R200_TXA_ARG_C_R0_ALPHA |
-					  R200_TXA_OP_MADD));
-    OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
     OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST |
 					  R200_CLAMP_T_CLAMP_LAST |
 					  R200_MAG_FILTER_NEAREST |
@@ -146,7 +275,7 @@ static void inline emit_tx_setup(struct r200_context *r200,
     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0);
     OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) |
 					((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
-    OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
+    OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32);
 
     OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
     OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
@@ -170,6 +299,8 @@ static inline void emit_cb_setup(struct r200_context *r200,
     switch (mesa_format) {
     case MESA_FORMAT_ARGB8888:
     case MESA_FORMAT_XRGB8888:
+    case MESA_FORMAT_RGBA8888:
+    case MESA_FORMAT_RGBA8888_REV:
 	    dst_format = RADEON_COLOR_FORMAT_ARGB8888;
 	    break;
     case MESA_FORMAT_RGB565:
@@ -182,6 +313,8 @@ static inline void emit_cb_setup(struct r200_context *r200,
 	    dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 	    break;
     case MESA_FORMAT_A8:
+    case MESA_FORMAT_L8:
+    case MESA_FORMAT_I8:
 	    dst_format = RADEON_COLOR_FORMAT_RGB8;
 	    break;
     default:
@@ -384,15 +517,15 @@ unsigned r200_blit(GLcontext *ctx,
     /* Flush is needed to make sure that source buffer has correct data */
     radeonFlush(r200->radeon.glCtx);
 
-    rcommonEnsureCmdBufSpace(&r200->radeon, 78, __FUNCTION__);
+    rcommonEnsureCmdBufSpace(&r200->radeon, 102, __FUNCTION__);
 
     if (!validate_buffers(r200, src_bo, dst_bo))
         return GL_FALSE;
 
     /* 14 */
     emit_vtx_state(r200);
-    /* 28 */
-    emit_tx_setup(r200, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
+    /* 52 */
+    emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
     /* 22 */
     emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
     /* 14 */
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index 4f1a56658cc..36a29350ccc 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -51,7 +51,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_context.h"
 #include "r200_ioctl.h"
 #include "r200_state.h"
-#include "r200_pixel.h"
 #include "r200_tex.h"
 #include "r200_swtcl.h"
 #include "r200_tcl.h"
@@ -325,7 +324,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
    _mesa_init_driver_functions(&functions);
    r200InitDriverFuncs(&functions);
    r200InitIoctlFuncs(&functions);
-   r200InitStateFuncs(&functions);
+   r200InitStateFuncs(&rmesa->radeon, &functions);
    r200InitTextureFuncs(&rmesa->radeon, &functions);
    r200InitShaderFuncs(&functions);
    radeonInitQueryObjFunctions(&functions);
@@ -474,7 +473,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
    /* XXX these should really go right after _mesa_init_driver_functions() */
    radeon_fbo_init(&rmesa->radeon);
    radeonInitSpanFuncs( ctx );
-   r200InitPixelFuncs( ctx );
    r200InitTnlFuncs( ctx );
    r200InitState( rmesa );
    r200InitSwtcl( ctx );
diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c
deleted file mode 100644
index bfb7e2a2ed3..00000000000
--- a/src/mesa/drivers/dri/r200/r200_pixel.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/*
-Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/*
- * Authors:
- *   Keith Whitwell <[email protected]>
- */
-
-#include "main/glheader.h"
-#include "main/enums.h"
-#include "main/mtypes.h"
-#include "main/macros.h"
-#include "swrast/swrast.h"
-
-#include "r200_context.h"
-#include "r200_ioctl.h"
-#include "r200_pixel.h"
-#include "r200_swtcl.h"
-
-#include "drirenderbuffer.h"
-
-
-static GLboolean
-check_color( const GLcontext *ctx, GLenum type, GLenum format,
-	     const struct gl_pixelstore_attrib *packing,
-	     const void *pixels, GLint sz, GLint pitch )
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLuint cpp = rmesa->radeon.radeonScreen->cpp;
-
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-   if (	(pitch & 63) ||
-	ctx->_ImageTransferState ||
-	packing->SwapBytes ||
-	packing->LsbFirst) {
-      if (R200_DEBUG & RADEON_PIXEL)
-	 fprintf(stderr, "%s: failed 1\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-
-   if ( type == GL_UNSIGNED_INT_8_8_8_8_REV &&
-	cpp == 4 &&
-	format == GL_BGRA ) {
-      if (R200_DEBUG & RADEON_PIXEL)
-	 fprintf(stderr, "%s: passed 2\n", __FUNCTION__);
-      return GL_TRUE;
-   }
-
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s: failed\n", __FUNCTION__);
-
-   return GL_FALSE;
-}
-
-static GLboolean
-check_color_per_fragment_ops( const GLcontext *ctx )
-{
-   int result;
-   result = (!(     ctx->Color.AlphaEnabled ||
-		    ctx->Depth.Test ||
-		    ctx->Fog.Enabled ||
-		    ctx->Scissor.Enabled ||
-		    ctx->Stencil._Enabled ||
-		    !ctx->Color.ColorMask[0][0] ||
-		    !ctx->Color.ColorMask[0][1] ||
-		    !ctx->Color.ColorMask[0][2] ||
-		    !ctx->Color.ColorMask[0][3] ||
-		    ctx->Color.ColorLogicOpEnabled ||
-		    ctx->Texture._EnabledUnits
-           ) &&
-	   ctx->Current.RasterPosValid);
-
-   return result;
-}
-
-
-#if 0
-static GLboolean
-clip_pixelrect( const GLcontext *ctx,
-		const GLframebuffer *buffer,
-		GLint *x, GLint *y,
-		GLsizei *width, GLsizei *height,
-		GLint *size )
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-
-   /* left clipping */
-   if (*x < buffer->_Xmin) {
-      *width -= (buffer->_Xmin - *x);
-      *x = buffer->_Xmin;
-   }
-
-   /* right clipping */
-   if (*x + *width > buffer->_Xmax)
-      *width -= (*x + *width - buffer->_Xmax - 1);
-
-   if (*width <= 0)
-      return GL_FALSE;
-
-   /* bottom clipping */
-   if (*y < buffer->_Ymin) {
-      *height -= (buffer->_Ymin - *y);
-      *y = buffer->_Ymin;
-   }
-
-   /* top clipping */
-   if (*y + *height > buffer->_Ymax)
-      *height -= (*y + *height - buffer->_Ymax - 1);
-
-   if (*height <= 0)
-      return GL_FALSE;
-
-   *size = ((*y + *height - 1) * rmesa->radeon.radeonScreen->frontPitch +
-	    (*x + *width - 1) * rmesa->radeon.radeonScreen->cpp);
-
-   return GL_TRUE;
-}
-#endif
-
-static GLboolean
-r200TryReadPixels( GLcontext *ctx,
-		  GLint x, GLint y, GLsizei width, GLsizei height,
-		  GLenum format, GLenum type,
-		  const struct gl_pixelstore_attrib *pack,
-		  GLvoid *pixels )
-{
-   return GL_FALSE;
-#if 0
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLint pitch = pack->RowLength ? pack->RowLength : width;
-   GLint blit_format;
-   GLuint cpp = rmesa->radeon.radeonScreen->cpp;
-   GLint size = width * height * cpp;
-
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-   /* Only accelerate reading to GART buffers.
-    */
-   if ( !r200IsGartMemory(rmesa, pixels,
-			 pitch * height * rmesa->radeon.radeonScreen->cpp ) ) {
-      if (R200_DEBUG & RADEON_PIXEL)
-	 fprintf(stderr, "%s: dest not GART\n", __FUNCTION__);
-   }
-
-   /* Need GL_PACK_INVERT_MESA to cope with upsidedown results from
-    * blitter:
-    */
-   if (!pack->Invert) {
-      if (R200_DEBUG & RADEON_PIXEL)
-	 fprintf(stderr, "%s: MESA_PACK_INVERT not set\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-
-   if (!check_color(ctx, type, format, pack, pixels, size, pitch))
-      return GL_FALSE;
-
-   switch ( rmesa->radeon.radeonScreen->cpp ) {
-   case 4:
-      blit_format = R200_CP_COLOR_FORMAT_ARGB8888;
-      break;
-   default:
-      return GL_FALSE;
-   }
-
-
-   /* Although the blits go on the command buffer, need to do this and
-    * fire with lock held to guarentee cliprects and drawOffset are
-    * correct.
-    *
-    * This is an unusual situation however, as the code which flushes
-    * a full command buffer expects to be called unlocked.  As a
-    * workaround, immediately flush the buffer on aquiring the lock.
-    */
-   LOCK_HARDWARE( &rmesa->radeon );
-
-   if (rmesa->store.cmd_used)
-      rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
-
-   if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height,
-		       &size)) {
-      UNLOCK_HARDWARE( &rmesa->radeon );
-      if (R200_DEBUG & RADEON_PIXEL)
-	 fprintf(stderr, "%s totally clipped -- nothing to do\n",
-		 __FUNCTION__);
-      return GL_TRUE;
-   }
-
-   {
-      __DRIdrawable *dPriv = rmesa->radeon.dri.drawable;
-      driRenderbuffer *drb = (driRenderbuffer *) ctx->ReadBuffer->_ColorReadBuffer;
-      int nbox = dPriv->numClipRects;
-      int src_offset = drb->offset
-		     + rmesa->radeon.radeonScreen->fbLocation;
-      int src_pitch = drb->pitch * drb->cpp;
-      int dst_offset = r200GartOffsetFromVirtual( rmesa, pixels );
-      int dst_pitch = pitch * rmesa->radeon.radeonScreen->cpp;
-      drm_clip_rect_t *box = dPriv->pClipRects;
-      int i;
-
-      r200EmitWait( rmesa, RADEON_WAIT_3D );
-
-      y = dPriv->h - y - height;
-      x += dPriv->x;
-      y += dPriv->y;
-
-
-      if (R200_DEBUG & RADEON_PIXEL)
-	 fprintf(stderr, "readpixel blit src_pitch %d dst_pitch %d\n",
-		 src_pitch, dst_pitch);
-
-      for (i = 0 ; i < nbox ; i++)
-      {
-	 GLint bx = box[i].x1;
-	 GLint by = box[i].y1;
-	 GLint bw = box[i].x2 - bx;
-	 GLint bh = box[i].y2 - by;
-
-	 if (bx < x) bw -= x - bx, bx = x;
-	 if (by < y) bh -= y - by, by = y;
-	 if (bx + bw > x + width) bw = x + width - bx;
-	 if (by + bh > y + height) bh = y + height - by;
-	 if (bw <= 0) continue;
-	 if (bh <= 0) continue;
-
-	 r200EmitBlit( rmesa,
-		       blit_format,
-		       src_pitch, src_offset,
-		       dst_pitch, dst_offset,
-		       bx, by,
-		       bx - x, by - y,
-		       bw, bh );
-      }
-
-      rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
-   }
-   UNLOCK_HARDWARE( &rmesa->radeon );
-
-   radeonFinish( ctx ); /* required by GL */
-#endif
-   return GL_TRUE;
-}
-
-static void
-r200ReadPixels( GLcontext *ctx,
-		 GLint x, GLint y, GLsizei width, GLsizei height,
-		 GLenum format, GLenum type,
-		 const struct gl_pixelstore_attrib *pack,
-		 GLvoid *pixels )
-{
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-   if (!r200TryReadPixels( ctx, x, y, width, height, format, type, pack,
-			   pixels))
-      _swrast_ReadPixels( ctx, x, y, width, height, format, type, pack,
-			  pixels);
-}
-
-
-
-
-static void do_draw_pix( GLcontext *ctx,
-			 GLint x, GLint y, GLsizei width, GLsizei height,
-			 GLint pitch,
-			 const void *pixels,
-			 GLuint planemask)
-{
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-#if 0
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
-   drm_clip_rect_t *box = dPriv->pClipRects;
-   struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorDrawBuffers[0];
-   driRenderbuffer *drb = (driRenderbuffer *) rb;
-   int nbox = dPriv->numClipRects;
-   int i;
-   int blit_format;
-   int size;
-   int src_offset = r200GartOffsetFromVirtual( rmesa, pixels );
-   int src_pitch = pitch * rmesa->radeon.radeonScreen->cpp;
-
-   switch ( rmesa->radeon.radeonScreen->cpp ) {
-   case 2:
-      blit_format = R200_CP_COLOR_FORMAT_RGB565;
-      break;
-   case 4:
-      blit_format = R200_CP_COLOR_FORMAT_ARGB8888;
-      break;
-   default:
-      return;
-   }
-
-
-   LOCK_HARDWARE( &rmesa->radeon );
-
-   if (rmesa->store.cmd_used)
-      rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
-
-   y -= height;			/* cope with pixel zoom */
-
-   if (!clip_pixelrect(ctx, ctx->DrawBuffer,
-		       &x, &y, &width, &height,
-		       &size)) {
-      UNLOCK_HARDWARE( &rmesa->radeon );
-      return;
-   }
-
-   y = dPriv->h - y - height; 	/* convert from gl to hardware coords */
-   x += dPriv->x;
-   y += dPriv->y;
-
-
-   r200EmitWait( rmesa, RADEON_WAIT_3D );
-
-   for (i = 0 ; i < nbox ; i++ )
-   {
-      GLint bx = box[i].x1;
-      GLint by = box[i].y1;
-      GLint bw = box[i].x2 - bx;
-      GLint bh = box[i].y2 - by;
-
-      if (bx < x) bw -= x - bx, bx = x;
-      if (by < y) bh -= y - by, by = y;
-      if (bx + bw > x + width) bw = x + width - bx;
-      if (by + bh > y + height) bh = y + height - by;
-      if (bw <= 0) continue;
-      if (bh <= 0) continue;
-
-      r200EmitBlit( rmesa,
-		    blit_format,
-		    src_pitch, src_offset,
-		    drb->pitch * drb->cpp,
-		    drb->offset + rmesa->radeon.radeonScreen->fbLocation,
-		    bx - x, by - y,
-		    bx, by,
-		    bw, bh );
-   }
-
-   rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
-   radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */
-   UNLOCK_HARDWARE( &rmesa->radeon );
-#endif
-}
-
-
-
-
-static GLboolean
-r200TryDrawPixels( GLcontext *ctx,
-		  GLint x, GLint y, GLsizei width, GLsizei height,
-		  GLenum format, GLenum type,
-		  const struct gl_pixelstore_attrib *unpack,
-		  const GLvoid *pixels )
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLint pitch = unpack->RowLength ? unpack->RowLength : width;
-   GLuint planemask;
-   GLuint cpp = rmesa->radeon.radeonScreen->cpp;
-   GLint size = height * pitch * cpp;
-
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-   /* check that we're drawing to exactly one color buffer */
-   if (ctx->DrawBuffer->_NumColorDrawBuffers != 1)
-     return GL_FALSE;
-
-   switch (format) {
-   case GL_RGB:
-   case GL_RGBA:
-   case GL_BGRA:
-      planemask = radeonPackColor(cpp,
-				ctx->Color.ColorMask[0][RCOMP],
-				ctx->Color.ColorMask[0][GCOMP],
-				ctx->Color.ColorMask[0][BCOMP],
-				ctx->Color.ColorMask[0][ACOMP]);
-
-      if (cpp == 2)
-	 planemask |= planemask << 16;
-
-      if (planemask != ~0)
-	 return GL_FALSE;	/* fix me -- should be possible */
-
-      /* Can't do conversions on GART reads/draws.
-       */
-      if ( !r200IsGartMemory( rmesa, pixels, size ) ) {
-	 if (R200_DEBUG & RADEON_PIXEL)
-	    fprintf(stderr, "%s: not GART memory\n", __FUNCTION__);
-	 return GL_FALSE;
-      }
-
-      if (!check_color(ctx, type, format, unpack, pixels, size, pitch)) {
-	 return GL_FALSE;
-      }
-      if (!check_color_per_fragment_ops(ctx)) {
-	 return GL_FALSE;
-      }
-
-      if (ctx->Pixel.ZoomX != 1.0F ||
-	  ctx->Pixel.ZoomY != -1.0F)
-	 return GL_FALSE;
-      break;
-
-   default:
-      return GL_FALSE;
-   }
-
-   if (0)// r200IsGartMemory(rmesa, pixels, size) )
-   {
-      do_draw_pix( ctx, x, y, width, height, pitch, pixels, planemask );
-      return GL_TRUE;
-   }
-   else if (0)
-   {
-      /* Pixels is in regular memory -- get dma buffers and perform
-       * upload through them.
-       */
-   }
-   else
-      return GL_FALSE;
-}
-
-static void
-r200DrawPixels( GLcontext *ctx,
-		 GLint x, GLint y, GLsizei width, GLsizei height,
-		 GLenum format, GLenum type,
-		 const struct gl_pixelstore_attrib *unpack,
-		 const GLvoid *pixels )
-{
-   if (R200_DEBUG & RADEON_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-   if (!r200TryDrawPixels( ctx, x, y, width, height, format, type,
-			  unpack, pixels ))
-      _swrast_DrawPixels( ctx, x, y, width, height, format, type,
-			  unpack, pixels );
-}
-
-
-static void
-r200Bitmap( GLcontext *ctx, GLint px, GLint py,
-		  GLsizei width, GLsizei height,
-		  const struct gl_pixelstore_attrib *unpack,
-		  const GLubyte *bitmap )
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-
-   if (rmesa->radeon.Fallback)
-      _swrast_Bitmap( ctx, px, py, width, height, unpack, bitmap );
-   else
-      r200PointsBitmap( ctx, px, py, width, height, unpack, bitmap );
-}
-
-
-
-void r200InitPixelFuncs( GLcontext *ctx )
-{
-   if (!getenv("R200_NO_BLITS")) {
-      ctx->Driver.ReadPixels = r200ReadPixels;
-      ctx->Driver.DrawPixels = r200DrawPixels;
-      if (getenv("R200_HW_BITMAP"))
-	 ctx->Driver.Bitmap = r200Bitmap;
-   }
-}
diff --git a/src/mesa/drivers/dri/r200/r200_pixel.h b/src/mesa/drivers/dri/r200/r200_pixel.h
deleted file mode 100644
index e62aa05d749..00000000000
--- a/src/mesa/drivers/dri/r200/r200_pixel.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
-Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/*
- * Authors:
- *   Keith Whitwell <[email protected]>
- */
-
-#ifndef __R200_PIXEL_H__
-#define __R200_PIXEL_H__
-
-extern void r200InitPixelFuncs( GLcontext *ctx );
-
-#endif
diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h
index 59115212cee..e331be223b8 100644
--- a/src/mesa/drivers/dri/r200/r200_reg.h
+++ b/src/mesa/drivers/dri/r200/r200_reg.h
@@ -690,7 +690,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R200_PVS_CNTL_1_PROGRAM_START_SHIFT   0
 #       define R200_PVS_CNTL_1_POS_END_SHIFT         10
 #       define R200_PVS_CNTL_1_PROGRAM_END_SHIFT     20
-/* Addresses are relative the the vertex program parameters area. */
+/* Addresses are relative to the vertex program parameters area. */
 #define R200_VAP_PVS_CNTL_2                 0x22d4
 #       define R200_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
 #       define R200_PVS_CNTL_2_PARAM_COUNT_SHIFT  16
@@ -1265,6 +1265,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define     R200_TXC_OUTPUT_MASK_G                 (5 << 20)
 #define     R200_TXC_OUTPUT_MASK_B                 (6 << 20)
 #define     R200_TXC_OUTPUT_MASK_NONE              (7 << 20)
+#define     R200_TXC_OUTPUT_ROTATE_RGB             (0 << 24)
+#define     R200_TXC_OUTPUT_ROTATE_ARG             (1 << 24)
+#define     R200_TXC_OUTPUT_ROTATE_GBA             (2 << 24)
+#define     R200_TXC_OUTPUT_ROTATE_RGA             (3 << 24)
 #define     R200_TXC_REPL_NORMAL                   0
 #define     R200_TXC_REPL_RED                      1
 #define     R200_TXC_REPL_GREEN                    2
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 050e5aa8770..9c2ac05ad6c 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -46,6 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/tnl.h"
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
+#include "drivers/common/meta.h"
 
 #include "radeon_common.h"
 #include "radeon_mipmap_tree.h"
@@ -2487,7 +2488,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask )
 }
 /* Initialize the driver's state functions.
  */
-void r200InitStateFuncs( struct dd_function_table *functions )
+void r200InitStateFuncs( radeonContextPtr radeon, struct dd_function_table *functions )
 {
    functions->UpdateState		= r200InvalidateState;
    functions->LightingSpaceChange	= r200LightingSpaceChange;
@@ -2495,6 +2496,12 @@ void r200InitStateFuncs( struct dd_function_table *functions )
    functions->DrawBuffer		= radeonDrawBuffer;
    functions->ReadBuffer		= radeonReadBuffer;
 
+   if (radeon->radeonScreen->kernel_mm) {
+	   functions->CopyPixels                = _mesa_meta_CopyPixels;
+	   functions->DrawPixels                = _mesa_meta_DrawPixels;
+	   functions->ReadPixels                = radeonReadPixels;
+   }
+
    functions->AlphaFunc			= r200AlphaFunc;
    functions->BlendColor		= r200BlendColor;
    functions->BlendEquationSeparate	= r200BlendEquationSeparate;
diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h
index 7b9b0c106aa..327ba837e25 100644
--- a/src/mesa/drivers/dri/r200/r200_state.h
+++ b/src/mesa/drivers/dri/r200/r200_state.h
@@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_context.h"
 
 extern void r200InitState( r200ContextPtr rmesa );
-extern void r200InitStateFuncs( struct dd_function_table *functions );
+extern void r200InitStateFuncs( radeonContextPtr radeon, struct dd_function_table *functions );
 extern void r200InitTnlFuncs( GLcontext *ctx );
 
 extern void r200UpdateMaterial( GLcontext *ctx );
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 364e0ba6b61..cfeb5407e91 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -500,7 +500,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 
 	_mesa_init_driver_functions(&functions);
 	r300InitIoctlFuncs(&functions);
-	r300InitStateFuncs(&functions);
+	r300InitStateFuncs(&r300->radeon, &functions);
 	r300InitTextureFuncs(&r300->radeon, &functions);
 	r300InitShaderFuncs(&functions);
 	radeonInitQueryObjFunctions(&functions);
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index d18ebab8ff2..ac93563ed9e 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -482,7 +482,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R300_PVS_FIRST_INST_SHIFT         0
 #       define R300_PVS_XYZW_VALID_INST_SHIFT    10
 #       define R300_PVS_LAST_INST_SHIFT          20
-/* Addresses are relative the the vertex program parameters area. */
+/* Addresses are relative to the vertex program parameters area. */
 #define R300_VAP_PVS_CONST_CNTL             0x22D4
 #       define R300_PVS_CONST_BASE_OFFSET_SHIFT  0
 #       define R300_PVS_MAX_CONST_ADDR_SHIFT     16
@@ -1760,7 +1760,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * The destination register index is in FPI1 (color) and FPI3 (alpha)
  * together with enable bits.
  * There are separate enable bits for writing into temporary registers
- * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
+ * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
  * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
  * same index must be used for both).
  *
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 87489412419..749a2464e7c 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -590,7 +590,7 @@ static void r300SetDepthState(GLcontext * ctx)
 					    R500_STENCIL_REFMASK_FRONT_BACK);
 	r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT);
 
-	if (ctx->Depth.Test) {
+	if (ctx->Depth.Test && ctx->DrawBuffer->_DepthBuffer) {
 		r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE;
 		if (ctx->Depth.Mask)
 			r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_WRITE_ENABLE;
@@ -2354,7 +2354,7 @@ static void r300RenderMode(GLcontext * ctx, GLenum mode)
 /**
  * Initialize driver's state callback functions
  */
-void r300InitStateFuncs(struct dd_function_table *functions)
+void r300InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
 {
 
 	functions->UpdateState = r300InvalidateState;
@@ -2396,9 +2396,11 @@ void r300InitStateFuncs(struct dd_function_table *functions)
 	functions->DrawBuffer = radeonDrawBuffer;
 	functions->ReadBuffer = radeonReadBuffer;
 
-	functions->CopyPixels = _mesa_meta_CopyPixels;
-	functions->DrawPixels = _mesa_meta_DrawPixels;
-	functions->ReadPixels = radeonReadPixels;
+	if (radeon->radeonScreen->kernel_mm) {
+		functions->CopyPixels = _mesa_meta_CopyPixels;
+		functions->DrawPixels = _mesa_meta_DrawPixels;
+		functions->ReadPixels = radeonReadPixels;
+	}
 }
 
 void r300InitShaderFunctions(r300ContextPtr r300)
diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h
index d46bf9f1796..e70f84f4e4b 100644
--- a/src/mesa/drivers/dri/r300/r300_state.h
+++ b/src/mesa/drivers/dri/r300/r300_state.h
@@ -55,7 +55,7 @@ void r300UpdateDrawBuffer (GLcontext * ctx);
 void r300UpdateShaders (r300ContextPtr rmesa);
 void r300UpdateShaderStates (r300ContextPtr rmesa);
 void r300InitState (r300ContextPtr r300);
-void r300InitStateFuncs (struct dd_function_table *functions);
+void r300InitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
 void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count);
 void r300SetupVAP(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten);
 
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 76d5027649e..fddac2f9bdc 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -384,7 +384,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 	 */
 	_mesa_init_driver_functions(&functions);
 
-	r700InitStateFuncs(&functions);
+	r700InitStateFuncs(&r600->radeon, &functions);
 	r600InitTextureFuncs(&r600->radeon, &functions);
 	r700InitShaderFuncs(&functions);
 	radeonInitQueryObjFunctions(&functions);
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 6f156b54096..2953ffd0288 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -39,6 +39,7 @@
 #include "swrast_setup/swrast_setup.h"
 #include "main/api_arrayelt.h"
 #include "main/framebuffer.h"
+#include "drivers/common/meta.h"
 
 #include "shader/prog_parameter.h"
 #include "shader/prog_statevars.h"
@@ -1816,7 +1817,7 @@ void r700InitState(GLcontext * ctx) //-------------------
 
 }
 
-void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
+void r700InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
 {
 	functions->UpdateState = r700InvalidateState;
 	functions->AlphaFunc = r700AlphaFunc;
@@ -1857,8 +1858,13 @@ void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
 
 	functions->Scissor = radeonScissor;
 
-	functions->DrawBuffer		= radeonDrawBuffer;
-	functions->ReadBuffer		= radeonReadBuffer;
+	functions->DrawBuffer = radeonDrawBuffer;
+	functions->ReadBuffer = radeonReadBuffer;
 
+	if (radeon->radeonScreen->kernel_mm) {
+		functions->CopyPixels = _mesa_meta_CopyPixels;
+		functions->DrawPixels = _mesa_meta_DrawPixels;
+		functions->ReadPixels = radeonReadPixels;
+	}
 }
 
diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h
index 60c6a7f23ca..56885e0b154 100644
--- a/src/mesa/drivers/dri/r600/r700_state.h
+++ b/src/mesa/drivers/dri/r600/r700_state.h
@@ -40,7 +40,7 @@ extern void r700UpdateShaderStates(GLcontext * ctx);
 extern void r700UpdateViewportOffset(GLcontext * ctx);
 
 extern void r700InitState (GLcontext * ctx);
-extern void r700InitStateFuncs (struct dd_function_table *functions);
+extern void r700InitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
 
 extern void r700SetScissor(context_t *context);
 
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index 07e0adc8905..05c65164d60 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -42,7 +42,7 @@
 #include "radeon_debug.h"
 #include "r600_context.h"
 #include "r600_cmdbuf.h"
-#include "shader/programopt.c"
+#include "shader/programopt.h"
 
 #include "r700_debug.h"
 #include "r700_vertprog.h"
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c
index e1e1f215508..143822361e1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.c
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.c
@@ -48,6 +48,8 @@ unsigned r100_check_blit(gl_format mesa_format)
     case MESA_FORMAT_ARGB4444:
     case MESA_FORMAT_ARGB1555:
     case MESA_FORMAT_A8:
+    case MESA_FORMAT_L8:
+    case MESA_FORMAT_I8:
 	    break;
     default:
 	    return 0;
@@ -103,6 +105,9 @@ static void inline emit_tx_setup(struct r100_context *r100,
     case MESA_FORMAT_ARGB8888:
 	    txformat |= RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 	    break;
+    case MESA_FORMAT_RGBA8888:
+            txformat |= RADEON_TXFORMAT_RGBA8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
+            break;
     case MESA_FORMAT_XRGB8888:
 	    txformat |= RADEON_TXFORMAT_ARGB8888;
 	    break;
@@ -116,8 +121,15 @@ static void inline emit_tx_setup(struct r100_context *r100,
 	    txformat |= RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 	    break;
     case MESA_FORMAT_A8:
+    case MESA_FORMAT_I8:
 	    txformat |= RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 	    break;
+    case MESA_FORMAT_L8:
+            txformat |= RADEON_TXFORMAT_I8;
+            break;
+    case MESA_FORMAT_AL88:
+            txformat |= RADEON_TXFORMAT_AI88 | RADEON_TXFORMAT_ALPHA_IN_MAP;
+            break;
     default:
 	    break;
     }
@@ -177,6 +189,8 @@ static inline void emit_cb_setup(struct r100_context *r100,
 	    dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 	    break;
     case MESA_FORMAT_A8:
+    case MESA_FORMAT_L8:
+    case MESA_FORMAT_I8:
 	    dst_format = RADEON_COLOR_FORMAT_RGB8;
 	    break;
     default:
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 78c5f5dd572..7f5fb99fa4f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -553,6 +553,8 @@ static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
 	}
 
 	if (mtCount == 0) {
+		free(mtSizes);
+		free(mts);
 		return NULL;
 	}
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
index 27841938e66..b180c1d9a5c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
+++ b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
@@ -96,7 +96,7 @@ do_blit_readpixels(GLcontext * ctx,
         return GL_FALSE;
     }
 
-    if (ctx->_ImageTransferState) {
+    if (ctx->_ImageTransferState || ctx->Color._LogicOpEnabled) {
         return GL_FALSE;
     }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 0ce97e86972..0afbc19c127 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -45,6 +45,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/tnl.h"
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
+#include "drivers/common/meta.h"
 
 #include "radeon_context.h"
 #include "radeon_mipmap_tree.h"
@@ -1900,7 +1901,7 @@ void radeonUploadTexMatrix( r100ContextPtr rmesa,
    So: if we need the q coord in the end (solely determined by the texture
    target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
    Additionally, if we don't have texgen but 4 tex coords submitted, we swap
-   column 3 and 4 (for the 2d / 1d / texrect targets) since the the q coord
+   column 3 and 4 (for the 2d / 1d / texrect targets) since the q coord
    will get submitted in the "wrong", i.e. 3rd, slot.
    If an app submits 3 coords for 2d targets, we assume it is saving on vertex
    size and using the texture matrix to swap the r and q coords around (ut2k3
@@ -2248,6 +2249,11 @@ void radeonInitStateFuncs( GLcontext *ctx , GLboolean dri2 )
 
    ctx->Driver.DrawBuffer		= radeonDrawBuffer;
    ctx->Driver.ReadBuffer		= radeonReadBuffer;
+   if (dri2) {
+	   ctx->Driver.CopyPixels               = _mesa_meta_CopyPixels;
+	   ctx->Driver.DrawPixels               = _mesa_meta_DrawPixels;
+	   ctx->Driver.ReadPixels               = radeonReadPixels;
+   }
 
    ctx->Driver.AlphaFunc		= radeonAlphaFunc;
    ctx->Driver.BlendEquationSeparate	= radeonBlendEquationSeparate;
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
index a4bb03d5d39..e57d77e7ef2 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
@@ -52,15 +52,18 @@ do_copy_texsubimage(GLcontext *ctx,
     gl_format dst_mesaformat;
     unsigned src_width;
     unsigned dst_width;
+    unsigned flip_y;
 
     if (!radeon->vtbl.blit) {
         return GL_FALSE;
     }
 
     if (_mesa_get_format_bits(timg->base.TexFormat, GL_DEPTH_BITS) > 0) {
-        rrb = radeon_get_depthbuffer(radeon);
+        rrb = radeon_renderbuffer(ctx->ReadBuffer->_DepthBuffer);
+        flip_y = ctx->ReadBuffer->Attachment[BUFFER_DEPTH].Type == GL_NONE;
     } else {
-        rrb = radeon_get_colorbuffer(radeon);
+        rrb = radeon_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
+        flip_y = ctx->ReadBuffer->Attachment[BUFFER_COLOR0].Type == GL_NONE;
     }
 
     if (!timg->mt) {
@@ -93,6 +96,10 @@ do_copy_texsubimage(GLcontext *ctx,
     src_bpp = _mesa_get_format_bytes(src_mesaformat);
     dst_bpp = _mesa_get_format_bytes(dst_mesaformat);
     if (!radeon->vtbl.check_blit(dst_mesaformat)) {
+	    /* depth formats tend to be special */
+	    if (_mesa_get_format_bits(dst_mesaformat, GL_DEPTH_BITS) > 0)
+		    return GL_FALSE;
+
 	    if (src_bpp != dst_bpp)
 		    return GL_FALSE;
 
@@ -120,7 +127,7 @@ do_copy_texsubimage(GLcontext *ctx,
                              timg->mt->bo, dst_offset, dst_mesaformat,
                              timg->mt->levels[level].rowstride / dst_bpp,
                              dst_width, timg->base.Height,
-                             dstx, dsty, width, height, 1);
+                             dstx, dsty, width, height, flip_y);
 }
 
 void