Replace gl_vert_result enum with gl_varying_slot.

This patch makes the following search-and-replace changes:

gl_vert_result -> gl_varying_slot
VERT_RESULT_* -> VARYING_SLOT_*

Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Tested-by: Brian Paul <[email protected]>

20 files changed, 201 insertions, 200 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 6cf2bd293cf..bfb64baf321 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -134,7 +134,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    struct brw_indirect plane_ptr = brw_indirect(4, 0);
    struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
    GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                  VERT_RESULT_HPOS);
+                                                  VARYING_SLOT_POS);
 
    brw_MOV(p, get_addr_reg(vtx0),      brw_address(c->reg.vertex[0]));
    brw_MOV(p, get_addr_reg(vtx1),      brw_address(c->reg.vertex[1]));
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index a29f8e05b34..548e7e9d067 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -233,7 +233,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
    struct brw_indirect outlist_ptr = brw_indirect(5, 0);
    struct brw_indirect freelist_ptr = brw_indirect(6, 0);
    GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                  VERT_RESULT_HPOS);
+                                                  VARYING_SLOT_POS);
    
    brw_MOV(p, get_addr_reg(vtxPrev),     brw_address(c->reg.vertex[2]) );
    brw_MOV(p, get_addr_reg(plane_ptr),   brw_clip_plane0_address(c));
@@ -485,7 +485,7 @@ static void brw_clip_test( struct brw_clip_compile *c )
     struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
 
     GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                   VERT_RESULT_HPOS);
+                                                   VARYING_SLOT_POS);
 
     brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0]));
     brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1]));
diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index 03c7d428bd2..e4f4835b23b 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -53,7 +53,7 @@ static void compute_tri_direction( struct brw_clip_compile *c )
    struct brw_reg e = c->reg.tmp0;
    struct brw_reg f = c->reg.tmp1;
    GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                  VERT_RESULT_HPOS);
+                                                  VARYING_SLOT_POS);
    struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset);
    struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset);
    struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset);
@@ -130,10 +130,10 @@ static void copy_bfc( struct brw_clip_compile *c )
 
    /* Do we have any colors to copy? 
     */
-   if (!(brw_clip_have_vert_result(c, VERT_RESULT_COL0) &&
-         brw_clip_have_vert_result(c, VERT_RESULT_BFC0)) &&
-       !(brw_clip_have_vert_result(c, VERT_RESULT_COL1) &&
-         brw_clip_have_vert_result(c, VERT_RESULT_BFC1)))
+   if (!(brw_clip_have_vert_result(c, VARYING_SLOT_COL0) &&
+         brw_clip_have_vert_result(c, VARYING_SLOT_BFC0)) &&
+       !(brw_clip_have_vert_result(c, VARYING_SLOT_COL1) &&
+         brw_clip_have_vert_result(c, VARYING_SLOT_BFC1)))
       return;
 
    /* In some wierd degnerate cases we can end up testing the
@@ -156,25 +156,25 @@ static void copy_bfc( struct brw_clip_compile *c )
       GLuint i;
 
       for (i = 0; i < 3; i++) {
-	 if (brw_clip_have_vert_result(c, VERT_RESULT_COL0) &&
-             brw_clip_have_vert_result(c, VERT_RESULT_BFC0))
+	 if (brw_clip_have_vert_result(c, VARYING_SLOT_COL0) &&
+             brw_clip_have_vert_result(c, VARYING_SLOT_BFC0))
 	    brw_MOV(p, 
 		    byte_offset(c->reg.vertex[i],
                                 brw_vert_result_to_offset(&c->vue_map,
-                                                          VERT_RESULT_COL0)),
+                                                          VARYING_SLOT_COL0)),
 		    byte_offset(c->reg.vertex[i],
                                 brw_vert_result_to_offset(&c->vue_map,
-                                                          VERT_RESULT_BFC0)));
+                                                          VARYING_SLOT_BFC0)));
 
-	 if (brw_clip_have_vert_result(c, VERT_RESULT_COL1) &&
-             brw_clip_have_vert_result(c, VERT_RESULT_BFC1))
+	 if (brw_clip_have_vert_result(c, VARYING_SLOT_COL1) &&
+             brw_clip_have_vert_result(c, VARYING_SLOT_BFC1))
 	    brw_MOV(p, 
 		    byte_offset(c->reg.vertex[i],
                                 brw_vert_result_to_offset(&c->vue_map,
-                                                          VERT_RESULT_COL1)),
+                                                          VARYING_SLOT_COL1)),
 		    byte_offset(c->reg.vertex[i],
                                 brw_vert_result_to_offset(&c->vue_map,
-                                                          VERT_RESULT_BFC1)));
+                                                          VARYING_SLOT_BFC1)));
       }
    }
    brw_ENDIF(p);
@@ -235,7 +235,7 @@ static void merge_edgeflags( struct brw_clip_compile *c )
       brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
       brw_MOV(p, byte_offset(c->reg.vertex[0],
                              brw_vert_result_to_offset(&c->vue_map,
-                                                       VERT_RESULT_EDGE)),
+                                                       VARYING_SLOT_EDGE)),
               brw_imm_f(0));
       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 
@@ -243,7 +243,7 @@ static void merge_edgeflags( struct brw_clip_compile *c )
       brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
       brw_MOV(p, byte_offset(c->reg.vertex[2],
                              brw_vert_result_to_offset(&c->vue_map,
-                                                       VERT_RESULT_EDGE)),
+                                                       VARYING_SLOT_EDGE)),
               brw_imm_f(0));
       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
    }
@@ -257,7 +257,7 @@ static void apply_one_offset( struct brw_clip_compile *c,
 {
    struct brw_compile *p = &c->func;
    GLuint ndc_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                 BRW_VERT_RESULT_NDC);
+                                                 BRW_VARYING_SLOT_NDC);
    struct brw_reg z = deref_1f(vert, ndc_offset +
 			       2 * type_sz(BRW_REGISTER_TYPE_F));
 
@@ -316,7 +316,7 @@ static void emit_lines(struct brw_clip_compile *c,
       brw_CMP(p, 
 	      vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, 
 	      deref_1f(v0, brw_vert_result_to_offset(&c->vue_map,
-                                                     VERT_RESULT_EDGE)),
+                                                     VARYING_SLOT_EDGE)),
 	      brw_imm_f(0));
       brw_IF(p, BRW_EXECUTE_1);
       {
@@ -358,7 +358,7 @@ static void emit_points(struct brw_clip_compile *c,
       brw_CMP(p, 
 	      vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, 
 	      deref_1f(v0, brw_vert_result_to_offset(&c->vue_map,
-                                                     VERT_RESULT_EDGE)),
+                                                     VARYING_SLOT_EDGE)),
 	      brw_imm_f(0));
       brw_IF(p, BRW_EXECUTE_1);
       {
@@ -473,7 +473,7 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c )
    brw_clip_tri_init_vertices(c);
    brw_clip_init_ff_sync(c);
 
-   assert(brw_clip_have_vert_result(c, VERT_RESULT_EDGE));
+   assert(brw_clip_have_vert_result(c, VARYING_SLOT_EDGE));
 
    if (c->key.fill_ccw == CLIP_CULL &&
        c->key.fill_cw == CLIP_CULL) {
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index bf8cc3ac815..4df2498a5b9 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -110,9 +110,9 @@ static void brw_clip_project_vertex( struct brw_clip_compile *c,
    struct brw_compile *p = &c->func;
    struct brw_reg tmp = get_tmp(c);
    GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                  VERT_RESULT_HPOS);
+                                                  VARYING_SLOT_POS);
    GLuint ndc_offset = brw_vert_result_to_offset(&c->vue_map,
-                                                 BRW_VERT_RESULT_NDC);
+                                                 BRW_VARYING_SLOT_NDC);
 
    /* Fixup position.  Extract from the original vertex and re-project
     * to screen space:
@@ -155,20 +155,20 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
       int vert_result = c->vue_map.slot_to_vert_result[slot];
       GLuint delta = brw_vue_slot_to_offset(slot);
 
-      if (vert_result == VERT_RESULT_EDGE) {
+      if (vert_result == VARYING_SLOT_EDGE) {
 	 if (force_edgeflag) 
 	    brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
 	 else
 	    brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
-      } else if (vert_result == VERT_RESULT_PSIZ ||
-                 vert_result == VERT_RESULT_CLIP_DIST0 ||
-                 vert_result == VERT_RESULT_CLIP_DIST1) {
+      } else if (vert_result == VARYING_SLOT_PSIZ ||
+                 vert_result == VARYING_SLOT_CLIP_DIST0 ||
+                 vert_result == VARYING_SLOT_CLIP_DIST1) {
 	 /* PSIZ doesn't need interpolation because it isn't used by the
           * fragment shader.  CLIP_DIST0 and CLIP_DIST1 don't need
           * intepolation because on pre-GEN6, these are just placeholder VUE
           * slots that don't perform any action.
           */
-      } else if (vert_result < VERT_RESULT_MAX) {
+      } else if (vert_result < VARYING_SLOT_MAX) {
 	 /* This is a true vertex result (and not a special value for the VUE
 	  * header), so interpolate:
 	  *
@@ -299,41 +299,41 @@ void brw_clip_copy_colors( struct brw_clip_compile *c,
 {
    struct brw_compile *p = &c->func;
 
-   if (brw_clip_have_vert_result(c, VERT_RESULT_COL0))
+   if (brw_clip_have_vert_result(c, VARYING_SLOT_COL0))
       brw_MOV(p, 
 	      byte_offset(c->reg.vertex[to],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_COL0)),
+                                                    VARYING_SLOT_COL0)),
 	      byte_offset(c->reg.vertex[from],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_COL0)));
+                                                    VARYING_SLOT_COL0)));
 
-   if (brw_clip_have_vert_result(c, VERT_RESULT_COL1))
+   if (brw_clip_have_vert_result(c, VARYING_SLOT_COL1))
       brw_MOV(p, 
 	      byte_offset(c->reg.vertex[to],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_COL1)),
+                                                    VARYING_SLOT_COL1)),
 	      byte_offset(c->reg.vertex[from],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_COL1)));
+                                                    VARYING_SLOT_COL1)));
 
-   if (brw_clip_have_vert_result(c, VERT_RESULT_BFC0))
+   if (brw_clip_have_vert_result(c, VARYING_SLOT_BFC0))
       brw_MOV(p, 
 	      byte_offset(c->reg.vertex[to],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_BFC0)),
+                                                    VARYING_SLOT_BFC0)),
 	      byte_offset(c->reg.vertex[from],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_BFC0)));
+                                                    VARYING_SLOT_BFC0)));
 
-   if (brw_clip_have_vert_result(c, VERT_RESULT_BFC1))
+   if (brw_clip_have_vert_result(c, VARYING_SLOT_BFC1))
       brw_MOV(p, 
 	      byte_offset(c->reg.vertex[to],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_BFC1)),
+                                                    VARYING_SLOT_BFC1)),
 	      byte_offset(c->reg.vertex[from],
                           brw_vert_result_to_offset(&c->vue_map,
-                                                    VERT_RESULT_BFC1)));
+                                                    VARYING_SLOT_BFC1)));
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index d80332c10b0..0f1d4519638 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -323,26 +323,26 @@ struct brw_wm_prog_data {
 
 /**
  * Enum representing the i965-specific vertex results that don't correspond
- * exactly to any element of gl_vert_result.  The values of this enum are
- * assigned such that they don't conflict with gl_vert_result.
+ * exactly to any element of gl_varying_slot.  The values of this enum are
+ * assigned such that they don't conflict with gl_varying_slot.
  */
 typedef enum
 {
-   BRW_VERT_RESULT_NDC = VERT_RESULT_MAX,
-   BRW_VERT_RESULT_HPOS_DUPLICATE,
-   BRW_VERT_RESULT_PAD,
+   BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
+   BRW_VARYING_SLOT_POS_DUPLICATE,
+   BRW_VARYING_SLOT_PAD,
    /*
     * It's actually not a vert_result but just a _mark_ to let sf aware that
     * he need do something special to handle gl_PointCoord builtin variable
     * correctly. see compile_sf_prog() for more info.
     */
-   BRW_VERT_RESULT_PNTC,
-   BRW_VERT_RESULT_MAX
-} brw_vert_result;
+   BRW_VARYING_SLOT_PNTC,
+   BRW_VARYING_SLOT_MAX
+} brw_varying_slot;
 
 
 /**
- * Data structure recording the relationship between the gl_vert_result enum
+ * Data structure recording the relationship between the gl_varying_slot enum
  * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
  * single octaword within the VUE (128 bits).
  *
@@ -354,23 +354,23 @@ typedef enum
  */
 struct brw_vue_map {
    /**
-    * Map from gl_vert_result value to VUE slot.  For gl_vert_results that are
+    * Map from gl_varying_slot value to VUE slot.  For gl_varying_slots that are
     * not stored in a slot (because they are not written, or because
     * additional processing is applied before storing them in the VUE), the
     * value is -1.
     */
-   int vert_result_to_slot[BRW_VERT_RESULT_MAX];
+   int vert_result_to_slot[BRW_VARYING_SLOT_MAX];
 
    /**
-    * Map from VUE slot to gl_vert_result value.  For slots that do not
-    * directly correspond to a gl_vert_result, the value comes from
-    * brw_vert_result.
+    * Map from VUE slot to gl_varying_slot value.  For slots that do not
+    * directly correspond to a gl_varying_slot, the value comes from
+    * brw_varying_slot.
     *
-    * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
+    * For slots that are not in use, the value is BRW_VARYING_SLOT_MAX (this
     * simplifies code that uses the value stored in slot_to_vert_result to
     * create a bit mask).
     */
-   int slot_to_vert_result[BRW_VERT_RESULT_MAX];
+   int slot_to_vert_result[BRW_VARYING_SLOT_MAX];
 
    /**
     * Total number of VUE slots in use
@@ -387,7 +387,8 @@ static inline GLuint brw_vue_slot_to_offset(GLuint slot)
 }
 
 /**
- * Convert a vert_result into a byte offset within the VUE.
+ * Convert a vertex output (brw_varying_slot) into a byte offset within the
+ * VUE.
  */
 static inline GLuint brw_vert_result_to_offset(struct brw_vue_map *vue_map,
                                                GLuint vert_result)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index def246c78c8..e5c0536d478 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1259,13 +1259,13 @@ fs_visitor::calculate_urb_setup()
       }
    } else {
       /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
-      for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
+      for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
          /* Point size is packed into the header, not as a general attribute */
-         if (i == VERT_RESULT_PSIZ)
+         if (i == VARYING_SLOT_PSIZ)
             continue;
 
 	 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
-	    int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
+	    int fp_index = _mesa_vert_result_to_frag_attrib((gl_varying_slot) i);
 
 	    /* The back color slot is skipped when the front color is
 	     * also written to.  In addition, some slots can be
@@ -3001,7 +3001,7 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
          key.proj_attrib_mask |= BITFIELD64_BIT(i);
 
       if (intel->gen < 6) {
-         int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
+         int vp_index = _mesa_vert_result_to_frag_attrib((gl_varying_slot) i);
 
          if (vp_index >= 0)
             key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index c6c6c140bdd..13289844035 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -197,7 +197,7 @@ static void populate_key( struct brw_context *brw,
          /* Make sure that the VUE slots won't overflow the unsigned chars in
           * key->transform_feedback_bindings[].
           */
-         STATIC_ASSERT(BRW_VERT_RESULT_MAX <= 256);
+         STATIC_ASSERT(BRW_VARYING_SLOT_MAX <= 256);
 
          /* Make sure that we don't need more binding table entries than we've
           * set aside for use in transform feedback.  (We shouldn't, since we
diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h
index 6e014fa65d7..f10d8e589ad 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.h
+++ b/src/mesa/drivers/dri/i965/brw_gs.h
@@ -58,7 +58,7 @@ struct brw_gs_prog_key {
 
    /**
     * Map from the index of a transform feedback binding table entry to the
-    * gl_vert_result that should be streamed out through that binding table
+    * gl_varying_slot that should be streamed out through that binding table
     * entry.
     */
    unsigned char transform_feedback_bindings[BRW_MAX_SOL_BINDINGS];
diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index 501cee42ea4..1e596d21fd8 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -446,8 +446,8 @@ gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key,
             struct brw_reg vertex_slot = c->reg.vertex[vertex];
             vertex_slot.nr += slot / 2;
             vertex_slot.subnr = (slot % 2) * 16;
-            /* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */
-            vertex_slot.dw1.bits.swizzle = vert_result == VERT_RESULT_PSIZ
+            /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
+            vertex_slot.dw1.bits.swizzle = vert_result == VARYING_SLOT_PSIZ
                ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
             brw_set_access_mode(p, BRW_ALIGN_16);
             brw_MOV(p, stride(c->reg.header, 4, 4, 1),
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index eb361a97092..1132c9a4c00 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -73,8 +73,8 @@ static void compile_sf_prog( struct brw_context *brw,
        * it manually to let SF shader generate the needed interpolation
        * coefficient for FS shader.
        */
-      c.vue_map.vert_result_to_slot[BRW_VERT_RESULT_PNTC] = c.vue_map.num_slots;
-      c.vue_map.slot_to_vert_result[c.vue_map.num_slots++] = BRW_VERT_RESULT_PNTC;
+      c.vue_map.vert_result_to_slot[BRW_VARYING_SLOT_PNTC] = c.vue_map.num_slots;
+      c.vue_map.slot_to_vert_result[c.vue_map.num_slots++] = BRW_VARYING_SLOT_PNTC;
    }
    c.urb_entry_read_offset = brw_sf_compute_urb_entry_read_offset(intel);
    c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset;
@@ -155,7 +155,7 @@ brw_upload_sf_prog(struct brw_context *brw)
        * edgeflag testing here, it is already done in the clip
        * program.
        */
-      if (key.attrs & BITFIELD64_BIT(VERT_RESULT_EDGE))
+      if (key.attrs & BITFIELD64_BIT(VARYING_SLOT_EDGE))
 	 key.primitive = SF_UNFILLED_TRIS;
       else
 	 key.primitive = SF_TRIANGLES;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index 5f3673bec08..7f254cfc878 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -86,11 +86,11 @@ static void copy_bfc( struct brw_sf_compile *c,
    GLuint i;
 
    for (i = 0; i < 2; i++) {
-      if (have_attr(c, VERT_RESULT_COL0+i) &&
-	  have_attr(c, VERT_RESULT_BFC0+i))
+      if (have_attr(c, VARYING_SLOT_COL0+i) &&
+	  have_attr(c, VARYING_SLOT_BFC0+i))
 	 brw_MOV(p, 
-		 get_vert_result(c, vert, VERT_RESULT_COL0+i),
-		 get_vert_result(c, vert, VERT_RESULT_BFC0+i));
+		 get_vert_result(c, vert, VARYING_SLOT_COL0+i),
+		 get_vert_result(c, vert, VARYING_SLOT_BFC0+i));
    }
 }
 
@@ -109,8 +109,8 @@ static void do_twoside_color( struct brw_sf_compile *c )
     * for user-supplied vertex programs, as t_vp_build.c always does
     * the right thing.
     */
-   if (!(have_attr(c, VERT_RESULT_COL0) && have_attr(c, VERT_RESULT_BFC0)) &&
-       !(have_attr(c, VERT_RESULT_COL1) && have_attr(c, VERT_RESULT_BFC1)))
+   if (!(have_attr(c, VARYING_SLOT_COL0) && have_attr(c, VARYING_SLOT_BFC0)) &&
+       !(have_attr(c, VARYING_SLOT_COL1) && have_attr(c, VARYING_SLOT_BFC1)))
       return;
    
    /* Need to use BRW_EXECUTE_4 and also do an 4-wide compare in order
@@ -138,8 +138,8 @@ static void do_twoside_color( struct brw_sf_compile *c )
  * Flat shading
  */
 
-#define VERT_RESULT_COLOR_BITS (BITFIELD64_BIT(VERT_RESULT_COL0) | \
-				BITFIELD64_BIT(VERT_RESULT_COL1))
+#define VARYING_SLOT_COLOR_BITS (BITFIELD64_BIT(VARYING_SLOT_COL0) | \
+                                 BITFIELD64_BIT(VARYING_SLOT_COL1))
 
 static void copy_colors( struct brw_sf_compile *c,
 		     struct brw_reg dst,
@@ -148,7 +148,7 @@ static void copy_colors( struct brw_sf_compile *c,
    struct brw_compile *p = &c->func;
    GLuint i;
 
-   for (i = VERT_RESULT_COL0; i <= VERT_RESULT_COL1; i++) {
+   for (i = VARYING_SLOT_COL0; i <= VARYING_SLOT_COL1; i++) {
       if (have_attr(c,i))
 	 brw_MOV(p, 
 		 get_vert_result(c, dst, i),
@@ -167,7 +167,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
    struct brw_compile *p = &c->func;
    struct intel_context *intel = &p->brw->intel;
    struct brw_reg ip = brw_ip_reg();
-   GLuint nr = _mesa_bitcount_64(c->key.attrs & VERT_RESULT_COLOR_BITS);
+   GLuint nr = _mesa_bitcount_64(c->key.attrs & VARYING_SLOT_COLOR_BITS);
    GLuint jmpi = 1;
 
    if (!nr)
@@ -206,7 +206,7 @@ static void do_flatshade_line( struct brw_sf_compile *c )
    struct brw_compile *p = &c->func;
    struct intel_context *intel = &p->brw->intel;
    struct brw_reg ip = brw_ip_reg();
-   GLuint nr = _mesa_bitcount_64(c->key.attrs & VERT_RESULT_COLOR_BITS);
+   GLuint nr = _mesa_bitcount_64(c->key.attrs & VARYING_SLOT_COLOR_BITS);
    GLuint jmpi = 1;
 
    if (!nr)
@@ -334,15 +334,15 @@ calculate_masks(struct brw_sf_compile *c,
    GLbitfield64 linear_mask;
 
    if (c->key.do_flat_shading)
-      persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VERT_RESULT_HPOS) |
-                                    BITFIELD64_BIT(VERT_RESULT_COL0) |
-                                    BITFIELD64_BIT(VERT_RESULT_COL1));
+      persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VARYING_SLOT_POS) |
+                                    BITFIELD64_BIT(VARYING_SLOT_COL0) |
+                                    BITFIELD64_BIT(VARYING_SLOT_COL1));
    else
-      persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VERT_RESULT_HPOS));
+      persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VARYING_SLOT_POS));
 
    if (c->key.do_flat_shading)
-      linear_mask = c->key.attrs & ~(BITFIELD64_BIT(VERT_RESULT_COL0) |
-                                     BITFIELD64_BIT(VERT_RESULT_COL1));
+      linear_mask = c->key.attrs & ~(BITFIELD64_BIT(VARYING_SLOT_COL0) |
+                                     BITFIELD64_BIT(VARYING_SLOT_COL1));
    else
       linear_mask = c->key.attrs;
 
@@ -358,7 +358,7 @@ calculate_masks(struct brw_sf_compile *c,
 
    /* Maybe only processs one attribute on the final round:
     */
-   if (vert_reg_to_vert_result(c, reg, 1) != BRW_VERT_RESULT_MAX) {
+   if (vert_reg_to_vert_result(c, reg, 1) != BRW_VARYING_SLOT_MAX) {
       *pc |= 0xf0;
 
       if (persp_mask & BITFIELD64_BIT(vert_reg_to_vert_result(c, reg, 1)))
@@ -381,20 +381,20 @@ calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg)
    uint16_t pc = 0;
 
    vert_result1 = vert_reg_to_vert_result(c, reg, 0);
-   if (vert_result1 >= VERT_RESULT_TEX0 && vert_result1 <= VERT_RESULT_TEX7) {
-      if (c->key.point_sprite_coord_replace & (1 << (vert_result1 - VERT_RESULT_TEX0)))
+   if (vert_result1 >= VARYING_SLOT_TEX0 && vert_result1 <= VARYING_SLOT_TEX7) {
+      if (c->key.point_sprite_coord_replace & (1 << (vert_result1 - VARYING_SLOT_TEX0)))
 	 pc |= 0x0f;
    }
-   if (vert_result1 == BRW_VERT_RESULT_PNTC)
+   if (vert_result1 == BRW_VARYING_SLOT_PNTC)
       pc |= 0x0f;
 
    vert_result2 = vert_reg_to_vert_result(c, reg, 1);
-   if (vert_result2 >= VERT_RESULT_TEX0 && vert_result2 <= VERT_RESULT_TEX7) {
+   if (vert_result2 >= VARYING_SLOT_TEX0 && vert_result2 <= VARYING_SLOT_TEX7) {
       if (c->key.point_sprite_coord_replace & (1 << (vert_result2 -
-                                                     VERT_RESULT_TEX0)))
+                                                     VARYING_SLOT_TEX0)))
          pc |= 0xf0;
    }
-   if (vert_result2 == BRW_VERT_RESULT_PNTC)
+   if (vert_result2 == BRW_VARYING_SLOT_PNTC)
       pc |= 0xf0;
 
    return pc;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 86921a033d1..88a3e3b025f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -299,8 +299,8 @@ public:
    /* Regs for vertex results.  Generated at ir_variable visiting time
     * for the ir->location's used.
     */
-   dst_reg output_reg[BRW_VERT_RESULT_MAX];
-   const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
+   dst_reg output_reg[BRW_VARYING_SLOT_MAX];
+   const char *output_reg_annotation[BRW_VARYING_SLOT_MAX];
    int uniform_size[MAX_UNIFORMS];
    int uniform_vector_size[MAX_UNIFORMS];
    int uniforms;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 32de82b11f3..60575d70871 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2379,11 +2379,11 @@ void
 vec4_visitor::emit_ndc_computation()
 {
    /* Get the position */
-   src_reg pos = src_reg(output_reg[VERT_RESULT_HPOS]);
+   src_reg pos = src_reg(output_reg[VARYING_SLOT_POS]);
 
    /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
    dst_reg ndc = dst_reg(this, glsl_type::vec4_type);
-   output_reg[BRW_VERT_RESULT_NDC] = ndc;
+   output_reg[BRW_VARYING_SLOT_NDC] = ndc;
 
    current_annotation = "NDC";
    dst_reg ndc_w = ndc;
@@ -2402,7 +2402,7 @@ void
 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
 {
    if (intel->gen < 6 &&
-       ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) ||
+       ((c->prog_data.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) ||
         c->key.userclip_active || brw->has_negative_rhw_bug)) {
       dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
       dst_reg header1_w = header1;
@@ -2411,8 +2411,8 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
 
       emit(MOV(header1, 0u));
 
-      if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
-	 src_reg psiz = src_reg(output_reg[VERT_RESULT_PSIZ]);
+      if (c->prog_data.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) {
+	 src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ]);
 
 	 current_annotation = "Point size";
 	 emit(MUL(header1_w, psiz, src_reg((float)(1 << 11))));
@@ -2423,7 +2423,7 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
       for (i = 0; i < c->key.nr_userclip_plane_consts; i++) {
 	 vec4_instruction *inst;
 
-	 inst = emit(DP4(dst_null_f(), src_reg(output_reg[VERT_RESULT_HPOS]),
+	 inst = emit(DP4(dst_null_f(), src_reg(output_reg[VARYING_SLOT_POS]),
                          src_reg(this->userplane[i])));
 	 inst->conditional_mod = BRW_CONDITIONAL_L;
 
@@ -2441,13 +2441,13 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
        * clipped against all fixed planes.
        */
       if (brw->has_negative_rhw_bug) {
-         src_reg ndc_w = src_reg(output_reg[BRW_VERT_RESULT_NDC]);
+         src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC]);
          ndc_w.swizzle = BRW_SWIZZLE_WWWW;
          emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L));
          vec4_instruction *inst;
          inst = emit(OR(header1_w, src_reg(header1_w), src_reg(1u << 6)));
          inst->predicate = BRW_PREDICATE_NORMAL;
-         inst = emit(MOV(output_reg[BRW_VERT_RESULT_NDC], src_reg(0.0f)));
+         inst = emit(MOV(output_reg[BRW_VARYING_SLOT_NDC], src_reg(0.0f)));
          inst->predicate = BRW_PREDICATE_NORMAL;
       }
 
@@ -2456,9 +2456,9 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
       emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
    } else {
       emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0)));
-      if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
+      if (c->prog_data.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) {
          emit(MOV(brw_writemask(reg, WRITEMASK_W),
-                  src_reg(output_reg[VERT_RESULT_PSIZ])));
+                  src_reg(output_reg[VARYING_SLOT_PSIZ])));
       }
    }
 }
@@ -2486,10 +2486,10 @@ vec4_visitor::emit_clip_distances(struct brw_reg reg, int offset)
     * gl_ClipDistance.  Accordingly, we use gl_ClipVertex to perform clipping
     * if the user wrote to it; otherwise we use gl_Position.
     */
-   gl_vert_result clip_vertex = VERT_RESULT_CLIP_VERTEX;
+   gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX;
    if (!(c->prog_data.outputs_written
-         & BITFIELD64_BIT(VERT_RESULT_CLIP_VERTEX))) {
-      clip_vertex = VERT_RESULT_HPOS;
+         & BITFIELD64_BIT(VARYING_SLOT_CLIP_VERTEX))) {
+      clip_vertex = VARYING_SLOT_POS;
    }
 
    for (int i = 0; i + offset < c->key.nr_userclip_plane_consts && i < 4;
@@ -2503,16 +2503,16 @@ vec4_visitor::emit_clip_distances(struct brw_reg reg, int offset)
 void
 vec4_visitor::emit_generic_urb_slot(dst_reg reg, int vert_result)
 {
-   assert (vert_result < VERT_RESULT_MAX);
+   assert (vert_result < VARYING_SLOT_MAX);
    reg.type = output_reg[vert_result].type;
    current_annotation = output_reg_annotation[vert_result];
    /* Copy the register, saturating if necessary */
    vec4_instruction *inst = emit(MOV(reg,
                                      src_reg(output_reg[vert_result])));
-   if ((vert_result == VERT_RESULT_COL0 ||
-        vert_result == VERT_RESULT_COL1 ||
-        vert_result == VERT_RESULT_BFC0 ||
-        vert_result == VERT_RESULT_BFC1) &&
+   if ((vert_result == VARYING_SLOT_COL0 ||
+        vert_result == VARYING_SLOT_COL1 ||
+        vert_result == VARYING_SLOT_BFC0 ||
+        vert_result == VARYING_SLOT_BFC1) &&
        c->key.clamp_vertex_color) {
       inst->saturate = true;
    }
@@ -2526,30 +2526,30 @@ vec4_visitor::emit_urb_slot(int mrf, int vert_result)
    reg.type = BRW_REGISTER_TYPE_F;
 
    switch (vert_result) {
-   case VERT_RESULT_PSIZ:
+   case VARYING_SLOT_PSIZ:
       /* PSIZ is always in slot 0, and is coupled with other flags. */
       current_annotation = "indices, point width, clip flags";
       emit_psiz_and_flags(hw_reg);
       break;
-   case BRW_VERT_RESULT_NDC:
+   case BRW_VARYING_SLOT_NDC:
       current_annotation = "NDC";
-      emit(MOV(reg, src_reg(output_reg[BRW_VERT_RESULT_NDC])));
+      emit(MOV(reg, src_reg(output_reg[BRW_VARYING_SLOT_NDC])));
       break;
-   case BRW_VERT_RESULT_HPOS_DUPLICATE:
-   case VERT_RESULT_HPOS:
+   case BRW_VARYING_SLOT_POS_DUPLICATE:
+   case VARYING_SLOT_POS:
       current_annotation = "gl_Position";
-      emit(MOV(reg, src_reg(output_reg[VERT_RESULT_HPOS])));
+      emit(MOV(reg, src_reg(output_reg[VARYING_SLOT_POS])));
       break;
-   case VERT_RESULT_CLIP_DIST0:
-   case VERT_RESULT_CLIP_DIST1:
+   case VARYING_SLOT_CLIP_DIST0:
+   case VARYING_SLOT_CLIP_DIST1:
       if (this->c->key.uses_clip_distance) {
          emit_generic_urb_slot(reg, vert_result);
       } else {
          current_annotation = "user clip distances";
-         emit_clip_distances(hw_reg, (vert_result - VERT_RESULT_CLIP_DIST0) * 4);
+         emit_clip_distances(hw_reg, (vert_result - VARYING_SLOT_CLIP_DIST0) * 4);
       }
       break;
-   case VERT_RESULT_EDGE:
+   case VARYING_SLOT_EDGE:
       /* This is present when doing unfilled polygons.  We're supposed to copy
        * the edge flag from the user-provided vertex array
        * (glEdgeFlagPointer), or otherwise we'll copy from the current value
@@ -2560,7 +2560,7 @@ vec4_visitor::emit_urb_slot(int mrf, int vert_result)
       emit(MOV(reg, src_reg(dst_reg(ATTR, VERT_ATTRIB_EDGEFLAG,
                                     glsl_type::float_type, WRITEMASK_XYZW))));
       break;
-   case BRW_VERT_RESULT_PAD:
+   case BRW_VARYING_SLOT_PAD:
       /* No need to write to this slot */
       break;
    default:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 75799af0bbe..c9dc797d5d6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -451,7 +451,7 @@ vec4_visitor::setup_vp_regs()
    /* PROGRAM_OUTPUT */
    for (int slot = 0; slot < c->prog_data.vue_map.num_slots; slot++) {
       int vert_result = c->prog_data.vue_map.slot_to_vert_result[slot];
-      if (vert_result == VERT_RESULT_PSIZ)
+      if (vert_result == VARYING_SLOT_PSIZ)
          output_reg[vert_result] = dst_reg(this, glsl_type::float_type);
       else
          output_reg[vert_result] = dst_reg(this, glsl_type::vec4_type);
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 3daed19546c..7f060cd0a05 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -66,9 +66,9 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c)
    int i;
 
    vue_map->num_slots = 0;
-   for (i = 0; i < BRW_VERT_RESULT_MAX; ++i) {
+   for (i = 0; i < BRW_VARYING_SLOT_MAX; ++i) {
       vue_map->vert_result_to_slot[i] = -1;
-      vue_map->slot_to_vert_result[i] = BRW_VERT_RESULT_MAX;
+      vue_map->slot_to_vert_result[i] = BRW_VARYING_SLOT_MAX;
    }
 
    /* VUE header: format depends on chip generation and whether clipping is
@@ -81,9 +81,9 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c)
        * dword 4-7 is ndc position
        * dword 8-11 is the first vertex data.
        */
-      assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
-      assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
-      assign_vue_slot(vue_map, VERT_RESULT_HPOS);
+      assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
+      assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
+      assign_vue_slot(vue_map, VARYING_SLOT_POS);
       break;
    case 5:
       /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
@@ -98,13 +98,13 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c)
        * contiguous with the other vert_results, so we make dword 24-27 a
        * duplicate copy of the 4D space position.
        */
-      assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
-      assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC);
-      assign_vue_slot(vue_map, BRW_VERT_RESULT_HPOS_DUPLICATE);
-      assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
-      assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
-      assign_vue_slot(vue_map, BRW_VERT_RESULT_PAD);
-      assign_vue_slot(vue_map, VERT_RESULT_HPOS);
+      assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
+      assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
+      assign_vue_slot(vue_map, BRW_VARYING_SLOT_POS_DUPLICATE);
+      assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
+      assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
+      assign_vue_slot(vue_map, BRW_VARYING_SLOT_PAD);
+      assign_vue_slot(vue_map, VARYING_SLOT_POS);
       break;
    case 6:
    case 7:
@@ -115,24 +115,24 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c)
        * enabled.
        * dword 8-11 or 16-19 is the first vertex element data we fill.
        */
-      assign_vue_slot(vue_map, VERT_RESULT_PSIZ);
-      assign_vue_slot(vue_map, VERT_RESULT_HPOS);
+      assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
+      assign_vue_slot(vue_map, VARYING_SLOT_POS);
       if (c->key.userclip_active) {
-         assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0);
-         assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1);
+         assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
+         assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
       }
       /* front and back colors need to be consecutive so that we can use
        * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
        * two-sided color.
        */
-      if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0))
-         assign_vue_slot(vue_map, VERT_RESULT_COL0);
-      if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0))
-         assign_vue_slot(vue_map, VERT_RESULT_BFC0);
-      if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1))
-         assign_vue_slot(vue_map, VERT_RESULT_COL1);
-      if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))
-         assign_vue_slot(vue_map, VERT_RESULT_BFC1);
+      if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_COL0))
+         assign_vue_slot(vue_map, VARYING_SLOT_COL0);
+      if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_BFC0))
+         assign_vue_slot(vue_map, VARYING_SLOT_BFC0);
+      if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_COL1))
+         assign_vue_slot(vue_map, VARYING_SLOT_COL1);
+      if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_BFC1))
+         assign_vue_slot(vue_map, VARYING_SLOT_BFC1);
       break;
    default:
       assert (!"VUE map not known for this chip generation");
@@ -143,14 +143,14 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c)
     * assign them contiguously.  Don't reassign outputs that already have a
     * slot.
     *
-    * Also, prior to Gen6, don't assign a slot for VERT_RESULT_CLIP_VERTEX,
-    * since it is unsupported.  In Gen6 and above, VERT_RESULT_CLIP_VERTEX may
+    * Also, prior to Gen6, don't assign a slot for VARYING_SLOT_CLIP_VERTEX,
+    * since it is unsupported.  In Gen6 and above, VARYING_SLOT_CLIP_VERTEX may
     * be needed for transform feedback; since we don't want to have to
     * recompute the VUE map (and everything that depends on it) when transform
     * feedback is enabled or disabled, just go ahead and assign a slot for it.
     */
-   for (int i = 0; i < VERT_RESULT_MAX; ++i) {
-      if (intel->gen < 6 && i == VERT_RESULT_CLIP_VERTEX)
+   for (int i = 0; i < VARYING_SLOT_MAX; ++i) {
+      if (intel->gen < 6 && i == VARYING_SLOT_CLIP_VERTEX)
          continue;
       if ((outputs_written & BITFIELD64_BIT(i)) &&
           vue_map->vert_result_to_slot[i] == -1) {
@@ -254,7 +254,7 @@ do_vs_prog(struct brw_context *brw,
    c.prog_data.inputs_read = vp->program.Base.InputsRead;
 
    if (c.key.copy_edgeflag) {
-      c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE);
+      c.prog_data.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE);
       c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
    }
 
@@ -267,7 +267,7 @@ do_vs_prog(struct brw_context *brw,
        */
       for (i = 0; i < 8; i++) {
          if (c.key.point_coord_replace & (1 << i))
-            c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_TEX0 + i);
+            c.prog_data.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_TEX0 + i);
       }
    }
 
diff --git a/src/mesa/drivers/dri/i965/brw_vs_constval.c b/src/mesa/drivers/dri/i965/brw_vs_constval.c
index f6ac256360e..e623b4c5e9f 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_constval.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_constval.c
@@ -111,13 +111,13 @@ static GLubyte get_active( struct tracker *t,
 }
 
 /**
- * Return the size (1,2,3 or 4) of the output/result for VERT_RESULT_idx.
+ * Return the size (1,2,3 or 4) of the output/result for VARYING_SLOT_idx.
  */
 static GLubyte get_output_size( struct tracker *t,
 				GLuint idx )
 {
    GLubyte active;
-   assert(idx < VERT_RESULT_MAX);
+   assert(idx < VARYING_SLOT_MAX);
    active = t->active[PROGRAM_OUTPUT][idx];
    if (active & (1<<3)) return 4;
    if (active & (1<<2)) return 3;
@@ -133,17 +133,17 @@ static void calc_sizes( struct tracker *t )
    GLint vertRes;
 
    if (t->twoside) {
-      t->active[PROGRAM_OUTPUT][VERT_RESULT_COL0] |= 
-	 t->active[PROGRAM_OUTPUT][VERT_RESULT_BFC0];
+      t->active[PROGRAM_OUTPUT][VARYING_SLOT_COL0] |= 
+	 t->active[PROGRAM_OUTPUT][VARYING_SLOT_BFC0];
 
-      t->active[PROGRAM_OUTPUT][VERT_RESULT_COL1] |= 
-	 t->active[PROGRAM_OUTPUT][VERT_RESULT_BFC1];
+      t->active[PROGRAM_OUTPUT][VARYING_SLOT_COL1] |= 
+	 t->active[PROGRAM_OUTPUT][VARYING_SLOT_BFC1];
    }
 
    /* Examine vertex program output sizes to set the size_masks[] info
     * which describes the fragment program input sizes.
     */
-   for (vertRes = 0; vertRes < VERT_RESULT_MAX; vertRes++) {
+   for (vertRes = 0; vertRes < VARYING_SLOT_MAX; vertRes++) {
 
       /* map vertex program output index to fragment program input index */
       GLint fragAttrib = _mesa_vert_result_to_frag_attrib(vertRes);
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 87f5bb10ebd..3da220ddb73 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -57,7 +57,7 @@ get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset,
                   int fs_attr, bool two_side_color, uint32_t *max_source_attr)
 {
    int vs_attr = _mesa_frag_attrib_to_vert_result(fs_attr);
-   if (vs_attr < 0 || vs_attr == VERT_RESULT_HPOS) {
+   if (vs_attr < 0 || vs_attr == VARYING_SLOT_POS) {
       /* These attributes will be overwritten by the fragment shader's
        * interpolation code (see emit_interp() in brw_wm_fp.c), so just let
        * them reference the first available attribute.
@@ -71,10 +71,10 @@ get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset,
    /* If there was only a back color written but not front, use back
     * as the color instead of undefined
     */
-   if (slot == -1 && vs_attr == VERT_RESULT_COL0)
-      slot = vue_map->vert_result_to_slot[VERT_RESULT_BFC0];
-   if (slot == -1 && vs_attr == VERT_RESULT_COL1)
-      slot = vue_map->vert_result_to_slot[VERT_RESULT_BFC1];
+   if (slot == -1 && vs_attr == VARYING_SLOT_COL0)
+      slot = vue_map->vert_result_to_slot[VARYING_SLOT_BFC0];
+   if (slot == -1 && vs_attr == VARYING_SLOT_COL1)
+      slot = vue_map->vert_result_to_slot[VARYING_SLOT_BFC1];
 
    if (slot == -1) {
       /* This attribute does not exist in the VUE--that means that the vertex
@@ -107,10 +107,10 @@ get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset,
     * do back-facing swizzling.
     */
    bool swizzling = two_side_color &&
-      ((vue_map->slot_to_vert_result[slot] == VERT_RESULT_COL0 &&
-        vue_map->slot_to_vert_result[slot+1] == VERT_RESULT_BFC0) ||
-       (vue_map->slot_to_vert_result[slot] == VERT_RESULT_COL1 &&
-        vue_map->slot_to_vert_result[slot+1] == VERT_RESULT_BFC1));
+      ((vue_map->slot_to_vert_result[slot] == VARYING_SLOT_COL0 &&
+        vue_map->slot_to_vert_result[slot+1] == VARYING_SLOT_BFC0) ||
+       (vue_map->slot_to_vert_result[slot] == VARYING_SLOT_COL1 &&
+        vue_map->slot_to_vert_result[slot+1] == VARYING_SLOT_BFC1));
 
    /* Update max_source_attr.  If swizzling, the SF will read this slot + 1. */
    if (*max_source_attr < source_attr + swizzling)
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 28cecf2d5cd..b55fccc0e0b 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -134,8 +134,8 @@ upload_3dstate_so_decl_list(struct brw_context *brw,
       unsigned component_mask =
          (1 << linked_xfb_info->Outputs[i].NumComponents) - 1;
 
-      /* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */
-      if (vert_result == VERT_RESULT_PSIZ) {
+      /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
+      if (vert_result == VARYING_SLOT_PSIZ) {
          assert(linked_xfb_info->Outputs[i].NumComponents == 1);
          component_mask <<= 3;
       } else {
diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c
index 80963274526..f3cf34d275f 100644
--- a/src/mesa/drivers/dri/r200/r200_tcl.c
+++ b/src/mesa/drivers/dri/r200/r200_tcl.c
@@ -431,23 +431,23 @@ static GLboolean r200_run_tcl_render( struct gl_context *ctx,
 	 rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten;
 
       vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0];
-      assert(vp_out & BITFIELD64_BIT(VERT_RESULT_HPOS));
+      assert(vp_out & BITFIELD64_BIT(VARYING_SLOT_POS));
       out_compsel = R200_OUTPUT_XYZW;
-      if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL0)) {
+      if (vp_out & BITFIELD64_BIT(VARYING_SLOT_COL0)) {
 	 out_compsel |= R200_OUTPUT_COLOR_0;
       }
-      if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL1)) {
+      if (vp_out & BITFIELD64_BIT(VARYING_SLOT_COL1)) {
 	 out_compsel |= R200_OUTPUT_COLOR_1;
       }
-      if (vp_out & BITFIELD64_BIT(VERT_RESULT_FOGC)) {
+      if (vp_out & BITFIELD64_BIT(VARYING_SLOT_FOGC)) {
          out_compsel |= R200_OUTPUT_DISCRETE_FOG;
       }
-      if (vp_out & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
+      if (vp_out & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) {
 	 out_compsel |= R200_OUTPUT_PT_SIZE;
       }
-      for (i = VERT_RESULT_TEX0; i < VERT_RESULT_TEX6; i++) {
+      for (i = VARYING_SLOT_TEX0; i < VARYING_SLOT_TEX6; i++) {
 	 if (vp_out & BITFIELD64_BIT(i)) {
-	    out_compsel |= R200_OUTPUT_TEX_0 << (i - VERT_RESULT_TEX0);
+	    out_compsel |= R200_OUTPUT_TEX_0 << (i - VARYING_SLOT_TEX0);
 	 }
       }
       if (rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] != out_compsel) {
diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c
index b371e80a4c7..ee867c29a7f 100644
--- a/src/mesa/drivers/dri/r200/r200_vertprog.c
+++ b/src/mesa/drivers/dri/r200/r200_vertprog.c
@@ -167,24 +167,24 @@ static unsigned long t_dst(struct prog_dst_register *dst)
 	 | R200_VSF_OUT_CLASS_TMP);
    case PROGRAM_OUTPUT:
       switch (dst->Index) {
-      case VERT_RESULT_HPOS:
+      case VARYING_SLOT_POS:
 	 return R200_VSF_OUT_CLASS_RESULT_POS;
-      case VERT_RESULT_COL0:
+      case VARYING_SLOT_COL0:
 	 return R200_VSF_OUT_CLASS_RESULT_COLOR;
-      case VERT_RESULT_COL1:
+      case VARYING_SLOT_COL1:
 	 return ((1 << R200_VPI_OUT_REG_INDEX_SHIFT)
 	    | R200_VSF_OUT_CLASS_RESULT_COLOR);
-      case VERT_RESULT_FOGC:
+      case VARYING_SLOT_FOGC:
 	 return R200_VSF_OUT_CLASS_RESULT_FOGC;
-      case VERT_RESULT_TEX0:
-      case VERT_RESULT_TEX1:
-      case VERT_RESULT_TEX2:
-      case VERT_RESULT_TEX3:
-      case VERT_RESULT_TEX4:
-      case VERT_RESULT_TEX5:
-	 return (((dst->Index - VERT_RESULT_TEX0) << R200_VPI_OUT_REG_INDEX_SHIFT)
+      case VARYING_SLOT_TEX0:
+      case VARYING_SLOT_TEX1:
+      case VARYING_SLOT_TEX2:
+      case VARYING_SLOT_TEX3:
+      case VARYING_SLOT_TEX4:
+      case VARYING_SLOT_TEX5:
+	 return (((dst->Index - VARYING_SLOT_TEX0) << R200_VPI_OUT_REG_INDEX_SHIFT)
 	    | R200_VSF_OUT_CLASS_RESULT_TEXC);
-      case VERT_RESULT_PSIZ:
+      case VARYING_SLOT_PSIZ:
 	 return R200_VSF_OUT_CLASS_RESULT_POINTSIZE;
       default:
 	 fprintf(stderr, "problem in %s, unknown dst output reg %d\n", __FUNCTION__, dst->Index);
@@ -429,10 +429,10 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2
 #endif
 
    if ((mesa_vp->Base.OutputsWritten &
-      ~((1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_COL0) | (1 << VERT_RESULT_COL1) |
-      (1 << VERT_RESULT_FOGC) | (1 << VERT_RESULT_TEX0) | (1 << VERT_RESULT_TEX1) |
-      (1 << VERT_RESULT_TEX2) | (1 << VERT_RESULT_TEX3) | (1 << VERT_RESULT_TEX4) |
-      (1 << VERT_RESULT_TEX5) | (1 << VERT_RESULT_PSIZ))) != 0) {
+      ~((1 << VARYING_SLOT_POS) | (1 << VARYING_SLOT_COL0) | (1 << VARYING_SLOT_COL1) |
+      (1 << VARYING_SLOT_FOGC) | (1 << VARYING_SLOT_TEX0) | (1 << VARYING_SLOT_TEX1) |
+      (1 << VARYING_SLOT_TEX2) | (1 << VARYING_SLOT_TEX3) | (1 << VARYING_SLOT_TEX4) |
+      (1 << VARYING_SLOT_TEX5) | (1 << VARYING_SLOT_PSIZ))) != 0) {
       if (R200_DEBUG & RADEON_FALLBACKS) {
 	 fprintf(stderr, "can't handle vert prog outputs 0x%llx\n",
                  (unsigned long long) mesa_vp->Base.OutputsWritten);
@@ -450,13 +450,13 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2
 /* FIXME: is changing the prog safe to do here? */
    if (mesa_vp->IsPositionInvariant &&
       /* make sure we only do this once */
-       !(mesa_vp->Base.OutputsWritten & (1 << VERT_RESULT_HPOS))) {
+       !(mesa_vp->Base.OutputsWritten & (1 << VARYING_SLOT_POS))) {
 	 _mesa_insert_mvp_code(ctx, mesa_vp);
       }
 
    /* for fogc, can't change mesa_vp, as it would hose swtnl, and exp with
       base e isn't directly available neither. */
-   if ((mesa_vp->Base.OutputsWritten & (1 << VERT_RESULT_FOGC)) && !vp->fogpidx) {
+   if ((mesa_vp->Base.OutputsWritten & (1 << VARYING_SLOT_FOGC)) && !vp->fogpidx) {
       struct gl_program_parameter_list *paramList;
       gl_state_index tokens[STATE_LENGTH] = { STATE_FOG_PARAMS, 0, 0, 0, 0 };
       paramList = mesa_vp->Base.Parameters;
@@ -578,7 +578,7 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2
       }
    }
 
-   if (!(mesa_vp->Base.OutputsWritten & (1 << VERT_RESULT_HPOS))) {
+   if (!(mesa_vp->Base.OutputsWritten & (1 << VARYING_SLOT_POS))) {
       if (R200_DEBUG & RADEON_FALLBACKS) {
 	 fprintf(stderr, "can't handle vert prog without position output\n");
       }
@@ -684,7 +684,7 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2
 
       dst = vpi->DstReg;
       if (dst.File == PROGRAM_OUTPUT &&
-	  dst.Index == VERT_RESULT_FOGC &&
+	  dst.Index == VARYING_SLOT_FOGC &&
 	  dst.WriteMask & WRITEMASK_X) {
 	  fog_temp_i = u_temp_i;
 	  dst.File = PROGRAM_TEMPORARY;