mesa: change gl_format to mesa_format

s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum

63 files changed, 190 insertions, 190 deletions

diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
index d648211123a..e8c0d91e264 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -806,7 +806,7 @@ driUpdateFramebufferSize(struct gl_context *ctx, const __DRIdrawable *dPriv)
 }
 
 uint32_t
-driGLFormatToImageFormat(gl_format format)
+driGLFormatToImageFormat(mesa_format format)
 {
    switch (format) {
    case MESA_FORMAT_RGB565:
@@ -836,7 +836,7 @@ driGLFormatToImageFormat(gl_format format)
    }
 }
 
-gl_format
+mesa_format
 driImageFormatToGLFormat(uint32_t image_format)
 {
    switch (image_format) {
diff --git a/src/mesa/drivers/dri/common/dri_util.h b/src/mesa/drivers/dri/common/dri_util.h
index a79a4ed7aea..a37a0bbbcd0 100644
--- a/src/mesa/drivers/dri/common/dri_util.h
+++ b/src/mesa/drivers/dri/common/dri_util.h
@@ -281,9 +281,9 @@ struct __DRIdrawableRec {
 };
 
 extern uint32_t
-driGLFormatToImageFormat(gl_format format);
+driGLFormatToImageFormat(mesa_format format);
 
-extern gl_format
+extern mesa_format
 driImageFormatToGLFormat(uint32_t image_format);
 
 extern void
diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c
index 3e35fe2d067..06981c20bc8 100644
--- a/src/mesa/drivers/dri/common/utils.c
+++ b/src/mesa/drivers/dri/common/utils.c
@@ -151,7 +151,7 @@ driGetRendererString( char * buffer, const char * hardware_name,
  *                      If the function fails and returns \c GL_FALSE, this
  *                      value will be unmodified, but some elements in the
  *                      linked list may be modified.
- * \param format        Mesa gl_format enum describing the pixel format
+ * \param format        Mesa mesa_format enum describing the pixel format
  * \param depth_bits    Array of depth buffer sizes to be exposed.
  * \param stencil_bits  Array of stencil buffer sizes to be exposed.
  * \param num_depth_stencil_bits  Number of entries in both \c depth_bits and
@@ -176,7 +176,7 @@ driGetRendererString( char * buffer, const char * hardware_name,
  * \c format).
  */
 __DRIconfig **
-driCreateConfigs(gl_format format,
+driCreateConfigs(mesa_format format,
 		 const uint8_t * depth_bits, const uint8_t * stencil_bits,
 		 unsigned num_depth_stencil_bits,
 		 const GLenum * db_modes, unsigned num_db_modes,
diff --git a/src/mesa/drivers/dri/common/utils.h b/src/mesa/drivers/dri/common/utils.h
index 22af123c3b0..0941434469f 100644
--- a/src/mesa/drivers/dri/common/utils.h
+++ b/src/mesa/drivers/dri/common/utils.h
@@ -48,7 +48,7 @@ struct __DRIconfigRec {
 };
 
 extern __DRIconfig **
-driCreateConfigs(gl_format format,
+driCreateConfigs(mesa_format format,
 		 const uint8_t * depth_bits, const uint8_t * stencil_bits,
 		 unsigned num_depth_stencil_bits,
 		 const GLenum * db_modes, unsigned num_db_modes,
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index e9895aa8609..c9effad6812 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -593,7 +593,7 @@ static bool
 i830_render_target_supported(struct intel_context *intel,
 			     struct gl_renderbuffer *rb)
 {
-   gl_format format = rb->Format;
+   mesa_format format = rb->Format;
 
    if (format == MESA_FORMAT_S8_Z24 ||
        format == MESA_FORMAT_X8_Z24 ||
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 1990f5b296b..40bd48a2401 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -39,7 +39,7 @@
 
 
 static GLuint
-translate_texture_format(gl_format mesa_format, GLenum DepthMode)
+translate_texture_format(mesa_format mesa_format, GLenum DepthMode)
 {
    switch (mesa_format) {
    case MESA_FORMAT_L8:
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 94fc05dfecf..137ca76a347 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -560,7 +560,7 @@ static bool
 i915_render_target_supported(struct intel_context *intel,
 			     struct gl_renderbuffer *rb)
 {
-   gl_format format = rb->Format;
+   mesa_format format = rb->Format;
 
    if (format == MESA_FORMAT_S8_Z24 ||
        format == MESA_FORMAT_X8_Z24 ||
diff --git a/src/mesa/drivers/dri/i915/intel_blit.c b/src/mesa/drivers/dri/i915/intel_blit.c
index e0d133739c1..267b096aeff 100644
--- a/src/mesa/drivers/dri/i915/intel_blit.c
+++ b/src/mesa/drivers/dri/i915/intel_blit.c
@@ -120,8 +120,8 @@ intel_miptree_blit(struct intel_context *intel,
     * consistent with what we want in the callers (glCopyTexSubImage(),
     * glBlitFramebuffer(), texture validation, etc.).
     */
-   gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
-   gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
+   mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
+   mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 
    /* The blitter doesn't support doing any format conversions.  We do also
     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c b/src/mesa/drivers/dri/i915/intel_fbo.c
index 64262a1ca38..2b82bb151a0 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915/intel_fbo.c
@@ -303,7 +303,7 @@ intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
  * not a user-created renderbuffer.
  */
 struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format)
+intel_create_renderbuffer(mesa_format format)
 {
    struct intel_renderbuffer *irb;
    struct gl_renderbuffer *rb;
@@ -338,7 +338,7 @@ intel_create_renderbuffer(gl_format format)
  * may be called at intel_update_renderbuffers() time.
  */
 struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format)
+intel_create_private_renderbuffer(mesa_format format)
 {
    struct intel_renderbuffer *irb;
 
@@ -682,8 +682,8 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
             return mask;
          }
 
-         gl_format src_format = _mesa_get_srgb_format_linear(src_rb->Format);
-         gl_format dst_format = _mesa_get_srgb_format_linear(dst_rb->Format);
+         mesa_format src_format = _mesa_get_srgb_format_linear(src_rb->Format);
+         mesa_format dst_format = _mesa_get_srgb_format_linear(dst_rb->Format);
          if (src_format != dst_format) {
             perf_debug("glBlitFramebuffer(): unsupported blit from %s to %s.  "
                        "Falling back to software rendering.\n",
diff --git a/src/mesa/drivers/dri/i915/intel_fbo.h b/src/mesa/drivers/dri/i915/intel_fbo.h
index 7e3050b4926..25a29d81eaf 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.h
+++ b/src/mesa/drivers/dri/i915/intel_fbo.h
@@ -121,22 +121,22 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, gl_buffer_index attIndex)
 }
 
 
-static INLINE gl_format
+static INLINE mesa_format
 intel_rb_format(const struct intel_renderbuffer *rb)
 {
    return rb->Base.Base.Format;
 }
 
 extern struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format);
+intel_create_renderbuffer(mesa_format format);
 
 struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format);
+intel_create_private_renderbuffer(mesa_format format);
 
 struct gl_renderbuffer*
 intel_create_wrapped_renderbuffer(struct gl_context * ctx,
 				  int width, int height,
-				  gl_format format);
+				  mesa_format format);
 
 extern void
 intel_fbo_init(struct intel_context *intel);
diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
index ece843f5098..b9a629fa9dd 100644
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
@@ -68,7 +68,7 @@ target_to_target(GLenum target)
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct intel_context *intel,
                             GLenum target,
-                            gl_format format,
+                            mesa_format format,
                             GLuint first_level,
                             GLuint last_level,
                             GLuint width0,
@@ -130,7 +130,7 @@ intel_miptree_create_layout(struct intel_context *intel,
  */
 static uint32_t
 intel_miptree_choose_tiling(struct intel_context *intel,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t width0,
                             enum intel_miptree_tiling_mode requested,
                             struct intel_mipmap_tree *mt)
@@ -166,7 +166,7 @@ intel_miptree_choose_tiling(struct intel_context *intel,
 struct intel_mipmap_tree *
 intel_miptree_create(struct intel_context *intel,
 		     GLenum target,
-		     gl_format format,
+		     mesa_format format,
 		     GLuint first_level,
 		     GLuint last_level,
 		     GLuint width0,
@@ -236,7 +236,7 @@ intel_miptree_create(struct intel_context *intel,
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct intel_context *intel,
                             drm_intel_bo *bo,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
@@ -295,7 +295,7 @@ intel_miptree_create_for_bo(struct intel_context *intel,
 struct intel_mipmap_tree*
 intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
                                      unsigned dri_attachment,
-                                     gl_format format,
+                                     mesa_format format,
                                      struct intel_region *region)
 {
    struct intel_mipmap_tree *mt = NULL;
@@ -334,7 +334,7 @@ intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
 struct intel_mipmap_tree*
 intel_miptree_create_for_image_buffer(struct intel_context *intel,
                                       enum __DRIimageBufferMask buffer_type,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t num_samples,
                                       struct intel_region *region)
 {
@@ -359,7 +359,7 @@ intel_miptree_create_for_image_buffer(struct intel_context *intel,
 
 struct intel_mipmap_tree*
 intel_miptree_create_for_renderbuffer(struct intel_context *intel,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t width,
                                       uint32_t height)
 {
@@ -449,7 +449,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
     */
    assert(target_to_target(image->TexObject->Target) == mt->target);
 
-   gl_format mt_format = mt->format;
+   mesa_format mt_format = mt->format;
 
    if (image->TexFormat != mt_format)
       return false;
@@ -629,7 +629,7 @@ intel_miptree_copy_slice(struct intel_context *intel,
 			 int depth)
 
 {
-   gl_format format = src_mt->format;
+   mesa_format format = src_mt->format;
    uint32_t width = src_mt->level[level].width;
    uint32_t height = src_mt->level[level].height;
    int slice;
diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h
index a7a82f60509..77b1f541a91 100644
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h
@@ -149,7 +149,7 @@ struct intel_mipmap_tree
     * This is just the same as the gl_texture_image->TexFormat or
     * gl_renderbuffer->Format.
     */
-   gl_format format;
+   mesa_format format;
 
    /**
     * The X offset of each image in the miptree must be aligned to this. See
@@ -223,7 +223,7 @@ enum intel_miptree_tiling_mode {
 
 struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
                                                GLenum target,
-					       gl_format format,
+					       mesa_format format,
                                                GLuint first_level,
                                                GLuint last_level,
                                                GLuint width0,
@@ -235,7 +235,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct intel_context *intel,
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct intel_context *intel,
                             GLenum target,
-                            gl_format format,
+                            mesa_format format,
                             GLuint first_level,
                             GLuint last_level,
                             GLuint width0,
@@ -246,7 +246,7 @@ intel_miptree_create_layout(struct intel_context *intel,
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct intel_context *intel,
                             drm_intel_bo *bo,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
@@ -256,13 +256,13 @@ intel_miptree_create_for_bo(struct intel_context *intel,
 struct intel_mipmap_tree*
 intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
                                      unsigned dri_attachment,
-                                     gl_format format,
+                                     mesa_format format,
                                      struct intel_region *region);
 
 struct intel_mipmap_tree*
 intel_miptree_create_for_image_buffer(struct intel_context *intel,
                                       enum __DRIimageBufferMask buffer_type,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t num_samples,
                                       struct intel_region *region);
 
@@ -275,7 +275,7 @@ intel_miptree_create_for_image_buffer(struct intel_context *intel,
  */
 struct intel_mipmap_tree*
 intel_miptree_create_for_renderbuffer(struct intel_context *intel,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t width,
                                       uint32_t height);
 
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c
index aa457eb3dc8..f921d29935b 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -844,7 +844,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
                   const struct gl_config * mesaVis, GLboolean isPixmap)
 {
    struct intel_renderbuffer *rb;
-   gl_format rgbFormat;
+   mesa_format rgbFormat;
    struct gl_framebuffer *fb;
 
    if (isPixmap)
@@ -1042,7 +1042,7 @@ intel_detect_swizzling(struct intel_screen *screen)
 static __DRIconfig**
 intel_screen_make_configs(__DRIscreen *dri_screen)
 {
-   static const gl_format formats[] = {
+   static const mesa_format formats[] = {
       MESA_FORMAT_RGB565,
       MESA_FORMAT_ARGB8888
    };
diff --git a/src/mesa/drivers/dri/i915/intel_tex_image.c b/src/mesa/drivers/dri/i915/intel_tex_image.c
index 975e77aa572..fc23a5ee02c 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_image.c
@@ -219,7 +219,7 @@ intel_set_texture_image_region(struct gl_context *ctx,
 			       struct intel_region *region,
 			       GLenum target,
 			       GLenum internalFormat,
-			       gl_format format,
+			       mesa_format format,
                                uint32_t offset,
                                GLuint width,
                                GLuint height,
@@ -287,7 +287,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
    struct gl_texture_object *texObj;
    struct gl_texture_image *texImage;
    int level = 0, internalFormat = 0;
-   gl_format texFormat = MESA_FORMAT_NONE;
+   mesa_format texFormat = MESA_FORMAT_NONE;
 
    texObj = _mesa_get_current_tex_object(ctx, target);
    intelObj = intel_texture_object(texObj);
diff --git a/src/mesa/drivers/dri/i915/intel_tex_layout.c b/src/mesa/drivers/dri/i915/intel_tex_layout.c
index 3a49a1b3570..647a2f8b31f 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_layout.c
@@ -39,7 +39,7 @@
 
 static unsigned int
 intel_horizontal_texture_alignment_unit(struct intel_context *intel,
-                                       gl_format format)
+                                       mesa_format format)
 {
    /**
     * From the "Alignment Unit Size" section of various specs, namely:
@@ -79,7 +79,7 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel,
 
 static unsigned int
 intel_vertical_texture_alignment_unit(struct intel_context *intel,
-                                     gl_format format)
+                                     mesa_format format)
 {
    /**
     * From the "Alignment Unit Size" section of various specs, namely:
@@ -114,7 +114,7 @@ intel_vertical_texture_alignment_unit(struct intel_context *intel,
 
 void
 intel_get_texture_alignment_unit(struct intel_context *intel,
-				 gl_format format,
+				 mesa_format format,
 				 unsigned int *w, unsigned int *h)
 {
    *w = intel_horizontal_texture_alignment_unit(intel, format);
diff --git a/src/mesa/drivers/dri/i915/intel_tex_layout.h b/src/mesa/drivers/dri/i915/intel_tex_layout.h
index 348ca3a6cc5..c1114b4e9f0 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/i915/intel_tex_layout.h
@@ -36,5 +36,5 @@ extern void i945_miptree_layout_2d(struct intel_mipmap_tree *mt);
 
 void
 intel_get_texture_alignment_unit(struct intel_context *intel,
-				 gl_format format,
+				 mesa_format format,
 				 unsigned int *w, unsigned int *h);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0939a317867..e7f6328d431 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -115,7 +115,7 @@ brw_blorp_surface_info::set(struct brw_context *brw,
       this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
       break;
    default: {
-      gl_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+      mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
       if (is_render_target) {
          assert(brw->format_supported_as_render_target[linear_format]);
          this->brw_surfaceformat = brw->render_target_format[linear_format];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c4d1108bcdf..00f37b37469 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -197,10 +197,10 @@ do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
 }
 
 static bool
-color_formats_match(gl_format src_format, gl_format dst_format)
+color_formats_match(mesa_format src_format, mesa_format dst_format)
 {
-   gl_format linear_src_format = _mesa_get_srgb_format_linear(src_format);
-   gl_format linear_dst_format = _mesa_get_srgb_format_linear(dst_format);
+   mesa_format linear_src_format = _mesa_get_srgb_format_linear(src_format);
+   mesa_format linear_dst_format = _mesa_get_srgb_format_linear(dst_format);
 
    /* Normally, we require the formats to be equal.  However, we also support
     * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
@@ -222,8 +222,8 @@ formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb,
     * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
     * between those formats.
     */
-   gl_format src_format = find_miptree(buffer_bit, src_irb)->format;
-   gl_format dst_format = find_miptree(buffer_bit, dst_irb)->format;
+   mesa_format src_format = find_miptree(buffer_bit, src_irb)->format;
+   mesa_format dst_format = find_miptree(buffer_bit, dst_irb)->format;
 
    return color_formats_match(src_format, dst_format);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index c55108a69fd..94672e00e35 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -147,7 +147,7 @@ brw_blorp_const_color_program::~brw_blorp_const_color_program()
  */
 static bool
 is_color_fast_clear_compatible(struct brw_context *brw,
-                               gl_format format,
+                               mesa_format format,
                                const union gl_color_union *color)
 {
    if (_mesa_is_format_integer_color(format))
@@ -193,7 +193,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
    dst.set(brw, irb->mt, irb->mt_level, layer, true);
 
    /* Override the surface format according to the context's sRGB rules. */
-   gl_format format = _mesa_get_render_format(ctx, irb->mt->format);
+   mesa_format format = _mesa_get_render_format(ctx, irb->mt->format);
    dst.brw_surfaceformat = brw->render_target_format[format];
 
    x0 = fb->_Xmin;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 42d40e67cfb..8d098e6c3b7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1644,7 +1644,7 @@ void brw_upload_abo_surfaces(struct brw_context *brw,
                              struct brw_stage_prog_data *prog_data);
 
 /* brw_surface_formats.c */
-bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
+bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
 bool brw_render_target_supported(struct brw_context *brw,
                                  struct gl_renderbuffer *rb);
 
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 56754b2f76c..77b8aa63007 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -188,12 +188,12 @@ void gen4_init_vtable_surface_functions(struct brw_context *brw);
 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 
-uint32_t brw_format_for_mesa_format(gl_format mesa_format);
+uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
 
 GLuint translate_tex_target(GLenum target);
 
 GLuint translate_tex_format(struct brw_context *brw,
-                            gl_format mesa_format,
+                            mesa_format mesa_format,
 			    GLenum srgb_decode);
 
 int brw_get_texture_swizzle(const struct gl_context *ctx,
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 9b75c2b8abb..ebbd335c536 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -310,7 +310,7 @@ const struct surface_format_info surface_formats[] = {
 #undef Y
 
 uint32_t
-brw_format_for_mesa_format(gl_format mesa_format)
+brw_format_for_mesa_format(mesa_format mesa_format)
 {
    /* This table is ordered according to the enum ordering in formats.h.  We do
     * expect that enum to be extended without our explicit initialization
@@ -530,7 +530,7 @@ brw_init_surface_formats(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
    int gen;
-   gl_format format;
+   mesa_format format;
 
    memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported));
 
@@ -654,7 +654,7 @@ bool
 brw_render_target_supported(struct brw_context *brw,
 			    struct gl_renderbuffer *rb)
 {
-   gl_format format = rb->Format;
+   mesa_format format = rb->Format;
 
    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
     * we would consider them renderable even though we don't have surface
@@ -685,7 +685,7 @@ brw_render_target_supported(struct brw_context *brw,
 
 GLuint
 translate_tex_format(struct brw_context *brw,
-                     gl_format mesa_format,
+                     mesa_format mesa_format,
 		     GLenum srgb_decode)
 {
    struct gl_context *ctx = &brw->ctx;
@@ -732,7 +732,7 @@ translate_tex_format(struct brw_context *brw,
 
 /** Can HiZ be enabled on a depthbuffer of the given format? */
 bool
-brw_is_hiz_depth_format(struct brw_context *brw, gl_format format)
+brw_is_hiz_depth_format(struct brw_context *brw, mesa_format format)
 {
    if (!brw->has_hiz)
       return false;
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index f5ea13437ae..a7e4ddd3a28 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -40,7 +40,7 @@
 
 static unsigned int
 intel_horizontal_texture_alignment_unit(struct brw_context *brw,
-                                       gl_format format)
+                                       mesa_format format)
 {
    /**
     * From the "Alignment Unit Size" section of various specs, namely:
@@ -86,7 +86,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
 
 static unsigned int
 intel_vertical_texture_alignment_unit(struct brw_context *brw,
-                                      gl_format format, bool multisampled)
+                                      mesa_format format, bool multisampled)
 {
    /**
     * From the "Alignment Unit Size" section of various specs, namely:
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c7386103c7b..dd96c9bfd3c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -237,7 +237,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
       intel_buffer_object(tObj->BufferObject);
    uint32_t size = tObj->BufferSize;
    drm_intel_bo *bo = NULL;
-   gl_format format = tObj->_BufferObjectFormat;
+   mesa_format format = tObj->_BufferObjectFormat;
    uint32_t brw_format = brw_format_for_mesa_format(format);
    int texel_size = _mesa_get_format_bytes(format);
 
@@ -596,7 +596,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    uint32_t tile_x, tile_y;
    uint32_t format = 0;
    /* _NEW_BUFFERS */
-   gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
    uint32_t surf_index =
       brw->wm.prog_data->binding_table.render_target_start + unit;
 
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index ff10ec84d56..12d0fa9de58 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -444,7 +444,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    struct intel_region *region = irb->mt->region;
    uint32_t format;
    /* _NEW_BUFFERS */
-   gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
    uint32_t surftype;
    bool is_array = false;
    int depth = MAX2(rb->Depth, 1);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 4d2218a9ce3..82720d174dd 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -162,8 +162,8 @@ intel_miptree_blit(struct brw_context *brw,
     * consistent with what we want in the callers (glCopyTexSubImage(),
     * glBlitFramebuffer(), texture validation, etc.).
     */
-   gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
-   gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
+   mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
+   mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 
    /* The blitter doesn't support doing any format conversions.  We do also
     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 6f5070a7956..7f6db9ddc65 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -335,7 +335,7 @@ intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
  * \param num_samples must be quantized.
  */
 struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format, unsigned num_samples)
+intel_create_renderbuffer(mesa_format format, unsigned num_samples)
 {
    struct intel_renderbuffer *irb;
    struct gl_renderbuffer *rb;
@@ -373,7 +373,7 @@ intel_create_renderbuffer(gl_format format, unsigned num_samples)
  * \param num_samples must be quantized.
  */
 struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format, unsigned num_samples)
+intel_create_private_renderbuffer(mesa_format format, unsigned num_samples)
 {
    struct intel_renderbuffer *irb;
 
@@ -739,8 +739,8 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
             return mask;
          }
 
-         gl_format src_format = _mesa_get_srgb_format_linear(src_rb->Format);
-         gl_format dst_format = _mesa_get_srgb_format_linear(dst_rb->Format);
+         mesa_format src_format = _mesa_get_srgb_format_linear(src_rb->Format);
+         mesa_format dst_format = _mesa_get_srgb_format_linear(dst_rb->Format);
          if (src_format != dst_format) {
             perf_debug("glBlitFramebuffer(): unsupported blit from %s to %s.  "
                        "Falling back to software rendering.\n",
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h
index 67f64d365ee..45e2cd89d9e 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -125,22 +125,22 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, gl_buffer_index attIndex)
 }
 
 
-static inline gl_format
+static inline mesa_format
 intel_rb_format(const struct intel_renderbuffer *rb)
 {
    return rb->Base.Base.Format;
 }
 
 extern struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format, unsigned num_samples);
+intel_create_renderbuffer(mesa_format format, unsigned num_samples);
 
 struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format, unsigned num_samples);
+intel_create_private_renderbuffer(mesa_format format, unsigned num_samples);
 
 struct gl_renderbuffer*
 intel_create_wrapped_renderbuffer(struct gl_context * ctx,
 				  int width, int height,
-				  gl_format format);
+				  mesa_format format);
 
 extern void
 intel_fbo_init(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c2901decf59..cadf622e587 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -70,7 +70,7 @@ target_to_target(GLenum target)
  * created, based on the chip generation and the surface type.
  */
 static enum intel_msaa_layout
-compute_msaa_layout(struct brw_context *brw, gl_format format, GLenum target)
+compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
 {
    /* Prior to Gen7, all MSAA surfaces used IMS layout. */
    if (brw->gen < 7)
@@ -225,7 +225,7 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct brw_context *brw,
                             GLenum target,
-                            gl_format format,
+                            mesa_format format,
                             GLuint first_level,
                             GLuint last_level,
                             GLuint width0,
@@ -391,7 +391,7 @@ intel_miptree_create_layout(struct brw_context *brw,
  */
 static uint32_t
 intel_miptree_choose_tiling(struct brw_context *brw,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t width0,
                             uint32_t num_samples,
                             enum intel_miptree_tiling_mode requested,
@@ -486,7 +486,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create(struct brw_context *brw,
 		     GLenum target,
-		     gl_format format,
+		     mesa_format format,
 		     GLuint first_level,
 		     GLuint last_level,
 		     GLuint width0,
@@ -497,8 +497,8 @@ intel_miptree_create(struct brw_context *brw,
                      enum intel_miptree_tiling_mode requested_tiling)
 {
    struct intel_mipmap_tree *mt;
-   gl_format tex_format = format;
-   gl_format etc_format = MESA_FORMAT_NONE;
+   mesa_format tex_format = format;
+   mesa_format etc_format = MESA_FORMAT_NONE;
    GLuint total_width, total_height;
 
    if (brw->gen < 8 && !brw->is_baytrail) {
@@ -618,7 +618,7 @@ intel_miptree_create(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct brw_context *brw,
                             drm_intel_bo *bo,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
@@ -677,7 +677,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 struct intel_mipmap_tree*
 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
                                      unsigned dri_attachment,
-                                     gl_format format,
+                                     mesa_format format,
                                      uint32_t num_samples,
                                      struct intel_region *region)
 {
@@ -748,7 +748,7 @@ intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
 struct intel_mipmap_tree*
 intel_miptree_create_for_image_buffer(struct brw_context *intel,
                                       enum __DRIimageBufferMask buffer_type,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t num_samples,
                                       struct intel_region *region)
 {
@@ -805,7 +805,7 @@ intel_miptree_create_for_image_buffer(struct brw_context *intel,
 
 struct intel_mipmap_tree*
 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t width,
                                       uint32_t height,
                                       uint32_t num_samples)
@@ -917,7 +917,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
     */
    assert(target_to_target(image->TexObject->Target) == mt->target);
 
-   gl_format mt_format = mt->format;
+   mesa_format mt_format = mt->format;
    if (mt->format == MESA_FORMAT_X8_Z24 && mt->stencil_mt)
       mt_format = MESA_FORMAT_S8_Z24;
    if (mt->format == MESA_FORMAT_Z32_FLOAT && mt->stencil_mt)
@@ -1118,7 +1118,7 @@ intel_miptree_copy_slice(struct brw_context *brw,
 			 int depth)
 
 {
-   gl_format format = src_mt->format;
+   mesa_format format = src_mt->format;
    uint32_t width = src_mt->level[level].width;
    uint32_t height = src_mt->level[level].height;
    int slice;
@@ -1215,7 +1215,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
     * accessing this miptree using MCS-specific hardware mechanisms, which
     * infer the correct format based on num_samples.
     */
-   gl_format format;
+   mesa_format format;
    switch (num_samples) {
    case 4:
       /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
@@ -1284,7 +1284,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
     * we'll need to scale the height down by the block height and then a
     * further factor of 8.
     */
-   const gl_format format = MESA_FORMAT_R_UINT32;
+   const mesa_format format = MESA_FORMAT_R_UINT32;
    unsigned block_width_px;
    unsigned block_height;
    intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 69d5b0a22c0..722e346c661 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -285,10 +285,10 @@ struct intel_mipmap_tree
     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
     */
-   gl_format format;
+   mesa_format format;
 
    /** This variable stores the value of ETC compressed texture format */
-   gl_format etc_format;
+   mesa_format etc_format;
 
    /**
     * The X offset of each image in the miptree must be aligned to this.
@@ -497,7 +497,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 
 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
                                                GLenum target,
-					       gl_format format,
+					       mesa_format format,
                                                GLuint first_level,
                                                GLuint last_level,
                                                GLuint width0,
@@ -510,7 +510,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct brw_context *brw,
                             GLenum target,
-                            gl_format format,
+                            mesa_format format,
                             GLuint first_level,
                             GLuint last_level,
                             GLuint width0,
@@ -522,7 +522,7 @@ intel_miptree_create_layout(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct brw_context *brw,
                             drm_intel_bo *bo,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
@@ -532,14 +532,14 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 struct intel_mipmap_tree*
 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
                                      unsigned dri_attachment,
-                                     gl_format format,
+                                     mesa_format format,
                                      uint32_t num_samples,
                                      struct intel_region *region);
 
 struct intel_mipmap_tree*
 intel_miptree_create_for_image_buffer(struct brw_context *intel,
                                      enum __DRIimageBufferMask buffer_type,
-                                     gl_format format,
+                                     mesa_format format,
                                      uint32_t num_samples,
                                      struct intel_region *region);
 
@@ -552,7 +552,7 @@ intel_miptree_create_for_image_buffer(struct brw_context *intel,
  */
 struct intel_mipmap_tree*
 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t width,
                                       uint32_t height,
                                       uint32_t num_samples);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 86eabd04e2a..f5b8aa57b0a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -962,7 +962,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
 {
    struct intel_renderbuffer *rb;
    struct intel_screen *screen = (struct intel_screen*) driScrnPriv->driverPrivate;
-   gl_format rgbFormat;
+   mesa_format rgbFormat;
    unsigned num_samples = intel_quantize_num_samples(screen, mesaVis->samples);
    struct gl_framebuffer *fb;
 
@@ -1124,7 +1124,7 @@ intel_supported_msaa_modes(const struct intel_screen  *screen)
 static __DRIconfig**
 intel_screen_make_configs(__DRIscreen *dri_screen)
 {
-   static const gl_format formats[] = {
+   static const mesa_format formats[] = {
       MESA_FORMAT_RGB565,
       MESA_FORMAT_ARGB8888
    };
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index cc50f84ea32..b774efe820e 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -211,7 +211,7 @@ intel_set_texture_image_region(struct gl_context *ctx,
 			       struct intel_region *region,
 			       GLenum target,
 			       GLenum internalFormat,
-			       gl_format format,
+			       mesa_format format,
                                uint32_t offset,
                                GLuint width,
                                GLuint height,
@@ -278,7 +278,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
    struct gl_texture_object *texObj;
    struct gl_texture_image *texImage;
    int level = 0, internalFormat = 0;
-   gl_format texFormat = MESA_FORMAT_NONE;
+   mesa_format texFormat = MESA_FORMAT_NONE;
 
    texObj = _mesa_get_current_tex_object(ctx, target);
    intelObj = intel_texture_object(texObj);
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index c7f145308d9..f1de6c96bfd 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -628,7 +628,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
     * the function.
     */
    DBG("%s: level=%d offset=(%d,%d) (w,h)=(%d,%d) format=0x%x type=0x%x "
-       "gl_format=0x%x tiling=%d "
+       "mesa_format=0x%x tiling=%d "
        "packing=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d) "
        "for_glTexImage=%d\n",
        __FUNCTION__, texImage->Level, xoffset, yoffset, width, height,
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c b/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
index 81e7d62971f..43651bf4950 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
@@ -269,7 +269,7 @@ nouveau_finish_render_texture(struct gl_context *ctx,
 }
 
 static int
-validate_format_bpp(gl_format format)
+validate_format_bpp(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_screen.c b/src/mesa/drivers/dri/nouveau/nouveau_screen.c
index ce98242f9d7..7117f51fc0e 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_screen.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_screen.c
@@ -52,7 +52,7 @@ nouveau_get_configs(void)
 	const uint8_t stencil_bits[] = { 0,  0,  0,  8 };
 	const uint8_t msaa_samples[] = { 0 };
 
-	static const gl_format formats[3] = {
+	static const mesa_format formats[3] = {
 		MESA_FORMAT_RGB565,
 		MESA_FORMAT_ARGB8888,
 		MESA_FORMAT_XRGB8888,
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_surface.h b/src/mesa/drivers/dri/nouveau/nouveau_surface.h
index 8915ee4ca0f..3e802067c4f 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_surface.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_surface.h
@@ -39,7 +39,7 @@ struct nouveau_surface {
 
 	enum nouveau_surface_layout layout;
 
-	gl_format format;
+	mesa_format format;
 	unsigned cpp, pitch;
 
 	unsigned width, height;
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
index 8904389d198..dfa6d12907a 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
@@ -160,7 +160,7 @@ nouveau_unmap_texture_image(struct gl_context *ctx, struct gl_texture_image *ti,
 	}
 }
 
-static gl_format
+static mesa_format
 nouveau_choose_tex_format(struct gl_context *ctx, GLenum target,
                           GLint internalFormat,
 			  GLenum srcFormat, GLenum srcType)
@@ -581,7 +581,7 @@ nouveau_bind_texture(struct gl_context *ctx, GLenum target,
 	context_dirty_i(ctx, TEX_ENV, ctx->Texture.CurrentUnit);
 }
 
-static gl_format
+static mesa_format
 get_texbuffer_format(struct gl_renderbuffer *rb, GLint format)
 {
 	struct nouveau_surface *s = &to_nouveau_renderbuffer(rb)->surface;
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_util.h b/src/mesa/drivers/dri/nouveau/nouveau_util.h
index e44e8efba29..6905c42c627 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_util.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_util.h
@@ -31,7 +31,7 @@
 #include "main/colormac.h"
 
 static inline unsigned
-pack_rgba_i(gl_format f, uint8_t c[])
+pack_rgba_i(mesa_format f, uint8_t c[])
 {
 	switch (f) {
 	case MESA_FORMAT_ARGB8888:
@@ -54,7 +54,7 @@ pack_rgba_i(gl_format f, uint8_t c[])
 }
 
 static inline unsigned
-pack_zs_i(gl_format f, uint32_t z, uint8_t s)
+pack_zs_i(mesa_format f, uint32_t z, uint8_t s)
 {
 	switch (f) {
 	case MESA_FORMAT_Z24_S8:
@@ -69,7 +69,7 @@ pack_zs_i(gl_format f, uint32_t z, uint8_t s)
 }
 
 static inline unsigned
-pack_rgba_f(gl_format f, float c[])
+pack_rgba_f(mesa_format f, float c[])
 {
 	return pack_rgba_i(f, (uint8_t []) {
 			   FLOAT_TO_UBYTE(c[RCOMP]),
@@ -79,7 +79,7 @@ pack_rgba_f(gl_format f, float c[])
 }
 
 static inline unsigned
-pack_rgba_clamp_f(gl_format f, float c[])
+pack_rgba_clamp_f(mesa_format f, float c[])
 {
 	GLubyte bytes[4];
 	_mesa_unclamped_float_rgba_to_ubyte(bytes, c);
@@ -87,7 +87,7 @@ pack_rgba_clamp_f(gl_format f, float c[])
 }
 
 static inline unsigned
-pack_zs_f(gl_format f, float z, uint8_t s)
+pack_zs_f(mesa_format f, float z, uint8_t s)
 {
 	return pack_zs_i(f, FLOAT_TO_UINT(z), s);
 }
@@ -208,7 +208,7 @@ get_texgen_coeff(struct gl_texgen *c)
 }
 
 static inline unsigned
-get_format_blocksx(gl_format format,
+get_format_blocksx(mesa_format format,
 		       unsigned x)
 {
 	GLuint blockwidth;
@@ -218,7 +218,7 @@ get_format_blocksx(gl_format format,
 }
 
 static inline unsigned
-get_format_blocksy(gl_format format,
+get_format_blocksy(mesa_format format,
 		       unsigned y)
 {
 	GLuint blockwidth;
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_fb.c b/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
index 6129b6d3ff1..fcf9fdf59c6 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
@@ -32,7 +32,7 @@
 #include "nv04_driver.h"
 
 static inline unsigned
-get_rt_format(gl_format format)
+get_rt_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
index 85d81664909..d0245da8ab9 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
@@ -139,7 +139,7 @@ get_input_arg(struct combiner_state *rc, int arg, int flags)
 		int i = (source == GL_TEXTURE ?
 			 rc->unit : source - GL_TEXTURE0);
 		struct gl_texture_object *t = rc->ctx->Texture.Unit[i]._Current;
-		gl_format format = t->Image[0][t->BaseLevel]->TexFormat;
+		mesa_format format = t->Image[0][t->BaseLevel]->TexFormat;
 
 		if (format == MESA_FORMAT_A8) {
 			/* Emulated using I8. */
diff --git a/src/mesa/drivers/dri/nouveau/nv04_surface.c b/src/mesa/drivers/dri/nouveau/nv04_surface.c
index 103453f1b9a..153cc9b32d8 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_surface.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_surface.c
@@ -34,7 +34,7 @@
 #include "nv04_driver.h"
 
 static inline int
-swzsurf_format(gl_format format)
+swzsurf_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_A8:
@@ -73,7 +73,7 @@ swzsurf_format(gl_format format)
 }
 
 static inline int
-surf2d_format(gl_format format)
+surf2d_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_A8:
@@ -112,7 +112,7 @@ surf2d_format(gl_format format)
 }
 
 static inline int
-rect_format(gl_format format)
+rect_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_A8:
@@ -151,7 +151,7 @@ rect_format(gl_format format)
 }
 
 static inline int
-sifm_format(gl_format format)
+sifm_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_A8:
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
index 6f554618814..3fce2e33743 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
@@ -33,7 +33,7 @@
 #include "nv10_driver.h"
 
 static inline unsigned
-get_rt_format(gl_format format)
+get_rt_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
index 467b762fa03..b6ccf45242e 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
@@ -170,7 +170,7 @@ get_input_arg(struct combiner_state *rc, int arg, int flags)
 		int i = (source == GL_TEXTURE ?
 			 rc->unit : source - GL_TEXTURE0);
 		struct gl_texture_object *t = rc->ctx->Texture.Unit[i]._Current;
-		gl_format format = t->Image[0][t->BaseLevel]->TexFormat;
+		mesa_format format = t->Image[0][t->BaseLevel]->TexFormat;
 
 		if (format == MESA_FORMAT_A8) {
 			/* Emulated using I8. */
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_fb.c b/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
index 9d8b1d173c8..1c1f86297fe 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
@@ -33,7 +33,7 @@
 #include "nv20_driver.h"
 
 static inline unsigned
-get_rt_format(gl_format format)
+get_rt_format(mesa_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c
index 666fbadc9f8..825358a4fbe 100644
--- a/src/mesa/drivers/dri/r200/r200_blit.c
+++ b/src/mesa/drivers/dri/r200/r200_blit.c
@@ -38,7 +38,7 @@ static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
 }
 
 /* common formats supported as both textures and render targets */
-unsigned r200_check_blit(gl_format mesa_format, uint32_t dst_pitch)
+unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch)
 {
     /* XXX others?  BE/LE? */
     switch (mesa_format) {
@@ -97,8 +97,8 @@ static inline void emit_vtx_state(struct r200_context *r200)
 }
 
 static void inline emit_tx_setup(struct r200_context *r200,
-				 gl_format src_mesa_format,
-				 gl_format dst_mesa_format,
+				 mesa_format src_mesa_format,
+				 mesa_format dst_mesa_format,
 				 struct radeon_bo *bo,
 				 intptr_t offset,
 				 unsigned width,
@@ -297,7 +297,7 @@ static void inline emit_tx_setup(struct r200_context *r200,
 static inline void emit_cb_setup(struct r200_context *r200,
 				 struct radeon_bo *bo,
 				 intptr_t offset,
-				 gl_format mesa_format,
+				 mesa_format mesa_format,
 				 unsigned pitch,
 				 unsigned width,
 				 unsigned height)
@@ -463,7 +463,7 @@ static inline void emit_draw_packet(struct r200_context *r200,
 unsigned r200_blit(struct gl_context *ctx,
                    struct radeon_bo *src_bo,
                    intptr_t src_offset,
-                   gl_format src_mesaformat,
+                   mesa_format src_mesaformat,
                    unsigned src_pitch,
                    unsigned src_width,
                    unsigned src_height,
@@ -471,7 +471,7 @@ unsigned r200_blit(struct gl_context *ctx,
                    unsigned src_y_offset,
                    struct radeon_bo *dst_bo,
                    intptr_t dst_offset,
-                   gl_format dst_mesaformat,
+                   mesa_format dst_mesaformat,
                    unsigned dst_pitch,
                    unsigned dst_width,
                    unsigned dst_height,
diff --git a/src/mesa/drivers/dri/r200/r200_blit.h b/src/mesa/drivers/dri/r200/r200_blit.h
index fb5dacbe870..23057476336 100644
--- a/src/mesa/drivers/dri/r200/r200_blit.h
+++ b/src/mesa/drivers/dri/r200/r200_blit.h
@@ -30,12 +30,12 @@
 
 void r200_blit_init(struct r200_context *r200);
 
-unsigned r200_check_blit(gl_format mesa_format, uint32_t dst_pitch);
+unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch);
 
 unsigned r200_blit(struct gl_context *ctx,
                    struct radeon_bo *src_bo,
                    intptr_t src_offset,
-                   gl_format src_mesaformat,
+                   mesa_format src_mesaformat,
                    unsigned src_pitch,
                    unsigned src_width,
                    unsigned src_height,
@@ -43,7 +43,7 @@ unsigned r200_blit(struct gl_context *ctx,
                    unsigned src_y_offset,
                    struct radeon_bo *dst_bo,
                    intptr_t dst_offset,
-                   gl_format dst_mesaformat,
+                   mesa_format dst_mesaformat,
                    unsigned dst_pitch,
                    unsigned dst_width,
                    unsigned dst_height,
diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index f655bc184a3..12afb767bda 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -721,7 +721,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	struct radeon_framebuffer *rfb;
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
-	gl_format texFormat;
+	mesa_format texFormat;
 
 	radeon = pDRICtx->driverPrivate;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c
index 22a5e036ac6..e5d49ee6b00 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.c
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.c
@@ -38,7 +38,7 @@ static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
 }
 
 /* common formats supported as both textures and render targets */
-unsigned r100_check_blit(gl_format mesa_format, uint32_t dst_pitch)
+unsigned r100_check_blit(mesa_format mesa_format, uint32_t dst_pitch)
 {
     /* XXX others?  BE/LE? */
     switch (mesa_format) {
@@ -92,7 +92,7 @@ static inline void emit_vtx_state(struct r100_context *r100)
 }
 
 static void inline emit_tx_setup(struct r100_context *r100,
-				 gl_format mesa_format,
+				 mesa_format mesa_format,
 				 struct radeon_bo *bo,
 				 intptr_t offset,
 				 unsigned width,
@@ -175,7 +175,7 @@ static void inline emit_tx_setup(struct r100_context *r100,
 static inline void emit_cb_setup(struct r100_context *r100,
 				 struct radeon_bo *bo,
 				 intptr_t offset,
-				 gl_format mesa_format,
+				 mesa_format mesa_format,
 				 unsigned pitch,
 				 unsigned width,
 				 unsigned height)
@@ -341,7 +341,7 @@ static inline void emit_draw_packet(struct r100_context *r100,
 unsigned r100_blit(struct gl_context *ctx,
                    struct radeon_bo *src_bo,
                    intptr_t src_offset,
-                   gl_format src_mesaformat,
+                   mesa_format src_mesaformat,
                    unsigned src_pitch,
                    unsigned src_width,
                    unsigned src_height,
@@ -349,7 +349,7 @@ unsigned r100_blit(struct gl_context *ctx,
                    unsigned src_y_offset,
                    struct radeon_bo *dst_bo,
                    intptr_t dst_offset,
-                   gl_format dst_mesaformat,
+                   mesa_format dst_mesaformat,
                    unsigned dst_pitch,
                    unsigned dst_width,
                    unsigned dst_height,
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.h b/src/mesa/drivers/dri/radeon/radeon_blit.h
index 4fac4afe889..421560b6773 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.h
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.h
@@ -30,12 +30,12 @@
 
 void r100_blit_init(struct r100_context *r100);
 
-unsigned r100_check_blit(gl_format mesa_format, uint32_t dst_pitch);
+unsigned r100_check_blit(mesa_format mesa_format, uint32_t dst_pitch);
 
 unsigned r100_blit(struct gl_context *ctx,
                    struct radeon_bo *src_bo,
                    intptr_t src_offset,
-                   gl_format src_mesaformat,
+                   mesa_format src_mesaformat,
                    unsigned src_pitch,
                    unsigned src_width,
                    unsigned src_height,
@@ -43,7 +43,7 @@ unsigned r100_blit(struct gl_context *ctx,
                    unsigned src_y_offset,
                    struct radeon_bo *dst_bo,
                    intptr_t dst_offset,
-                   gl_format dst_mesaformat,
+                   mesa_format dst_mesaformat,
                    unsigned dst_pitch,
                    unsigned dst_width,
                    unsigned dst_height,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index c925ad9eaca..fedaf5063a7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -29,7 +29,7 @@ void
 radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb,
 			   struct radeon_bo *bo);
 struct radeon_renderbuffer *
-radeon_create_renderbuffer(gl_format format, __DRIdrawable *driDrawPriv);
+radeon_create_renderbuffer(mesa_format format, __DRIdrawable *driDrawPriv);
 
 void
 radeonReadPixels(struct gl_context * ctx,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index ce1eb1ea274..6cd15356634 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -474,11 +474,11 @@ struct radeon_context {
 	   void (*free_context)(struct gl_context *ctx);
 	   void (*emit_query_finish)(radeonContextPtr radeon);
 	   void (*update_scissor)(struct gl_context *ctx);
-	   unsigned (*check_blit)(gl_format mesa_format, uint32_t dst_pitch);
+	   unsigned (*check_blit)(mesa_format mesa_format, uint32_t dst_pitch);
 	   unsigned (*blit)(struct gl_context *ctx,
                         struct radeon_bo *src_bo,
                         intptr_t src_offset,
-                        gl_format src_mesaformat,
+                        mesa_format src_mesaformat,
                         unsigned src_pitch,
                         unsigned src_width,
                         unsigned src_height,
@@ -486,7 +486,7 @@ struct radeon_context {
                         unsigned src_y_offset,
                         struct radeon_bo *dst_bo,
                         intptr_t dst_offset,
-                        gl_format dst_mesaformat,
+                        mesa_format dst_mesaformat,
                         unsigned dst_pitch,
                         unsigned dst_width,
                         unsigned dst_height,
@@ -495,7 +495,7 @@ struct radeon_context {
                         unsigned reg_width,
                         unsigned reg_height,
                         unsigned flip_y);
-	   unsigned (*is_format_renderable)(gl_format mesa_format);
+	   unsigned (*is_format_renderable)(mesa_format mesa_format);
    } vtbl;
 };
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index eacd58f4bfe..7a0ce47e141 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -636,7 +636,7 @@ radeon_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
  * Not used for user-created renderbuffers.
  */
 struct radeon_renderbuffer *
-radeon_create_renderbuffer(gl_format format, __DRIdrawable *driDrawPriv)
+radeon_create_renderbuffer(mesa_format format, __DRIdrawable *driDrawPriv)
 {
     struct radeon_renderbuffer *rrb;
     struct gl_renderbuffer *rb;
@@ -833,7 +833,7 @@ static void
 radeon_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-	gl_format mesa_format;
+	mesa_format mesa_format;
 	int i;
 
 	for (i = -2; i < (GLint) ctx->Const.MaxColorAttachments; i++) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 4cb18388800..57cd725cd84 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -39,7 +39,7 @@
 #include "radeon_tile.h"
 
 static unsigned get_aligned_compressed_row_stride(
-		gl_format format,
+		mesa_format format,
 		unsigned width,
 		unsigned minStride)
 {
@@ -71,7 +71,7 @@ static unsigned get_aligned_compressed_row_stride(
 }
 
 unsigned get_texture_image_size(
-		gl_format format,
+		mesa_format format,
 		unsigned rowStride,
 		unsigned height,
 		unsigned depth,
@@ -96,7 +96,7 @@ unsigned get_texture_image_size(
 	return rowStride * height * depth;
 }
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, GLuint target)
 {
 	if (_mesa_is_format_compressed(format)) {
 		return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
@@ -177,7 +177,7 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree
  * Create a new mipmap tree, calculate its layout and allocate memory.
  */
 radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
-					  GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
+					  GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
 					  GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
 {
 	radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index 74007ffdebc..f919a581b52 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -91,16 +91,16 @@ GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 				   GLuint face, GLuint level);
 uint32_t get_base_teximage_offset(radeonTexObj *texObj);
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target);
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, unsigned target);
 
 unsigned get_texture_image_size(
-		gl_format format,
+		mesa_format format,
 		unsigned rowStride,
 		unsigned height,
 		unsigned depth,
 		unsigned tiling);
 
 radeon_mipmap_tree *radeon_miptree_create(radeonContextPtr rmesa,
-					  GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
+					  GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
 					  GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
 #endif /* __RADEON_MIPMAP_TREE_H_ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
index 0aa00bd95b0..e9bfc0df265 100644
--- a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
+++ b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
@@ -38,7 +38,7 @@
 #include "radeon_debug.h"
 #include "radeon_mipmap_tree.h"
 
-static gl_format gl_format_and_type_to_mesa_format(GLenum format, GLenum type)
+static mesa_format gl_format_and_type_to_mesa_format(GLenum format, GLenum type)
 {
     switch (format)
     {
@@ -94,7 +94,7 @@ do_blit_readpixels(struct gl_context * ctx,
 {
     radeonContextPtr radeon = RADEON_CONTEXT(ctx);
     const struct radeon_renderbuffer *rrb = radeon_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
-    const gl_format dst_format = gl_format_and_type_to_mesa_format(format, type);
+    const mesa_format dst_format = gl_format_and_type_to_mesa_format(format, type);
     unsigned dst_rowstride, dst_imagesize, aligned_rowstride, flip_y;
     struct radeon_bo *dst_buffer;
     GLint dst_x = 0, dst_y = 0;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 15bf5f859ae..d90bafa9818 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -598,7 +598,7 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv,
     const GLboolean swAccum = mesaVis->accumRedBits > 0;
     const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 	mesaVis->depthBits != 24;
-    gl_format rgbFormat;
+    mesa_format rgbFormat;
     struct radeon_framebuffer *rfb;
 
     if (isPixmap)
@@ -708,7 +708,7 @@ radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
 static const
 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
 {
-   static const gl_format formats[3] = {
+   static const mesa_format formats[3] = {
       MESA_FORMAT_RGB565,
       MESA_FORMAT_XRGB8888,
       MESA_FORMAT_ARGB8888
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
index 675eb78ec5c..fc723842c11 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
@@ -50,8 +50,8 @@ do_copy_texsubimage(struct gl_context *ctx,
     const GLuint level = timg->base.Base.Level;
     unsigned src_bpp;
     unsigned dst_bpp;
-    gl_format src_mesaformat;
-    gl_format dst_mesaformat;
+    mesa_format src_mesaformat;
+    mesa_format dst_mesaformat;
     unsigned flip_y;
 
     if (!radeon->vtbl.blit) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 09a7ccb1fff..5550a5aa1ec 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -598,7 +598,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_form
 	struct radeon_framebuffer *rfb;
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
-	gl_format texFormat;
+	mesa_format texFormat;
 
 	radeon = pDRICtx->driverPrivate;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 52cf95dffb8..8455b826270 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -213,7 +213,7 @@ radeon_unmap_texture_image(struct gl_context *ctx,
 }
 
 /* try to find a format which will only need a memcopy */
-static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa,
+static mesa_format radeonChoose8888TexFormat(radeonContextPtr rmesa,
 					   GLenum srcFormat,
 					   GLenum srcType, GLboolean fbo)
 {
@@ -242,7 +242,7 @@ static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa,
 #endif
 }
 
-gl_format radeonChooseTextureFormat_mesa(struct gl_context * ctx,
+mesa_format radeonChooseTextureFormat_mesa(struct gl_context * ctx,
 					 GLenum target,
 					 GLint internalFormat,
 					 GLenum format,
@@ -252,7 +252,7 @@ gl_format radeonChooseTextureFormat_mesa(struct gl_context * ctx,
 					 type, 0);
 }
 
-gl_format radeonChooseTextureFormat(struct gl_context * ctx,
+mesa_format radeonChooseTextureFormat(struct gl_context * ctx,
 				    GLint internalFormat,
 				    GLenum format,
 				    GLenum type, GLboolean fbo)
@@ -504,7 +504,7 @@ static void teximage_assign_miptree(radeonContextPtr rmesa,
 				"%s Failed to allocate miptree.\n", __func__);
 }
 
-unsigned radeonIsFormatRenderable(gl_format mesa_format)
+unsigned radeonIsFormatRenderable(mesa_format mesa_format)
 {
 	if (mesa_format == _radeon_texformat_argb8888 || mesa_format == _radeon_texformat_rgb565 ||
 		mesa_format == _radeon_texformat_argb1555 || mesa_format == _radeon_texformat_argb4444)
@@ -579,12 +579,12 @@ void radeon_image_target_texture_2d(struct gl_context *ctx, GLenum target,
 		fprintf(stderr, "miptree doesn't match image\n");
 }
 
-gl_format _radeon_texformat_rgba8888 = MESA_FORMAT_NONE;
-gl_format _radeon_texformat_argb8888 = MESA_FORMAT_NONE;
-gl_format _radeon_texformat_rgb565 = MESA_FORMAT_NONE;
-gl_format _radeon_texformat_argb4444 = MESA_FORMAT_NONE;
-gl_format _radeon_texformat_argb1555 = MESA_FORMAT_NONE;
-gl_format _radeon_texformat_al88 = MESA_FORMAT_NONE;
+mesa_format _radeon_texformat_rgba8888 = MESA_FORMAT_NONE;
+mesa_format _radeon_texformat_argb8888 = MESA_FORMAT_NONE;
+mesa_format _radeon_texformat_rgb565 = MESA_FORMAT_NONE;
+mesa_format _radeon_texformat_argb4444 = MESA_FORMAT_NONE;
+mesa_format _radeon_texformat_argb1555 = MESA_FORMAT_NONE;
+mesa_format _radeon_texformat_al88 = MESA_FORMAT_NONE;
 /*@}*/
 
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h
index 6ef640c3e20..286b2a20a30 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.h
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.h
@@ -33,12 +33,12 @@
 
 #include "main/formats.h"
 
-extern gl_format _radeon_texformat_rgba8888;
-extern gl_format _radeon_texformat_argb8888;
-extern gl_format _radeon_texformat_rgb565;
-extern gl_format _radeon_texformat_argb4444;
-extern gl_format _radeon_texformat_argb1555;
-extern gl_format _radeon_texformat_al88;
+extern mesa_format _radeon_texformat_rgba8888;
+extern mesa_format _radeon_texformat_argb8888;
+extern mesa_format _radeon_texformat_rgb565;
+extern mesa_format _radeon_texformat_argb4444;
+extern mesa_format _radeon_texformat_argb1555;
+extern mesa_format _radeon_texformat_al88;
 
 extern 
 void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride,
@@ -51,13 +51,13 @@ int radeon_validate_texture_miptree(struct gl_context * ctx,
 				    struct gl_texture_object *texObj);
 
 
-gl_format radeonChooseTextureFormat_mesa(struct gl_context * ctx,
+mesa_format radeonChooseTextureFormat_mesa(struct gl_context * ctx,
                                          GLenum target,
                                          GLint internalFormat,
                                          GLenum format,
                                          GLenum type);
 
-gl_format radeonChooseTextureFormat(struct gl_context * ctx,
+mesa_format radeonChooseTextureFormat(struct gl_context * ctx,
                                     GLint internalFormat,
                                     GLenum format,
                                     GLenum type, GLboolean fbo);
@@ -69,7 +69,7 @@ void radeonCopyTexSubImage(struct gl_context *ctx, GLuint dims,
                            GLint x, GLint y,
                            GLsizei width, GLsizei height);
 
-unsigned radeonIsFormatRenderable(gl_format mesa_format);
+unsigned radeonIsFormatRenderable(mesa_format mesa_format);
 
 void radeon_image_target_texture_2d(struct gl_context *ctx, GLenum target,
 				    struct gl_texture_object *texObj,
diff --git a/src/mesa/drivers/dri/radeon/radeon_tile.c b/src/mesa/drivers/dri/radeon/radeon_tile.c
index b95961fc188..433199fdc9a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tile.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tile.c
@@ -211,7 +211,7 @@ static void micro_tile_1_x_1_128bit(const void * src, unsigned src_pitch,
 
 void tile_image(const void * src, unsigned src_pitch,
                 void *dst, unsigned dst_pitch,
-                gl_format format, unsigned width, unsigned height)
+                mesa_format format, unsigned width, unsigned height)
 {
     assert(src_pitch >= width);
     assert(dst_pitch >= width);
@@ -435,7 +435,7 @@ static void micro_untile_1_x_1_128bit(const void * src, unsigned src_pitch,
 
 void untile_image(const void * src, unsigned src_pitch,
                   void *dst, unsigned dst_pitch,
-                  gl_format format, unsigned width, unsigned height)
+                  mesa_format format, unsigned width, unsigned height)
 {
     assert(src_pitch >= width);
     assert(dst_pitch >= width);
@@ -474,7 +474,7 @@ void untile_image(const void * src, unsigned src_pitch,
     }
 }
 
-void get_tile_size(gl_format format, unsigned *block_width, unsigned *block_height)
+void get_tile_size(mesa_format format, unsigned *block_width, unsigned *block_height)
 {
     switch (_mesa_get_format_bytes(format))
     {
diff --git a/src/mesa/drivers/dri/radeon/radeon_tile.h b/src/mesa/drivers/dri/radeon/radeon_tile.h
index 31d9c5611c3..6654c7db73d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tile.h
+++ b/src/mesa/drivers/dri/radeon/radeon_tile.h
@@ -29,10 +29,10 @@
 
 void tile_image(const void * src, unsigned src_pitch,
                 void *dst, unsigned dst_pitch,
-                gl_format format, unsigned width, unsigned height);
+                mesa_format format, unsigned width, unsigned height);
 
 void untile_image(const void * src, unsigned src_pitch,
                   void *dst, unsigned dst_pitch,
-                  gl_format format, unsigned width, unsigned height);
+                  mesa_format format, unsigned width, unsigned height);
 
-void get_tile_size(gl_format format, unsigned *block_width, unsigned *block_height);
+void get_tile_size(mesa_format format, unsigned *block_width, unsigned *block_height);
diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c
index 30e6805e960..ddb810f7032 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -76,7 +76,7 @@ static void swrastSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
     struct gl_texture_image *texImage;
     struct swrast_texture_image *swImage;
     uint32_t internalFormat;
-    gl_format texFormat;
+    mesa_format texFormat;
 
     dri_ctx = pDRICtx->driverPrivate;
 
@@ -130,7 +130,7 @@ swrastFillInModes(__DRIscreen *psp,
     __DRIconfig **configs;
     unsigned depth_buffer_factor;
     unsigned back_buffer_factor;
-    gl_format format;
+    mesa_format format;
 
     /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
      * support pageflipping at all.
@@ -627,7 +627,7 @@ viewport(struct gl_context *ctx)
     swrast_check_and_update_window_size(ctx, read);
 }
 
-static gl_format swrastChooseTextureFormat(struct gl_context * ctx,
+static mesa_format swrastChooseTextureFormat(struct gl_context * ctx,
                                            GLenum target,
 					   GLint internalFormat,
 					   GLenum format,